HP AT-30533-TR1, AT-30533-BLK, AT-30511-TR1, AT-30511-BLK Datasheet

Low Current, High Performance

NPN Silicon Bipolar Transistor

Technical Data

AT-30511

AT-30533

Features

•High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation

•900 MHz Performance:

AT-30511:1.1dB NF, 16 dB GA AT-30533:1.1dB NF, 13 dB GA

•Characterized for End-Of- Life Battery Use (2.7 V)

•SOT-23 and SOT-143 SMT Plastic Packages

•Tape-And-Reel Packaging Option Available[1]

Outline Drawing

EMITTER COLLECTOR

305

BASE EMITTER

SOT-143 (AT-30511)

COLLECTOR

305

BASE EMITTER

SOT-23 (AT-30533)

Note:

1.Refer to “Tape-and-Reel Packaging for Semiconductor Devices”.

Description

Hewlett-Packard’s AT-30511 and AT-30533 are high performance NPN bipolar transistors that have been optimized for maximum fT at low voltage operation, making them ideal for use in battery powered applications in wireless markets. The AT-30533 uses the 3 lead SOT-23, while the AT-30511 places the same die in the higher performance 4 lead SOT-143. Both packages are industry standard, and compatible with high volume surface mount assembly techniques.

The 3.2 micron emitter-to-emitter pitch and reduced parasitic design of these transistors yields extremely high performance products that can perform a multiplicity of tasks. The 5 emitter finger interdigitated geometry yields an extremely fast transistor with high gain and low operating currents.

Optimized performance at 2.7 V makes these devices ideal for use in 900 MHz, 1.8 GHz, and 2.4 GHz battery operated systems as an LNA, gain stage, buffer, oscillator, or active mixer. Typical amplifier designs at 900 MHz yield 1.3 dB noise figures with 13 dB or more associated gain at a 2.7 V, 1 mA bias. Voltage breakdowns are high enough for use at 5 volts. High gain capability at 1 V, 1 mA makes these devices a good fit for

900Ê MHzpagerapplications.

The AT-3 series bipolar transistors are fabricated using an optimized version of HewlettPackard’s

10Ê GHz f, 30 GHz f	MAX	Self-
T

Aligned-Transistor (SAT) process. The die are nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, selfalignment techniques, and gold metalization in the fabrication of these devices.

4-23	5965-8918E

AT-30511, AT-30533 Absolute Maximum Ratings

Symbol	Parameter	Units	Absolute Maximum[1]		Thermal Resistance[2]:
VEBO	Emitter-Base Voltage	V	1.5		θjc =550°C/W
VCBO	Collector-Base Voltage	V	11
VCEO	Collector-Emitter Voltage	V	5.5
IC	Collector Current	mA	8
PT	Power Dissipation[2] [3]	mW	100
Tj	Junction Temperature	°C	150
TSTG	Storage Temperature	°C	-65to150

Notes:

1.Operation of this device above any one of these parameters may cause permanent damage.

2.TMounting Surface = 25°C.

3.Derate at 1.82 mW/°C for TC > 95°C.

Electrical Specifications, TA = 25°C

AT-30511

AT-30533

Symbol

Parameters and Test Conditions

Units

Min

Typ

Max

Min

Typ

Max

NF

Noise Figure

1.1[1]

1.4[1]

1.1[2]

1.4[2]

VCE = 2.7 V, IC = 1 mA

f=0.9GHz

dB

GA

Associated Gain

14[1]

16[1]

11[2]

13[2]

VCE = 2.7 V, IC = 1 mA

f=0.9GHz

dB

hFE

Forward Current

VCE =2.7V

-

70

300

70

300

Transfer Ratio

IC = 1 mA

ICBO

Collector Cutoff Current

VCB = 3 V

μA

0.03

0.2

0.03

0.2

IEBO

Emitter Cutoff Current

VEB = 1 V

μA

0.1

1.5

0.1

1.5

Notes:

1.Test circuit B, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.

2.Test circuit A, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.

VBB

VCC 25 Ω

W = 10

L = 1860

W = 10 L = 1860

1000 pF

1000 pF

W = 10 L = 1000

W = 30

W = 30 L = 100

W = 10 L = 1025

L = 100

TEST CIRCUIT

TEST CIRCUIT A: W = 20

L = 100

BOARD MATL = 0.062" FR-4 (ε = 4.8)

TEST CIRCUIT B: W = 20

L = 200 x 2

DIMENSIONS IN MILS

NOT TO SCALE

Figure 1. Test Circuit for Noise Figure and Associated Gain. This Circuit is a

Compromise Match Between Best Noise Figure, Best Gain, Stability, a Practical,

Synthesizable Match, and a Circuit Capable of Matching Both the AT-305 and

AT-310 Geometries.

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AT-30511, AT-30533 Characterization Information, TA = 25°C

				AT-30511	AT-30533
Symbol	Parameters and Test Conditions		Units	Typ	Typ
P1dB	Power at 1 dB Gain Compression (opt tuning)
	VCE = 2.7 V, IC = 5 mA	f=0.9GHz	dBm	7	7
G1dB	Gain at 1 dB Gain Compression (opt tuning)
	VCE = 2.7 V, IC = 5 mA	f=0.9GHz	dB	16.5	15
IP3	Output Third Order Intercept Point,
	VCE = 2.7 V, IC = 5 mA (opt tuning)	f = 0.9 GHz	dBm	17	17
|S21|E2	Gain in 50 Ω System; VCE = 2.7 V, IC = 1 mA	f=0.9GHz	dB	10	9
CCB	Collector-Base Capacitance	VCB = 3V, f = 1 MHz	pF	0.04	0.04

Typical Performance

	2.5
	2.0
(dB)							AMPLIFIER NF
	1.5
FIGURE
NOISE	1.0
			NF	MIN.
	0.5
												1 mA
												5 mA
	0
			0.5			1.0		1.5		2.0				2.5
	0

FREQUENCY (GHz)

Figure 2. AT-30511 and AT-30533 Minimum Noise Figure and Amplifier NF[1] vs. Frequency and Current at VCEÊ =2 .7 V.

	25
	20
			5 mA
Ga (dB)	15
	10
				1 mA
	5
	0	0.5	1.0	1.5	2.0	2.5
	0
			FREQUENCY (GHz)

Figure 3. AT-30511 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCEÊ = 2 .7 V.

	25
	20
			5 mA
Ga (dB)	15
	10
				1 mA
	5
	0	0.5	1.0	1.5	2	2.5
	0
			FREQUENCY (GHz)

Figure 4. AT-30533 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCEÊ = 2 .7 V.

	10
	8
1dB (dBm)	6	5 mA
	4
P
	2	2 mA
	0	0.5	1.0	1.5	2.0	2.5
	0
			FREQUENCY (GHz)

	25
	20
			5 mA
(dBm)	15
				2 mA
1dB
	10
G
	5
	0	0.5	1.0	1.5	2.0	2.5
	0
			FREQUENCY (GHz)

	25
	20
1dB (dBm)	15		5 mA
	10			2 mA
G
	5
	0	0.5	1.0	1.5	2.0	2.5
	0
			FREQUENCY (GHz)

Figure 5. AT-30511 and AT-30533 Power at 1 dB Gain Compression vs. Frequency and Current at VCEÊ = 2.7 V.

Note:

Figure 6. AT-30511 1 dB Compressed Gain vs. Frequency and Current at VCEÊ =2.7 V.

Figure 7. AT-30533 1 dB Compressed Gain vs. Frequency and Current at VCEÊ =2.7 V.

1.Amplifier NF represents the noise figure which can be expected in a real circuit representing reasonable reflection coefficients and including circuit losses.

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