MOTOROLA SN74LS377DW, SN74LS377DWR2, SN74LS377H, SN74LS377N Datasheet
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS377/D
SN74LS377
Octal D Flip-Flop
with Enable
The SN74LS377 is an 8-bit register built using advanced Low
Power Schottky technology. This register consists of eight D-type
flip-flops with a buffered common clock and a buffered common
clock enable.
• 8-Bit High Speed Parallel Registers
• Positive Edge-Triggered D-Type Flip Flops
• Fully Buffered Common Clock and Enable Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS377N 16 Pin DIP 1440 Units/Box
SN74LS377DW 16 Pin
SOIC
DW SUFFIX
CASE 751D
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 738
20
1
20
1
SN74LS377
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Enable (Active LOW) Input
Data Inputs
Clock (Active HIGH Going Edge) Input
True Outputs
Complemented Outputs
E
D0 – D
3
CP
Q
0
– Q
3
Q0 – Q
3
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)
LOADING
PIN NAMES
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
18 17 16 15 14 13
123456
7
20 19
8
V
CC
E
Q7D7D6Q
6
D
5
Q
5
D
4
Q0D0D1Q1Q2D2D
3
910
Q
3
GND
12 11
Q
4
CP
LOGIC DIAGRAM
E
ENABLE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
CP
CLOCK
CP D
Q
14
26
7
3 84
5 9 12 16
13 17
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
18
15 19
1
11
SN74LS377
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3
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
p
20 µA VCC = MAX, VIN = 2.7 V
IIHInput HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
I
IL
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
I
OS
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
I
CC
Power Supply Current 28 mA VCC = MAX, NOTE 1
NOTE: With al l inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock.
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
f
MAX
Maximum Clock Frequency 30 40 MHz
t
PLH
t
PHL
Propagation Delay,
Clock to Output
17
18
27
27
ns
V
CC
= 5.0
V
CL = 15 pF
AC SETUP REQUIREMENTS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
W
Any Pulse Width 20 ns
t
s
Data Setup Time 20 ns
Enable Setup
Inactive — State 10 ns
VCC = 5.0 V
t
s
Time
Active — State 25 ns
t
h
Any Hold Time 5.0 ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
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