MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The 3850 group (spec. H) is the 8-bit microcomputer based on the 740 family core technology.
The 3850 group (spec. H) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.
FEATURES |
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●Basic machine-language instructions |
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●Minimum instruction execution time .................................. |
0.5 μs |
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(at 8 MHz oscillation frequency) |
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●Memory size |
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ROM ................................................................... |
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8K to 32K bytes |
RAM ................................................................. |
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512 to 1024 bytes |
●Programmable input/output ports ............................................ |
34 |
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●Interrupts ................................................. |
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14 sources, 14 vectors |
●Timers ............................................................................. |
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8 - bit 4 |
●Serial I/O1 .................... |
8-bit 1(UART or Clock-synchronized) |
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●Serial I/O2 ................................... |
8-bit 1(Clock-synchronized) |
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●PWM ............................................................................... |
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8 - bit 1 |
●A-D converter ............................................... |
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10 - bit 5 channels |
●Watchdog timer ............................................................ |
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16 - bit 1 |
●Clock generating circuit ..................................... |
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Built - in 2 circuits |
(connect to external ceramic resonator or quartz-crystal oscillator) |
●Power source voltage |
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In high-speed mode .................................................. |
4.0 to 5.5 V |
(at 8 MHz oscillation frequency) |
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In middle-speed mode ............................................... |
2.7 to 5.5 V |
(at 8 MHz oscillation frequency) |
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In low-speed mode .................................................... |
2.7 to 5.5 V |
(at 32 kHz oscillation frequency) |
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●Power dissipation |
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In high-speed mode .......................................................... |
34 mW |
(at 8 MHz oscillation frequency, at 5 V power source voltage) |
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In low-speed mode ............................................................ |
60 μW |
(at 32 kHz oscillation frequency, at 3 V power source voltage) |
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●Operating temperature range .................................... |
–20 to 85°C |
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
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VCC |
1 |
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VREF |
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2 |
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AVSS |
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P44/INT3/PWM |
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3 |
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4 |
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P43/INT2/SCMP2 |
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5 |
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P42/INT1 |
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6 |
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P41/INT0 |
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7 |
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P40/CNTR1 |
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8 |
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P27/CNTR0/SRDY1 |
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9 |
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P26/SCLK |
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10 |
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P25/TxD |
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11 |
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P24/RxD |
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12 |
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P23 |
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13 |
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P22 |
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14 |
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CNVSS |
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15 |
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P21/XCIN |
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16 |
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P20/XCOUT |
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17 |
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RESET |
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18 |
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XIN |
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19 |
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XOUT |
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20 |
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VSS |
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21 |
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XXXFP-38503M4HM XXXSP-M38503M4H
42 |
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P30/AN0 |
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P31/AN1 |
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P32/AN2 |
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P33/AN3 |
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P34/AN4 |
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P00/SIN2 |
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P01/SOUT2 |
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P02/SCLK2 |
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P03/SRDY2 |
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34 |
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P04 |
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P05 |
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P06 |
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P07 |
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P10/(LED0) |
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P11/(LED1) |
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P12/(LED2) |
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27 |
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P13/(LED3) |
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P14/(LED4) |
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25 |
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P15/(LED5) |
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24 |
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P16/(LED6) |
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23 |
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P17/(LED7) |
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Package type : |
FP ........................... |
42P2R-A/E (42-pin plastic-molded SSOP) |
Package type : |
SP ........................... |
42P4B (42-pin plastic-molded SDIP) |
Fig. 1 M38503M4H-XXXFP/SP pin configuration
2 |
diagramblockFunctional 2 .Fig |
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BLOCKFUNCTIONAL |
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FUNCTIONAL BLOCK DIAGRAM |
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Main-clock |
Main-clock |
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Reset input |
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input |
output |
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CNVSS |
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XIN |
XOUT |
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VSS |
VCC |
RESET |
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19 |
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21 |
1 |
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15 |
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Sub-clock Sub-clock |
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input |
output |
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XCIN |
XCOUT |
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Clock generating circuit |
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Timer |
1( 8 ) |
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Prescaler |
12(8) |
Timer |
2( 8 ) |
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Prescaler |
X(8) |
Timer |
X( 8 ) |
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CNTR0 |
Prescaler |
Y(8) |
Timer |
Y( 8 ) |
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Watchdog |
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Reset |
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timer |
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CNTR1 |
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A-D |
PWM |
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SI/O1(8) |
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SI/O2(8) |
SINGLE |
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converter |
(8) |
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(10) |
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XCOUT |
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XCIN |
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MICROCOMPUTERCMOSBIT-8CHIP- |
H).(SpecGroup3850 |
MICROCOMPUTERSMITSUBISHI |
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INT0– |
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INT3 |
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P4(5) |
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P3(5) |
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P2(8) |
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P1(8) |
P0(8) |
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2 |
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5 |
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7 |
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38 39 40 41 42 |
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9 |
10 11 12 13 1416 17 |
22 23 24 25 26 27 28 29 |
30 31 32 33 34 35 36 37 |
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I/O port P4 |
I/O port P3 |
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I/O port P2 |
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I/O port P1 |
I/O port P0 |
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VREF |
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AVSS |
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MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 1 Pin description
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Pin |
Name |
Functions |
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Function except a port function |
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VCC, VSS |
Power source |
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. |
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CNVSS |
CNVSS input |
•This pin controls the operation mode of the chip. |
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•Normally connected to VSS. |
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Reset input |
•Reset input pin for active “L.” |
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RESET |
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XIN |
Clock input |
•Input and output pins for the clock generating circuit. |
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•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set |
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the oscillation frequency. |
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XOUT |
Clock output |
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT |
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pin open. |
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P00/SIN2 |
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•8-bit CMOS I/O port. |
• Serial I/O2 function pin |
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P01/SOUT2 |
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•I/O direction register allows each pin to be individually |
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P02/SCLK2 |
I/O port P0 |
programmed as either input or output. |
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•CMOS compatible input level. |
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P03/SRDY2 |
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•CMOS 3-state output structure. |
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P04–P07 |
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•P10 to P17 (8 bits) are enabled to output large current for LED drive. |
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P10–P17 |
I/O port P1 |
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P20/XCOUT |
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•8-bit CMOS I/O port. |
• Sub-clock generating circuit I/O |
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P21/XCIN |
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•I/O direction register allows each pin to be individually |
pins (connect a resonator) |
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P22 |
I/O port P2 |
programmed as either input or output. |
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P23 |
•CMOS compatible input level. |
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P24/RxD |
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•P20, P21, P24 to P27: CMOS3-state output structure. |
• Serial I/O1 function pin |
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P25/TxD |
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•P22, P23: N-channel open-drain structure. |
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P26/SCLK |
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P27/CNTR0/ |
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• Serial I/O1 function pin/ |
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SRDY1 |
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Timer X function pin |
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P30/AN0– |
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•8-bit CMOS I/O port with the same function as port P0. |
• A-D converter input pin |
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I/O port P3 |
•CMOS compatible input level. |
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P34/AN4 |
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•CMOS 3-state output structure. |
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P40/CNTR1 |
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•8-bit CMOS I/O port with the same function as port P0. |
• Timer Y function pin |
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P41/INT0 |
I/O port P4 |
•CMOS compatible input level. |
• Interrupt input pins |
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P42/INT1 |
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•CMOS 3-state output structure. |
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P43/INT2/SCMP2 |
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• Interrupt input pin |
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• SCMP2 output pin |
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P44/INT3/PWM |
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• Interrupt input pin |
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• PWM output pin |
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3
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Product name |
M3850 3 M 4 H– XXX SP |
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Package type
SP : 42P4B
FP : 42P2R-A/E
SS : 42S1B-A
ROM number
Omitted in One Time PROM version shipped in blank,
EPROM version, and flash memory version.
– : standard
Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version.
H–: Partial specification changed version
ROM/PROM/Flash memory size
1 |
: 4096 bytes |
9 : 36864 bytes |
2 |
: 8192 bytes |
A : 40960 bytes |
3 |
: 12288 bytes |
B : 45056 bytes |
4 |
: 16384 bytes |
C : 49152 bytes |
5 |
: 20480 bytes |
D : 53248 bytes |
6 |
: 24576 bytes |
E : 57344 bytes |
7 |
: 28672 bytes |
F : 61440 bytes |
8 |
: 32768 bytes |
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The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version, so that the users can use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size |
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0 : 192 bytes |
5 |
: 768 bytes |
1 : 256 bytes |
6 |
: 896 bytes |
2 : 384 bytes |
7 |
: 1024 bytes |
3 : 512 bytes |
8 |
: 1536 bytes |
4 : 640 bytes |
9 |
: 2048 bytes |
Fig. 3 Part numbering
4
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mitsubishi plans to expand the 3850 group (spec. H) as follows.
Support for mask ROM, One Time PROM, and flash memory versions.
42P4B ......................................... |
42-pin shrink plastic-molded DIP |
42P2R-A/E ........................................... |
42-pin plastic-molded SOP |
42S1B-A .................. |
42-pin shrink ceramic DIP (EPROM version) |
Flash memory size ......................................................... |
32 |
K bytes |
One Time PROM size ..................................................... |
24 |
K bytes |
Mask ROM size ................................................... |
8 K to 32 |
K bytes |
RAM size ............................................................... |
512 to 1 |
K bytes |
ROM size (bytes)
As of Feb. 2000
ROM |
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exteranal |
Under development |
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32K |
M38507M8/F8 |
28K |
Mass production |
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24K |
M38504M6/E6 |
20K
Mass production
16K M38503M4H
12K
Mass production
8K M38503M2H
384 |
512 |
640 |
768 |
896 |
1024 |
1152 |
1280 |
1408 |
1536 |
2048 |
RAM size (bytes)
Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped.
Fig. 4 Memory expansion plan
5
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Currently planning products are listed below.
Table 2 Support products |
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As of Feb. 2000 |
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Product name |
ROM size (bytes) |
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RAM size (bytes) |
Package |
Remarks |
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ROM size for User in ( |
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M38503M2H-XXXSP |
8192 |
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512 |
42P4B |
Mask ROM version |
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M38503M2H-XXXFP |
(8062) |
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42P2R-A/E |
Mask ROM version |
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M38503M4H-XXXSP |
16384 |
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512 |
424P4B |
Mask ROM version |
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M38503M4H-XXXFP |
(16254) |
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42P2R-A/E |
Mask ROM version |
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M38504M6-XXXSP |
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Mask ROM version |
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M38504E6-XXXSP |
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424P4B |
One Time PROM version |
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M388504E6SP |
24576 |
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One Time PROM version (blank) |
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M388504E6SS |
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640 |
42S1B-A |
EPROM version |
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(24446) |
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M38504M6-XXXFP |
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Mask ROM version |
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M38504E6-XXXFP |
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42P2R-A/E |
One Time PROM version |
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M38504E6FP |
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One Time PROM version (blank) |
Table 3 3850 group (standard) and 3850 group (spec. H)
3850 group (standard) |
3850 group (spec. H) |
M38503M2-XXXFP/SP |
M38503M2H-XXXFP/SP |
M38503M4-XXXFP/SP |
M38503M4H-XXXFP/SP |
M38503E4-XXXFP/SP |
M38504M6-XXXFP/SP |
M38503E4FP/SP |
M38504E6-XXXFP/SP |
M38503E4SS |
M38504E6FP/SP |
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M38504E6SS |
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M38507M8-XXXFP/SP |
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M38507F8FP/SP |
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Table 4 Differences between 3850 group (standard) and 3850 group (spec. H)
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3850 group (standard) |
3850 group (spec. H) |
Serial I/O |
1: Serial I/O (UART or Clock-synchronized) |
2: Serial I/O1 (UART or Clock-synchronized) |
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Serial I/O2 (Clock-synchronized) |
A-D converter |
Unserviceable in low-speed mode |
Serviceable in low-speed mode |
Large current port |
5: P13–P17 |
8: P10–P17 |
Notes on differences between 3850 group (standard) and 3850 group (spec. H)
(1)The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2)The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H).
(3)Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.)
(4)Fix bit 3 of the CPU mode register to “1”.
(5)Be sure to perform the termination of unused pins.
6
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
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b7 |
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b0 |
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A |
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Accumulator |
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b7 |
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b0 |
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X |
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Index register X |
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b7 |
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b0 |
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Y |
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Index register Y |
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b7 |
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b0 |
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S |
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Stack pointer |
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b15 |
b7 |
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b0 |
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PCH |
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PCL |
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Program counter |
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b7 |
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b0 |
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N |
V |
T |
B |
D |
I |
Z |
C |
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Processor status register (PS) |
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Carry flag |
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Zero flag |
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Interrupt disable flag |
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Decimal mode flag |
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Break flag |
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Index X mode flag |
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Overflow flag |
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Negative flag |
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Fig. 5 740 Family CPU register structure |
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7
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request
(Note)
Execute JSR
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M (S) |
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(PCH) |
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Push return address |
(S) |
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(S) – 1 |
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on stack |
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M (S) |
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(PCL) |
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(S) |
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(S)– 1 |
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Subroutine
Execute RTS
(S) (S) + 1
POP return
address from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
M(S) (PCH)
(S)(S) – 1
M (S) (PCL)
(S) (S) – 1
M (S)(PS)
(S) (S) – 1
Interrupt
Service Routine
Execute RTI
Push return address on stack
Push contents of processor status register on stack
I Flag is set from “0” to “1” Fetch the jump vector
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(S) |
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(S) + 1 |
POP contents of |
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processor status |
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(PS) |
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M (S) |
register from stack |
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(S) |
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(S) + 1 |
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(PCL) |
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M (S) |
POP return |
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address |
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(S) |
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(S) + 1 |
from stack |
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(PCH) |
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M (S) |
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Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
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Push instruction to stack |
Pop instruction from stack |
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Accumulator |
PHA |
PLA |
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Processor status register |
PHP |
PLP |
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8
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)] |
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•Bit 4: Break flag (B) |
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The B flag is used to indicate that the current interrupt was |
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The processor status register is an 8-bit register consisting of 5 |
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generated by the BRK instruction. The BRK flag in the processor |
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flags which indicate the status of the processor after an arithmetic |
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status register is always “0”. When the BRK instruction is used to |
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operation and 3 flags which decide MCU operation. Branch opera- |
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generate an interrupt, the processor status register is pushed |
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tions can be performed by testing the Carry (C) flag , Zero (Z) flag, |
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onto the stack with the break flag set to “1”. |
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Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, |
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•Bit 5: Index X mode flag (T) |
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V, N flags are not valid. |
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When the T flag is “0”, arithmetic operations are performed |
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•Bit 0: Carry flag (C) |
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between accumulator and memory. When the T flag is “1”, direct |
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The C flag contains a carry or borrow generated by the arithmetic |
arithmetic operations and direct data transfers are enabled |
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logic unit (ALU) immediately after an arithmetic operation. It can |
between memory locations. |
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also be changed by a shift or rotate instruction. |
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•Bit 6: Overflow flag (V) |
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•Bit 1: Zero flag (Z) |
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The V flag is used during the addition or subtraction of one byte |
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The Z flag is set if the result of an immediate arithmetic operation |
of signed data. It is set if the result exceeds +127 to -128. When |
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or a data transfer is “0”, and cleared if the result is anything other |
the BIT instruction is executed, bit 6 of the memory location |
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than “0”. |
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operated on by the BIT instruction is stored in the overflow flag. |
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•Bit 2: Interrupt disable flag (I) |
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•Bit 7: Negative flag (N) |
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The I flag disables all interrupts except for the interrupt |
The N flag is set if the result of an arithmetic operation or data |
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generated by the BRK instruction. |
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transfer is negative. When the BIT instruction is executed, bit 7 of |
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Interrupts are disabled when the I flag is “1”. |
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the memory location operated on by the BIT instruction is stored |
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•Bit 3: Decimal mode flag (D) |
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in the negative flag. |
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The D flag determines whether additions and subtractions are |
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executed in binary or decimal. Binary arithmetic is executed when |
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this flag is “0”; decimal arithmetic is executed when it is “1”. |
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Decimal correction is automatic in decimal mode. Only the ADC |
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and SBC instructions can be used for decimal arithmetic. |
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Table 6 Set and clear instructions of each bit of processor status register |
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C flag |
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Z flag |
I flag |
D flag |
B flag |
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T flag |
V flag |
N flag |
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Set instruction |
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SEC |
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SEI |
SED |
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SET |
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Clear instruction |
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CLC |
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CLI |
CLD |
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CLT |
CLV |
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9
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7 |
b0 |
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 |
b0 |
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0 |
0 |
: Single-chip mode |
0 |
1 |
: |
1 |
0 |
: Not available |
1 |
1 |
: |
Stack page selection bit 0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit 0 : Oscillating
1 : Stopped
Main clock division ratio selection bits b7 b6
0 0 : φ = f(XIN)/2 (high-speed mode)
0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available
Fig. 7 Structure of CPU mode register
10
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MITSUBISHI MICROCOMPUTERS |
|||
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3850 Group (Spec. H) |
|||
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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MEMORY |
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Zero Page |
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Special Function Register (SFR) Area |
Access to this area with only 2 bytes is possible in the zero page |
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The Special Function Register area in the zero page contains |
addressing mode. |
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control registers such as I/O ports and timers. |
Special Page |
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RAM |
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Access to this area with only 2 bytes is possible in the special |
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RAM is used for data storage and for stack area of subroutine |
page addressing mode. |
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calls and interrupts. |
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ROM |
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The first 128 bytes and the last 2 bytes of ROM are reserved for |
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device testing and the rest is user area for storing programs. |
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Interrupt Vector Area |
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The interrupt vector area contains reset and interrupt vectors. |
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RAM area |
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RAM size |
Address |
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000016 |
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(bytes) |
XXXX16 |
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SFR area |
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192 |
00FF16 |
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Zero page |
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256 |
013F16 |
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004016 |
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384 |
01BF16 |
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010016 |
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512 |
023F16 |
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RAM |
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640 |
02BF16 |
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768 |
033F16 |
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896 |
03BF16 |
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XXXX16 |
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1024 |
043F16 |
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Not used |
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1536 |
063F16 |
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2048 |
083F16 |
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0FF016 |
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SFR area (Note) |
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0FFF16 |
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Not used |
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ROM area |
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YYYY16 |
Reserved ROM area |
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ROM size |
Address |
Address |
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(128 bytes) |
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(bytes) |
YYYY16 |
ZZZZ16 |
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ZZZZ16 |
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4096 |
F00016 |
F08016 |
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8192 |
E00016 |
E08016 |
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12288 |
D00016 |
D08016 |
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16384 |
C00016 |
C08016 |
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ROM |
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20480 |
B00016 |
B08016 |
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24576 |
A00016 |
A08016 |
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FF0016 |
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28672 |
900016 |
908016 |
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32768 |
800016 |
808016 |
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FFDC16 |
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36864 |
700016 |
708016 |
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Interrupt vector area |
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Special page |
|
40960 |
600016 |
608016 |
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45056 |
500016 |
508016 |
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FFFE16 |
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49152 |
400016 |
408016 |
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Reserved ROM area |
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FFFF16 |
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53248 |
300016 |
308016 |
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57344 |
200016 |
208016 |
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61440 |
100016 |
108016 |
|
Note: Flash memory version only |
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Fig. 8 Memory map diagram |
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11
000016 |
Port P0 (P0) |
002016 |
Prescaler 12 (PRE12) |
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|
000116 |
Port P0 direction register (P0D) |
002116 |
Timer 1 (T1) |
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|
000216 |
Port P1 (P1) |
002216 |
Timer 2 (T2) |
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|
000316 |
Port P1 direction register (P1D) |
002316 |
Timer XY mode register (TM) |
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|
000416 |
Port P2 (P2) |
002416 |
Prescaler X (PREX) |
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|
000516 |
Port P2 direction register (P2D) |
002516 |
Timer X (TX) |
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|
000616 |
Port P3 (P3) |
002616 |
Prescaler Y (PREY) |
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|
000716 |
Port P3 direction register (P3D) |
002716 |
Timer Y (TY) |
|
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000816 |
Port P4 (P4) |
002816 |
Timer count source selection register (TCSS) |
|
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|
000916 |
Port P4 direction register (P4D) |
002916 |
|
000A16 |
|
002A16 |
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||
000B16 |
|
002B16 |
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Reserved |
||
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000C16 |
|
002C16 |
Reserved |
000D16 |
|
002D16 |
|
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Reserved |
||
000E16 |
|
002E16 |
|
|
Reserved |
||
000F16 |
|
002F16 |
|
|
Reserved |
||
001016 |
|
003016 |
|
|
Reserved |
||
001116 |
|
003116 |
|
|
Reserved |
||
001216 |
|
003216 |
|
Reserved |
|
||
001316 |
|
003316 |
|
Reserved |
|
||
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001416 |
Reserved |
003416 |
A-D control register (ADCON) |
|
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|
001516 |
Serial I/O2 control register 1 (SIO2CON1) |
003516 |
A-D conversion low-order register (ADL) |
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001616 |
Serial I/O2 control register 2 (SIO2CON2) |
003616 |
A-D conversion high-order register (ADH) |
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|
001716 |
Serial I/O2 register (SIO2) |
003716 |
Reserved |
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|
001816 |
Transmit/Receive buffer register (TB/RB) |
003816 |
MISRG |
|
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|
001916 |
Serial I/O1 status register (SIOSTS) |
003916 |
Watchdog timer control register (WDTCON) |
|
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|
001A16 |
Serial I/O1 control register (SIOCON) |
003A16 |
Interrupt edge selection register (INTEDGE) |
|
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|
|
001B16 |
UART control register (UARTCON) |
003B16 |
CPU mode register (CPUM) |
|
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|
|
001C16 |
Baud rate generator (BRG) |
003C16 |
Interrupt request register 1 (IREQ1) |
|
|
|
|
001D16 |
PWM control register (PWMCON) |
003D16 |
Interrupt request register 2 (IREQ2) |
|
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|
001E16 |
PWM prescaler (PREPWM) |
003E16 |
Interrupt control register 1 (ICON1) |
|
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|
001F16 |
PWM register (PWM) |
003F16 |
Interrupt control register 2 (ICON2) |
|
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|
|
Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 9 Memory map of special function register (SFR)
12
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.
Table 5 I/O port function
|
Pin |
Name |
Input/Output |
I/O Structure |
Non-Port Function |
Related SFRs |
Ref.No. |
|||
P00/SIN2 |
|
|
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|
|
(1) |
||||
P01/SOUT2 |
|
|
|
Serial I/O2 function I/O |
Serial I/O2 control |
(2) |
||||
P02/SCLK2 |
Port P0 |
|
|
register |
(3) |
|||||
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|
||||||||
|
CMOS compatible |
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|||||||
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(4) |
|
P03/SRDY2 |
|
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|
||||||
|
|
input level |
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|
||||||
P04–P07 |
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|||||
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CMOS 3-state output |
|
|
(5) |
|||||
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P10–P17 |
Port P1 |
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|||||
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||||||
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P20/XCOUT |
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|
|
Sub-clock generating |
CPU mode register |
(6) |
||||
P21/XCIN |
|
|
|
circuit |
(7) |
|||||
|
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|
|||||||
P22 |
|
|
CMOS compatible |
|
|
|
||||
|
|
input level |
|
|
(8) |
|||||
P23 |
|
|
|
|
||||||
|
|
N-channel open-drain |
|
|
||||||
Port P2 |
|
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||||||
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output |
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Input/output, |
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|
P24/RxD |
|
|
|
|
(9) |
|||||
|
individual |
|
Serial I/O1 function I/O |
Serial I/O1 control |
||||||
|
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|
|
(10) |
|||
P25/TxD |
|
bits |
|
register |
||||||
|
|
|
||||||||
|
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|
||
P26/SCLK |
|
|
|
Serial I/O1 function I/O |
Serial I/O1 control |
(11) |
||||
|
|
|
|
|
|
|
|
|
register |
|
|
|
|
|
|
|
|
|
Serial I/O1 function I/O |
Serial I/O1 control |
(12) |
P27/CNTR0/SRDY1 |
|
|
CMOS compatible |
register |
||||||
|
|
Timer X function I/O |
||||||||
|
|
|
|
|
|
|
Timer XY mode register |
|
||
|
|
|
|
|
|
|
input level |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P30/AN0– |
Port P3 |
|
CMOS 3-state output |
A-D conversion input |
|
(13) |
||||
|
|
A-D control register |
||||||||
P34/AN4 |
|
|
||||||||
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
||
P40/CNTR1 |
|
|
|
Timer Y function I/O |
Timer XY mode register |
(14) |
||||
P41/INT0 |
|
|
|
External interrupt input |
Interrupt edge selection |
(15) |
||||
P42/INT1 |
|
|
|
register |
||||||
Port P4 |
|
|
|
|
||||||
|
|
|
|
|
||||||
P43/INT2/SCMP2 |
|
|
External interrupt input |
Interrupt edge selection |
|
|||||
|
|
|
|
|||||||
|
|
|
register |
(16) |
||||||
|
|
|
SCMP2 output |
|||||||
|
|
|
|
|
|
|
|
Serial I/O2 control register |
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
P44/INT3/PWM |
|
|
|
External interrupt input |
Interrupt edge selection |
(17) |
||||
|
|
|
register |
|||||||
|
|
|
PWM output |
|||||||
|
|
|
|
|
|
|
|
PWM control register |
|
|
|
|
|
|
|
|
|
|
|
|
|
13
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P00 |
|
|
Direction |
|
register |
Data bus |
Port latch |
Serial I/O2 input
(2) Port P01
P01/SOUT2 P-channel output disable bit
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
|
Direction |
|
register |
Data bus |
Port latch |
Serial I/O2 output
(3) Port P02 |
|
|
|
(4) Port P03 |
|
P02/SCLK2 P-channel output disable bit |
|
|
Serial I/O2 synchronous |
SRDY2 output enable bit |
|
|
clock selection bit |
Direction |
Serial I/O2 port selection bit |
||
|
Direction |
register |
|
register |
|
|
Data bus |
Port latch |
Data bus |
Port latch |
|
|
Serial I/O2 ready output |
|
Serial I/O2 clock output |
|
|
|
Serial I/O2 external clock input |
|
(5) Ports P04-P07,P1
|
Direction |
|
register |
Data bus |
Port latch |
(7) Port P21
Port XC switch bit
Direction register
Data bus Port latch
Sub-clock generating circuit input
(6) Port P20
Port XC switch bit
Direction register
Data bus Port latch
Oscillator
Port P21
Port XC switch bit
(8) Ports P22,P23
|
Direction |
|
register |
Data bus |
Port latch |
Fig. 10 Port block diagram (1)
14
|
|
MITSUBISHI MICROCOMPUTERS |
|
|
3850 Group (Spec. H) |
|
|
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
|
|
|
|
|
|
(9) Port P24 |
|
(10) Port P25 |
Serial I/O1 enable bit |
|
|
|
|
|
Receive enable bit |
|
P-channel output disable bit |
|
|
Direction |
Serial I/O1 enable bit |
|
Transmit enable bit |
|
|
register |
|
|
|
|
|
|
Direction |
Data bus |
Port latch |
register |
Data bus Port latch
Serial I/O1 input
(11) Port P26
Serial I/O1 synchronous clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit |
|
Serial I/O1 enable bit |
|
|
Direction |
|
register |
Data bus |
Port latch |
|
Serial I/O1 clock output |
|
External clock input |
(13) Ports P30-P34 |
|
Direction |
|
register |
Data bus |
Port latch |
|
A-D converter input |
|
Analog input pin selection bit |
Serial I/O1 output
(12) Port P27
Pulse output mode
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit |
|
|
Direction |
|
register |
Data bus |
Port latch |
Pulse output mode
Serial ready output
Timer output
CNTR0 interrupt input
(14) Port P40 |
|
|
Direction |
|
register |
Data bus |
Port latch |
Pulse output mode Timer output
CNTR1 interrupt input
|
(16) Port P43 |
(15) Ports P41,P42 |
Serial I/O2 I/O |
|
comparison signal control bit |
|
Direction |
|
register |
Data bus |
Port latch |
Direction register
Data bus Port latch
Interrupt input |
|
Serial I/O2 I/O |
|
||
|
|
comparison signal output |
Interrupt input
Fig. 11 Port block diagram (2)
15
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port P44 |
|
|
PWM output enable bit |
|
Direction |
|
register |
Data bus |
Port latch |
|
PWM output |
|
Interrupt input |
Fig. 12 Port block diagram (3)
16