iMAC G5 IMG5 20 MLB 051-6863 RevF
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TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD
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ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPD
ENG
DATE
APPD
CK
ECN
ZONE
REV
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
D
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OF
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
TABLE_TABLEOFCONTENTS_ITEM
11/01/05
IMG5 20" REV F
FINO-M23
Vesta Core / Misc
17
08/26/2005
14
FINO-M23
5V & 3.3V Fets
16
08/26/2005
13
FINO-M23
2.5V Vreg
15
08/26/2005
12
FINO-M23
1.2V Vreg
13
08/26/2005
11
FINO-M23
1.5V Vreg
12
10/07/2005
10
M33-PC
1.8V VREG
11
06/20/2005
9
FINO-M23
FUNC TEST 2 OF 2
9
08/26/2005
8
FINO-M23
Signal Alias
8
08/29/2005
7
M33-PC
POWER CONN / ALIAS
7
06/20/2005
6
FINO-M23
FUNC TEST 1 OF 2
6
08/26/2005
5
FINO-M23
Power Block Diagram
4
08/26/2005
3
130
08/26/2005
FINO-M23
73
ENET SERIES TERM
129
06/20/2005
M33-DC
72
Disk Connectors
127
06/20/2005
M33-DC
71
Shasta Disk
125
08/26/2005
Q63
70
BootROM
122
08/26/2005
Q63
69
USB 2.0 PCI Interface
121
08/26/2005
FINO-M23
68
AIRPORT & BLUETOOTH
120
08/26/2005
FINO-M23
67
PCI SERIES TERMINATION
119
08/26/2005
Q63
66
Shasta PCI Interface
103
08/26/2005
Q63
65
Shasta HyperTransport
101
08/26/2005
FINO-M23
64
HT ALIASES
FINO-M23
KODIAK & SHASTA MISC
20
08/26/2005
16
98
08/26/2005
Q63
63
KODIAK HT16
Q63
KODIAK CORE & BYPASS
19
08/26/2005
15
FINO-M23
CPU VCORE MORE BYPASS
52
08/26/2005
37
M33-HS
CPU VCORE VREG
50
06/20/2005
36
FINO-M23
PROC DECOUPLING
49
08/26/2005
35
FINO-M23
CPU POWER AND BYPASS
48
08/26/2005
34
FINO-M23
CPU STRAPS
47
08/26/2005
33
Q63
KODIAK EI B
44
08/26/2005
32
FINO-M23
CPU EI AND IO
43
08/26/2005
31
Q63
KODIAK EI A
42
08/26/2005
30
Q63
KODIAK EI PWR & CAPS
41
08/26/2005
29
FINO-M23
I2C Connections
39
08/26/2005
28
M33-HS
Fan 2 & HD Temp
33
08/04/2005
27
FINO-M23
Fan 0, 1 & System Temp
32
08/26/2005
26
FINO-M23
SMU SUPPLEMENTAL (4)
31
08/26/2005
25
FINO-M23
SMU SUPPLEMENTAL (3)
30
09/20/2005
24
FINO-M23
SMU SUPPLEMENTAL (2)
29
09/20/2005
23
Q63
System Management Unit
28
08/26/2005
22
FINO-M23
Pulsar Aliases
27
08/26/2005
21
FINO-M23
PULSAR2 CLOCKS
26
08/26/2005
20
Q63
PULSAR2 POWER
25
08/26/2005
19
FINO-M23
Shasta Serial / Misc
24
08/26/2005
18
Q63
Shasta Core Power
23
08/26/2005
17
96
06/20/2005
M33-DD
61
TMDS / ExtVGA
AUDIO: LINE INPUT AMP
85
FINO-SO
10/07/2005
148
AUDIO: CODEC
84
FINO-SO
10/07/2005
147
Flash Connector
83
FINO-M23
09/27/2005
145
Flash Media Ctrl
82
FINO-M23
09/27/2005
144
USB Device Interfaces
81
FINO-M23
09/20/2005
143
USB Host Interfaces
80
FINO-M23
08/26/2005
142
FIREWIRE CONNECTORS
79
FINO-M23
08/26/2005
140
Vesta FireWire PHY
78
Q63
08/26/2005
139
Shasta FireWire
77
Q63
08/26/2005
138
ETHERNET CONNECTOR
76
FINO-M23
08/26/2005
136
Vesta Ethernet PHY
75
Q63
08/26/2005
132
54
10/07/2005
FINO-M23
38
CPU AVDD VREG
DATE
SYNC MASTER
CONTENTS
PDF CSA
CONTENTS
DATE
SYNC MASTER
PDF CSADATECSAPDF
SYNC MASTER
CONTENTS
Shasta Ethernet
74
Q63
08/26/2005
131
FINO-M23
Table Items
5
10/07/2005
4
68
08/26/2005
FINO-M23
47
MLB Mem Series Term
82
08/26/2005
Q63
50
KODIAK PCI-E X16
63
08/26/2005
FINO-M23
45
MEMORY ADDR BRANCHING
FINO-M23
System Block Diagram
2
08/26/2005
2
SCH,MLB,IMG5,20
051-6863
F
PRODUCTION RELEASED
408133
11/01/05
?
1
154
F
AUDIO: LINE OUT AMP
86
FINO-SO
10/07/2005
150
93
10/07/2005
FINO-M23
60
GPU DVI & DACs
92
08/26/2005
FINO-M23
59
GPU Straps
91
06/20/2005
M33-DD
58
FB Parallel Termination
90
10/07/2005
FINO-M23
57
GPU GDDR SDRAM B
89
10/07/2005
FINO-M23
56
GPU GDDR SDRAM A
88
08/26/2005
FINO-M23
55
FB Series Termination
87
10/07/2005
FINO-M23
54
GPU Frame Buffer
86
10/07/2005
FINO-M23
53
GPU Core Power
85
06/20/2005
M33-DD
52
Graphics Vregs
84
08/18/2005
FINO-M23
51
GPU PCIe
70
08/26/2005
FINO-M23
49
On-Board DDR SDRAM
69
08/26/2005
FINO-M23
48
On-Board DDR SDRAM
67
08/26/2005
FINO-M23
46
Memory Dimm A
62
08/26/2005
FINO-M23
44
Main Memory Clock Buffer
61
08/26/2005
FINO-M23
43
Parallel Term
59
08/26/2005
FINO-M23
42
Kodiak Memory Dq/Ctl
58
08/26/2005
Q63
41
KODIAC NBMEM PWR & CAPS
56
08/26/2005
FINO-M23
40
CPU ALIASES & MISC
55
08/29/2005
FINO-M23
39
T,V,I SENSORS
97
08/26/2005
FINO-M23
62
KODIAK PCI-E CONST
AUDIO: POWER SUPPLIES
89
FINO-SO
10/07/2005
154
AUDIO: CONNECTORS
88
FINO-SO
10/07/2005
153
AUDIO: SPEAKER AMP
87
FINO-SO
10/07/2005
152
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PAGES 29,30
SMU SUPPLEMENTAL
U2801
RTC
PAGE 28
BATTERY
SYSTEM LED
ALS
BUTTONS
TEMP SENSORS
PAGE 28
SMU
U2800
PAGES 32,33
FANS
UE400
FLASH
667MHZ OR 733MHZ
JF303
PAGE 153
PAGE 153
JF301
PAGE 150
PAGE 152
JF300
PAGE 153
PAGE 148
PAGE 147
UE700
INTERFACE
BNDI
JEC00, JEC01
JD600
PAGE 136 PAGE 140
PAGE 139PAGE 132
U1701
PAGE 142
PAGE 127
PAGE 131 PAGE 138
PAGE 24
PAGE 24
PAGE 119
PAGE 103
PAGE 127
JC901
PAGE 129
PAGE 129
JC900
PAGE 142
UC200
UC500
PAGE 125 PAGE 122 PAGE 121
JC150
PAGE 145
PAGE 144
JE500
CF
CTLR
SD
MEDIA CARD CONNECTOR
UE401
PAGE 144
USB
HUB
PAGE 143 PAGE 143
JE350
JE310/JE320/JE330
PAGES 67,70
PAGES 68
J6700
PAGE 67
PAGE 61
ELASTIC INTERFACE
PARALLEL
U6200
64-BIT
PAGE 62
PAGE 39
PAGE 26PAGE 25
U2500
EXT VGA
TMDS
PAGE 96
PAGE 90
U9000, U9001
PAGE 89
U8900, U8901
M33:1.8V/700MHZ
M33:1.8V/700MHZ
M23:1.8V/600MHZ
M23:1.8V/600MHZ
M33:RV380 XT
PAGES 84,86,87,93
U8400
U1900
PAGE 19
PAGE 59
PAGE 98PAGE 20
82
PAGE 42
PAGE 43,48
U4300
GPU
TERM
DIMM
64MX8
MEMORY
SERIES
MAIN MEMORY
TERM
PCIE X16
MAIN MEMORY
1.8V/533MHZ
64-BIT
FRAME BUFFER
I2C
SATA
CONNECTOR
PCIE
KODIAK
PAGE
NEO 10S
CPU
HYPERTRANSPORT
HYPERTRANSPORT
CORE
CONTROL = 2.5V
HYPERTRANSPORT
8-BIT
APPLE PI
32-BIT
APPLE PI
BUFFER B
64-BIT
FRAME
BUFFER A
FRAME
MISC
SATA
U2300
SATA1 SATA2
1.2V/1.5GHZ
SATA/150
UATA/133
UATA
UATA
3.3V/133MHZ
CONNECTOR
PCI
GPIO/PCI64
CORE
PAGE 23
ETHERNET FIREWIRE
I2S2I2S0
I2S
I2S1
SCCA SCCB
8-bit TX/RX
2 Diff pairs
1
FIREWIRE A
0
GMII (3.3V/125MHz)
8-bit TX & 8-bit RX
CONNECTOR
4 Diff pairs
CLOCKS
POWER
ETHERNET
CONNECTORS
32-bit PCI (5V-3.3V/33MHz)
AMP
SPEAKER
CONNECTOR
COMBO OUT
OPTICAL OUT
LINE OUT
SPEAKER
CONNECTOR
LINE IN
CONNECTOR
LINE IN
AMP
AUDIO CODEC
AMP
LINE OUT
1394 OHCI (3.3V/98MHz)
S/PDIF
NCs
FRAME BUFFER
1.2V/800MHZ
PCM3052A
FIREWIRE A
GIG ETHERNET
SHASTA
VESTA
HARD DRIVE
OPTICAL
5
USB
321
uPD720101
PCI
BOOTROM
CONNECTOR
PULSAR2
CLOCK
BUFFER
ONBOARD MEMORY
4
WIRELESS
USB 2.0
USB
INTERFACE
BNDI
CONNECTORS
J9602, J9603
M23:RV370 XT
2.5GHZ
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
System Block Diagram
154
051-6863
F
2
IN
IN
GND
V+
LM339A
GND
V+
LM339A
IN
GND
V+
LM339A
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
HT BUS
SWITCHER
LINEAR
PP1V8_GPU
PAGE 13
SHASTA CORE
PAGE 85
FET SWITCH
PP1V2_ALL
PCI BUS
PP3V3_RUNPP3V3_ALL
SWITCHER
SYS_POWERUP_L
PAGE 13
CPU CORE
LINEAR
GPU CORE
FET SWITCH
PP5V_ALL
PP12V_RUN
POWER SW
PP1V8_RUN
PP12V_ALL
FW CONN
AUDIO CODEC
PP5V_RUN
PAGE 7
J700
SYS_POWERUP_L
USB CONN
PP5V_PWRON
VESTA CORE
SWITCHER
PP2V5_RUN
LINEAR
PP1V8_TPVDD
POWER CONNECTOR
FET SWITCH
PP2V5_PWRON
PP1V5_RUN
PP1V5_PWRON
PAGE 12
PAGE 12
PAGE 85 PAGE 11
PAGE 50
PAGE 11
PAGE 91
PAGE 15
PAGE 16
PAGE 85
PAGE 85
PAGE 13
PP0V9_GPU_VTT
SWITCHER
20" PANEL POWER
EI
PULSAR
KODIAK CORE
17" LCD INVERTER
GPU MEMORY
OPTICAL
VESTA
MODEM & BT
SMU
POWER SEQUENCE PIN
PAGE 15
MAIN MEMORY
PP1V8_PWRON
PP3V3_PWRON
FET SWITCH
PAGE 16
PAGE 15
PP2V5_ALL
USB2 HOST
SWITCHER
PP1V2_TPVDD
LINEAR
LINEAR
PP2V5_GPU_A2VDD
LINEAR
PP2V5_RUN_CPU_AVDD
PAGE 54
AUDIO CODEC
LINEAR
PP4V5_RUN_AUDIO
FET SWITCH
LINEAR
PAGE 85
PP1V2_RUN
FET SWITCH
PAGE 85
LINEAR
PP1V5_VDDC_CT
FET SWITCH
PP1V2_PWRON
PAGE 154
0.01UF
402
CERM
16V
20%
2
1
C440
12 13 12 13
PP1V8_RUN
150K
5%
1/16W
MF-LF
402
2
1
R442
1%
1/16W
402
MF-LF
100K
2
1
R443
402
10K
MF-LF
1/16W
5%
2
1
R441
402
10K
MF-LF
1/16W
5%
2
1
R431
PP2V5_ALL
PP2V5_ALL
PP2V5_ALL
SOI-LF
3
14
9
8
12
U400
SOI-LF
3
1
7
6
12
U400
PP3V3_PWRON
SOI-LF
3
2
5
4
12
U400
PP5V_ALL
PP2V5_ALL
10V
0.1UF
20%
CERM
402
2
1
C441
PP1V5_PWRON
5%
100K
402
MF-LF
1/16W
21
R430
16V
CERM
402
0.01UF
20%
2
1
C430
100K
5%
1/16W
MF-LF
402
21
R440
051-6863
154
4
SYNC_DATE=08/26/2005
F
Power Block Diagram
SYNC_MASTER=FINO-M23
TURN_ON_PP1V2_L
COMPARE_PP1V5
PWR_GOOD_PP1V5
PWR_GOOD_PP1V8
PS_1V_REF
COMPARE_PP1V8
U400P2
SMU_PWRSEQ_P1_3
NC_SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
PS_1V_REF
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P9_5
TURN_ON_PP3V3_PWRON_L
SMU_PWRSEQ_P1_4
NC_SMU_PWRSEQ_P1_4
16
4
28
6
28
28
4
28
28
28
15
28
6
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_11_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_11_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_11_HEAD
REFERENCE DESIGNATOR(S)
BOM OPTION
QTY
DESCRIPTION
VALUE VOLT. WATT.
TOL.PART #
PACKAGE
DEVICE
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
HEATSINKS ARE NOW ON THE PD BOM
ALTERNATES
MISC PARTS
NEED TO UPDATED BIN CODES AS NOTES
PROCESSORS ASICS
341T1752
U2800
CRITICAL
PURCH ASSY, SMU BIG
1
OMIT603-7322
MECH2
1
CRITICAL
M33 GPU HEATSINK
GAP1
1
875-1905
CPU GAP FILLER
CRITICALOMIT
MECH3
1
603-7323
M33 NB HEATSINK
IC,ASIC,VESTA,V1.3,LF
1
U1701
343S0356
CRITICAL
IC,DD3.1,2.1G,1.25V
337S3223 337S3220
20_INCH_LCD
U4300
IC,GPUL,DD3.1,1.9G,85C
337S3224
CRITICAL
17_INCH_LCD
50MV
U4300
1
45W
CBGA-576-1MM
1.9GHZ
PROCESSOR
1.10V
IC,PULSAR2,100P,P8MM,BGA
CRITICAL
1
343S0319
U2500
20_INCH_LCD
SCH1
1
PCB,SCHEM,MLB,M33
051-6863
051-6863
Table Items
154
5
F
SYNC_DATE=10/07/2005SYNC_MASTER=FINO-M23
BARCODE LABEL, MLB
LBL1
1
825-6447
PCB,FAB,MLB,M33
CRITICAL
20_INCH_LCD
MLB1
1
820-1766
051-6790
PCB,SCHEM,MLB,M23
17_INCH_LCD
SCH1
1
337S3224
U4300
17_INCH_LCD
337S3231
IC,DD3.0X,1.9G,1.30V
IC,DD3.1,2.1G,1.20V
337S3222
20_INCH_LCD
337S3220
U4300
U4300
IC,DD3.1,1.9G,1.15V
337S3225
17_INCH_LCD
337S3224
337S3224
U4300
17_INCH_LCD
337S3227
IC,DD3.1,1.9G,1.25V
U4300
17_INCH_LCD
337S3224
IC,DD3.0X,1.9G,1.15V
337S3228
SPEC,VENDOR PACKAGING PROCEDURE
VPP1
1
062-2082
UC500
CRITICAL
1
341T1751
IC,FLASH,1MX8,3.3V,90NS
353S1105353S1321
LM339
U400
124-0338 124-0333
PANASONIC CAPS
138S0558
10UF CAP ALL LOC.
138S0547
CF000
EL CAP
126S0068 126S0088
126S0086 C722
EL CAP
126S0078
343S0356
U1701
VESTA A4343S0388
378S0141378S0140
LED700,LED702
KINGBRIGHT LED
TAPE1
17_INCH_LCD
LED COVER TAPE
1
875-2429
OMIT603-7319
M23 GPU HEATSINK
1
MECH2
CRITICAL
OMIT603-7321
M33 CPU HEATSINK
CRITICAL
1
MECH1
M23 CPU HEATSINK
OMIT
MECH1
603-7318
1
CRITICAL
OMIT
1
MECH3
CRITICAL603-7320
M23 NB HEATSINK
CRITICAL
17_INCH_LCD
MLB1
1
820-1783
PCB,FAB,MLB,M23
U2300
IC,ASIC,SHASTA,V1.1,PBGA,LF
CRITICAL
343S0377
1
337S3226
IC,DD3.1,1.9G,1.20V
337S3224
U4300
17_INCH_LCD
IC,GPUL,DD3.1,2.1G,85C
1.10V
337S3220
CBGA-576-1MM
CRITICAL
20_INCH_LCD
50MV
U4300
1
PROCESSOR
45W
2.1GHZ
U4300
IC,DD3.1,2.1G,1.15V
20_INCH_LCD
337S3220337S3221
337S3224
U4300
17_INCH_LCD
337S3230
IC,DD3.0X,1.9G,1.25V
U1900
1
CRITICAL
IC,KODIAK,V1.2,PBGA,200MM
343S0379
U4300
337S3224
17_INCH_LCD
337S3229
IC,DD3.0X,1.9G,1.20V
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TOP SIDE ONLY
USE FAT TRACES
PLACE WITHIN 1 INCH OF EACH OTHER
FOR PP3V3_ALL AND GND
PLACE TWO TEST POINTS ON TOP SIDE
NOTES FROM TOM FUSSELMAN
FUNC TEST NETS
EE IDENTIFIED NO TEST NETS
NO TEST XW NETS
I1000
I1001
I1002
I1003
I1004
I1005
I1006
I1007
I1008
I1009
I1010
I1011
I1012
I1013
I1014
I1015
I1016
I1017
I1018
I1019
I1020
I1022
I1023
I1024
I1026
I1027
I1028
I1029
I1030
I1031
I1032
I1033
I1034
I1035
I1036
I1037
I1038
I1039
I1040
I1041
I1042
I1043 I1044
I1045
I1046
I1047
I1048
I1049
I1050
I1051
I1052
I1053
I1054
I1055
I1056
I1057
I1058
I1059
I1060
I1061
I1062
I1063
I1064
I1065
I1066
I1067
I1068
I1069
I1070
I1071
I1072
I1080
I1088
I1089
I1090
I1091
I1092
I1093
I1094
I1095
I1096
I1097
I1098
I1099
I1100
I1101
I1102
I1103
I1104
I1105
I1106
I1107
I1108
I1109
I1110
I1111
I1112
I1113
I1114
I1115
I1116
I1117
I1118
I1120
I1121
I1122
I1123
I1124
I1125
I1126
I1127
I1128
I1129
I1130
I1131
I1132
I1133
I1134
I1135
I1136
I1137
I1138
I1139
I1140
I1141
I1142
I1143
PP1V8_RUN PP3V3_RUN
PP1V5_PWRON
PP1V2_ALL
PP2V5_RUN
PP5V_ALL
PP3V3_ALL
PP12V_RUN
I1155
I1156
I1157
I1158
I1160
I1161
I1162
I1164
I1165
I1166
I1167
I1168
I1170
I1171
I1172
I1173
I1175
I1176
I1177
I1179
I1181
I1182
I1183
I1184
I1185
I1187
I1188
I1189
I1190
I1192
I1193
I1195
I1196
I1197
I1199
I1200
I1202
I1203
I1204
I1206
I1207
I1208
I1210
I1211
I1212
I1214
I1215
I1216
I1218
I1219
I1220
I1221
I1223
I1224
I1226
I1227
I1228
I1229
I1230
I1232
I1233
I1234
I1236
I1237
I1238
I1239
I1241
I1242
I1244
I1245
I1246
I1248
I1249
I1250
I1252
I1253
I1254
I1255
I1257
I1258
I1259
I1262
I1263
I1264
I1266
I1267
I1268
I1269
I1271
I1272
I1273
I1275
I1276
I1277
I1278
I1280
I1281
I1283
I1285
I1286
I1287
I1288
I1289
I1291
I1292
I1293
I1294
I1296
I1297
I1299
I1300
I1301
I1302
I1303
I1305
I1306
I1307
I1310
I1311
I1312
I1313
I1314
I1316
I1317
I1318
I1320
I1322
I1323
I1324
I1325
I1326
I1327
I1329
I1330
I1332
I1333
I1334
I1335
I1336
I1337
I1338
I1339
I1340
I1341
I1343
I1344
I1345
I1346
I1348
I1349
I1350
I307
I348
I349
I350
I356
I357
I358
I360
I361
I362
I375
I376
I428
I429
I826
I836
I837
I839
I841
I846
I847
I848
I849
I850
I851
I883
I947
I948
I949
I950
I951
I952
I953
I954
I955
I957
I958
I959
I960
I961
I962
I963
I964
I965
I969
I971
I972
I973
I974
I975
I976
I977
I978
I982
I984
I985
I986
I987
I988
I989
I990
I991
I992
I993
I994
I995
I996
I997
I998
I999
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
F
6
154
051-6863
FUNC TEST 1 OF 2
PP1V8_RUN
FUNC_TEST=TRUE
FUNC_TEST=TRUE
PP3V3_RUN
FUNC_TEST=TRUE
PP1V5_PWRON
FUNC_TEST=TRUE
PP1V2_ALL
FUNC_TEST=TRUE
PP2V5_RUN
FUNC_TEST=TRUE
PP5V_ALL
FUNC_TEST=TRUE
PP3V3_ALL
PP12V_RUN
FUNC_TEST=TRUE
FUNC_TEST=TRUE
GND
GND_AUDIO_CODEC
NO_TEST=YES
NO_TEST=YES
RFBD<94>
NO_TEST=YES
RFBD<92>
NO_TEST=YES
RFBD<91>
NO_TEST=YES
RFBD<90>
RAM_DQ_R<30>
NO_TEST=YES
RAM_DQ_R<29>
NO_TEST=YES
RAM_DQ_R<31>
NO_TEST=YES
RAM_DQ_R<22>
NO_TEST=YES
RAM_DQ_R<21>
NO_TEST=YES
RAM_DQ_R<20>
NO_TEST=YES
RAM_DQ_R<19>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<24>
RAM_DQ_R<32>
NO_TEST=YES
RAM_DQ_R<33>
NO_TEST=YES
RAM_DQ_R<34>
NO_TEST=YES
RAM_DQ_R<50>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<52>
NO_TEST=YES
RAM_DQ_R<53>
RAM_DQ_R<54>
NO_TEST=YES
RAM_DQ_R<5>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<7>
NO_TEST=YES
RAM_DQ_R<2>
RAM_DQ_R<44>
NO_TEST=YES
NO_TEST=YES
RFBD<85>
NO_TEST=YES
RFBD<106>
NO_TEST=YES
RFBD<112>
NO_TEST=YES
RFBD<109>
NO_TEST=YES
RFBD<105>
NO_TEST=YES
RFBD<104>
NO_TEST=YES
RFBD<102>
NO_TEST=YES
RFBD<101>
NO_TEST=YES
RFBD<108>
NO_TEST=YES
RFBD<126>
Q803_B
NO_TEST=YES
Q802_E
NO_TEST=YES
Q801_B
NO_TEST=YES
Q800_D
NO_TEST=YES
PCI_CLK66M_SB_INT_R
NO_TEST=YES
LED801_1
NO_TEST=YES
Q800_G
NO_TEST=YES
Q802_B
NO_TEST=YES
TP_USB2_PWREN<1>
NO_TEST=YES
TP_SB_FSTEST
NO_TEST=YES
TP_NEC_SMC
NO_TEST=YES
TP_NEC_TEST
NO_TEST=YES
UATA_DASP_L_DS
NO_TEST=YES
RFBD<16>
NO_TEST=YES
RFBD<15>
NO_TEST=YES
NO_TEST=YES
RFBD<11>
RFBD<6>
NO_TEST=YES
NO_TEST=YES
RFBD<2>
RAM_DQ_R<60>
NO_TEST=YES
RAM_DQ_R<59>
NO_TEST=YES
RAM_DQ_R<57>
NO_TEST=YES
RAM_DQ_R<56>
NO_TEST=YES
RAM_DQ_R<38>
NO_TEST=YES
RAM_DQ_R<25>
NO_TEST=YES
RAM_DQ_R<6>
NO_TEST=YES
RAM_DQ_R<9>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<8>
NO_TEST=YES
RAM_DQ_R<1>
RAM_DQ_R<12>
NO_TEST=YES
RAM_DQ_R<11>
NO_TEST=YES
RAM_DQ_R<13>
NO_TEST=YES
RAM_DQ_R<14>
NO_TEST=YES
RAM_DQ_R<16>
NO_TEST=YES
RAM_DQ_R<17>
NO_TEST=YES
NO_TEST=YES
RAM_DQ_R<3>
NO_TEST=YES
RAM_DQ_R<43>
RFBD<3>
NO_TEST=YES
NO_TEST=YES
RFBD<1>
RAM_DQ_R<63>
NO_TEST=YES
RAM_DQ_R<58>
NO_TEST=YES
RAM_DQ_R<46>
NO_TEST=YES
RAM_DQ_R<36>
NO_TEST=YES
RFBD<8>
NO_TEST=YES
NC_CLK_RAI_REFCLK_66M
NO_TEST=YES
NC_CPU_B_TBEN_CLK_US
NO_TEST=YES
NC_CLK_RAI_PCIEA_P<0>
NO_TEST=YES
NC_CLK_RAI_PCIEB_P<0>
NO_TEST=YES
NO_TEST=YES
NC_CLK_RAI_200M_N<0>
NC_HT_MB_TO_NB_CAD_N<8..15>
NO_TEST=YES
NO_TEST=YES
NC_CPU_B0_QACK_L
RAM_DQ_R<40>
NO_TEST=YES
RAM_DQ_R<41>
NO_TEST=YES
RAM_DQ_R<28>
NO_TEST=YES
RAM_DQ_R<37>
NO_TEST=YES
NO_TEST=YES
NC_SATA_TXD_N2
NC_PMR_CLK_DIS_L
NO_TEST=YES
KOD_H05_GND
NO_TEST=YES
DAGND
NO_TEST=YES
TDIODE_NEG_FMAX
NO_TEST=YES
NO_TEST=YES
PP12V_AUDIO_SPKRAMP
NO_TEST=YES
PP_2V5PWRONSB_B9
NO_TEST=YES
PP_1V2PWRONSBPLL45VDD
NO_TEST=YES
PP_1V2PWRONSBVCORE
GND_U1300
NO_TEST=YES
PP_3V3PWRONSBPCI64
NO_TEST=YES
NO_TEST=YES
NC_NB_CPU_B1_INT_L
NO_TEST=YES
NC_CPU_A1_QACK_L
NC_EI_CPU_B_TO_NB_SR_N<0..1>
NO_TEST=YES
NC_NB_CPU_A1_INT_L
NO_TEST=YES
NO_TEST=YES
RFBD<124>
GND_AUD_LOAMP_CHGPMP
NO_TEST=YESNO_TEST=YES
GND_AUD_LOAMP
NO_TEST=YES
PP_2V5PWRONSB
NO_TEST=YES
PP_OVDD_PULSAR1
RFBD<13>
NO_TEST=YES
LED802_1
NO_TEST=YES
RFBD<7>
NO_TEST=YES
NC_I2S2_MCLK
NO_TEST=YES
TP_SB<11>
NO_TEST=YES
NO_TEST=YES
RFBD<49>
NO_TEST=YES
RFBD<31>
NC_NCV1009_2
NO_TEST=YES
NC_SATA_RXD_P2_C
NO_TEST=YES
TP_SB<17>
NO_TEST=YES
TP_SB<20>
NO_TEST=YES
TP_SB<23>
NO_TEST=YES
TP_SB<22>
NO_TEST=YES
TP_SB<16>
NO_TEST=YES
NO_TEST=YES
RFBD<30>
TP_NEC_SMI_L
NO_TEST=YES
TP_USB2_PWREN<4>
NO_TEST=YES
TP_NEC_NTEST1
NO_TEST=YES
TP_USB2_PWREN<3>
NO_TEST=YES
TP_USB2_PWREN<2>
NO_TEST=YES
TP_SB_PLLTEST
NO_TEST=YES
TP_USB2_PWREN<0>
NO_TEST=YES
NO_TEST=YES
ITS_RUNNING
TP_FBBCS1_L
NO_TEST=YES
AUD_4V5_FB
NO_TEST=YES
NO_TEST=YES
RFBD<41>
NO_TEST=YES
RFBD<42>
NO_TEST=YES
RFBD<44>
NO_TEST=YES
RFBD<45>
NO_TEST=YES
RFBD<52>
NO_TEST=YES
RFBD<54>
NO_TEST=YES
RFBD<56>
NO_TEST=YES
RFBD<59>
NO_TEST=YES
RFBD<60>
NO_TEST=YES
RFBD<23>
NO_TEST=YES
RFBD<22>
NO_TEST=YES
RFBD<21>
NO_TEST=YES
RFBD<25>
NO_TEST=YES
RFBD<26>
NO_TEST=YES
RFBD<27>
NO_TEST=YES
RFBD<28>
TP_SB<0>
NO_TEST=YES
TP_SB<1>
NO_TEST=YES
TP_SB<3>
NO_TEST=YES
TP_SB<2>
NO_TEST=YES
TP_SB<5>
NO_TEST=YES
TP_SB<4>
NO_TEST=YES
TP_SB<6>
NO_TEST=YES
TP_SB<8>
NO_TEST=YES
TP_SB<7>
NO_TEST=YES
TP_SB<9>
NO_TEST=YES
TP_SB<10>
NO_TEST=YES
TP_SB<13>
NO_TEST=YES
TP_SB<12>
NO_TEST=YES
TP_SB<14>
NO_TEST=YES
TP_SB<15>
NO_TEST=YES
TP_SB<18>
NO_TEST=YES
TP_SB<19>
NO_TEST=YES
TP_SB<21>
NO_TEST=YES
NC_SMU_PWRSEQ_P1_4
NO_TEST=YES
NC_SMU_PWRSEQ_P1_0
NO_TEST=YES
NC_RAM_ARB1_REF25MHZ
NO_TEST=YES
NC_RAM_ARB0_REF25MHZ
NO_TEST=YES
NC_NCV1009_4
NO_TEST=YES
NC_NCV1009_ADJ
NO_TEST=YES
NC_NCV1009_5
NO_TEST=YES
NC_NCV1009_3
NO_TEST=YES
NC_NCV1009_1
NO_TEST=YES
NC_J2904_12
NO_TEST=YES
NC_J2904_11
NO_TEST=YES
NO_TEST=YES
NC_HT_NB_TO_MB_CLK_P<1>
NC_EI_CPU_B_SYSCLK_P
NO_TEST=YES
NO_TEST=YES
NC_HT_NB_TO_MB_CLK_N<1>
NC_EI_CPU_B_SYSCLK_N
NO_TEST=YES
NC_CPU_B_APSYNC
NO_TEST=YES
NC_A_AVREG_2
NO_TEST=YES
NC_A_AVREG_0
NO_TEST=YES
NC_A_AVREG_1
NO_TEST=YES
NO_TEST=YES
NC_CLK_RAI_PCIEC_P<0>
NO_TEST=YES
NC_CLK_RAI_PCIEC_N<0>
NC_CLK_RAI_PCIEB_N<0>
NO_TEST=YES
NC_CLK_RAI_PCIEA_N<0>
NO_TEST=YES
NO_TEST=YES
NC_CLK_RAI_200M_P<0>
NC_HT_NB_TO_MB_CAD_N<8..15>
NO_TEST=YES
NO_TEST=YES
NC_HT_NB_TO_MB_CAD_P<8..15>
NO_TEST=YES
NC_HT_MB_TO_NB_CAD_P<8..15>
NO_TEST=YES
NC_CPU_B1_QACK_L
NO_TEST=YES
NC_NB_CPU_B0_INT_L
NC_EI_CPU_B_TO_NB_SR_P<0..1>
NO_TEST=YES
NC_EI_CPU_B_TO_NB_AD<0..43>
NO_TEST=YES
NC_EI_CPU_B_TO_NB_CLK_N
NO_TEST=YES
NC_EI_CPU_B_TO_NB_CLK_P
NO_TEST=YES
NC_EI_NB_TO_CPU_B_SR_N<0..1>
NO_TEST=YES
NC_EI_NB_TO_CPU_B_SR_P<0..1>
NO_TEST=YES
NO_TEST=YES
NC_EI_NB_TO_CPU_B_AD<0..43>
NC_EI_NB_TO_CPU_B_CLK_N
NO_TEST=YES
NC_EI_NB_TO_CPU_B_CLK_P
NO_TEST=YES
GND_AUDIO_MIC
NO_TEST=YES
NO_TEST=YES
GND_GPU_MPVSS
NO_TEST=YES
VC_OUTSEN_R
NO_TEST=YES
KPVDD2_FMAX
NO_TEST=YES
GND_GPU_PVSS
NO_TEST=YES
VC_AGND
GND_CPU_AVDD
NO_TEST=YES
NO_TEST=YES
GND_SMU_AVSS
NO_TEST=YES
PP_3V3ALLSMUAVCC
NO_TEST=YES
PP_3V3ALLSMU
PP_VEINB
NO_TEST=YES
NO_TEST=YES
PP_1V5PWRONPULSAR2
NO_TEST=YES
PP_1V5PULSAR2
NO_TEST=YES
PP_1V2PWRONPULSAR1
NO_TEST=YES
PP_2V5PWRONNBMISC
NO_TEST=YES
GND_U1200
TP_SB<27>
NO_TEST=YES
TP_SB<29>
NO_TEST=YES
TP_SB<28>
NO_TEST=YES
NO_TEST=YES
NC_SATA_RXD_N2_C
PPV_RUN_CPU_AVDD_R_L
NO_TEST=YES
NO_TEST=YES
CORE_ISNS_M
NO_TEST=YES
CORE_ISNS_P
FMAXT_M
NO_TEST=YES
NO_TEST=YES
CPU_DIODE_NEG
NO_TEST=YES
FMAXT_P
CPU_DIODE_POS
NO_TEST=YES
KPGND2
NO_TEST=YES
KPVDD2
NO_TEST=YES
PP3V3_PWRON_NEC_AVDD
NO_TEST=YES
PP3V3_VESTA_FAVDDH
NO_TEST=YES
PP2V5_VESTA_FAVDDM
NO_TEST=YES
PP1V2_VESTA_FAVDDL
NO_TEST=YES
PP2V5_VESTA_XTALVDD2
NO_TEST=YES
PP2V5_VESTA_BIASVDD2
NO_TEST=YES
PP1V2_VESTA_PLLVDD1
NO_TEST=YES
PP1V2_VESTA_PLLVDD2
NO_TEST=YES
PP2V5_VESTA_XTALVDD1
NO_TEST=YES
PP2V5_VESTA_BIASVDD1
NO_TEST=YES
NO_TEST=YES
PP_1V2PWRONDISKSB_CC
NO_TEST=YES
PP_VIOPCIUSB2_C2
PP_3V3SBPCI_B9
NO_TEST=YES
NO_TEST=YES
KOD_L15_GND
NO_TEST=YES
GND_GPU_A2VSSQ
NO_TEST=YES
GND_GPU_A2VSSN
NO_TEST=YES
GND_GPU_AVSSQ
GND_GPU_AVSSN
NO_TEST=YES
GND_GPU_VSSDI
NO_TEST=YES
NO_TEST=YES
GND_GPU_TXVSSR
U8500_GND
NO_TEST=YES
PCIE_SLOTA_PRSNT_L
NO_TEST=YES
KOD_H08_GND
NO_TEST=YES
KOD_L13_GND
NO_TEST=YES
KOD_J13_GND
NO_TEST=YES
KOD_G10_GND
NO_TEST=YES
KOD_K07_GND
NO_TEST=YES
GND_AUDIO_SPKRAMP
NO_TEST=YES
GND_AUDIO
NO_TEST=YES
RAMCLK_AVSS
NO_TEST=YES
INA138_OUT
NO_TEST=YES
TDIODE_POS_FMAX
NO_TEST=YES
NO_TEST=YES
KPGND2_FMAX
NO_TEST=YES
GND_AUDIO_SPKRAMP_PLANE
NO_TEST=YES
GND_U1100
NO_TEST=YES
GND_GPU_TPVSS
NO_TEST=YES
GND_NEC_AVSS_R
NO_TEST=YES
RFBD<53>
NO_TEST=YES
RFBD<57>
NO_TEST=YES
RFBD<61>
NO_TEST=YES
RFBD<47>
NO_TEST=YES
RFBD<48>
NO_TEST=YES
RFBD<50>
NO_TEST=YES
RFBD<38>
NO_TEST=YES
RFBD<37>
NO_TEST=YES
RFBD<40>
NO_TEST=YES
RFBD<36>
NO_TEST=YES
RFBD<34>
NO_TEST=YES
RFBD<33>
NO_TEST=YES
RFBD<32>
RFBD<19>
NO_TEST=YES
RFBD<18>
NO_TEST=YES
NO_TEST=YES
RFBD<14>
NO_TEST=YES
RFBD<10>
RAM_DQ_R<45>
NO_TEST=YES
RFBD<5>
NO_TEST=YES
NC_CLK_RAI_GIGE_25MHZ
NO_TEST=YES
TP_SB<24>
NO_TEST=YES
RAM_DQ_R<49>
NO_TEST=YES
TP_NEC_SRMOD
NO_TEST=YES
TP_NEC_SRCLK
NO_TEST=YES
PPVCORE_CPU
FUNC_TEST=TRUE
FUNC_TEST=TRUE
=PP3V3_ALL_SMU
FUNC_TEST=TRUE
=PP5V_RUN_CPU
FUNC_TEST=TRUE
SYS_POWER_BUTTON_L
FUNC_TEST=TRUE
SMU_RESET_L
FUNC_TEST=TRUE
RESET_BUTTON_L
FUNC_TEST=TRUE
SYS_POWERUP_L
FUNC_TEST=TRUE
POWER_BUTTON_L
FUNC_TEST=TRUE
SMU_BOOT_SCLK
FUNC_TEST=TRUE
SMU_BOOT_RXD
SMU_BOOT_CNVSS
FUNC_TEST=TRUE
SMU_BOOT_CE
FUNC_TEST=TRUE
SMU_BOOT_BUSY
FUNC_TEST=TRUE
SMU_BOOT_TXD
FUNC_TEST=TRUE
SMU_MANUAL_RESET_L
FUNC_TEST=TRUE
NO_TEST=YES
RFBD<65>
NO_TEST=YES
RFBD<78>
NO_TEST=YES
RFBD<81>
NO_TEST=YES
RFBD<69>
NO_TEST=YES
RFBD<70>
NO_TEST=YES
RFBD<72>
NO_TEST=YES
RFBD<71>
NO_TEST=YES
RFBD<82>
NO_TEST=YES
RFBD<83>
NO_TEST=YES
RFBD<79>
NO_TEST=YES
RFBD<76>
NO_TEST=YES
RFBD<75>
NO_TEST=YES
RFBD<74>
NO_TEST=YES
RFBD<67>
NO_TEST=YES
RFBD<95>
NO_TEST=YES
RFBD<88>
NO_TEST=YES
RFBD<87>
NO_TEST=YES
RFBD<86>
NO_TEST=YES
RFBD<114>
NO_TEST=YES
RFBD<120>
RFBD<117>
NO_TEST=YES
NO_TEST=YES
RFBD<118>
NO_TEST=YES
RFBD<122>
RFBD<98>
NO_TEST=YES
NO_TEST=YES
RFBD<100>
NO_TEST=YES
RFBD<97>
NO_TEST=YES
RFBD<125>
NO_TEST=YES
RFBD<121>
NO_TEST=YES
RFBD<116>
NO_TEST=YES
RFBD<110>
NO_TEST=YES
RFBD<96>
NO_TEST=YES
RFBD<66>
NO_TEST=YES
RFBD<62>
TP_SB<26>
NO_TEST=YES
NO_TEST=YES
RFBD<113>
RAM_DQ_R<48>
NO_TEST=YES
NC_SATA_TXD_P2
NO_TEST=YES
TP_SB<25>
NO_TEST=YES
85
154
50
150
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
69
69
69
70
70
70
70
70
70
69
69
69
69
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
69
70
55
55
154
70
70
29
28
70
16
148
90
90
90
90
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
90
90
90
90
90
90
90
90
90
90
89
89
89
89
89
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
68
89
89
68
68
68
68
89
68
68
68
68
97
152
90
154 154
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
154
55
55
55
50
50
101
84
97
97
97
97
97
152
154
154
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
68
89
68
28
8
29
29
12
29
29
29
29
29
29
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
90
89
90
68
7
7
7
7
7
7
7
7
147
88
88
88
88
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
88
88
88
88
88
88
88
88
88
88
8
8
8
8
26
8
8
8
143
24
122
122
129
88
88
88
88
88
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
88
88
61
61
61
61
88
27
26
27
27
27
101
56
61
61
61
61
129
20
82
55
55
7
119
24
23
13
23
56
56
56
56
88
150 150
23
25
88
8
88
154
142
88
88
55
129
142
142
142
142
142
88
122
143
122
143
143
24
143
7
87
154
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
142
4
4
27
27
55
55
55
55
55
29
29
101
27
101
27
27
82
82
82
27
27
27
27
27
101
101
101
56
56
56
56
56
56
56
56
56
56
56
153
87
50
55
86
50
48
28
28
28
41
25
25
25
20
12
142
142
142
129
48
55
55
55
48
55
48
48
48
142
139
139
139
139
139
132
139
132
132
127
122
98
93
93
93
93
93
93
85
82
82
82
82
82
82
7
7
62
55
55
55
152
11 93
142
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
61
88
27
142
61
122
122
50
7
7
28
28
29
7
29
28
28
28
28
28
28
29
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
88
142
88
61
129
142
125
OUT
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
LEAKAGE HACK
P/N 518-0188
SILKSCREEN:2
ON IN RUN AND SLEEP
PWRON RAILS
CHASSIS MOUNTING
GPU MOUNTING
ALL RAILS
RUN RAILS
GND RAILS
ONLY ON IN RUN
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
SILKSCREEN:1
SILKSCREEN:RUN
CHASSIS GND
PP5V_RUN
PP3V3_PWRON
PP1V5_PWRON
PP2V5_PWRON
PP1V2_PWRON
PP5V_ALL
PP5V_ALL
PP3V3_RUN
PP2V5_RUN
PP5V_PWRON
PP1V5_RUN
PP3V3_RUN
PP5V_RUN
SM
21
XW701
SM
21
XW702
SM
21
XW703
PP12V_RUN
74LC125
CRITICAL
TSSOP
3
14
17
2
U700
402
20%
10V
0.1UF
CERM
2
1
C700
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
LED701
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
LED702
PP3V3_PWRON
820
1/10W
603
MF-LF
5%
21
R700
GREEN-3.6MCD
2.0X1.25MM-SM
2
1
LED700
SM
21
XW705
SM
21
XW706
SM
21
XW707
PP12V_RUN
PP3V3_RUN
M-RT-TH1
CRITICAL
HM9607E-P2
9
87
65
43
2
1413
1211
10
1
J700
PP3V3_ALL PP12V_ALL
PP1V8_PWRON
OMIT
4P75R4
1
ZH700
OMIT
4P75R4
1
ZH701
OMIT
4P75R4
1
ZH702
OMIT
4P75R4
1
ZH703
0.01UF
20%
CERM
402
NOSTUFF
16V
2
1
C704
CERM
0.01UF
NOSTUFF
20%
16V
402
2
1
C702
NOSTUFF
16V
20%
CERM
402
0.01UF
2
1
C703
PP1V8_RUN
4P25R3P5
OMIT
ZH704
OMIT
4P25R3P5
ZH705
NOSTUFF
16V
0.01UF
20%
CERM
402
2
1
C707
0.01UF
20%
16V
CERM
402
NOSTUFF
2
1
C706
NOSTUFF
0.01UF
CERM
20%
16V
402
2
1
C705
1/16W
402
10K
5%
MF-LF
2
1
R702
PP3V3_ALL
PP3V3_ALL
PP1V2_ALL
PP2V5_ALL
PP12V_ALL
PP3V3_ALL
1.5K
5%
1/10W
MF-LF
603
21
R710
402
1/16W
5%
0
NOSTUFF
MF-LF
21
R721
MF-LF
1/16W
5%
0
402
NOSTUFF
21
R711
SM
21
XW700
4P25R3P5
OMIT
1
ZH706
SM
21
XW708
ELEC
6.3V
20%
330UF
6.3X8-SM
2
1
C722
1206
1/4W
33
MF-LF
5%
2
1
R790
2N7002
SOT23-LF
2
1
3
Q790
PP3V3_RUN
603
DEVELOPMENT
1/10W
330
5%
MF-LF
21
R701
PP5V_ALL
SYNC_DATE=06/20/2005
POWER CONN / ALIAS
051-6863
154
7
F
SYNC_MASTER=M33-PC
GND_CHASSIS_AUDIO_INTERNAL
HS_SDF801
=PP1V2_PWRON_HT_NBTX
=PP1V5_PWRON_PULSAR
=PP1V5_PULSAR
GND_CHASSIS_LEFT
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=0
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
GND_CHASSIS_AUDIO_EXTERNAL
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=0
MIN_LINE_WIDTH=0.6MM
GND_CHASSIS_RIGHT
VOLTAGE=0V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.60MM
GND_CHASSIS_TMDS
GND_CHASSIS_USB
GND_CHASSIS_VGA
SYS_POWERFAIL_L
LCD_PWM
SYS_POWERUP_L_BUF
SYS_POWERUP_L_BUF
PPVCORE_GPU
MAKE_BASE=TRUE
=PP3V3_SB_PCI
=PP3V3_RUN_SB_PCI
=PP3V3_RUN_SMU
PP3V3_RUN_SB
=PP2V5_RUN_I2C
=PP3V3_RUN_PULSAR
=PPV_PWRON_NB_REFCLK
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V5_PWRON_PULSAR
=PP5V_PWRON_BNDI
=PP5V_PWRON_USB
=PP3V3_ENET
=PP3V3_PWRON_BNDI
=PP3V3_PWRON_BT
=PP3V3_PWRON_CPU
=PP3V3_PWRON_SB_PCI32
=PP3V3_PWRON_SB_PCI64
=PP3V3_PWRON_SMU
=PP3V3_PWRON_USB
=PP2V5_PWRON_NB_MISC
=PP2V5_PWRON_HT
=PP2V5_PWRON_NB_PCIE
=PP1V8_RUN_RAM
ZH706P1
=PP5V_PATA
=PP3V3_AUDIO
=PP3V3_RUN_I2C
=PPVIO_PCI_USB2
=PP1V2_PWRON_PULSAR
=PP1V2_PWRON_SB_HT
=PP1V2_PWRON_SB_VCORE
GND_CHASSIS_FIREWIRE
GND_CHASSIS_RJ45
ZH700P1
=PPOVDD_PULSAR
GND_AUDIO_SPKRAMP
=PPV_EI_CPU
=PPV_EI_NB
=PP1V8_PWRON_DIMM
=PP12V_GPU
=PP1V8_PWRON_NBMEM
=PP1V8_PWRON_RAM
=PPVCORE_PWRON_NB_HT
=PPVCORE_PWRON_NB
=PPVCORE_PWRON_NB_PCIE
=PP3V3_ALL_GPU
=PP2V5_ENETFW
=PP3V3_ENETFW
=PPV_GPU_MEM
ZH703P1
=PP2V5_ENET
=PP2V5_PWRON_SB
GND_AUDIO
=PP1V2_GPU_PCIE
=PP2V5_PWRON_PULSAR
=PP1V2_ENETFW
=PP3V3_ALL_SMU
=PP3V3_FW
=PP12V_ALL_GPU
=PP5V_ALL_GPU
=PP3V3_ALL_CPU
ZH702P1
=PP12V_ALL_FW
=PP12V_CPU
ZH705P1
=PP2V5_PWRON_NB_HT
PP5V_AUDIO_ANALOG
=PP3V3_RUN_CPU
=PP3V3_GPU
=PP3V3_PCI
=PP1V8_PWRON_RAM_I2C_VDD
=PP5V_GPU
MIN_NECK_WIDTH=0.2MM
GND_CHASSIS_BNDI
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
=PP1V2_PWRON_SB
=PP1V2_PWRON_DISK_SB
=PP3V3_PWRON_PULSAR
=PP3V3_PWRON_SB
=PP5V_RUN_CPU
PP12V_AUDIO_SPKRAMP
INV_CUR_HI
ITS_RUNNING
ITS_ALIVE
SYS_POWERUP_L
ITS_PLUGGED_IN
ZH704P1
=PP1V5_PWRON_PULSAR
=PP3V3_PATA
Q790_D
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
VOLTAGE=12V
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
VOLTAGE=3.3V
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MAKE_BASE=TRUE
PP5V_ALL
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
PP12V_ALL
VOLTAGE=12V
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP2V5_ALL
VOLTAGE=2.5V
NET_SPACING_TYPE=POWER
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
PP1V2_ALL
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP3V3_ALL
PP1V8_RUN
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=2.5V
MAKE_BASE=TRUE
PP1V8_PWRON
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
PP3V3_RUN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
PP12V_RUN
PP1V5_RUN
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
PP5V_PWRON
VOLTAGE=2.5V
PP2V5_RUN
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PP1V2_PWRON
VOLTAGE=2.5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP2V5_PWRON
NET_SPACING_TYPE=POWER
PP1V5_PWRON
NET_SPACING_TYPE=POWER
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
PP3V3_PWRON
VOLTAGE=5V
PP5V_RUN
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=0V
56
119
85
39
154
48
59
91
138
96
56
50
96
96
30
43
145
30
153
154
47
56
70
58
139
139
90
119
139
29
154
93
24
28
25
154
16
16
86
28
59
136
30
144
28
103
62
152
152
30
42
69
39
132
132
89
24
154
132
28
55
153
55
92
125
23
8
152
12
25
16
153
8
98
7
25
153
96
96
143
96
28
92
7
7
85
24
20
119
39
25
42
12
143
143
132
121
55
23
23
28
142
20
98
82
61
129
147
39
122
25
103
23
140
136
25
6
29
41
67
96
20
62
98
19
82
85
17
17
87
136
23
6
84
25
17
6
140
85
85
55
140
50
98
150
54
85
121
67
143
24
127
25
20
6
6
92
6
6
7
129
6
6
6
6
6
6
62
6
6
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU HEATSINK MOUNTING HOLES
SCC_GPIO_L
SCC_TRXC
SCC_TXD_L
SCC_RTS_L
SCC_DTR_L
CHKSTOP LED
PLL LOCK LED
DIAG LED
(OVERTEMP LED)
SCC_RXD
SERIAL DEBUG
OMIT
4P75R4
1
ZH800
OMIT
4P75R4
1
ZH801
OMIT
4P75R4
1
ZH803
OMIT
4P75R4
1
ZH802
402
0.01UF
20%
16V
CERM
2
1
C880
402
0.01UF
20%
16V
CERM
2
1
C881
402
0.01UF
20%
CERM
16V
2
1
C882
402
0.01UF
20%
16V
CERM
2
1
C883
DEVELOPMENT
2N7002
SOT23-LF
Q800_D
2
1
3
Q800
2N3904LF
SOT23
DEVELOPMENT
Q801_B
2
3
1
Q801
SOT23-LF
DEVELOPMENT
2N3906
2
3
1
Q802
1K
MF-LF
1/16W
DEVELOPMENT
402
5%
2
1
R835
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
2
1
LED802
180
MF-LF
402
5%
DEVELOPMENT
1/16W
2
1
R837
1/16W
MF-LF
DEVELOPMENT
1K
402
5%
2
1
R838
2N3904LF
SOT23
DEVELOPMENT
2
3
1
Q803
180
1/16W
MF-LF
402
5%
DEVELOPMENT
21
R839
SOT23
2N3904LF
2
3
1
Q850
5%
402
1/16W
1K
MF-LF
21
R851
PP5V_ALL
402
2.0K
MF-LF
1/16W
5%
2
1
R850
DEVELOPMENT
M-ST-5087
SM-LF
9
8
7
65
4
3
2
10
1
J800
PP5V_PWRON
MF-LF
1/16W
5%
180
DEVELOPMENT
402
2
1
R833
402
4.7K
5%
1/16W
MF-LF
DEVELOPMENT
2
1
R834
1/16W
5%
MF-LF
10K
402
DEVELOPMENT
21
R836
RED-4.0MCD
2X1.25MM-SM
2
1
LED850
RED-4.0MCD
DEVELOPMENT
2X1.25MM-SM
2
1
LED801
SYNC_DATE=08/29/2005SYNC_MASTER=FINO-M23
Signal Alias
F
8
154
051-6863
I2S1_DEV_TO_SB_DTI
I2S1_SYNC
CPU_CHKSTOP_L
Q803_B
LED801_1
=PP5V_RUN_CPU
Q802_B
=PP5V_RUN_CPU
Q800_G
LED802_1
Q803_C
I2S1_RESET_L
I2S1_MCLK
I2S1_BITCLK
I2S1_SB_TO_DEV_DTO
HS_SDF800
DIAG_LED
MAKE_BASE=TRUE
DIAG_LED_R
PLLLOCK
Q802_E
HS_SDF801 HS_SDF802 HS_SDF803
LED850P2
LED850P1
8
8
56
7
7
43
6
6
24 24
43
6
6
6
6
6
6
6
9
24
24 24
24
28
9
6
7
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
JTAG TEST POINTS NEED TO BE ON THE BOTTOM
THE FOLLOWING NETS ARE USED ONLY
TEST POINT BECAUSE OF ROUTING DENSITY
TEST COVERAGE WILL BE BY FCT
AND SIGNAL INTEGRITY.
THE FOLLOWING NETS DO NOT HAVE
WHEN THE DEVELOPMENT BOM OPTION IS ENABLED
NOTE FOR SHARING: DO NOT INCLUDE THIS LIST UNTIL
LAYOUT HAVING DIFFICULTY PLACING TEST POINTS ON THESE NETS
OF THE BOARD
ADDING FUNC_TEST=TRUE TO THESE NETS
PCB LAYOUT ADDS TEST POINTS. THIS LIST IS A RESULT OF PCB
ADDING NO_TEST TO ALL PCIE NETS
TO AVOID STUBS
WILL GET COVERAGE IN FCT WITH A DIAG
THAT CHECKS THAT THE BUS IS 16 LANES WIDE
THE FOLLOWING PULSAR NETS WILL BE
TESTED VIA TEST JET
I1
I10
I100
I101
I102
I103
I106
I109
I11
I114
I115
I116
I117
I118
I119
I12
I120
I121
I122
I123
I124
I125
I126
I127
I128
I129
I13
I130
I131
I132
I133
I134
I135
I136
I137
I138
I139
I14
I140
I141
I142
I143
I144
I145
I146
I147
I148
I149
I15
I150
I151
I152
I153
I154
I155
I156
I157
I158
I159
I16
I160
I161
I162
I163
I164
I165
I166
I167
I168
I169
I17
I170
I171
I172
I173
I174
I175
I176
I177
I178
I179
I18
I180
I181
I182
I183
I184
I185
I186
I187
I188
I189
I19
I191
I192
I193
I194
I195
I196
I197
I198
I199
I2
I20
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I21
I210
I211
I212
I213
I214
I215
I216
I217
I218
I219
I22
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229
I23
I230
I232
I233
I234
I235
I236
I238
I239
I24
I240
I241
I242
I244
I245
I246
I247
I248
I249
I25
I250
I251
I252
I253
I254
I255
I256
I257
I258
I259
I26
I260
I261
I262
I263
I264
I265
I266
I267
I27
I28
I29
I3
I30
I31
I32
I33
I34
I35
I36
I37
I38
I39
I4
I40
I41
I42
I43
I44
I45
I46
I47
I48
I49
I5
I50
I51
I52
I53
I54
I55
I56
I57
I58
I59
I6
I60
I61
I62
I63
I64
I65
I66
I67
I68
I69
I7
I70
I71
I72
I73
I74
I75
I76
I77
I78
I79
I8
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
I9
I90
I91
I92
I93
I94
I95
I96
I97
I98
I99
154
9
051-6863
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
F
FUNC TEST 2 OF 2
NB_PMR_CLK_N_R
NO_TEST=YES
NB_PCIE_REFCLK_P_C
NO_TEST=YES
EI_NB_TO_CPU_SR_P<0>
NO_TEST=YES
EI_NB_TO_CPU_SR_N<0>
NO_TEST=YES
PCIE_B_REFCLKIN_P_C
NO_TEST=YES
PCIE_B_REFCLKIN_N_C
NO_TEST=YES
NO_TEST=YES
GFX_SLOT_PCIE_REFCLK_N_C
GFX_SLOT_PCIE_REFCLK_P_C
NO_TEST=YES
NO_TEST=YES
PLLTESTOUT
NO_TEST=YES
RFBD<51>
NO_TEST=YES
SB_AIRPRT_CLK_33MHZ_R
NO_TEST=YES
CLK_RAI_REFCLK_66M_R
PCIE_C_REFCLKIN_P_C
NO_TEST=YES
NO_TEST=YES
CLK_RAIREF_200M_N_R
NO_TEST=YES
NB_PMR_CLK_P_R
NO_TEST=YES
CPU_A_TBEN_CLK_R
NO_TEST=YES
CPU_A_APSYNC_R
NO_TEST=YES
EI_CPU_TO_NB_SR_P<1>
NO_TEST=YES
EI_NB_TO_CPU_SR_N<0>
NO_TEST=YES
CPU_B_TBEN_CLK_R
NO_TEST=YES
CPU_B_APSYNC_R
NO_TEST=YES
EI_CPU_TO_NB_SR_N<1>
NO_TEST=YES
EI_NB_TO_CPU_CLK_P
PCI_CLK33M_SB_EXT_R
NO_TEST=YES
SB_CLK25M_SATA_R
NO_TEST=YES
NO_TEST=YES
PCIE_SLOTA_TO_NB_P<0..15>
NO_TEST=YES
PCIE_SLOTA_TO_NB_N<0..15>
NO_TEST=YES
PCIE_SLOTA_TO_NB_PF<0..15>
NO_TEST=YES
PCIE_SLOTA_TO_NB_NF<0..15>
NO_TEST=YES
PCIE_NB_TO_SLOTA_P<0..15>
NO_TEST=YES
PCIE_NB_TO_SLOTA_N<0..15>
PCIE_NB_TO_SLOTA_PF<0..15>
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<0..15>
NO_TEST=YES
NO_TEST=YES
CLK_KOD_100M_PF<0>
NO_TEST=YES
HT_NB_TO_SB_CTL_N<0>
NO_TEST=YES
HT_NB_TO_MB_CTL_P<1>
NO_TEST=YES
HT_NB_TO_MB_CTL_N<1>
NO_TEST=YES
HT_MB_TO_NB_CTL_N<1>
NO_TEST=YES
UATA_DD<1>
NO_TEST=YES
UATA_DA<0>
NO_TEST=YES
UATA_DD<14>
CPU_SENSE_KP_V
NO_TEST=YES
NO_TEST=YES
LED_PP1V5_RUN_N
NO_TEST=YES
LED_PP1V5_RUN_P
NO_TEST=YES
PULSAR_1V5_RUN_SWITCH
NO_TEST=YES
PP1V2_RUN_FOR_LED
NO_TEST=YES
LED_PP1V2_RUN_N
NO_TEST=YES
T555_DISC
TSENSE_GPU_OVERTEMP_L
NO_TEST=YES
NO_TEST=YES
NB_APSYNC_R
NO_TEST=YES
CLK_RAIREF_200M_P_R
NO_TEST=YES
NB_PCIE_REFCLK_N_C
NC_PSRO_ENABLE
NO_TEST=YES
NO_TEST=YES
NC_CPU_AFN
PCIE_A_REFCLKIN_N_C
NO_TEST=YES
NO_TEST=YES
CLK_RAI_GIGE_25MHZ_R
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<10>
HT_NB_REFCLK_PF<0>
NO_TEST=YES
NO_TEST=YES
PLLLOCK
NO_TEST=YES
PP5V_T555
NO_TEST=YES
T555_THRES
NO_TEST=YES
ENET_TXD<5>
ENET_TXD_R<4>
NO_TEST=YES
NO_TEST=YES
HT_MB_TO_NB_CTL_P<1>
JTAG_CPU_TMS
FUNC_TEST=TRUE
JTAG_CPU_TRST_L
FUNC_TEST=TRUE
JTAG_CPU_TDO
FUNC_TEST=TRUE
JTAG_CPU_TDI
FUNC_TEST=TRUE
JTAG_CPU_TCK
FUNC_TEST=TRUE
TP_JTAG_SB_TDI
FUNC_TEST=TRUE
FUNC_TEST=TRUE
TP_JTAG_SB_TDO
FUNC_TEST=TRUE
TP_JTAG_SB_TMS
FUNC_TEST=TRUE
JTAG_NB_TDO
FUNC_TEST=TRUE
TP_JTAG_VESTA_TMS
FUNC_TEST=TRUE
TP_JTAG_VESTA_TRST_L
FUNC_TEST=TRUE
JTAG_NB_TDI
FUNC_TEST=TRUE
JTAG_NB_TRST_L
NO_TEST=YES
TP_VESTA_FAVDDL
TP_VESTA_TEST<1>
NO_TEST=YES
TP_VESTA_TDBL<2>
NO_TEST=YES
TP_VESTA_TDBL<1>
NO_TEST=YES
TP_VESTA_TEST<0>
NO_TEST=YES
TP_VESTA_TVCO
NO_TEST=YES
NO_TEST=YES
CARD_READER_ACTIVITY_R
NO_TEST=YES
TP_NB_A_TRIGGER_OUT
NO_TEST=YES
TP_NB_B_TRIGGER_OUT
TP_VESTA_TEST_1394<0>
NO_TEST=YES
TP_VESTA_TEST_1394<1>
NO_TEST=YES
HT_NB_TO_SB_CAD_N<0..7>
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<13>
NO_TEST=YES
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<7>
PCIE_SLOTA_TO_NB_N<0..15>
NO_TEST=YES
HT_NB_N<0>
NO_TEST=YES
CKA_N<0>
NO_TEST=YES
HT_SB_TO_NB_CLK_N<0>
NO_TEST=YES
NO_TEST=YES
T555_OUT
NO_TEST=YES
T555_PWM
NO_TEST=YES
PP3V3_GPU_TSENSE
LED8701_P
NO_TEST=YES
NO_TEST=YES
GPU_DIODE_MINUS
NO_TEST=YES
NB_PLL_OUT_TRG PCIE_NB_TO_SLOTA_N<0>
NO_TEST=YES
PCIE_NB_TO_SLOTA_N<3>
NO_TEST=YES
PCIE_NB_TO_SLOTA_P<1>
NO_TEST=YES
NO_TEST=YES
PCIE_NB_TO_SLOTA_P<10>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<13>
NO_TEST=YES
KP_V<2>
NO_TEST=YES
KP_V<1>
LED_PP1V2_RUN_P
NO_TEST=YES
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<14>
HT_SB_TO_NB_CLK_P<0>
NO_TEST=YES
NO_TEST=YES
PCIE_NB_TO_SLOTA_NF<12>
NO_TEST=YES
PCIE_NB_TO_SLOTA_PF<4>
NO_TEST=YES
HT_SB_TO_NB_CTL_P<0>
NO_TEST=YES
CLK_KOD_100M_NF<0>
NO_TEST=YES
EI_CPU_TO_NB_CLK_N
NO_TEST=YES
EI_CPU_TO_NB_CLK_P
NO_TEST=YES
EI_NB_TO_CPU_CLK_N
NO_TEST=YES
HT_SB_TO_NB_CAD_P<0..7>
NO_TEST=YES
HT_SB_TO_NB_CAD_N<0..7>
HT_NB_TO_SB_CLK_N<0>
NO_TEST=YES
HT_NB_TO_SB_CLK_P<0>
NO_TEST=YES
HT_NB_TO_SB_CAD_P<0..7>
NO_TEST=YES
HT_NB_REFCLK_NF<0>
NO_TEST=YES
HT_NB_P<0>
NO_TEST=YES
CKA_P<0>
NO_TEST=YES
100M_N<0>
NO_TEST=YES
Q803_C
NO_TEST=YESNO_TEST=YES
TP_I2S2_SB_TO_DEV_DTO
NO_TEST=YES
TP_NB_APSYNC
NO_TEST=YES
TP_SB_WATCHDOG
NO_TEST=YES
NC_CPU_TBEN_CLK
NC_J3108_12
NO_TEST=YES
NC_J3108_8
NO_TEST=YES
NC_JTAGMUX_3
NO_TEST=YES
NO_TEST=YES
NC_PP1V5_PULSAR
NO_TEST=YES
ENET_TXD<0>
NO_TEST=YES
SB_USB2_CLK_33MHZ_R
PCIE_A_REFCLKIN_P_C
NO_TEST=YES
PCIE_C_REFCLKIN_N_C
NO_TEST=YES
NB_DDR_REFCLK_P_R
NO_TEST=YES
NB_DDR_REFCLK_N_R
NO_TEST=YES
NO_TEST=YES
QUA1_REF_25MHZ_R
NO_TEST=YES
GPU_DIODE_PLUS
NO_TEST=YES
TSENSE_GPU_ADD1
ENET_RXD_R<7>
NO_TEST=YES
NC_J3108_9
NO_TEST=YES NO_TEST=YES
LED_PP1V8_RUN_P
ENET_RXD_R<1>
NO_TEST=YES
TP_VESTA_TDBL<0>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_REGSUP1
TP_VESTA_PHYA<2>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_F1000
TP_VESTA_PHYA<3>
NO_TEST=YES
TP_VESTA_REGCTL2
NO_TEST=YES
NO_TEST=YES
TP_VESTA_RBC1
NO_TEST=YES
TP_VESTA_RBC0
TP_VESTA_PHYA<1>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_REGSEN1
TP_VESTA_PHYA<0>
NO_TEST=YES
NO_TEST=YES
NC_SMU_CPU_VID_LE0
ENET_RXD_R<6>
NO_TEST=YES
ENET_TXD<1>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_ER
NO_TEST=YES
NC_SMU_FAN_TACH5
NO_TEST=YES
TP_VESTA_AN_EN
NO_TEST=YES
TP_VESTA_FDX
NO_TEST=YES
TP_VESTA_EN_10B
NO_TEST=YES
TP_VESTA_DNC_E9
NO_TEST=YES
TP_VESTA_DNC_C9
NO_TEST=YES
TP_VESTA_2_5V_EN
NO_TEST=YES
TP_VESTA_LINK1_L
NO_TEST=YES
TP_VESTA_HUB
NO_TEST=YES
TP_VESTA_FDXLED_L
NO_TEST=YES
TP_VESTA_MANMS
TP_VESTA_REGSEN2
NO_TEST=YES
NO_TEST=YES
TP_VESTA_REGCTL1
NO_TEST=YES
TP_VESTA_RGMIIEN
NO_TEST=YES
TP_VESTA_REGSUP2
NO_TEST=YES
TP_VESTA_SPD0
TP_VESTA_PHYA<4>
NO_TEST=YES
NO_TEST=YES
ENET_TX_ER
ENET_TX_EN_R
NO_TEST=YES
NO_TEST=YES
NC_SMU_FAN_TACH4
NO_TEST=YES
NC_SMU_FAN_RPM5
NO_TEST=YES
TP_HT_MB_TO_NB_CLK_N<1>
NO_TEST=YES
NC_SLOT_TOTAL_PWR
ENET_TXD_R<5>
NO_TEST=YES
ENET_TXD<7>
NO_TEST=YES
ENET_TXD_R<0>
NO_TEST=YES
ENET_TXD_R<1>
NO_TEST=YES
ENET_TXD<2>
NO_TEST=YES
ENET_RXD_R<0>
NO_TEST=YES
ENET_RXD<6>
NO_TEST=YES
ENET_RXD<7>
NO_TEST=YES
NO_TEST=YES
ENET_TX_ER_R
ENET_RXD<1>
NO_TEST=YES
NC_PSRO
NO_TEST=YES
NC_I2C_SMU_CPU_SCL_IN
NO_TEST=YES
NO_TEST=YES
TP_HT_MB_TO_NB_CLK_P<1>
NO_TEST=YES
NC_SMU_FAN_RPM4
NO_TEST=YES
NC_SMU_FAN_RPM3
NO_TEST=YES
NC_SMU_CPU_VID_LE1
NO_TEST=YES
NC_SYS_DOOR_AJAR_L
NC_SMU_SER_SEL
NO_TEST=YES
NC_SMU_FAN_TACH7
NO_TEST=YES
NO_TEST=YES
NC_SMU_FAN_TACH3
ENET_TXD<3>
NO_TEST=YES
ENET_RXD_R<5>
NO_TEST=YES
ENET_TXD_R<2>
NO_TEST=YES
ENET_TXD_R<3>
NO_TEST=YES
ENET_TXD_R<6>
NO_TEST=YES
ENET_TXD_R<7>
NO_TEST=YES
NO_TEST=YES
NC_J3108_10
NO_TEST=YES
NC_J3108_11
NO_TEST=YES
LED_PP1V8_RUN_N
ENET_TXD<4>
NO_TEST=YES
NO_TEST=YES
TP_VESTA_LINK2_L
NO_TEST=YES
LED8700_P
NO_TEST=YES
ENET_TXD<6>
NO_TEST=YES
TSENSE_GPU_ADD0
ENET_RXD<3>
NO_TEST=YES
NO_TEST=YES
QUA0_REF_25MHZ_R
TP_VESTA_TVCO_24
NO_TEST=YES
TP_VESTA_TXC_RXC_DELAY
NO_TEST=YES
NO_TEST=YES
ENET_RXD_R<2>
ENET_RXD_R<3>
NO_TEST=YES
NO_TEST=YES
PP1V5_RUN_FOR_LED
100M_P<0>
NO_TEST=YES
ENET_RXD_R<4>
NO_TEST=YES
ENET_RXD<2>
NO_TEST=YES
ENET_RXD<0>
NO_TEST=YES
NO_TEST=YES
ENET_TX_EN
NO_TEST=YES
NB_PLL_OUT_TRG_R
NO_TEST=YES
PCIE_SLOTA_TO_NB_P<0..15>
JTAG_SB_TRST_L
FUNC_TEST=TRUE
TP_JTAG_SB_TCK
FUNC_TEST=TRUE
JTAG_NB_TCK
FUNC_TEST=TRUE
FUNC_TEST=TRUE
JTAG_NB_TMS
FUNC_TEST=TRUE
TP_JTAG_VESTA_TCK
FUNC_TEST=TRUE
TP_JTAG_VESTA_TDI
FUNC_TEST=TRUE
TP_JTAG_VESTA_TDO
ENET_RXD<4>
NO_TEST=YES
ENET_RXD<5>
NO_TEST=YES
NO_TEST=YES
HT_NB_REFCLK_H0_R
NO_TEST=YES
HT_SB_REFCLK_R
NO_TEST=YES
HT_NB_REFCLK_L0_R
EI_CPU_TO_NB_SR_P<1>
NO_TEST=YES
EI_CPU_TO_NB_SR_N<1>
NO_TEST=YES
EI_CPU_SYSCLK_P
NO_TEST=YES
NO_TEST=YES
UATA_DD<12>
NO_TEST=YES
TP_CPU_TRIGGER_OUT
NO_TEST=YES
CPU_SPARE2
UATA_DD<13>
NO_TEST=YES
NO_TEST=YES
EI_NB_TO_CPU_SR_P<0>
97
97
97
97
97
97
97
97
97
97
56
56
56
56
56
84
84
84
84
97
97
97
132
47
97
97
84
84
84
84
84
97
97
97
97
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
132
84
56
56
56
43
43
47
89
43
43
43
56
82
82
97
97
82
82
82
82
97
129
129
129
82
101
43
131
131
43
47
43
43
43
30
30
82
82
82
101
97
82
82
82
82
82
82
82
82
97
56
56
56
101
101
97
97
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
131
97
131
131
131
131
82
24
30
30
131
131
43
43
56
129
47
129
43
26
26
9
9
26
26
26
26
43
88
26
26
26
26
26
26
26
9
9
26
26
9
43
26
26
9
9
84
84
9
9
9
9
82
101
98
98
98
127
127
127
55
12
12
12
13
13
93
26
26
26
56
56
26
26
9
98
8
130
130
98
30
43
30
30
30
20
20
20
20
17
17
20
20
139
132
139
139
132
132
144
56
56
139
139
101
9
9
9
98
84
101
93
136
93
59
9
9
9
9
9
55
55
13
9
101
9
9
101
82
43
43
43
101
101
101
101
101
98
98
84
82
8
154
44
24
31
31
30
12
130
26
26
26
26
26
26
93
93
130
31 11
130
139
17
132
132
132
17
132
132
132
17
132
31
130
130
132
31
132
132
132
17
17
17
132
132
132
132
17
17
132
17
132
132
130
130
31
31
101
31
130
130
130
130
130
130
130
130
130
130
56
31
101
31
31
31
31
31
31
31
130
130
130
130
130
130
31
31
11
130
132
136
130
93
130
26
139
132
130
130
12
82
130
130
130
130
9
20
20
20
20
17
17
17
130
130
26
26
26
9
9
43
127
56
43
127
9
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
G
D
S
G
D
S
GND
V+
LM339A
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
HIGH TO ENABLE
2.3A CONTINUOUS
VOUT=VREF*(R903+R905)/R905=1.85VDC
2.7A PEAK
POWER BUDGET CURRENT OF FET
IRU3037ACS VREF=0.8VDC
SET OUTPUT=1.85V FOR FRAMEBUFFER.
7.2A CONTINUOUS
10.9A PEAK
NOTE:
POWER BUDGET CURRENT OF TOTAL RAILS
PLACE LED NEAR VREG
1.8V VOLTAGE REGULATOR
U1100_FEEDBACK
0
805
1/8W
5%
MF-LF
21
R1102
MF-LF
1/16W
1%
402
9.31K
2
1
R1105
1/4W
1%
5.11
1206
MF-LF
2
1
R1104
PP5V_ALL
10%
1UF
CERM
6.3V
402
2
1
C1104
PP12V_ALL
MBR0520LXXG
SOD-123
2 1
D1100
SOD-123
MBR0520LXXG
2 1
D1101
SOD-123
MBR0520LXXG
2
1
D1102
CERM
20%
25V
805
1UF
2
1
C1117
50V
0.0018UF
402
CERM
10%
2
1
C1105
805
CERM
25V
20%
1UF
2
1
C1116
PP1V8_PWRON
PP1V8_RUN
220PF
25V
5%
CERM
402
2
1
C1106
CRITICAL
1.5UH
IHLP
21
L1101
SOI-LF
IRU3037ACS
2 6
8
3
5
4
1
7
U1100
12.4K
402
MF-LF
1/16W
1%
2
1
R1103
CERM
603
25V
20%
0.1UF
2
1
C1115
MF-LF
1/16W
1%
402
9.31K
2
1
R1101
50V
CERM
5%
100PF
805
2
1
C1113
603
NOSTUFF
3300PF
10%
CERM
50V
2
1
C1107
CERM
50V
6800PF
10%
603
2
1
C1114
4.7
805
1/8W
MF-LF
5%
2
1
R1100
SO-8
IRF7413PBF
321
4
8765
Q1103
PP12V_RUN
2N7002
SOT23-LF
2
1
3
Q1140
402
5%
MF-LF
1/16W
470K
2
1
R1140
CERM
50V
5%
1000PF
1206
2
1
C1112
CASE369-LF
NTD60N02R
3
1
4
Q1101
CASE369-LF
NTD60N02R
3
1
4
Q1102
20%
ELEC
TH-MCZ
16V
680UF
2
1
C1102
20%
ELEC
TH-MCZ
16V
680UF
2
1
C1103
CERM
10UF
10%
16V
1210
2
1
C1111
CERM
0.001UF
20%
50V
402
2
1
C1140
TH-MCZ
1500UF
20%
ELEC
6.3V
2
1
C1109
DEVELOPMENT
330
MF-LF
402
1/16W
5%
2
1
R1160
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
2
1
LED1100
CERM
20%
6.3V
1206
10UF
C1110
PP1V8_RUN
SOI-LF
DEVELOPMENT
3
14
9
8
12
U1201
PP3V3_RUN
SOT23-LF
2N7002
2
1
3
Q1100
SM
21
XW1100
330UF
20%
CASE-D2E-LF
POLY
2.5V-ESR9V
NOSTUFF
2
1
C1119
SYNC_DATE=06/20/2005
SYNC_MASTER=M33-PC
1.8V VREG
051-6863
F
11
154
Q1101,Q1102
376S0340 376S0388
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1100_GATE_L
GND_U1100
U1100_COMP
VOLTAGE=0 V
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
GND_U1100
Q1102_DRAIN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
Q1101_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
GND_U1100
PWRON_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_VC
SYS_SLEEP
R904_P2
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_VC_D
LED_PP1V8_RUN_P
LED_PP1V8_RUN_N
1V1_REF
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1100_VC_R
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1100_GATE_H
Q903_GATE
R1101_P2
U1100_SS
U1100_FEEDBACK
54 30 26
16
16
15
15
85
11
11
11
13
13
13
6
6
6
12
12
9
9
12
G
D
S
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
GND
V+
LM339A
G
D
S
CONT
NOISE
VIN
VOUT
GND
S
G
D
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
SO THAT 1.5V IS THE FIRST RAIL UP ON KODIAK
TURNING ON PP2V5_PWRON WITH 1V2_PWRON
PP1V5_PWRON_PULSAR
RDSON=0.012 OHM
KODIAK CORE VOLTAGE REGULATOR
1.25V R1205=3.65K
VOUT=VREF*(R1203+R1205)/R1205=1.25VDC
IRU3037ACS VREF=0.8VDC
1.35V R1205=2.87K
PLACE LED NEAR VREG
8.5A PEAK CURRENT DRAW
NOTE:
1.3A PEAK CURRENT DRAW
U1200_FEEDBACK
LOAD FROM POWER BUDGET
@ VGS=3.5 V
LOAD FROM POWER BUDGET
1.30V R1205=3.24K
7.2A CONTINUOUS CURRENT DRAW
1.0A CONTINUOUS CURRENT DRAW
10UF
10%
16V
CERM
1210
2
1
C1201
TH-MCZ
6.3V
20%
1500UF
ELEC
CRITICAL
2
1
C1209
TH-MCZ
20%
6.3V
1500UF
ELEC
CRITICAL
2
1
C1208
1%
2.87K
402
1/16W
MF-LF
2
1
R1205
1UF
10V
20%
CERM
603
NOSTUFF
2
1
C1207
5%
CERM
1206
50V
1000PF
2
1
C1212
PP5V_ALL
CRITICAL
NTD60N02R
CASE369-LF
3
1
4
Q1201
402
50V
CERM
10%
0.0018UF
2
1
C1205
5%
MF-LF
1/8W
805
0
21
R1202
10%
6.3V
402
1UF
CERM
2
1
C1204
5%
402
CERM
25V
220PF
2
1
C1206
PP12V_ALL
CERM
16V
20%
603
0.1UF
2
1
C1214
1UF
10%
25V
X5R
603
2
1
C1216
20%
805
1UF
25V
CERM
2
1
C1217
SOD-123
MBR0520LXXG
2 1
D1200
SOD-123
MBR0520LXXG
2 1
D1201
MBR0520LXXG
SOD-123
2
1
D1202
CASE369-LF
NTD60N02R
CRITICAL
3
1
4
Q1202
1.53UH
SM
CRITICAL
3
2
1
L1201
1206
1%
1/4W
MF-LF
5.11
2
1
R1204
SOI-LF
IRU3037ACS
CRITICAL
2 6
8
3
5
4
1
7
U1200
2.05K
1/16W
1%
402
MF-LF
2
1
R1203
MF-LF
1%
1/16W
402
15.8K
2
1
R1201
10%
50V
CERM
603
6800PF
2
1
C1215
5%
CERM
402
50V
56PF
2
1
C1213
10
5%
805
MF-LF
1/8W
2
1
R1200
PP1V5_RUN
0.1UF
20%
10V
CERM
402
2
1
C1250
SOT23-LF
2N7002
2
1
3
Q1251
PP5V_PWRON
1/16W
100K
402
MF-LF
5%
2 1
R1250
TH-MCZ
16V
680UF
ELEC
20%
2
1
C1202
CERM
10%
16V
1210
10UF
2
1
C1210
5%
1/16W
MF-LF
330
402
DEVELOPMENT
2
1
R1260
GREEN-3.6MCD
DEVELOPMENT
2.0X1.25MM-SM
2
1
LED1200
SOI-LF
DEVELOPMENT
3
1
7
6
12
U1201
402
0
5%
MF-LF
1/16W
DEVELOPMENT
21
R1261
6.3V
10UF
10%
X5R
805
2
1
C1218
PP1V5_PWRON
PP1V5_PWRON
PP3V3_RUN
SOT23-LF
2N7002
2
1
3
Q1200
402
5%
0
1/16W
MF-LF
NOSTUFF
21
R1206
MF-LF
1/16W
402
5%
0
21
R1207
6.3V
X5R
10%
10UF
805
2
1
C1272
402
20%
CERM
16V
0.01UF
2
1
C1271
MM1571FN
SOT-25A
CRITICAL
U1270
5%
1/16W
10K
402
MF-LF
2
1
R1270
10V
1UF
20%
CERM
805
2
1
C1270
PP3V3_PWRON
SM
21
XW1200
SOT23
IRLM2402PBF
DEVELOPMENT
2
1
3
Q1271
DEVELOPMENT
2N7002
SOT23-LF
2
1
3
Q1270
402
MF-LF
1/16W
10K
DEVELOPMENT
5%
2
1
R1273
DEVELOPMENT
402
MF-LF
1/16W
10K
5%
2
1
R1274
PP12V_RUN
SI3446DV
TSOP-LF
CRITICAL
4
36
5
2
1
Q1250
402
16V
DEVELOPMENT
0.01UF
20%
CERM
2 1
C1275
SYNC_DATE=10/07/2005
154
12
F
051-6863
1.5V Vreg
SYNC_MASTER=FINO-M23
376S0388376S0340
Q1201,Q1202
R2204_P2
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
LED_PP1V5_RUN_N
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP1V5_RUN_PULSAR
NC_PP1V5_PULSAR
MAKE_BASE=TRUE
SYS_POWERUP_L
LED_PP1V5_RUN_P
PWRON_L
TURN_ON_PP1V5_L
TURN_ON_PP1V2_L
R1201_P2
MIN_NECK_WIDTH=0.25MM
U1200_VC
MIN_LINE_WIDTH=0.45MM
GND_U1200
Q1201_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1270_CONT
PP1V5_RUN_FOR_LED
U1270_NOISE
1V1_REF
Q1250G
MIN_LINE_WIDTH=0.6MM
Q1202_DRAIN
MIN_NECK_WIDTH=0.2MM
U1200_SS
U1200_COMP
U1200_GATE_H
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1200_GATE_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1200_VC_R
PP1V5_PWRON_PULSAR
PULSAR_1V5_RUN_SWITCH
SYS_SLEEP
GND_U1200
VOLTAGE=0 V
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1200_FEEDBACK
GND_U1200
MIN_LINE_WIDTH=0.45MM
U1200_VC_D
MIN_NECK_WIDTH=0.25MM
54 30
85
26
50
16
16
28
15
85
15
7
13
13
12
13
13
12
12
9
9
6
9
11
4
6
9
11
7
9
11
6
6
G
D
S
G
D
S
FB
LD
HD
GND
COMP
SS
VCC
VC
G
D
S
GND
V+
LM339A
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.0A CONTINUOUS
@ VGS=2.5 V
RDSON=0.04 OHM
2.6A CONTINUOUS
@ VGS=2.5 V
PP1V2_PWRON FET SWITCH
RDSON=0.04 OHM
SET OUTPUT=1.22-1.23V
U1300_FEEDBACK
VOUT=VREF*(R1003+R1005)/R1005=1.22-1.23VDC
IRU3037ACS VREF=0.8VDC
NOTE:
PLACE LED NEAR VREG
POWER BUDGET CURRENT OF TOTAL RAILS
3.2A PEAK
PP1V2_PWRON COMES UP BEFORE GPU_POWERUP_L SO THAT SHASTA CORE GETS POWER BEFORE ANYTHING ELSE
PEAK CURRENT 1.3A
PP1V2_ALL VOLTAGE REGULATOR
PEAK CURRENT 1.3A IF KODIAK 1.2V CAN BE TURNED OFF IN SLEEP. 0.6A/M33 0.0A/M23 IF NOT
PP1V2_RUN FET SWITCH
NOSTUFF
5%
0
1/16W
MF-LF
402
21
R1314
47K
5%
1/16W
MF-LF
402
DEVELOPMENT
21
R1315
PP1V2_ALL
PP1V2_ALL
PP1V2_ALL
PP3V3_RUN
PP5V_RUN
PP3V3_RUN
CERM
20%
402
16V
0.01UF
DEVELOPMENT
2
1
C1320
SM2
3.8UH
21
L1301
SOT23-LF
2N7002
DEVELOPMENT
2
1
3
Q1304
2N7002
NOSTUFF
SOT23-LF
2
1
3
Q1307
NOSTUFF
1%
MF-LF
402
10K
1/16W
2
1
R1306
SM
21
XW1300
0.01UF
402
20%
CERM
16V
2
1
C1321
20%
16V
CERM
402
0.01UF
DEVELOPMENT
21
C1322
3300PF
10%
CERM
603
50V
NOSTUFF
2
1
C1307
1/16W
1%
MF-LF
402
10K
2
1
R1305
MF-LF
1/4W
1%
5.11
1206
2
1
R1304
CERM
50V
5%
1000PF
1206
2
1
C1312
SOD-123
MBR0520LXXG
2
1
D1302
PP12V_ALL
25V
805
20%
CERM
1UF
2
1
C1317
402
10%
0.0018UF
CERM
50V
2
1
C1305
MBR0520LXXG
SOD-123
2 1
D1300
SOD-123
MBR0520LXXG
2 1
D1301
805
MF-LF
1/8W
5%
0
21
R1300
805
25V
1UF
20%
CERM
2
1
C1300
220PF
CERM
5%
25V
402
2
1
C1306
1UF
10%
6.3V
402
CERM
2
1
C1304
IRU3037ACS
SOI-LF
CRITICAL
2 6
8
3
5
4
1
7
U1300
1800UF
20%
ELEC
6.3V
TH-KZJ-LF
CRITICAL
2
1
C1309
5.36K
402
MF-LF
1/16W
1%
2
1
R1303
PP1V2_RUN
PP5V_ALL
1/16W
MF-LF
5%
402
100K
DEVELOPMENT
2 1
R1308
PP5V_ALL
SI3446DV
TSOP-LF
CRITICAL
4
3 6
5
2
1
Q1306
PP1V2_PWRON
2N7002
SOT23-LF
2
1
3
Q1305
1/16W
5%
MF-LF
402
100K
2 1
R1309
PP5V_ALL
402
25V
10%
0.0068UF
CERM
2
1
C1314
402
56PF
5%
50V
CERM
2
1
C1313
603
16V
CERM
20%
0.1UF
2
1
C1315
5%
18K
1/16W
MF-LF
402
2
1
R1301
5%
MF-LF
1/16W
0
402
21
R1312
402
MF-LF
NOSTUFF
1/16W
5%
0
21
R1313
805
4.7
5%
1/8W
MF-LF
2
1
R1302
SO-8
IRF7807ZPBF
CRITICAL
321
4
8765
Q1301
IRF7807ZPBF
SO-8
CRITICAL
321
4
8765
Q1302
1210
10UF
CERM
16V
10%
2
1
C1302
1210
10UF
CERM
16V
10%
2
1
C1303
TSOP-LF
SI3446DV
DEVELOPMENT
CRITICAL
4
3 6
5
2
1
Q1303
10UF
16V
10%
CERM
1210
2
1
C1301
DEVELOPMENT
SOI-LF
3
2
5
4
12
U1201
402
330
DEVELOPMENT
MF-LF
1/16W
5%
2
1
R1350
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
2
1
LED1300
MF-LF
1/16W
5%
100K
402
DEVELOPMENT
2
1
R1351
1/16W
5%
47K
402
DEVELOPMENT
MF-LF
2
1
R1352
5%
DEVELOPMENT
402
1/16W
MF-LF
0
21
R1353
CERM
10V
20%
402
DEVELOPMENT
0.1UF
2
1
C1350
1.2V Vreg
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
154
13
F
051-6863
U1300_FEEDBACK
PP1V2_RUN_FOR_LED
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_GATE_L
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
Q1302_DRAIN
Q1305_G
Q1006_G
PWRON_L
U1300_SS
GPU_POWERUP_L
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
Q1301_GATE
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_GATE_H
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.45MM
U1300_VC_R
MIN_NECK_WIDTH=0.25MM
R1304_P2
MIN_LINE_WIDTH=0.45MM
MIN_LINE_WIDTH=0.45MM
U1300_VC
MIN_NECK_WIDTH=0.25MM
R1301_P2
LED_PP1V2_RUN_N
LED_PP1V2_RUN_P
TURN_ON_PP1V2_L
U1300_COMP
VOLTAGE=0 V
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
GND_U1300
TURN_ON_PP1V2_L
Q1304_G
GND_U1300
1V1_REF
GND_U1300
MIN_LINE_WIDTH=0.45MM
MIN_NECK_WIDTH=0.25MM
U1300_VC_D
Q1003_G
SYS_SLEEP
54 30 26
16
16
15
13
13
85
15
12
12
13
12
13
12
13
12
9
11
85
9
9
4
6
4
6
11
6
11
G
D
S
G
D
S
G
D
S
EN
GND
IN
OUT
ADJ
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE:
PEAK CURRENT 0.1A
0.2A PEAK
POWER BUDGET CURRENT OF TOTAL RAILS
@ VGS=2.5 V
PP2V5_RUN FET SWITCH
SET OUTPUT=2.5V
IRU3037CS VREF=1.24VDC
VOUT=VREF*(R1581+R1582)+1=5.505VDC
NOSTUFF OPTION TO DELAY 2.5V PWRON TO COME UP WITH 3.3V PWRON
0.1A CONTINUOUS
RDSON=0.04 OHM
PP2V5_ALL VOLTAGE REGULATOR
RDSON=0.04 OHM
@ VGS=2.5 V
PEAK CURRENT 0.1A
PP2V5_PWRON FET SWITCH
6.3V
CERM
1206
20%
10UF
2
1
C1580
PP2V5_ALL
PP3V3_ALL
PP2V5_ALL
PP2V5_ALL
0.01UF
20%
402
CERM
16V
2
1
C1581
20%
16V
CERM
402
0.01UF
21
C1582
PP2V5_RUN
SOT-363
2N7002DW-X-F
4
5
3
Q1504
2N7002DW-X-F
SOT-363
1
2
6
Q1504
PP5V_ALL
5%
100K
402
1/16W
MF-LF
2 1
R1508
SI3446DV
TSOP-LF
CRITICAL
4
3 6
5
2
1
Q1506
PP2V5_PWRON
2N7002
SOT23-LF
2
1
3
Q1505
5%
MF-LF
1/16W
402
100K
2 1
R1509
PP5V_ALL
NOSTUFF
402
0
1/16W
MF-LF
5%
21
R1512
0
5%
1/16W
MF-LF
402
21
R1513
SI3446DV
TSOP-LF
CRITICAL
4
3 6
5
2
1
Q1503
330UF
6.3V
ELEC
20%
CRITICAL
6.3X8-SM
2
1
C1583
1%
1/16W
MF-LF
402
1.02K
2
1
R1581
1/16W
1%
402
1K
MF-LF
2
1
R1582
SOP-8-LF
MIC39102
CRITICAL
3
2
8765
1
4
U1580
402
5%
3.3K
1/16W
MF-LF
2
1
R1580
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
154
15
F
051-6863
2.5V Vreg
U1580_ADJ
Q1506_G
Q1505_G
PWRON_L
SYS_SLEEP
TURN_ON_PP3V3_PWRON_L
Q1503_G
U1580_EN
54 30 26
16
16
13
13
12
12
16
11
11
4
G
D
S
G
D
S
02
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
POWER SEQUENCING PIN TO DELAY TO BRING UP 3.3V LAST FOR SHASTA
IRF7413PBF
SO-8
CRITICAL
321
4
8765
Q1600
1/16W
MF-LF
402
47K
5%
2
1
R1600
1/16W
402
3.6K
5%
MF-LF
2
1
R1602
SO-8
CRITICAL
IRF7413PBF
321
4
8765
Q1602
402
5%
MF-LF
1/16W
3.6K
2
1
R1607
1/16W
402
5%
47K
MF-LF
2
1
R1601
SOT-363
2N7002DW-X-F
4
5
3
Q1601
2N7002DW-X-F
SOT-363
1
2
6
Q1601
CERM
402
0.01UF
20%
16V
2
1
C1600
CERM
20%
0.1UF
10V
402
2
1
C1601
SOT23-5-LF
SN74LVC1G02
4
5
3
2
1
U1601
PP12V_ALL
PP5V_ALL
PP3V3_ALL
PP12V_ALL
PP5V_PWRON
PP3V3_ALL
PP3V3_PWRON
5%
MF-LF
0
1/16W
402
2
1
R1604
NOSTUFF
402
0
1/16W
5%
MF-LF
21
R1603
20%
0.1UF
402
CERM
10V
2
1
C1603
SOT23-LF
2N7002
2
1
3
Q1603
10K
1/16W
402
5%
MF-LF
2
1
R1605
NOSTUFF
402
5%
MF-LF
1/16W
10K
2
1
R1608
NOSTUFF
1/16W
MF-LF
5%
402
3.3K
2
1
R1609
SYNC_MASTER=FINO-M23
051-6863
F
16
154
SYNC_DATE=08/26/2005
5V & 3.3V Fets
Q1601G
TURN_ON_PP3V3_PWRON_L
GATE_5V_PWRON
SYS_POWERUP_L_BUF
PP3V3_RUN
SYS_SLEEP
PWRON_L
SYS_POWERUP
GATE_3V3_PWRON
54 30 26 15
15
13
13
15
96
7
12
12
4
7
6
11
11
RESET*
TDI
DVDD
VESTA MISC
1 OF 3
PVDD
AVDDL
AVDD
GND
AGND
OVDD
REGSUP1
REGSEN1
REGCTL1
REGSUP2
REGSEN2
REGCTL2
2.5V_EN
DNC
DNC
TDO
TCK
TMS
TRST*
NC
NC
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Page Notes
IPU
IPU
VESTA HAS INTERNAL PULLUPS. MLB
PULLUPS MAY BE NOSTUFFED IN EVT.
To keep Vesta from being held
IPU
IPU
IPU
0 - OVDD=3.3V
1 - OVDD=2.5V
2.5V_EN
WHEN OVDD=2.5V GMII PINS ARE NOT 3.3V TOLERANT
IPD
SCHMITT TRIGGER W/ INTERNAL PULLUP
M23: PP3V3_ENETFW IS AN ALL RAIL
M23: PP3V3_ENETFW IS AN ALL RAIL
VESTA JTAG
(NONE)
regulator will be in continuous mode.
Signal aliases required by this page:
Controls operating mode of Vesta 1.2V
Power aliases required by this page:
regulator. If both options are off the
NC
NC
L9/M9 N5/N6
N9/N10
M23: ADDED C1726 AND C1744 PER BROADCOM RECOMMENDATIONS
in reset when system is off
NOTE: Reset GPIO is active HIGH
L6/M6
BOM options provided by this page:
- VESTA1V2_BURST / VESTA1V2_PULSE
RESET ASSERT REQUIREMENT IS 20MS TO 100MS
10V
402
CERM
0.1uF
20%
2
1
C1710
402
CERM
10V
20%
0.1uF
2
1
C1711
402
10V
20%
CERM
0.1uF
2
1
C1712
20%
10V
CERM
402
0.1uF
2
1
C1713
CERM
20%
10V
402
0.1uF
2
1
C1703
10V
CERM
402
20%
0.1uF
2
1
C1702
402
10V
20%
CERM
0.1uF
2
1
C1701
20%
10V
0.1uF
402
CERM
2
1
C1700
402
CERM
10V
20%
0.1uF
2
1
C1722
10V
CERM
402
20%
0.1uF
2
1
C1725
CERM
10V
402
20%
0.1uF
2
1
C1721
402
CERM
10V
20%
0.1uF
2
1
C1724
0.1uF
402
CERM
10V
20%
2
1
C1731
0.1uF
20%
10V
CERM
402
2
1
C1730
10V
CERM
402
20%
0.1uF
2
1
C1720
10V
CERM
402
20%
0.1uF
2
1
C1723
0.1uF
402
CERM
10V
20%
2
1
C1743
402
20%
10V
CERM
0.1uF
2
1
C1742
402
CERM
10V
0.1uF
20%
2
1
C1741
0.1uF
402
CERM
10V
20%
2
1
C1740
805
10%
10UF
X5R
6.3V
2
1
C1708
FERR-EMI-600-OHM
SM
21
L1700
VESTA-V1.3
FBGA-200-LF
SEE_TABLE
D8
E8
E10
D7
E7
H4
E2
E1
F2
F1
G4
G5
N4
A15
K1
F15
A7
A1
M13
C3
K2
J2
F14
C14
B7
B2
A2
J1
C15
B15
B1
E9
C9
N10
N9
N6
N5
M9
M6
L9
L6
R12
R3
P11
P10
P5
P4
N8
N7
M8
M7
L8
L7
J12
J11
P9
P8
P7
P6
H12
H11
M3
U1701
5%
1/16W
MF-LF
402
1K
2
1
R1740
402
MF-LF
1/16W
5%
1K
2
1
R1743
402
MF-LF
1/16W
5%
1K
2
1
R1742
402
MF-LF
1/16W
5%
1K
2
1
R1741
10UF
10%
X5R
6.3V
805
2
1
C1726
805
X5R
10%
10UF
6.3V
2
1
C1744
0
5%
1/16W
402
MF-LF
NOSTUFF
21
R1720
402
CERM
10%
1UF
6.3V
2
1
C1750
47K
MF-LF
402
5%
1/16W
2
1
R1751
SOT-363
2N7002DW-X-F
1
2
6
Q1750
10K
5%
MF-LF
402
1/16W
2
1
R1750
SOT-363
2N7002DW-X-F
4
5
3
Q1750
10UF
805
6.3V
X5R
10%
2
1
C1714
10K
1/16W
402
MF-LF
5%
2
1
R1752
Vesta Core / Misc
051-6863
F
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
17
154
=PP1V2_ENETFW
VESTA_RESET_L
=PP2V5_ENETFW
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.50 MM
PP1V2_VESTA_AVDDL
MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDO
=JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L
VESTA_RESET_RC
=PP3V3_ENETFW
VESTA_RESET_H
ENETFW_RESET
=PP3V3_ENETFW
MAKE_BASE=TRUE
TP_JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L
=JTAG_VESTA_TCK
=JTAG_VESTA_TDO
TP_VESTA_2_5V_EN
TP_VESTA_REGCTL1
TP_VESTA_REGSUP1
TP_VESTA_REGSEN1
TP_VESTA_REGCTL2
TP_VESTA_REGSUP2
TP_VESTA_REGSEN2
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
=JTAG_VESTA_TCK
=JTAG_VESTA_TDI
=JTAG_VESTA_TDO
MAKE_BASE=TRUE
TP_JTAG_VESTA_TCK
=PP3V3_ENETFW
=JTAG_VESTA_TDI
=PP3V3_ENETFW
=PP3V3_ENETFW
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDI
MAKE_BASE=TRUE
TP_JTAG_VESTA_TRST_L
=JTAG_VESTA_TMS
139
139
139
139
139
139
139
132
132
132
132
132
132
132
17
17
17
17
17
7
7
9
17
17
7
132
24
7
9
17
17
17
9
9
9
9
9
9
9
9
9
17
17
17
9
7
17
7
7
9
9
17
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
CORE_GND
VDD_CORE
CORE & PCI-E POWER
(9 OF 10)
(1.6V-1.2V)
PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
DRAWING
Q63 = PP1V6
1.6V
2
PAGE 19
KODIAK CORE
KODIAK-ASIC-040812
BGA
SEE_TABLE
U15
T20
T16
R22
R18
R14
P21
AC22
AC18
AC14
AB21
AB17
AA23
P17
AA19
AA15
Y20
Y16
W22
W18
W14
V21
V17
U19
N15
U14
T21
T17
R23
R19
R15
P20
AC23
AC19
AC15
AB20
AB16
AA22
P16
AA18
AA14
Y21
Y17
W23
W19
W15
V20
V16
U18
N14
U1900
6.3V
1UF
CERM
402
10%
2
1
C1906
6.3V
1UF
CERM
402
10%
2
1
C1900
6.3V
1UF
CERM
402
10%
2
1
C1905
6.3V
1UF
CERM
402
10%
2
1
C1914
6.3V
1UF
CERM
402
10%
2
1
C1913
6.3V
1UF
CERM
402
10%
2
1
C1919
6.3V
1UF
CERM
402
10%
2
1
C1924
6.3V
1UF
CERM
402
10%
2
1
C1918
6.3V
1UF
CERM
402
10%
2
1
C1923
6.3V
1UF
CERM
402
10%
2
1
C1912
6.3V
1UF
CERM
402
10%
2
1
C1911
6.3V
1UF
CERM
402
10%
2
1
C1917
6.3V
1UF
CERM
402
10%
2
1
C1922
6.3V
1UF
CERM
402
10%
2
1
C1916
6.3V
1UF
CERM
402
10%
2
1
C1921
6.3V
1UF
CERM
402
10%
2
1
C1910
6.3V
1UF
CERM
402
10%
2
1
C1915
6.3V
1UF
CERM
402
10%
2
1
C1920
6.3V
1UF
CERM
402
10%
2
1
C1904
P4MM
SM
1
PP1900
6.3V
1UF
CERM
402
10%
2
1
C1909
6.3V
1UF
CERM
402
10%
2
1
C1903
6.3V
1UF
CERM
402
10%
2
1
C1908
6.3V
1UF
CERM
402
10%
2
1
C1902
6.3V
1UF
CERM
402
10%
2
1
C1907
6.3V
1UF
CERM
402
10%
2
1
C1901
F
051-6863
19
154
SYNC_DATE=08/26/2005
SYNC_MASTER=Q63
KODIAK CORE & BYPASS
=PPVCORE_PWRON_NB
LAST_MODIFIED=Tue Nov 1 13:46:17 2005
7
PP
PP
ADD1
ADD0
ALERT
SMBDATA
SMBCLK
VCC
NC_5
NC_1
STBY
DXP
NC_16
GND
NC_9
NC_13
DXN
(SYM_VER2)
PMR_CLK_STOP_L
CE1_LT_TCK
CE1_B_TDO
CE1_DI1_TMS
CE1_MC_TDI
CE1_DI2_TRST
CE0_TEST
SYS_THDIO_D
SYS_THDIO_G
VD5_0
VD5_1
VD5_2
NORTH_BRIDGE_RESET_L
HRESET_L
SUSPENDACK_L
SUSPENDREQ_L
SYS_ISCL0
SYS_ISCA0
SYS_ISCA1
SYS_ISCL1
API_ISCA
API_ISCL
PMR_CLK_P
PMR_CLK_N
(10 OF 10)
POWER/TEST/MISC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NEED TO CHECK ALL I2C ADDRESSES
PMR_CLK_STOP CAN BE USED TO STOP ALL CLOCKS IN KODIAK
NOTE:
ON PAGE 24 )
SHASTA GPIO TERMINATIONS
PLACE TERM R/C CLOSE TO KODIAK
NOTE: LOW = DISABLE PMR_CLK
KODIAK JTAG_TRST PULLED HIGH
AND SYS_IO_RESET_L (SMU)
PCI_RESET_L IS AN ’AND’ OF SB_PCI_RESET_L (SB)
THESE PINS HAVE INTERNAL PULLUPS OR PULLDOWNS
PLACE R2012 IN AN ACCESSIBLE LOCATION
C2055 ADDED FOR KODIAK RAM DECOUPLING
PAGE 58 IS SHORT ONE CAP
KODIAK ALIASES
1 | 0 | 98/99
hiZ | 1 | 56/57
1 | hiZ| 9A/9B
A0 | A1 | ADDR
----+----+------
0 | 0 | 30/31
0 | hiZ| 32/33
0 | 1 | 34/35
hiZ | 0 | 52/53
1 | 1 | 9C/9D
hiZ | hiZ| 54/55
TO ALLOW SMU DEBUG ACCESS
(SOME OF THESE ARE NOSTUFF
SHASTA ALIASES
SHASTA JTAG
NB_OVERTEMP
PLACE BY IC
USED FOR DEBUG
1UF
402
CERM
6.3V
10%
2
1
C2052
402
CERM
6.3V
10%
1UF
2
1
C2051
CERM
402
1UF
10%
6.3V
2
1
C2050
1.5PF
402
CERM
NOSTUFF
50V
+/-0.25PF
2
1
C2053
402
5%
MF-LF
0
1/16W
2
1
R2000
402
1/16W
1%
MF-LF
60.4
NOSTUFF
2
1
R2001
402
1/16W
1%
MF-LF
60.4
NOSTUFF
2
1
R2002
402
1/16W
1%
MF-LF
1K
2
1
R2003
NOSTUFF
0
5%
1/16W
402
MF-LF
21
R2012
10K
MF-LF
5%
1/16W
402
2
1
R2013
SM
2
1
XW2000
SM
P4MM
1
TP2000
SM
P4MM
1
TP2002
402
MF-LF
4.7K
5%
1/16W
2
1
R2053
1/16W
MF-LF
402
5%
4.7K
NOSTUFF
2
1
R2054
10K
5%
1/16W
MF-LF
402
21
R2061
10K
5%
1/16W
MF-LF
402
21
R2062
402
MF-LF
1/16W
5%
10K
21
R2063
402
MF-LF
1/16W
5%
10K
21
R2064
0
NOSTUFF
5%
1/16W
MF-LF
402
21
R2074
1/16W
MF-LF
5%
4.7K
402
2
1
R2073
1UF
10%
6.3V
CERM
402
2
1
C2055
1/16W
5%
MF-LF
0
402
NOSTUFF
21
R2087
5%
1/16W
MF-LF
1K
402
NOSTUFF
2
1
R2084
402
5%
1/16W
MF-LF
1K
2
1
R2085
5%
1/16W
MF-LF
1K
402
2
1
R2083
5%
1/16W
MF-LF
1K
NOSTUFF
402
2
1
R2086
CERM
1UF
10%
6.3V
402
2
1
C2080
10%
50V
402
CERM
0.0022UF
21
C2081
CRITICAL
MAX6690MEE
QSOP
2
15
12
14
9
5
16
13
1
87
3
4
11
6
10
U2080
MF-LF
2.2
1/16W
5%
402
21
R2082
BGA
KODIAK-ASIC-040812
AH01
AF05
AF02
G15
F15
AJ05
AK03
AH06
AG04
AJ01
AJ03
AG02
AE09
AE10
AL01
AG01
AG07
AJ04
AK06
AL02
AG05
AG08
AH03
AG03
U1900
KODIAK & SHASTA MISC
051-6863
F
20
154
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
=PCI_ROM_RESET_L
I2C_NB_TEMP_SCL
I2C_NB_TEMP_SDA
TSENSE_NB_ADD0
TSENSE_NB_OVERTEMP_L
TSENSE_NB_ADD1
SYS_OVERTEMP_L
=PP1V8_PWRON_NBMEM
JTAG_SB_TRST_L
JTAG_NB_TCK
NB_PU_RST_L
=PP2V5_PWRON_NB_MISC
JTAG_NB_TRST_L
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
MAKE_BASE=TRUE
NB_SLOT_RESET_L
JTAG_SB_TDI
JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TDO
RAI_EXP_INTR_L<1>
MAKE_BASE=TRUE
TP_JTAG_SB_TDI
NB_PU_RST_L
NB_THERM_A
CE0TEST
JTAG_NB_TRST_L
JTAG_NB_TDO
NB_PMR_CLK_P
NB_HRST_L
I2C_NB_A_SCL
NB_PMR_CLK_N
I2C_NB_C_SCL
I2C_NB_B_SDA
JTAG_NB_TDI
JTAG_NB_TMS
I2C_NB_B_SCL
I2C_NB_A_SDA
I2C_NB_C_SDA
NB_SUSPEND_REQ_L
NB_SUSPEND_ACK_L
TERM_RC
=PP2V5_PWRON_NB_MISC
PCI_RESET_L
MAKE_BASE=TRUE
=PCI_USB2_RESET_L
=PCI_AIRPORT_RESET_L
=GPU_RESET_L
JTAG_SB_TDO
JTAG_SB_TMS
RAI_EXP_INTR_L<3>
MAKE_BASE=TRUE
NC_PMR_CLK_DIS_L
PMR_CLK_DIS_L
NB_THERM_K
NB_PMR_CLK_STOP_L
=PP2V5_PWRON_NB_MISC
=PP3V3_PWRON_SB
PMR_CLK_DIS_L
PP_2V5PWRONNBMISC
RAI_EXP_INTR_L<2>
RAI_EXP_INTR_L<0>
NB_THERM_K
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.25MM
DIFFERENTIAL_PAIR=TSENSE_NB
NET_SPACING_TYPE=TSENSE_DIFPAIR
NET_PHYSICAL_TYPE=10MIL_WIDTH
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.25MM
DIFFERENTIAL_PAIR=TSENSE_NB
NET_PHYSICAL_TYPE=10MIL_WIDTH
NET_SPACING_TYPE=TSENSE_DIFPAIR
NB_THERM_A
MIN_NECK_WIDTH=0.38MM
MIN_LINE_WIDTH=0.38mm
TSENSE_NB_VCC
=PP3V3_RUN_SMU
39
39
39
119
59
30
30
30
56
93
58
28
28
28
24
30
28
39
24
30
30
20
20
30
20
30
27
27
30
30
62
20
119
20
23
28
125
39
39
24
7
9
9
20
7
9
9
24
24
24
9
9
24
9
20
20
9
9
26
39
26
39
39
9
9
39
39
39
30
30
7
92
122
121
84
24
24
24
6
20
20
7
7
20
6
24
24
20
20
7
VIO1
POWER
VDDO33
VDDO25
VIO2
VDDP_KL
VDDC
GND
GND
GND
(1 OF 8)
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
- =PP3V3_PWRON_SB_PCI32 (VIO2) (TO 5V OR 3.3V)
VIO1 TO SAME IF 64-BIT
CONNECT VIO2 TO
NOTE: PCI pads use the VIO supply to meet
different drive timing
spec for 5V vs. 3.3V operation.
BOM options provided by this page:
Must power Shasta VCore rail before any
Total: 3015 mW
Power Sequencing:
(NONE)
(NONE)
PCI, otherwise 3.3V.
For PCI_AD<31..0>
I/O 2.5 - 2.5V - 20 mA ( 60 mW)
ANALOG12 - 1.2V - 600 mA ( 760 mW)
For PCI_AD<63..32>
Signal aliases required by this page:
other Shasta supplies.
appropriate PCI bus voltage and
characteristics required by the PCI
- =PP1V2_PWRON_SB_VCORE
- =PP2V5_PWRON_SB
- =PP3V3_PWRON_SB
- =PP3V3_PWRON_SB_PCI64 (VIO1) (TO 5V OR 3.3V)
Power aliases required by this page:
Page Notes
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
VDDPs - 2.5V - 100 mA ( 250 mW)
DIGITAL - 1.2V - 950 mA (1175 mW)
Shasta max (est 06/30/03) current:
20%
402
CERM
0.1uF
10V
2
1
C2304
20%
402
CERM
0.1uF
10V
2
1
C2305
20%
402
CERM
0.1uF
10V
2
1
C2306
20%
402
CERM
0.1uF
10V
2
1
C2307
20%
402
CERM
0.1uF
10V
2
1
C2308
20%
402
CERM
0.1uF
10V
2
1
C2309
20%
402
CERM
0.1uF
10V
2
1
C2302
20%
402
CERM
0.1uF
10V
2
1
C2301
20%
402
CERM
0.1uF
10V
2
1
C2300
20%
402
CERM
0.1uF
10V
2
1
C2314
20%
402
CERM
0.1uF
10V
2
1
C2313
20%
402
CERM
0.1uF
10V
2
1
C2312
20%
402
CERM
0.1uF
10V
2
1
C2311
20%
402
CERM
0.1uF
10V
2
1
C2310
20%
402
CERM
10V
0.1uF
2
1
C2334
20%
402
CERM
10V
0.1uF
2
1
C2333
20%
402
CERM
0.1uF
10V
2
1
C2339
20%
402
CERM
0.1uF
10V
2
1
C2338
20%
402
CERM
0.1uF
10V
2
1
C2332
20%
402
CERM
0.1uF
10V
2
1
C2331
20%
402
CERM
0.1uF
10V
2
1
C2337
20%
402
CERM
0.1uF
10V
2
1
C2336
20%
402
CERM
0.1uF
10V
2
1
C2330
20%
402
CERM
0.1uF
10V
2
1
C2335
20%
402
CERM
0.1uF
10V
2
1
C2324
20%
CERM
0.1uF
10V
402
2
1
C2323
20%
402
CERM
0.1uF
10V
2
1
C2329
20%
CERM
0.1uF
10V
402
2
1
C2328
20%
402
CERM
10V
0.1uF
2
1
C2322
20%
402
CERM
0.1uF
10V
2
1
C2321
20%
402
CERM
0.1uF
10V
2
1
C2327
20%
402
CERM
10V
0.1uF
2
1
C2326
20%
402
CERM
0.1uF
10V
2
1
C2320
20%
402
CERM
0.1uF
10V
2
1
C2325
20%
402
CERM
0.1uF
10V
2
1
C2351
20%
402
CERM
0.1uF
10V
2
1
C2350
20%
402
CERM
0.1uF
10V
2
1
C2357
20%
402
CERM
0.1uF
10V
2
1
C2356
20%
402
CERM
0.1uF
10V
2
1
C2355
20%
402
CERM
0.1uF
10V
2
1
C2362
20%
402
CERM
0.1uF
10V
2
1
C2361
20%
402
CERM
0.1uF
10V
2
1
C2360
20%
402
CERM
0.1uF
10V
2
1
C2365
BGA-LF
SHASTA
SEE_TABLE
V1.1
Y19
W22
L21
K21
H17
H18
V8
D1
B5
B2
B1
AB6
AB2
AB10
AA3
W4
V7
U9
U12
R2
M1
L7
H1
F8
F4
AA2
AA1
G15
D19
P15
N8
M15
L8
L15
K8
J15
J12
T15
T10
R9
R12
R10
H8
H15
D2
C19
AB22
AB1
W5
W19
U22
U13
U10
T12
R19
P9
P4
AA6
P14
P13
P12
P10
N9
N22
N13
N12
N11
N10
AA10
M2
M14
M13
M12
M11
M10
L9
L16
L14
L13
A5
L12
L11
L10
K9
K7
K13
K12
K11
K10
J22
A22
J16
J14
J13
J11
J10
H9
H2
F7
F3
E22
A2
A1
U2300
SM
2
1
XW2304
SM
2
1
XW2303
SM
2
1
XW2300
P4MM
SM
1
PP2300
SM
P4MM
1
PP2303
P4MM
SM
1
PP2304
20%
402
CERM
0.1uF
10V
2
1
C2303
TITLE=KILOHANA
ABBREV=DRAWING
Shasta Core Power
SYNC_DATE=08/26/2005
SYNC_MASTER=Q63
F
051-6863
154
23
=PP2V5_PWRON_SB
PP_1V2PWRONSBVCORE
=PP3V3_PWRON_SB_PCI32
=PP2V5_PWRON_SB
=PP1V2_PWRON_SB_VCORE
=PP3V3_PWRON_SB_PCI64
PP_3V3PWRONSBPCI64
=PP3V3_PWRON_SB
PP_2V5PWRONSB
NO_TEST=YES
LAST_MODIFIED=Tue Nov 1 13:46:20 2005
138
138
119
119
119
56
24
24
24
23
23
20
7
6
7
7
7
7
6
7
6
GND
PLL_49
GND
XTAL_18 PLL_45
GND
VIO
PME
PLL_49
VDD
PLL_45
VDD
XGI
XTALS
TEST
PWR_MGT
PCI
GPIO
I2C
I2S2 I2S1 I2S0
(2 OF 8)
PCI1C_BE_4_L
PCI1C_BE_5_L
PCI1C_BE_6_L
PCI1C_BE_7_L
PCI1PAR64_H
XGI_DTI_H
XGI_DTO1_H
XGI_CLK_H
XGI_DTO0_H
PCI1ACK64_L
PCI1REQ64_L
PCI1AD_60_H
PCI1AD_63_H
PCI1AD_62_H
PCI1AD_61_H
PCI1AD_50_H
PCI1AD_52_H
PCI1AD_53_H
PCI1AD_51_H
PCI1AD_59_H
PCI1AD_58_H
PCI1AD_57_H
PCI1AD_56_H
PCI1AD_55_H
PCI1AD_54_H
PCI1AD_40_H
PCI1AD_41_H
PCI1AD_42_H
PCI1AD_43_H
PCI1AD_44_H
PCI1AD_49_H
PCI1AD_48_H
PCI1AD_47_H
PCI1AD_46_H
PCI1AD_45_H
PCI1AD_39_H
PCI1REQ_5_L
PCI1AD_32_H
PCI1AD_34_H
PCI1AD_38_H
PCI1AD_37_H
PCI1AD_36_H
PCI1AD_33_H
PCI1AD_35_H
PCI1GNT_5_L
PCI1GNT_4_L
PCI1REQ_4_L
PCI1GNT_3_L
PCI1REQ_3_L
XTAL_18XTAL
VDD VDD
FSTEST
XTAL_18_I
XTAL_18_O
XTALI
XTALO
PLLTEST
TEST_MODE_H
TDI
TCK
TMS
TDO
INTRWD_H
I2CDATA_H
I2CCLK_H
PCI_SEL32BIT_H
GPIO_H_3
GPIO_H_2
GPIO_H_1
I2S2SYNC_H
I2S2BITCLK_H
I2S2MCLK_H
I2S2DTO_H
I2S2DTI_H
GPIO_H_0
I2S1DTO_H
I2S1MCLK_H
I2S1BITCLK_H
I2S1SYNC_H
I2S1DTI_H
I2S0BITCLK_H
I2S0SYNC_H
I2S0DTI_H
I2S0DTO_H
I2S0MCLK_H
RESET_L
STOPXTALS_L
SUSPENDREQ_L
SUSPENDACK_L
PCI1PME_L
TRST_L
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE R2402 CLOSE TO SHASTA
AUDIO GPIO - see note on right
NorthBridge / SouthBridge MPIC Routing
DIFFERENTIAL_PAIR
DO NOT swap between RPAKs
ELECTRICAL_CONSTRAINT_SET
- _PP2V5_PWRON_SB
- _PP3V3_PCI
Power aliases required by this page:
Signal aliases required by this page:
BOM options provided by this page:
- PCI_64BIT:
- MPIC_NB/MPIC_SB:
Page Notes
- _PP3V3_PWRON_SB
- _PP1V2_PWRON_SB
(NONE)
NOTE: XGC required for Shasta GPIOs
the audio circuit to provide the
NOTE: It is the responsibility of
36
8
14
GPIO
16
24
13
(SCCB)
20
19
21
9
22
15
12
45
26
35
(I2S1_RESET_L)
I2S2: S/P-DIF
NC
46
53
54
52
48
27
34
33
32
30
49
7
(SCCA)
51
(I2S0_DEV_TO_SB_DTI)
6
50
47
31
29
I2S0: Audio DAC
(I2S2_DEV_TO_SB_DTI)
25
28
10
11
17
37
38
39
40
41
42
43
44
AUDIO GPIOS
SPEC SHOWS LOAD CAPACITANCE OF 16PF FOR 197S0004
necessary pull-ups & pull-downs.
FROM SOUTHBRIDGE
FROM NORTHBRIDGE
TO CPU
Configures Shasta for 64-bit PCI
To SouthBridge ->
NET_SPACING_TYPE
AUDIO PAGES IS RESPONSIBLE FOR TERMINATION OF I2S0 AND I2S2
DO NOT ADD PULLUP/DOWN FOR I2S0 AND IS=2S2 IN THIS PAGE
(I2S1_DEV_TO_SB_DTI)
Re-pin within each RPAK as necessary
interrupt controller.
Selects whether NorthBridge or
SouthBridge MPIC will be used for
I2S1: Soft Modem
23
18
(I2S2_RESET_L)
PLACE R2432 CLOSE TO SHASTA
805
X5R
6.3V
10%
10UF
2
1
C2400
10%
6.3V
1uF
CERM
402
2
1
C2401
10%
6.3V
1uF
CERM
402
2
1
C2411
805
X5R
6.3V
10%
10UF
2
1
C2410
805
X5R
6.3V
10%
10UF
2
1
C2420
10%
6.3V
1uF
CERM
402
2
1
C2421
805
X5R
6.3V
10%
10UF
2
1
C2430
10%
6.3V
1uF
CERM
402
2
1
C2431
1/16W
5%
402
10K
MF-LF
2
1
R2400
CRITICAL
18.432M
SM
21
Y2490
200
MF-LF
402
1%
1/16W
2
1
R2490
50V
22pF
CERM
402
5%
2
1
C2491
50V
22pF
CERM
402
5%
2
1
C2490
4.7K
MF-LF
402
1%
1/16W
2
1
R2480
SHASTA
V1.1
BGA-LF
Y13
V13
W13
AB12
W14
V15
U15
T9
U7
W2
Y4
W17
W12
Y11
A3
W11
AA11
AB11
U11
V11
W10
E9
Y12
AA12
AA13AB13
U14
W6
U16
AB21
U17
K17
W18
E18
Y20
AA20
AA19
K20
K22
H22
J20
H21
G22
F22
J19
H20
G21
F21
J17
H19
K18
D22
G20
D21
C22
G19
F20
C21
E20
D20
F19
E19
G18
G17
C20
B21
A21
F16
G16
F17
F18
A20
D18
L17
V12
W9
Y7
Y8
AA5
AB4
AA7
V9
AB5
V10
AA8
Y6
U8
Y5
W7
AA4
AB7
Y9
W8
AB3
Y2
V5
V14
U2300
10V
0.1uF
CERM
402
20%
2
1
C2440
10K
MF-LF
402
5%
1/16W
1 2
R2450
10K
MF-LF
402
5%
1/16W
1 2
R2451
10K
MF-LF
402
5%
1/16W
1 2
R2452
10K
MF-LF
402
5%
1/16W
1 2
R2453
10K
MF-LF
402
5%
1/16W
21
R2456
10K
MF-LF
402
5%
1/16W
1 2
R2457
10K
MF-LF
402
5%
1/16W
21
R2459
1/16W
5%
402
10K
MF-LF
21
R2463
SAT_PWRON
1K
MF-LF
402
1%
1/16W
21
R2460
MF-LF
402
5%
1/16W
4.7K
21
R2461
10K
MF-LF
402
5%
1/16W
21
R2466
10K
MF-LF
402
5%
1/16W
21
R2465
10K
MF-LF
402
5%
1/16W
21
R2467
10K
MF-LF
402
5%
1/16W
21
R2468
1K
MF-LF
402
1%
1/16W
NOSTUFF
21
R2462
10K
MF-LF
402
5%
1/16W
21
R2455
10K
MF-LF
402
5%
1/16W
21
R2454
3.3
MF-LF
805
5%
1/8W
21
R2405
MF-LF
3.3
805
5%
1/8W
21
R2410
3.3
MF-LF
805
5%
1/8W
21
R2420
3.3
MF-LF
805
5%
1/8W
21
R2430
10K
MF-LF
402
5%
1/16W
21
R2464
10K
MF-LF
402
5%
1/16W
21
R2422
MF-LF
402
5%
1/16W
4.7K
NOSTUFF
21
R2406
10K
MF-LF
402
5%
1/16W
21
R2404
10K
MF-LF
402
5%
1/16W
21
R2421
SAT_RUN
1K
MF-LF
402
1%
1/16W
21
R2416
NOSTUFF
10K
MF-LF
402
5%
1/16W
21
R2417
10K
MF-LF
402
5%
1/16W
2 1
R2413
10K
MF-LF
402
5%
1/16W
2 1
R2414
10K
MF-LF
402
5%
1/16W
2 1
R2415
1/16W
5%
MF-LF
10K
402
2
1
R2476
MPIC_SB
2N3904LF
SOT23
2
3
1
Q2476
MPIC_SB
10K
MF-LF
402
5%
1/16W
21
R2475
1/16W
5%
402
MF-LF
0
MPIC_SB
21
R2478
MPIC_NB
0
MF-LF
402
5%
1/16W
2
1
R2479
NO STUFF
0
MF-LF
402
5%
1/16W
21
R2407
MPIC_NB
10K
21
R2408
MPIC_NB
21
R2409
MPIC_NB
21
R2412
MPIC_NB
MF-LF
402
5%
1/16W
21
R2418
10K
MF-LF
402
5%
1/16W
21
R2419
SM
2
1
XW2400
P4MM
SM
1
PP2400
P4MM
SM
1
PP2405
P4MM
SM
1
PP2406
I586
I587
I588
I589
I590
I591
I592
I593
I594
I595
I596
I597
I598
I599
I600
I601
33
63
RP2410
33
54
RP2410
33
81
RP2420
33
72
RP2410
33
63
RP2420
33
81
RP2410
33
63
RP2430
33
72
RP2430
33
54
RP2430
33
81
RP2430
33
72
RP2420
33
54
RP2420
0
MF-LF
402
5%
1/16W
21
R2402
0
MF-LF
402
5%
1/16W
21
R2432
Shasta Serial / Misc
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
154
051-6863
F
24
TITLE=KILOHANA
ABBREV=DRAWING
SB_CPU_VDNAP2
NB_SLOT_RESET_L
PCI_AIRPORT_INT_L
NB_SLOT_RESET_L_R
SB_PCI_SEL32BIT
RAI_EXP_INTR_L<3>
RAI_EXP_INTR_L<0>
=PP3V3_PWRON_SB
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL45VDD
MIN_NECK_WIDTH=0.38mm
MIN_LINE_WIDTH=0.50mm
P3MM SPACING
PCI_AIRPORT_INT_L
I2S1_DEV_TO_SB_DTI
I2S1_RESET_L
CPU_A0_INT_R_L
NB_CPU_A0_INT_L
I2S0_MCLK
I2S0_TO_DEV
AUDIO
I2S0_MCLK
I2S0_BITCLK
I2S0_MCLK_R
I2S2_SB_TO_DEV_DTO_R
I2S2_MCLK_R
I2S2_BITCLK_R
I2S2_SYNC_R
I2S2_SB_TO_DEV_DTO
I2S1_SYNC_R
I2S1_BITCLK_R
I2S1_MCLK_R
I2S1_SB_TO_DEV_DTO_R
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S0_SYNC_R
I2S0_BITCLK_R
I2S0_SB_TO_DEV_DTO_R
I2S0_SYNC
I2S0_SB_TO_DEV_DTO
P3MM SPACING
PCI_USB2_INT_L
P3MM SPACING
SB_CPU_A1_SRESET_L
SB_CPU_B0_SRESET_L
P3MM SPACING
SB_CPU_B1_SRESET_L
P3MM SPACING
=PP2V5_PWRON_SB
I2S0_DEV_TO_SB_DTI
P3MM SPACING
I2S1_RESET_L
SB_GPIO_H_3
=PP3V3_RUN_SB_PCI
NB_TO_SB_INT
SB_CPU_A0_INT_L
NB_INT_L_R
=PP3V3_RUN_SB_PCI
MAKE_TBEN_SYNC_L
SYS_OVERTEMP_L
PCI_USB2_INT_L
PCI_AIRPORT_INT_L
I2S1_RESET_L
SB_CPU_A0_INT_L
SB_CPU_A1_INT_L
SB_CPU_B0_INT_L
SB_CPU_B1_INT_L
RAI_ALERT_L
SB_CLK18M_XTALO
PP_1V2PWRONSBPLL45VDD
ENET_ENERGYDET
FW_LOWPWR
ENETFW_RESET
MAKE_TBEN_SYNC_L
SMU_TO_SB_INT_L
SYS_SLEWING_L
RAI_FATAL_L
GIGE_P2_INTB_L
GIGE_P1_INTA_L
FW_LOWPWR_R
=PP3V3_PWRON_SB
NB_CHP_FLT_N_B
SB_CPU_VDNAP1
SB_TO_SMU_INT_L
SB_VDNAP0
SB_GPIO14
SB_CPU_VDNAP2
LOGIC_BRD_GOOD
SYS_OVERTEMP_L
MB_SLOT_RESET_L
NB_SLOT_RESET_L
PCIX_INT_L
=PP1V2_PWRON_SB
SB_SFC_RESET_L
I2S2_DEV_TO_SB_DTI
I2S2_TO_SB
SB_CLK18M_XTALO
0.38mm SPACING
I2S2_BIDIR
I2S2_SYNC
I2S1_SYNC
I2S1_BIDIR
I2S1_BITCLK
I2S1_BIDIR
I2S1_MCLK
I2S1_TO_DEV
0.25mm SPACING
I2S0_BITCLK
I2S0_BIDIR
I2S0_DEV_TO_SB_DTI
I2S0_TO_SB
SB_CLK25M_SATA
SB_CLK25M_ATA
0.38mm SPACING
SB_CLK18M_XTALO_R
0.38mm SPACING
I2S2_MCLK
I2S2_TO_DEV
0.25mm SPACING
I2S0_SB_TO_DEV_DTO
I2S0_TO_DEV
I2S1_SB_TO_DEV_DTO
I2S1_TO_DEV
SB_CLK18M_XTAL 0.38mm SPACING
SB_CLK18M_XTALI
I2S0_SYNC
I2S0_BIDIR
I2S1_DEV_TO_SB_DTI
I2S1_TO_SB
I2S2_SB_TO_DEV_DTO
I2S2_TO_DEV
TP_SB_FSTEST
=PP3V3_PWRON_SB
VOLTAGE=1.2V
PP1V2_PWRON_SB_PLL49VDD
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
SB_CPU_B0_SRESET_L
SB_CPU_B1_SRESET_L
SB_CPU_A1_SRESET_L
SB_CPU_A0_SRESET_L
SB_CPU_B1_INT_L
SB_CPU_B0_INT_L
SB_CPU_A1_INT_L
SB_CPU_A0_INT_L
AUDIO_MIC_ID
AUDIO_HP_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_LO_DET_L
AUDIO_LO_OPTICAL_PLUG_L
ENET_ENERGYDET
MAKE_TBEN_SYNC_L
PCI_USB2_INT_L
ENETFW_RESET
FW_LOWPWR_R
RAI_FATAL_L
RAI_ALERT_L
GIGE_P2_INTB_L
GIGE_P1_INTA_L
RAI_EXP_INTR_L<1>
RAI_EXP_INTR_L<2>
PCIX_INT_L
SB_GPIO14
MB_SLOT_RESET_L
SYS_OVERTEMP_L
SB_VDNAP0
LOGIC_BRD_GOOD
SB_TO_SMU_INT_L
SB_CPU_VDNAP1
NB_CHP_FLT_N_B
SB_CLK25M_SATA
SB_CLK18M_XTALO_R
SB_CLK18M_XTALI
SB_TEST_MODE_PD
TP_SB_PLLTEST
JTAG_SB_TMS
JTAG_SB_TDI
JTAG_SB_TDO
JTAG_SB_TCK
TP_SB_WATCHDOG
I2C_SB_SDA
I2C_SB_SCL
SB_GPIO_H_3
I2S0_RESET_L
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTALVDD
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
VOLTAGE=2.5V
PP2V5_PWRON_SB_XTAL18VDD
MIN_LINE_WIDTH=0.50mm
MIN_NECK_WIDTH=0.38mm
SB_STOPXTALS_L
SMU_SUSPENDREQ_L
SB_SUSPENDACK_L
SYS_PME_L
JTAG_SB_TRST_L
SYS_SLEWING_L
NB_TO_SB_INT
SMU_TO_SB_INT_L
SB_SFC_RESET_L
NET_SPACING_TYPE=P3MM SPACING
I2S0_RESET_L
P3MM SPACING
P3MM SPACING
SB_CPU_B0_INT_L
P3MM SPACING
SB_CPU_B1_INT_L
MB_SLOT_RESET_L
P3MM SPACING
SB_CPU_A0_SRESET_L
P3MM SPACING
P3MM SPACING
SB_CPU_A0_INT_L
P3MM SPACING
NB_TO_SB_INT
P3MM SPACING
NB_SLOT_RESET_L
P3MM SPACING
I2S2_RESET_L
I2S2_SYNC
I2S2_RESET_L
I2S2_BITCLK
=PP3V3_PWRON_SB
SHASTA_SYS_IO_RESET_L
SYS_IO_RESET_L
I2S2_DEV_TO_SB_DTI
I2S2_MCLK
P3MM SPACING
SB_CPU_A1_INT_L
I2S2_BITCLK
I2S2_BIDIR
AUDIO_LI_DET_L
AUDIO_SPKR_ID
AUDIO_SPDIFIN_INT_L
AUDIO_HP_MUTE_L
AUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_EXT_MCLK_SEL
LAST_MODIFIED=Tue Nov 1 13:46:21 2005
119
119
119
119
56
56
56
56
24
138
93
50
24
93
24
93
50
24
122
23
119
28
28
23
28
23
28
43
28
23
119
28
24
121
20
121
24
24
154
154
147
154
24
24
24
24
147
147
122
56
56
56
23
147
24
24
24
24
122
121
24
132
24
26
20
28
28
31
143
28
24
24
154
154
24
24
24
147
147
26
154
147
24
147
24
154
20
56
56
56
56
132
122
24
143
24
31
28
28
26
147
30
122
20
26
147
56
24
154
154
154
154
20
30
154
154
154
24
20
24
20
20
7
24
8
8
56
42
24
24
24
24
8
8
8
8
24
24
24
24
24
24
7
24
8
24
7
24
24
7
24
20
24
24
8
24
24
24
24
24
24
6
24
139
17
24
24
24
24
24
24
24
7
24
24
24
24
24
24
24
20
24
20
24
7
24
24
24
24
8
8
8
24
24
24
24
24
24
8
24
24
8
24
6
7
24
24
24
24
24
24
24
24
154
154
154
153
153
24
24
24
17
24
24
24
24
24
20
20
24
24
24
20
24
24
24
24
24
24
24
24
6
20
20
20
20
9
39
39
24
24
28
28
28
28
9
24
24
24
24
24
24
24
24
24
24
24
20
24
24
24
24
7
28
24
24
24
24
153
153
154
154
150
152
154
VDD_OVDD_2
VDD_OVDD_3
VDD_OVDD_5 VSS_OVDD_5
VSS_OVDD_3
VSS_OVDD_1VDD_OVDD_1
VDD_33_XTAL
VDD_OVDD_4 VSS_OVDD_4
VSS_15_C4
VSS_OVDD_2
VSS_15_PLL2VDD_15_PLL2
VDD_15_12_4
VDD_15_C4
VDD_15_PLL1
VSS_33_XTAL
VSS_15_PLL1
VDD_33_I VSS_33_I
VSS_12_6
VDD_15_C1
VDD_12_5
VSS_25
VSS_15_C3VDD_15_C3
VDD_25
VSS_12_5
VSS_33_BC
VSS_12_4VDD_12_4
VSS_15_PLL4
VSS_12_1
VSS_12_2
VDD_33_BC
VDD_12_1
VSS_15_C2
VDD_12_2
VDD_12_3 VSS_12_3
VDD_15_PLL4
VDD_15_C2
VDD_15_PLL3 VSS_15_PLL3
VDD_15_12_1
VDD_15_12_2
VDD_15_12_3
SHARED PIN
SYM 2 OF 2
VSS_15_C1
PP
PP
PP
PP
PP
PP
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Q63 APPLICATION IS RUN
Q63 APPLICATION IS POWER ON
Q63 APPLICATION IS RUN
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
PLACE NEAR PULSAR2
ON IN SLEEP
ON IN SLEEP
PLL_VDD ON IN SLEEP
Q63 APPLICATION IS PWRON
4.7
MF-LF
402
5%
1/16W
21
R2501
SEE_TABLE
PULSAR2
BGA
A3
B5
A7
B7
B10
D11
E1
K2
G1
L8
M4
D1
D12
C8
G11
M6
E12
J10
K11
M12
K8
K4
A1
B4
A5
C9
B11
B12
C2
L2
G2
K9
L4
D2
D10
B8
F11
L6
F2
C5
A9
J11
K5
H11
K12
M10
M7
M3
U2500
0
MF-LF
402
5%
1/16W
21
R2510
NOSTUFF
0
MF-LF
402
5%
1/16W
21
R2511
10V
0.1UF
CERM
402
20%
2
1
C2572
10V
0.1UF
CERM
402
20%
2
1
C2573
0
MF-LF
402
5%
1/16W
21
R2512
0
MF-LF
402
5%
1/16W
21
R2513
0
MF-LF
402
5%
1/16W
21
R2514
0
MF-LF
402
5%
1/16W
21
R2515
0
MF-LF
402
5%
1/16W
21
R2516
10V
0.1UF
CERM
402
20%
2
1
C2501
10V
0.1UF
CERM
402
20%
2
1
C2575
SM
2
1
XW2500
P4MM
SM
1
PP2500
SM
2
1
XW2501
SM
2
1
XW2502
SM
2
1
XW2503
P4MM
SM
1
PP2501
P4MM
SM
1
PP2502
SM
P4MM
1
PP2503
P4MM
SM
1
PP2506
P4MM
SM
1
PP2505
SM
P4MM
1
PP2507
P4MM
SM
1
PP2504
SM
P4MM
1
PP2508
4.7
MF-LF
402
5%
1/16W
21
R2503
4.7
MF-LF
402
5%
1/16W
21
R2505
10V
0.1UF
CERM
402
20%
2
1
C2505
180-OHM-1.5A
0603
21
L2501
10V
0.1UF
CERM
402
20%
2
1
C2509
10V
0.1UF
CERM
402
20%
2
1
C2511
180-OHM-1.5A
0603
21
L2503
10V
0.1UF
CERM
402
20%
2
1
C2513
180-OHM-1.5A
0603
21
L2505
10V
0.1UF
CERM
402
20%
2
1
C2515
180-OHM-1.5A
0603
21
L2507
10V
0.1UF
CERM
402
20%
2
1
C2517
10V
0.1UF
CERM
402
20%
2
1
C2519
10V
0.1UF
CERM
402
20%
2
1
C2522
4.7
MF-LF
402
5%
1/16W
21
R2507
180-OHM-1.5A
0603
21
L2509
10V
0.1UF
CERM
402
20%
2
1
C2520
10V
0.1UF
CERM
402
20%
2
1
C2527
10V
0.1UF
CERM
402
20%
2
1
C2528
10V
0.1UF
CERM
402
20%
2
1
C2529
20%
402
CERM
0.1UF
10V
2
1
C2530
10V
0.1UF
CERM
402
20%
2
1
C2551
10V
0.1UF
CERM
402
20%
2
1
C2523
10V
0.1UF
CERM
402
20%
2
1
C2524
10V
0.1UF
CERM
402
20%
2
1
C2525
10V
0.1UF
CERM
402
20%
2
1
C2526
10V
0.1UF
CERM
402
20%
2
1
C2531
10V
0.1UF
CERM
402
20%
2
1
C2532
10V
0.1UF
CERM
402
20%
2
1
C2533
10V
0.1UF
CERM
402
20%
2
1
C2534
20%
402
CERM
0.1UF
10V
2
1
C2535
20%
402
CERM
0.1UF
10V
2
1
C2536
20%
402
CERM
0.1UF
10V
2
1
C2537
20%
402
CERM
0.1UF
10V
2
1
C2538
20%
402
CERM
0.1UF
10V
2
1
C2574
4.7
MF-LF
402
5%
1/16W
21
R2509
6.3V
2.2UF
CERM1
603
20%
2
1
C2545
6.3V
2.2UF
CERM1
603
20%
2
1
C2569
6.3V
2.2UF
CERM1
603
20%
2
1
C2503
6.3V
2.2UF
CERM1
603
20%
2
1
C2507
6.3V
2.2UF
CERM1
603
20%
2
1
C2521
TITLE=KILOHANA
ABBREV=DRAWING
25
154
F
051-6863
SYNC_MASTER=Q63
SYNC_DATE=08/26/2005
PULSAR2 POWER
=PPOVDD_PULSAR
=PP1V5_PWRON_PULSAR
=PP2V5_PWRON_PULSAR
=PPOVDD_PULSAR
PP1V5_PSL_PLL3
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.64mm
VOLTAGE=1.5V
PP1V5_PSL_PLL4
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.64mm
VOLTAGE=1.5V
PP1V5_PSL_PLL1
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.64mm
VOLTAGE=1.5V
PP3V3_PLSR_I
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.64MM
MIN_NECK_WIDTH=0.22MM
NO_TEST=YES
PP_1V5PWRONPULSAR2
PP_OVDD_PULSAR1
PP3V3_PLSR_I
=PP2V5_PWRON_PULSAR
=PP1V2_PWRON_PULSAR
=PP3V3_RUN_PULSAR
C2569_1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
C2503_1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
C2507_1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
C2521_1
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
=PP3V3_PWRON_PULSAR
=PP1V5_PWRON_PULSAR
=PP1V5_PULSAR
=PP1V2_PWRON_PULSAR
=PP1V5_PULSAR
=PP1V5_PWRON_PULSAR
PP_1V2PWRONPULSAR1
PP_1V5PULSAR2
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.64mm
VOLTAGE=1.5V
PP1V5_PSL_PLL2
PP3V3_PSL_XTAL
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.64mm
VOLTAGE=3.3V
=PP3V3_PWRON_PULSAR
=PP3V3_PWRON_PULSAR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
C2545_1
LAST_MODIFIED=Tue Nov 1 13:46:22 2005
25
25
25
25
26
26
25
25
25
25
25
25
25
25
25
25
7
7
7
7
25
6
6
25
7
7
7
7
7
7
7
7
7
6
6
7
7
XIN
GPCLK33_F1
GPCLK33_F2
GPCLK33_F0
GPCLK33_E1
GPCLK33_E0
GPCLK25_F0
GPCLK25_F1
GPCLK25_E0
GPCLK25_E1
HTBEN_1
HTBEN_0
SLEWING*
HCLKN_2
HCLKN_1
HCLKP_0
HSYNC_2
SCLK
SDATA
HCLKP_2
HCLKN_0
HSYNC_1
PD
HSYNC_0
XOUT
HCLKP_1
RESET*
OEMODE
TEST_MODE
GPCLK12_C0
REF_25
REF_15
REF_33
GPCLK12P_A1
GPCLK12P_B0
GPCLK12N_A0
GPCLK12N_A1
GPCLK12N_B0
GPCLK12P_A0
ASEL_INT*
GPCLK12P_C0
GPCLK12N_C0
GPCLK12P_C1
GPCLK12N_C1
GPCLK12P_C2
GPCLK12N_C2
GPCLK12P_C3
GPCLK12N_C3
GPCLK12P_C4
GPCLK12N_C4
GPCLK12P_D0
GPCLK12N_D0
SYM 1 OF 2
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
33MHZ, 3.3V
33MHZ, 3.3V
PLACE ALL 0-OHM SERIES RESISTORSRES
ON THIS PAGE NEAR PULSAR
PULLED UP TO PP3V3_RUN ON P.28
1.5VOVDD
1.5VOVDD
33MHZ, 3.3V
66MHZ, 3.3V
66MHZ, 3.3V
25MHZ, 2.5V
25MHZ, 2.5V
25MHZ, 2.5V
25MHZ, 2.5V
66MHZ, 1.2V
66MHZ, 1.2V
66MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
100MHZ, 1.2V
300MHZ, 1.2V
300MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
200MHZ, 1.2V
(100MHZ FOR ASPEN)
66MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
LAST MODIFIED: APR 26, 04
200MHZ, 1.5VOVDD
200MHZ, 1.5VOVDD
MB_PCIX_REFCLK
QUASAR CLOCKS ARE RESISTOR DIVIDED DOWN
REMOVED R2632 AND R2630
FROM UNUSED CLOCKS FOR EMC
1.5VOVDD
66MHZ, 1.5VOVDD
TO 1.8V ON QUASAR PAGES
200MHZ, 1.5VOVDD
PULSAR2
BGA
C11
C12
E3
A12
B2
B1
C3
L1
F1
H10
C1
E2
A10
A11
C10
B9
A8
B3
C4
A6
A2
A4
B6
M2
M1
K1
J2
J1
J3
H2
H3
H1
E10
G12
K10
L11
L10
M9
L7
M5
K3
E11
F12
J12
L12
M11
L9
M8
L5
L3
H12
D3
U2500
0
MF-LF
402
5%
1/16W
21
R2654
1/16W
0
MF-LF
402
5%
21
R2656
NO STUFF
0
MF-LF
402
1/16W
5%
21
R2652
MF-LF
5%
NO STUFF
330K
402
1/16W
21
R2658
8X4.5MM-SM2
25.0000M
CRITICAL
21
Y2601
CERM
33PF
50V
5%
402
2
1
C2605
33PF
50V
CERM
402
5%
2
1
C2607
5%
NOSTUFF
24
MF-LF
402
1/16W
2
1
R2662
NOSTUFF
U.FL-R_SMT
F-ST-SM
1
2
3
J2600
NOSTUFF
24
MF-LF
402
5%
1/16W
2
1
R2664
1K
MF-LF
402
1%
1/16W
2
1
R2625
1K
1%
1/16W
402
MF-LF
2
1
R2626
1K
MF-LF
402
1%
1/16W
2
1
R2627
0
402
5%
21
R2612
10K
MF-LF
402
5%
1/16W
2
1
R2613
NOSTUFF
1K
MF-LF
402
1%
1/16W
2
1
R2618
1K
MF-LF
402
1%
1/16W
NOSTUFF
2
1
R2621
10K
NOSTUFF
MF-LF
402
5%
1/16W
2
1
R2614
0
MF-LF
402
5%
1/16W
2
1
R2623
10K
MF-LF
402
5%
1/16W
2
1
R2616
0
MF-LF
402
5%
1/16W
21
R2628
MF-LF
1/16W
5%
402
0
21
R2631
0
MF-LF
402
5%
1/16W
21
R2635
0
MF-LF
402
5%
1/16W
21
R2636
MF-LF
0
402
5%
1/16W
21
R2641
0
MF-LF
402
5%
1/16W
21
R2643
0
MF-LF
402
5%
1/16W
21
R2645
0
MF-LF
402
5%
1/16W
21
R2647
0
MF-LF
402
5%
1/16W
21
R2649
0
MF-LF
402
5%
1/16W
21
R2651
MF-LF
0
402
5%
1/16W
21
R2653
5%
1/16W
MF-LF
402
0
21
R2655
1/16W
5%
402
MF-LF
0
21
R2657
1/16W
MF-LF
402
5%
0
21
R2659
0
MF-LF
402
5%
1/16W
21
R2660
5%
0
MF-LF
402
1/16W
21
R2663
0
MF-LF
402
5%
1/16W
21
R2665
0
MF-LF
402
5%
1/16W
21
R2637
0
MF-LF
402
5%
1/16W
21
R2639
5%
0
MF-LF
402
1/16W
21
R2634
MF-LF
0
1/16W
5%
402
21
R2633
MF-LF
0
402
5%
1/16W
21
R2629
0
MF-LF
402
5%
1/16W
21
R2668
0
MF-LF
402
5%
1/16W
21
R2669
0
MF-LF
402
5%
1/16W
21
R2670
1/16W
0
MF-LF
402
5%
21
R2671
0
MF-LF
402
5%
1/16W
21
R2672
0
MF-LF
402
5%
1/16W
21
R2673
0
MF-LF
402
5%
1/16W
21
R2666
0
MF-LF
402
1/16W
5%
21
R2667
5%
1/16W
MF-LF
0
402
21
R2675
0
MF-LF
402
5%
1/16W
21
R2674
0
402
5%
21
R2600
P4MM
SM
1
PP2602
SM
P4MM
1
PP2600
SM
P4MM
1
PP2601
TITLE=KILOHANA
ABBREV=DRAWING
PULSAR2 CLOCKS
154
F
051-6863
26
SYNC_MASTER=FINO-M23 SYNC_DATE=08/26/2005
EI_NB_SYSCLK_P
SYS_SLEWING_L_R
CPU_A_APSYNC_R
GFX_SLOT_PCIE_REFCLK_N_C
CLK_RAIREF_200M_N_R
NB_PMR_CLK_N
CLK_RAI_200M_P<0>
NB_DDR_REFCLK_N
PCIE_C_REFCLKIN_P_C
PCIE_C_REFCLKIN_N_C
PCIE_A_REFCLKIN_N_C
NB_PMR_CLK_P_R
CPU_A_TBEN_CLK_R
CPU_B_TBEN_CLK_R
CPU_B_APSYNC_R
CPU_A_APSYNC
NC_CPU_B_TBEN_CLK_US
MAKE_BASE=TRUE
EI_NB_SYSCLK_N
NB_PCIE_REFCLK_P_C
EI_CPU_B_SYSCLK_N
NB_APSYNC_R
HT_SB_REFCLK_R
HT_NB_REFCLK_L0_R
CPU_B_APSYNC
NB_APSYNC
QUA0_REF_25MHZ_R
QUA1_REF_25MHZ_R
PCI_CLK66M_SB_INT_R
PLSR2_OEMODE
EI_CPU_A_SYSCLK_P
EI_CPU_A_SYSCLK_N
EI_CPU_B_SYSCLK_P
HT_CLK66M_SB
HT_NB_REFCLK_H0_R
CLK_RAIREF_200M_P_R
HT_NB_REFCLK_P<0>
PLSR2_PD
PLS2_X_IN_B
PLS2_X_OUT_B
NB_DDR_REFCLK_P_R
PCIE_B_REFCLKIN_N_C
PCIE_A_REFCLKIN_P_C
NB_PMR_CLK_N_R
SB_CLK25M_SATA
PCI_CLK33M_SB_EXT_R
CLK_RAI_REFCLK_66M_R
SB_AIRPRT_CLK_33MHZ_R
NB_DDR_REFCLK_N_R
CLK_RAI_GIGE_25MHZ
PCI_CLK33M_SB_EXT_RR
RAM_ARB0_REF25MHZ
PCI_CLK66M_SB_INT
CLK_RAI_GIGE_25MHZ_R
CLK_RAI_PCIEB_N<0>
HT_NB_REFCLK_N<0>
CLK_KOD_100M_P<0>
PCIE_B_REFCLKIN_P_C
CLK_RAI_PCIEA_P<0>
CLK_RAI_PCIEC_N<0>
CLK_RAI_PCIEC_P<0>
CLK_RAI_PCIEB_P<0>
CLK_RAI_PCIEA_N<0>
NB_PCIE_REFCLK_N_C
GFX_SLOT_PCIE_REFCLK_P_C
SB_USB2_CLK_33MHZ_R
NB_DDR_REFCLK_P
PLS2_INTERM
PCI_CLK33M_USB2
CLOCK_RESET_L
NB_PMR_CLK_P
PLS2_REF33
PLS2_REF25
SB_CLK25M_SATA_R
SYS_SLEWING_L
CPU_A_TBEN_CLK_US
CLK_RAI_200M_N<0>
CLK_KOD_100M_N<0>
CLK_PCIE_SLOTA_P<0>
CLK_PCIE_SLOTA_N<0>
RAM_ARB1_REF25MHZ
PLS2_EXTCLK
I2C_CLOCK_B_SDA
SYS_SLEEP
PLS2_REF15
PP3V3_PLSR_I
PLSR2_TM
I2C_CLOCK_B_SCL
PLSR2_ASEL_INT_L
PLS2_RESET_L
PLS2_X_IN
PCI_CLK33M_AIRPORT
PLS2_X_OUT
CLK_RAI_REFCLK_66M
LAST_MODIFIED=Tue Nov 1 13:46:22 2005
54 30 16 15
50
13
56
27
56
56
101
119
119
101
97
27
28
97
97
97
12
42
9
9
9
20
27
59
9
9
9
9
9
9
9
56
6
42
9
27
9
9
9
27
42
9
9
6
56
56
27
103
9
9
98
9
9
9
9
24
9
9
9
9
27
27
27
27
9
27
98
82
9
27
27
27
27
27
9
9
9
59
27
28
20
9
24
56
27
82
84
84
27
39
11
25 39
121
27
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTAINT_SET
NET_SPACING_TYPE
NOTE:
CLOCK CONSTRAINTS
N/C QUASAR CLOCKS
N/C ALIASES
N/C CPUB CLOCKS
N/C RAINIER CLOCKS
DIFFERENTIAL_PAIR NET_PHYSICAL_TYPE
RESPECTIVE BUS PAGES
ALL OTHER CLOCK CONTRAINTS ON THEIR
I67
I68
I69
I70
SYNC_MASTER=FINO-M23
Pulsar Aliases
154
27
F
051-6863
SYNC_DATE=08/26/2005
PCI_CLK_SB_CAP
PCI_CLK_SB PCI_CLK_SBPCI_CLK33M_SB_EXT_RR
P3MM SPACING
PCI_CLK_SB
PCI_CLK_SB
PCI_CLK66M_SB_INT
NB_PMR_CLK_N
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK_SP
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK
NB_PMR_CLK_SP
NB_PMR_CLK
NB_PMR_CLK_P
MAKE_BASE=TRUE
NC_CPU_B_APSYNC
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_P
MAKE_BASE=TRUE
NC_EI_CPU_B_SYSCLK_N
MAKE_BASE=TRUE
NC_CLK_RAI_GIGE_25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB1_REF25MHZ
RAM_ARB1_REF25MHZ
MAKE_BASE=TRUE
NC_RAM_ARB0_REF25MHZ
RAM_ARB0_REF25MHZ
CPU_B_APSYNC
EI_CPU_B_SYSCLK_N
EI_CPU_B_SYSCLK_P
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEC_N<0>
CLK_RAI_PCIEC_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEC_P<0>
CLK_RAI_PCIEC_P<0>
CLK_RAI_200M_P<0>
CLK_RAI_REFCLK_66M
CLK_RAI_PCIEB_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEB_P<0>
CLK_RAI_PCIEB_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEB_N<0>
CLK_RAI_PCIEA_P<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEA_P<0>
CLK_RAI_PCIEA_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_PCIEA_N<0>
MAKE_BASE=TRUE
NC_CLK_RAI_200M_P<0>
CLK_RAI_GIGE_25MHZ
MAKE_BASE=TRUE
NC_CLK_RAI_200M_N<0>
CLK_RAI_200M_N<0>
=PCI_CLK33M_USB2
MAKE_BASE=TRUE
PCI_CLK33M_USB2
MAKE_BASE=TRUE
NC_CLK_RAI_REFCLK_66M
119
119
26
26
26
26
20
20
6
6
6
6
6
26
6
26
26
26
26
6
26
6
26
26
26
26
6
26
6
26
6
26
6
6
26
6
26
122
26
6
P9[7]
P9[6]
P9[5]
P8[7]
P8[6]
P8[5]
P3[7]
P3[6]
P3[5]
P3[4]
P2[6]
P2[7]
P2[4]
P2[5]
P1[4]
P1[3]
P1[2]
P1[1]
P1[0]
P0[4]
P0[0]
P0[2]
P0[3]
P0[1]
P0[7]
P0[6]
P0[5]
P3[3]
P3[2]
P3[1]
P3[0]
P2[3]
P2[2]
P2[1]
P2[0]
P1[5]
P1[6]
P1[7]
PCNVSS
RESET*
XOUT
VREF
XIN
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P6[7]
P6[6]
P6[5]
P6[4]
P6[3]
P6[2]
P6[1]
P6[0]
P10[0]
P10[1]
P9[3]
P9[2]
P9[1]
P9[0]
P8[4]
P8[3]
P8[2]
P8[1]
P8[0]
P10[6]
P10[7]
P10[2]
P10[3]
P10[4]
P10[5]
VCC
AVSS
VSS
AVCC
SQW/
OUT
VBAT
SDA
SCL
X1
X2
GND
VCC
PP
PP
PP
PP
PP
DRAWING
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ELECTRICAL_CONSTRAINT_SET
- =PP3V3_ALL_SMU
- =PP3V3_ALL_RTC
- =PP3V3_PWRON_SMU
- =PPVREF_SMU (SMU AVCC OR 2.5V REFERENCE)
DIFFERENTIAL_PAIR
NET_SPACING_TYPE
SMU Pull-ups / pull-down
7.4
Y2800’S LOAD CAPACITANCE IS 12PF
NET_SPACING_TYPE
ELECTRICAL_CONSTRAINT_SET
DIFFERENTIAL_PAIR
Y Y
AN23
TA1in
Y Y
8.5
10.7
3.3
3.2
3.1
3.0
Y
Y Y Y Y
Y Y
AN01
AN00
Y
Y S
N
KI2*
SDAmm
IOC4
Keep crystal subcircuit close to SMU.
INT3*
TB0in
TB1in
SCLmm
Y
Y
Y
N
circuit, but be aware that this will
reference used by monitoring
SMU_VREF should be same signal or
100K/10uF RC filter at SMU pins.
(CPU_SENSE_I/CPU_SENSE_V) requires
Signal aliases required by this page:
Power aliases required by this page:
Page Notes
INT1*
INT0*
TA4in
TA4out
CLK0
TXD0
RTS1*
(BUSY)
TXD1
SCL
TA1out
Y
S
Y
Y
7.2
6.0
6.2
6.1
Port
6.3
6.4
Port
Alternate Functions
NC
Real Time Clock
Tower & Server
YY NN
Entry Desktop
Server
Desktop
Consumer
S
Entry Desktop
Y
Consumer
Portable
Server
YY
N = Alternate function
S
S
S
N
N
S
SY
Y
Y
Y
YY
Y Y N
Y
Y
Y
Y
Y
YYY
Y Y Y
Y
Y
Y
Y Y
Y
Y
Y
N
Y
N
Y Y
Y
N
Y
S
Y
NY
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SDA
Y
Y
Y
N
Y
Y
Y
Y
TA2out
TA3out
TA3in
S SS S
Y
Y
Y YYY
Y
YY
Y
Y
SSYY
Y
Y
Y
Y
S
Y
Y
Y
Y
YYY
Y
Y
Y
S
Y
Y
Y
YY
S S
S Y Y S
S S
Y Y YY
Y
Y
Y
Y
Y
Y
Y
YY Y
YY Y
Y
Y
Y
Y
Y Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
NMI*
TB2in
AN24
CE*
INT2*
AN25
S
S
Y
Y
Y
Y
Y
Y
KI0*
AN3
AN1
AN0
KI1*
AN26
AN27
Y
S
Y Y Y
Y Y SY
Y
KI3*
AN03
AN20
AN04
AN05
IOC2
AN22
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
S
S
YY
S
SY
SY
Y
Y
Y Y
S
S
N
N
YY
Y Y
YY
YY
Y
Y
YYYY
YYN S
YY
S
Y Y
Y
Y
S
Y Y
Y
N
N
Y Y
S
Y
Y YSN
Y
Y
Y Y
Y
Y
YY
Y
Y Y
Y
Y Y YY Y
Sout3
IOC5
IOC6
Sin3
IOC7
CLK3
IOC3
S
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
YYYY
S
S N
Y YNS
Y
Y
Y Y
Y
Y
YY
Y
Y
Y
Y
Y
YY
Y
Y
Y
YY
S S
S S
YY
S
S
Y
Y
BOM options provided by this page:
NOTE: CPU current/voltage monitoring
(NONE)
(NONE)
Caps should connect to GND_SMU_AVSS.
NOTE: Pinout matches SMU pinout v1.51.
those capacitors are provided on
review the latest SMU specification
to ensure missing pull-ups are
reuire pull-ups that are not.
provided on this page. Please.
provided on another page.
signal (GND_SMU_AVSS). None of
a 100pF capacitor to the SMU AVSS
NOTE: All analog inputs to SMU should have
NOTE: Some primary and alternate functions
this page.
affect other analog inputs such as
AC adapter ID.
Y
Y
INT5*
TA2in
YY
S
Y
Y
Y
Y
Y
AN2
INT4*
AN21
AN07
AN06
S = Spare
(see aliases below)
Y = Primary function
RXD1
CTS0*
S
Desktop
RTS0*/
AN02
S
RXD0
Portable
Y
CLK1
PULLUP AT LEVEL SHIFTER P.30
DRIVEN PUSH/PULL
System Management Unit
P1[0] NOT USED --->
8X4.5MM-SM
10.0000M
CRITICAL
21
Y2800
QFP-80
M30280F8-LF
SEE_TABLE
10
12
11
77
13
9
79
80
1
2
3
4
5
7
8
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
40
41
42
43
32
33
34
35
36
37
38
39
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
68
69
70
71
72
73
74
76
59
60
61
62
63
64
65
66
67
6
75
78
U2800
MSOP
DS1338U-33
CRITICAL
2
1
8
3
7
5
6
4
U2801
10%
402
CERM
1uF
6.3V
2
1
C2825
1/16W
5%
402
MF-LF
10K
2
1
R2825
5%
402
CERM
18PF
50V
2
1
C2804
5%
402
CERM
18PF
50V
2
1
C2805
MF-LF
402
5%
1/16W
470
2
1
R2817
1/16W
5%
402
MF-LF
10M
21
R2816
1/16W
5%
402
MF-LF
10K
2
1
R2827
2.0K
MF-LF
402
1%
1/16W
21
R2812
NOSTUFF
2.0K
MF-LF
402
1%
1/16W
21
R2811
NOSTUFF
10K
MF-LF
402
5%
1/16W
21
R2813
100K
MF-LF
402
1%
1/16W
21
R2810
MF-LF
402
5%
1/16W
10K
21
R2802
1/16W
5%
402
MF-LF
10K
21
R2800
10K
MF-LF
402
5%
1/16W
12
R2804
20%
402
CERM
0.1uF
10V
2
1
C2809
20%
402
CERM
0.1uF
10V
2
1
C2808
20%
402
CERM
10V
0.1uF
2
1
C2802
402
CERM
10V
20%
0.1uF
2
1
C2801
10%
X5R
6.3V
10UF
805
2
1
C2800
10%
402
CERM
1uF
6.3V
2
1
C2803
1/16W
5%
402
MF-LF
4.7
21
R2815
SM
21
XW2800
SM-LF
32.768K
CRITICAL
4
1
Y2801
I456
I457
MF-LF
402
5%
1/16W
10K
21
R2801
SM
P4MM
1
PP2800
SM
2
1
XW2802
SM
P4MM
1
PP2801
SM
2
1
XW2801
P4MM
SM
1
PP2806
P4MM
SM
1
PP2805
SM
P4MM
1
PP2804
I472
I473
I474
I475
TITLE=KILOHANA
ABBREV=DRAWING
System Management Unit
SYNC_DATE=08/26/2005
SYNC_MASTER=Q63
154
28
F
051-6863
SYS_NORTH_RESET_L
0.25MM SPACING
SYS_NORTH_RESET_L
SYS_NORTH_RESET_L
SMU_RESET
0.25MM SPACING
SYS_NORTH_RESET_L
SYS_RESET_BUTTON_L
SYS_RESET_BUTTON_L
CLOCK_RESET_L
SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF
SB_CPU_VDNAP1
SYS_SLOT_PWR
SMU_PWRSEQ_P9_6
SMU_FAN_RPM0
SB_CPU_VDNAP2
I2C_SMU_CPU_SCL_IN
I2C_SMU_CPU_SDA_IN
CPU_VID<0>
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.38mm
PP3V3_ALL_SMU_AVCC
CPU_VID<3>
CPU_VID<4>
CPU_SENSE_I
CPU_TEMP
MIN_LINE_WIDTH=0.38mm
MIN_NECK_WIDTH=0.2MM
GND_SMU_AVSS
VOLTAGE=0V
SMU_CLK10M_XOUT_R
0.38MM SPACING
=PPVREF_SMU
SYS_POWER_BUTTON_L
NB_SUSPENDACK_L
SB_SUSPENDACK_L
SYS_LED
SYS_PME_L
SYS_SLEWING_L
I2C_SMU_CPU_SDA_OUT_L
MAKE_BASE=TRUE
SYS_POWERUP_L
SMU_BOOT_RXD
SMU_FAN_RPM2
SMU_FAN_RPM1
SMU_BOOT_CNVSS
SMU_BOOT_TXD
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
CPU_SENSE_V
CPU_BYPASS
SMU_FAN_RPM5
GND_SMU_AVSS
I2C_RTC_SCL
RTC_CLK32K_X2
RTC_CLK32K_X1
=PP3V3_ALL_RTC
=PP3V3_ALL_SMU
I2C_RTC_SDA
CPU_VID<3>
CPU_VID<4>
CPU_VID<0>
CPU_VID<1>
I2C_SMU_CPU_SCL_IN
SYS_POWERFAIL_L
SMU_SUSPENDREQ_L
DIAG_LED
I2C_SMU_A_SDA_OUT_L
SMU_FAN_TACH0
SYS_DOOR_AJAR_L
SMU_FAN_TACH9
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
I2C_SMU_CPU_SCL_OUT_L
SMU_PWRSEQ_P9_5
SB_STOPXTALS_L
SB_TO_SMU_INT_L
SMU_FAN_TACH8
SMU_SLEEP
I2C_SMU_B_SCL
I2C_SMU_B_SDA
CPU_VID<1>
CPU_VID<2>
SMU_FAN_RPM4
SMU_CLK10M_XOUT
SYS_OVERTEMP_L
I2C_SMU_E_SCL
SMU_FAN_TACH3
SMU_FAN_TACH7
SMU_FAN_TACH6
I2C_SMU_A_SCL_IN
I2C_SMU_A_SDA_IN
SMU_FAN_TACH5
SMU_FAN_TACH4
SMU_FAN_TACH2
SMU_FAN_TACH1
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_OUT_L
I2C_SMU_E_SDA
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
I2C_SMU_CPU_SDA_OUT_L
I2C_SMU_CPU_SCL_OUT_L
SMU_BOOT_SCLK
CPU_VID<5>
MAKE_BASE=TRUE
SMU_BOOT_BUSY
NB_TDO_SMU
NB_TMS
NB_TCK
NB_TDI
0.38MM SPACING
RTC_CLK32K_X2
0.38MM SPACING
SMU_CLK10M_XOUT
SMU_FAN_PWM9
CPU_B_INSERTED_L
SMU_FAN_PWM8
CPU_A_INSERTED_L
SAT_MRESET_L
SMU_FAN_RPM7
SMU_FAN_RPM6
SMU_PWRSEQ_P1_4
SMU_FAN_RPM3
SMU_SER_SEL
0.38MM SPACING
RTC_CLK32K_XTAL
RTC_CLK32K_X1
I2C_SMU_A_SCL
I2C_SMU_A_SDA
I2C_SMU_A_SDA_IN
I2C_SMU_CPU_SDA_IN
CPU_VID<2>
=PP3V3_PWRON_SMU
=PP3V3_RUN_SMU
=PP2V5_PWRON_NB_MISC
SYS_PME_L
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SMU_SLEEP
SYS_POWERUP_L
0.25MM SPACING
SYS_IO_RESET_L
SMU_RESET
=PP3V3_ALL_SMU
SMU_BOOT_CE
0.38MM SPACING
SMU_CLK10M_XTAL
SMU_CLK10M_XIN
PP_3V3ALLSMU
=PP3V3_ALL_SMU
PP_3V3ALLSMUAVCC
SMU_CLK10M_XOUT_R
SYS_POWER_BUTTON_L
SMU_IO_RESET_L
SMU_RESET_L
SMU_IO_RESET_L
P3MM SPACING
CLOCK_RESET_L
P3MM SPACING
SYS_RESET_BUTTON_L
P3MM SPACING
SMU_CLK10M_XIN
LAST_MODIFIED=Tue Nov 1 13:46:23 2005
85
85
50
50
50
28
29
43
39
50
43
28
122
29
29
55
29
122
28
12
55
28
30
93
43
30
30
122
28
30
12
119
28
28
29
30
30
30
30
29
29
28
31
31
31
31
31
28
28
28
26
31
7
29
29
29
28
7
31
31
31
31
31
28
31
31
30
31
31
24
31
31
31
31
31
31
31
31
29
29
39
39 31
31
31
30
20
20
28
26
28
30
7
30
7
29
7
28
30
29
30
28
29
28
28
28
28
28
28
26
31
24
31
4
32
24
28
28
28
28
28
55
55
6
28
55
6
30
24
29
24
24
28
6
6
33
32
6
6
4
4
55
29
31
6
39
28
28
29
6
39
28
28
28
28
28
7
24
8
28
32
31
31
4
4
28
4
24
24
31
28
39
39
28
28
31
28
20
39
31
31
31
28
28
31
31
33
32
28
28
39
28
28
28
28
6
31
6
28
28
4
31
31
28
31
31 28
28
28
7
7
7
24
24
24
28
6
24
6
6
28
6
6
6
28
6
28
6
28
26
28
28
G
D
S
G
D
S
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
QTY
DESCRIPTION
PART#
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SMU DEBUG/DOWNLOAD CONNECTOR
SYS POWER AND RESET BUTTON
POWER BUTTON HEADER
518S0328
DIGITAL GND THROUGHOUT
RTC BATTERY
SYS LED’S
POWER
FROM SMU
DRIVE STRONG HRESET AND BYPASS TO CPU
PCB: PLACE Q2984 NEAR CPU
ALWAYS ON (TRICKLE)
RESET
I2C ADDR:72(1001000)
518S0327
SMU RESET BUTTON
SAME CONNECTOR AS Q63 CPU CARD FOR SAT
R2930, R2931, J2904 SHOULD BE MOVED BACK TO THE DEVLOPMENT BOM POST-RAMP
AMBIENT LIGHT SENSOR CONNECTOR
CRITICAL
BB10209-A5
TH
1 2
J2902
SPST
SM-LF
43
21
SW2902
SM-LF
SPST
DEVELOPMENT
43
21
SW2900
1/16W
402
1K
5%
MF-LF
21
R2913
SPST
DEVELOPMENT
SM-LF
43
21
SW2901
DEVELOPMENT
1K
1/16W
5%
402
MF-LF
21
R2912
1K
402
MF-LF
1/16W
5%
21
R2902
PP5V_PWRON
WHITE-500MCD
CRITICAL
3X2MM-SM
2
1
LED2901
0
5%
1/16W
MF-LF
402
NOSTUFF
21
R2900
402
1/16W
MF-LF
1%
56.2
17_INCH_LCD
2
1
R2903
SOT23-LF
FDV301N
2
1
3
Q2901
NOSTUFF
1/16W
4.7K
402
MF-LF
5%
2
1
R2908
MMBD914XXG
SOT23
3
1
D2900
SOD-123
B0530WXF
2 1
DS2900
30K
5%
1/16W
402
MF-LF
2
1
R2929
10%
1UF
402
CERM
6.3V
2
1
C2900
402
0
5%
1/16W
MF-LF
21
R2931
F-RT-SM
SM12B-SRSS-TB-LF
9
8
7
6
5
4
3
2
12
11
10
1
13
14
J2904
I6
NOSTUFF
0
5%
MF-LF
402
1/16W
2
1
R2925
100
1%
402
1/16W
MF-LF
21
R2930
1K
5%
1/16W
MF-LF
402
21
R2983
1K
5%
1/16W
MF-LF
402
21
R2984
SOT-363
2N7002DW-X-F
1
2
6
Q2984
2N7002DW-X-F
SOT-363
4
5
3
Q2984
F-ST-SM
53398-0476
CRITICAL
4
3
2
1
6
5
J2901
PP3V3_PWRON
M-ST-SM
53398-0276
CRITICAL
2
1
4
3
J2903
10K
1/16W
402
MF-LF
5%
2
1
R2924
NOSTUFF
1/16W
10K
402
MF-LF
5%
2
1
R2923
0.1UF
20%
10V
402
CERM
2
1
C2904
CERM
20%
402
10V
0.1UF
2
1
C2905
SYNC_DATE=09/20/2005SYNC_MASTER=FINO-M23
154
29
051-6863
F
SMU SUPPLEMENTAL (2)
114S0081
RES, 39.2 OHM, 1%, 402, LF
1
20_INCH_LCD
R2903
SMU_BOOT_SCLK
SMU_BOOT_RXD
NC_J2904_6
SMU_BOOT_TXD
NC_J2904_11
SMU_BOOT_BUSY_R
SMU_MANUAL_RESET_L
RESET_BUTTON_L
POWER_BUTTON_L
=PP3V3_ALL_RTC
PP3V3_ALL_RTC
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
=PP3V3_ALL_SMU
POWER_BUTTON_L
SMU_RESET_L
CPU_HRESET_L
CPU_BYPASS_L
CPU_BYPASS
CPU_HRESET
SYS_RESET_BUTTON_L
SYS_POWER_BUTTON_L
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
PP3V3_ALL_BATT_SAFETY PP3V3_ALL_BATT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
=PPV_EI_CPU
=PP3V3_ALL_SMU
SYS_LED_DRV_C
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
SYS_LED
SYS_LED_DRV_K
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
I2C_ALS_SDA
I2C_ALS_SCL
SMU_BOOT_BUSY
NC_J2904_12
SMU_BOOT_CNVSS
SMU_MANUAL_RESET_L
SMU_BOOT_CE
56
29
48
29
28
47
28
28
28
28
29
29
7
29
28
28
30
7
28
28
29
28
6
6
6
6
6
6
6
28
6
6
6
43
43
28
31
28
6
7
6
28
39
39
6
6
6
6
6
G
D
S
G
D
S
125
125
G
D
S
G
D
S
G
D
S
EN*
GND
B
A
A*/B
Y*
Y
VCC
G
D
S
G
D
S
Y0
Y1
GND
E*
A
VCC
G
D
S
Y
A
GND
VCC
125
Y
GND
VCC
A
34
Y
GND
VCC
A
34
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CONSIDER COMBINING Q3040 AND Q3006 TO A DUAL PART
PULLUP IF
LEVEL SHIFT SMU TMS TO CPU (BACKUP PLAN)
KODIAK JTAG IS NOSTUFFED
VIH = 2.0V, 3.3V TOLERANT
LEFTOVER FROM UNUSED PRIMARY PLAN - NOT STUFFED
SMU JTAG TCK TO CPU (BACKUP PLAN)
U700 IS POWERED BY PP3V3_ALL
TO LEVEL SHIFTER
VIH=2V
SYS_NORTH_RESET FROM SMU TO NB_PU_RST
SAME AS Q63
SAME AS Q63
MISC. SMU BUFFERS
SAME AS (Q63).
NB SUSPEND_ACK_L LEVEL 2.5V TO 3.3V LEVEL SHIFTER
SHARE CPU AND NB JTAG TMS WITH SMU
ALL JTAG-RELATED PINS
STRAIGHT TO NB
PCB: PLACE R3050, Q3050, R3051 NEAR CPU. PLACE Q3021, R3052 NEAR SMU.
PCB: PLACE U3070 NEAR SMU
3.3V TOLERANT
SMU DRIVES 3.3V PUSH-PULL ON
STUFF IF USING REGISTERED DIMM
VIH = 2.0V, 3.3V TOLERANT
VCC RANGE 0.8V - 2.7V VCC RANGE 0.8V - 2.7V
PCB: PLACE 33 OHM RES NEAR U3030/31 PART.
PCB: PLACE U3071 NEAR SMU OR NEAR KODIAK.
SHARE CPU AND NB JTAG TDO WITH SMU
LEVEL SHIFT TDO FROM CPU TO MUX
PULLDOWNS TO BUFFERS/LOGIC GATES
PLACE O-OHM R3030 AND R3031 TO AVOID STUBS
NB JTAG IS A DEVELOPMENT ONLY FEATURE
PCB: PLACE U3030 AND U3031 NEAR CPU AND KODIAK.
SMU TO NB SUSPEND_REQ
SMU JTAG TDI TO CPU (BACKUP PLAN)
R3030,R3031,C3031,U3031,R3032,R3033 SHOULD MOVE TO DEVELOPMENT BOM POST RAMP
SHARE SMU JTAG TCK WITH CPU AND NB (PRIMARY PLAN)
TO AVOID STUBS
NOTE: WE WENT WITH BACKUP PLAN, PRIMARY REMOVED
SHARE SMU JTAG TDI WITH CPU AND NB (PRIMARY PLAN)
SOT-363
2N7002DW-X-F
1
2
6
Q3005
2N7002DW-X-F
SOT-363
4
5
3
Q3000
402
1/16W
0
NOSTUFF
5%
MF-LF
21
R3008
5%
100
402
MF-LF
1/16W
2 1
R3022
5%
100
MF-LF
402
1/16W
2 1
R3023
TSSOP
74LC125
8
14
107
9
U700
MF-LF
402
5%
1/16W
4.7K
2
1
R3021
TSSOP
74LC125
6
14
47
5
U700
2N7002
NOSTUFF
SOT23-LF
2
1
3
Q3040
1K
1/16W
MF-LF
402
NOSTUFF
5%
2
1
R3040
2N7002DW-X-F
SOT-363
4
5
3
Q3005
5%
4.7K
402
MF-LF
1/16W
2
1
R3003
5%
1/16W
MF-LF
402
4.7K
2
1
R3010
SOT23-LF
2N7002
NOSTUFF
2
1
3
Q3006
CRITICAL
TSSOP
SN74LVC2G157
3
5
8
4
7
2
6
1
U3070
0.1UF
CERM
10V
20%
402
2
1
C3070
0
1/16W
MF-LF
402
5%
NOSTUFF
21
R3009
5%
MF-LF
1/16W
10K
402
2 1
R3050
5%
402
MF-LF
1/16W
1K
2
1
R3051
100
MF-LF
402
1/16W
5%
2
1
R3052
SOT23
2N3904LF
2
3
1
Q3050
0.1UF
CERM
10V
20%
402
2
1
C3071
5%
1K
1/16W
402
MF-LF
2
1
R3093
5%
402
MF-LF
1/16W
1K
2
1
R3091
SOT23
2N3904LF
NB_SUSPEND_ACK_L_R
2
3
1
Q3090
MF-LF
402
1/16W
10K
5%
2 1
R3090
5%
MF-LF
1/16W
0
NOSTUFF
402
2 1
R3092
2N7002DW-X-F
SOT-363
1
2
6
Q3000
2N7002DW-X-F
SOT-363
4
5
3
Q3021
CRITICAL
74LVC1G
SC70-6
4
6
5
2
3
1
U3071
33
5%
402
1/16W
MF-LF
2 1
R3033
MF-LF
1/16W
33
402
5%
2 1
R3032
CERM
10V
402
0.1UF
20%
2
1
C3031
MF-LF
1/16W
5%
10K
402
2
1
R3034
MF-LF
402
1/16W
10K
5%
2
1
R3035
SOT-363
2N7002DW-X-F
1
2
6
Q3021
MF-LF
402
1/16W
10K
5%
2 1
R3038
100K
5%
402
1/16W
MF-LF
21
R3036
1/16W
MF-LF
402
5%
100K
21
R3071
100K
5%
402
MF-LF
1/16W
21
R3037
5%
402
1/16W
100K
MF-LF
21
R3070
VSSOP
SN74AUC2G125
NOSTUFF
6
8
1
4
2
U5640
SN74AUC2G34
SOT23-6
6
5
2
1
U3031
SOT23-6
SN74AUC2G34
4
5
2
3
U3031
2N7002DW-X-F
SOT-363
1
2
6
Q3080
1/16W
MF-LF
4.7K
402
5%
2
1
R3083
SOT-363
2N7002DW-X-F
1
2
6
Q3081
MF-LF
402
5%
1K
1/16W
2
1
R3084
33
1/16W
402
MF-LF
5%
2 1
R3085
MF-LF
1/16W
402
5%
33
2 1
R3082
1K
5%
402
MF-LF
1/16W
2
1
R3081
SOT-363
2N7002DW-X-F
4
5
3
Q3081
MF-LF
1/16W
5%
402
4.7K
2
1
R3080
2N7002DW-X-F
SOT-363
4
5
3
Q3080
NOSTUFF
0
1/16W
402
MF-LF
5%
21
R3099
NOSTUFF
0
1/16W
402
MF-LF
5%
21
R3098
MF-LF
402
1/16W
5%
1K
2
1
R3027
SOT-363
2N7002DW-X-F
4
5
3
Q3031
1K
1/16W
5%
402
MF-LF
2
1
R3026
SOT23
2N3904LF
2
3
1
Q3030
5%
MF-LF
402
1/16W
10K
2 1
R3020
5%
MF-LF
402
1/16W
33
2 1
R3028
402
0
5%
1/16W
MF-LF
2
1
R3031
MF-LF
5%
0
402
1/16W
2
1
R3030
5%
402
MF-LF
1/16W
1K
2
1
R3000
MF-LF
5%
1/16W
402
100
2
1
R3001
5%
MF-LF
402
1/16W
0
NOSTUFF
21
R3002
5%
4.7K
1/16W
MF-LF
402
2
1
R3007
5%
10K
1/16W
402
MF-LF
2
1
R3006
SMU SUPPLEMENTAL (3)
SYNC_MASTER=FINO-M23 SYNC_DATE=09/20/2005
051-6863
F
30
154
JTAG_NB_TDI
=PP3V3_PWRON_SMU
JTAG_NB_TDO
JTAG_CPU_TDO_3V3
SYS_2SLEEP_R
SMU_JTAG_NB_TCK
=PP2V5_PWRON_NB_MISC
SMU_JTAG_NB_TDI
=PP2V5_PWRON_NB_MISC
SYS_NORTH_RESET_L
SMU_SUSPENDREQ_L
JTAG_NB_TDO
SMU_JTAG_TCK
SMU_JTAG_TCK
NB_PU_RST_L
SMU_JTAG_TDI
JTAG_CPU_TCK
SMU_JTAG_TDI
SMU_JTAG_TDI_L
JTAG_CPU_TDI
JTAG_CPU_TDI_2_R
=PP3V3_RUN_SMU
=PPV_EI_CPU
=PP3V3_PWRON_SMU
JTAG_CPU_TMS_2_L
SMU_CPU_TMS
JTAG_SMU_TMS_2_R
SMU_JTAG_TCK_L
=PP3V3_RUN_SMU
=PPV_EI_CPU
SYS_IO_RST_L_R
SMU_IO_RESET
=PP3V3_PWRON_SMU
JTAG_CPU_TMS_2_R
JTAG_CPU_TMS
=PPV_EI_CPU
JTAG_NB_TCK_RJTAG_NB_TDI_R
SMU_CPU_NB_SEL
NB_SUSPENDACK_L
JTAG_NB_TMS
SMU_CPU_TMS
=PP2V5_PWRON_NB_MISC
JTAG_NB_TCK
=PP3V3_PWRON_SMU
SYS_IO_RESET_L
=PP3V3_PWRON_SMU
SYS_SLEEP_R
SYS_SLEEP
NB_PU_RESET
=PP2V5_PWRON_NB_MISC
SYS_IO_RST_L_R
=PP3V3_PWRON_SMU
=PP3V3_PWRON_SMU
NC_JTAGMUX_3
SMU_JTAG_TDO
SMU_JTAG_TMS
NB_SUSPEND_ACK_L
SMU_JTAG_TDI
SMU_JTAG_TCK
SMU_JTAG_TMS
SMU_CPU_NB_SEL
SYS_NORTH_RESET_L_R
JTAG_CPU_TDO
JTAG_CPU_TDO_R
JTAG_CPU_TDO_L
=PP3V3_PWRON_SMU
JTAG_CPU_TDO_3V3
=PP2V5_PWRON_NB_MISC
SMU_SUSPENDREQ_L_R
JTAG_CPU_TCK_2_R
SMU_SLEEP
SMU_IO_RESET_L
NB_SUSPENDACK
NB_SUSPEND_REQ_L
PMU_SUSPEND_REQ
=PP2V5_PWRON_NB_MISC
SYS_SLEEP
54
54
30
30
56
56
56
26
26
39
39
48
48
48
39
16
39
39
39
16
43
30
30
30
47
43
30
47
43
47
30
43
122
43
15
30
43
43
43
30
30
15
30
30
28
28
43
30
28
30
30
28
30
30
30
28
30
119
30
13
28
30
30
47
30
28
28
13
20
28
20
20
20
28
20
31
31 31
43
31
43
20
29
28
20
29
28
43
29
31
20
20
20
28
28
28
12
20
28
28
31
62
31
31
31
31
43
28
20
20
12
9
7
9
30
7
7
28
24
9
30
30
20
30
9
30
9
7
7
7
30
7
7
30
67
7
9
7
30
28
9
30
7
9
7
24
7
11
7
30
7
7
9
31
30
20
30
30
30
30
9
7
30
7
28
28
20
7
11
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SELECT BETWEEN CPU OR NB TMS AND TDO FROM/TO SMU
M23/M33 ONLY CONNECTS I2C TO KODIAK NOW; CPU HAS PULLUPS ON ITS PG.
Q63 NET NAME (SHARED PAGE)
P0.5
P0.6
P0.4
P0.3
P0.2
P0.1
P0.0
P0.7
P1.6
P1.7
P2.0
P1.5
P1.4
P1.0
P1.1
P1.2
P1.3
M23 SMU ALLOCATION
CPU_VID_LE0
CPU_VID_LE1
CPU_SENSE_I1
CPU_SENSE_V1
CPU_TEMP1
POWERFAIL*
FAN_TACH2_1
DOOR_AJAR*
SMU_SCCL_SEL
FAN_CNTL0_6
FAN_CNTL0_5
FAN_CNTL0_4
CPU_SENSE_I0
CPU_TEMP0
CPU_BYPASS
PS1_3
PS1_4
P2.7
P3.0
P3.1
P3.2
P3.3
P2.6
P2.5
P2.3
P2.4
P3.4
P3.5
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
CPU_VID[2]
CPU_VID[1]
CPU_VID[0]
OVERTEMP*
IIC_E_CLK
IIC_E_DAT
IIC_A_CLK
IIC_A_DAT
FAN_TACH2_7
FAN_TACH2_3
FAN_TACH2_2
DIAG_LED
TCK
TDI
P7.2
P7.7
P7.6
P7.5
P7.4
P7.3
P7.0
P7.1
P6.6
P6.7
P8.0
P9.2
P9.1
P9.0
P8.1
P8.2
P8.3
P8.6
P8.7
SMU_DOORBELL*
CPU_HRESET
CLK_RESET*
NB_RESET*
SYSTEM_LED
FAN_CNTL7_7
FAN_CNTL7_5
FAN_CNTL7_4
FAN_CNTL7_3
DEBUG_TXD
IIC_B_DAT
IIC_B_CLK
SLEEP
POWERUP*
NB_TMS
SLEWING*
VDNAP0
VDNAP2
CPU_TMS
P10.1
P10.4
P10.3
P10.2
P10.0
P9.3
P9.5
P9.6
P9.7
P10.5
P10.6
P10.7
RST_BUTTON*
PWR_BUTTON*
SUSPEND_REQ*
SUSPEND_IO_ACK*
SUSPEND_ACK*
IO_RESET*
STOP_XTAL*
SLOT_TOTAL_PWR
TDO
VDNAP1
PS9_5
PS9_6
M23 NET NAME
M23/M33 DOESN’T USE. P1.0 NC ON PG 7.
M23/M33 DOESN’T USE P1.4. NC ON PG 7.
M23/M33 DOESN’T NEED TO MAKE VDNAP0 DO TRIPLE-DUTY.
M23/M33 USES TACH0 (P2.2), TACH1 (P2.3), TACH2 (P2.4) ONLY.
M23/M33 DOESN’T HAVE THIS FAN (P7.4)
M23/M33 USES FAN_RPM0 (P7.3), FAN_RPM1 (P7.5), FAN_RPM2 (P7.7) ONLY.
Q63 USE OF P7.2 IS PWM FAN
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
Q63 USE OF P9.1 IS TACH 8.
M23/M33 HAS NO SLOTS.
M23/M33 DOESN’T HAVE FAN TACHS P2.5, P2.6, P2.7.
CPU_VID_LE0 FOR Q82. NOT M23/M33 FEATURE.
CPU_VID_LE1 FOR Q82. NOT M23/M33 FEATURE.
M23/M33 DOESN’T HAVE THIS FAN.
CONSIDER DOOR_AJAR FOR M23/M33 DIMM ACCESS DOOR?
Q63 NC’S THESE AS IT USES A SAT.
SMU USES P1.1, P1.2, P1.3, P9.5, P9.6 FOR PWRSEQ ON PG 7.
CPU_VID[3]
P6.4
P6.5
DEBUG_RXD
CPU_VID[5]
NOTE:PULL UP CPU_VID<5>TO
2.2V FOR CPU VRM10.
SO PULLUPS MUST BE 1K
CPU_VID[4]
NOTE: SC2642 VID PINS HAVE LEAKAGE TO GND.
CPU_SENSE_V0
COMMENT (ONLY IF USE DIFFERS FROM Q63)
ALIASES ARE ONLY NECESSARY WHERE USE DIFFERS FROM Q63.
SMU ALIASES
P2.1
P2.2
FAN_TACH2_4
FAN_TACH2_5
FAN_TACH2_6
PME*
P8.4
P8.5
Q63 USES SMU_SER_SEL FOR SPDIF-SMU-DEBUG. NOT M23/M33 FEATURE.
M23/M33 DOESN’T HAVE THOSE FANS.
CPU VID<0:5>
VID CONTROLLED BY SMU
PP3V3_RUN
402
5%
MF-LF
1/16W
1K
2
1
R3104
5%
MF-LF
402
1/16W
1K
2
1
R3109
5%
MF-LF
402
1/16W
1K
2
1
R3108
402
5%
1/16W
MF-LF
2.0K
2
1
R3111
NOSTUFF
5%
1/16W
MF-LF
1K
402
2
1
R3127
1/16W
NOSTUFF
1K
5%
MF-LF
402
2
1
R3129
NOSTUFF
1/16W
1K
5%
MF-LF
402
2
1
R3130
402
MF-LF
1K
5%
1/16W
2
1
R3117
402
MF-LF
5%
1/16W
1K
2
1
R3116
402
MF-LF
1/16W
5%
1K
2
1
R3114
NOSTUFF
1K
5%
1/16W
MF-LF
402
2
1
R3131
1K
NOSTUFF
5%
1/16W
MF-LF
402
2
1
R3132
NOSTUFF
F-ST-SM
BM12B-SRSS-TB
9
8
7
6
5
4
3
2
12
11
10
1
13
14
J3108
5%
402
MF-LF
1/16W
0
21
R3120
5%
1/16W
MF-LF
402
0
21
R3122
402
MF-LF
1/16W
5%
0
21
R3119
402
5%
MF-LF
0
1/16W
21
R3121
402
5%
MF-LF
1/16W
0
21
R3124
402
5%
1/16W
0
MF-LF
21
R3123
SOD-123
B0530WXF
2 1
DS3100
31
154
F
051-6863
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
SMU SUPPLEMENTAL (4)
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
PP3V3_CPU_VID_D
CPU_VID<1>
MAKE_BASE=TRUE
CPU_VID_R<0>
MAKE_BASE=TRUE
CPU_VID<2>
CPU_VID<3>
MAKE_BASE=TRUE
CPU_VID<4>
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT_L
MAKE_BASE=TRUE
SMU_JTAG_TMS
MAKE_BASE=TRUE
SB_VDNAP0
MAKE_BASE=TRUE
NC_I2C_SMU_CPU_SCL_IN
MAKE_BASE=TRUE
SMU_CPU_NB_SEL
MAKE_BASE=TRUE
SMU_JTAG_TCK
MAKE_BASE=TRUE
SMU_JTAG_TDI
MAKE_BASE=TRUE
I2C_SMU_A_SDA
MAKE_BASE=TRUE
NC_SMU_FAN_TACH5
MAKE_BASE=TRUE
NC_SMU_CPU_VID_LE1
SYS_DOOR_AJAR_L
SMU_FAN_TACH9
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<4>
CPU_VID_R<5>
CPU_VID_R<3>
CPU_VID<5>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU_VID<0>
MAKE_BASE=TRUE
SMU_JTAG_TDO
I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
NC_SLOT_TOTAL_PWR
SYS_SLOT_PWR
MAKE_BASE=TRUE
CPU_HRESET
SMU_FAN_TACH8
SB_CPU_VDNAP0_OR_QREQ_OR_SPDIF
I2C_SMU_CPU_SCL_IN
I2C_SMU_CPU_SDA_IN
I2C_SMU_A_SCL_OUT_L
I2C_SMU_A_SCL_IN
SMU_FAN_TACH5
MAKE_BASE=TRUE
NC_SMU_FAN_TACH7
SMU_FAN_TACH7
SMU_FAN_TACH6
MAKE_BASE=TRUE
NC_SYS_DOOR_AJAR_L
MAKE_BASE=TRUE
NC_SMU_CPU_VID_LE0
MAKE_BASE=TRUE
NC_SMU_SER_SEL
SMU_SER_SEL
MAKE_BASE=TRUE
NC_SMU_FAN_RPM5
SMU_FAN_RPM5
MAKE_BASE=TRUE
NC_SMU_FAN_RPM3
SMU_FAN_RPM3
MAKE_BASE=TRUE
NC_SMU_FAN_RPM4
SMU_FAN_RPM4
MAKE_BASE=TRUE
NC_SMU_FAN_TACH3
SMU_FAN_TACH4
SMU_FAN_TACH3
MAKE_BASE=TRUE
NC_SMU_FAN_TACH4
MAKE_BASE=TRUE
I2C_SMU_A_SCL
I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT_L
NC_J3108_8
NC_J3108_9
NC_J3108_10
NC_J3108_11
NC_J3108_12
39
39
28
50
28
28
28
28 30
24
9
30
30
30
28
9
9
28
28
50
50
50
50
50
28
28
30 28
9
28
29 28
28
28
28
28
28
28
9
28
28
9
9
9
28
9
28
9
28
9
28
9
28
28
9
28
28
28
9
9
9
9
9
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
M33: CPU FAN
M23: HD FAN
M33: ODD FAN
M23: ODD FAN
518S0193
MOTOR CONTROL
MOTOR CONTROL
TACH
FAN 1
FAN 0
GND
TACH
GND
12V DC
12V DC
518S0326
PP3V3_RUN
10K
402
1/16W
MF-LF
5%
2
1
R3210
PP3V3_RUN
5%
402
MF-LF
1/16W
10K
2
1
R3259
NOSTUFF
603
0.1UF
20%
25V
CERM
2
1
C3202
1206
MF-LF
1/4W
5%
1.5K
2
1
R3205
CRITICAL
1206A-03-LF
NTHS5443T1
5
4
8
7
6
3
2
1
Q3203
805
MF-LF
5%
1.5K
1/8W
2
1
R3207
MMBD914XXG
SOT23
3
1
D3202
805
0
5%
1/8W
MF-LF
21
R3208
16V
X7R
805
0.47UF
10%
2
1
C3204
805
MF-LF
1/8W
5%
3.9K
R3206
PP12V_RUN
SOT-363
2N7002DW-X-F
4
5
3
Q3201
MF-LF
1/8W
5%
1.0K
805
2
1
R3202
SOT-363
2N7002DW-X-F
1
2
6
Q3201
NTHS5443T1
1206A-03-LF
CRITICAL
5
4
8
7
6
3
2
1
Q3253
CERM
20%
0.1UF
603
NOSTUFF
25V
2
1
C3252
805
MF-LF
5%
1.5K
1/8W
2
1
R3257
805
5%
0
1/8W
MF-LF
21
R3258
16V
X7R
0.47UF
805
10%
2
1
C3254
MF-LF
805
1/8W
5%
3.9K
R3256
SOT23
MMBD914XXG
3
1
D3252
1206
1.5K
5%
1/4W
MF-LF
2
1
R3255
SOT-363
2N7002DW-X-F
4
5
3
Q3251
PP12V_RUN
1.0K
MF-LF
1/8W
5%
805
2
1
R3252
SOT-363
2N7002DW-X-F
1
2
6
Q3251
ELEC
16V
20%
6.3X11-TH-LF
120UF
2
1
C3203
120UF
6.3X11-TH-LF
ELEC
20%
16V
2
1
C3253
805
1.0K
5%
1/8W
MF-LF
NOSTUFF
2
1
R3215
805
MF-LF
1/8W
5%
1.0K
NOSTUFF
2
1
R3265
805
0
5%
1/8W
MF-LF
21
R3266
1/8W
MF-LF
5%
0
805
21
R3216
B130LBT01XF
NOSTUFF
SMB
21
D3203
NOSTUFF
B130LBT01XF
SMB
21
D3253
CRITICAL
M-RT-SM
53261-0498
4
3
2
1
6
5
J3200
CRITICAL
M-RT-SM
53261-0598
5
4
3
2
1
7
6
J3201
SYNC_DATE=08/26/2005SYNC_MASTER=FINO-M23
Fan 0, 1 & System Temp
F
051-6863
154
32
SMU_FAN_TACH1
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_1_PWR
F1_VOLTAGE8R5
F1_RCFEEDBK
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
F0_GATESLOWDN
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_0_OUT
SMU_FAN_TACH0
FAN_0_PWR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
F0_RCFEEDBK
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
F1_GATESLOWDN
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_1_OUT
SMU_FAN_RPM0
F0_DRV
F0_VOLTAGE8R5
SMU_FAN_RPM1
F1_DRV
28
28
28
28
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
HD TEMP SENSOR
TO ALLOW EMC CAPS ON M23 ONLY
NOTE: BROKE SYNC ON THIS PAGE
I2C ADDR:0X92(1001001)
I2C ADDR:0X90(1001000)
ODD TEMP SENSOR
12V DC
518S0193
518S0193
518S0328
M23: CPU FAN
MOTOR CONTROL
M33: HD FAN
FAN 2
TACH
GND
PP3V3_RUN
5%
402
MF-LF
1/16W
10K
2
1
R3309
PP3V3_RUN
53261-0498
M-RT-SM
CRITICAL
4
3
2
1
6
5
J3301
1206A-03-LF
NTHS5443T1
5
4
8
7
6
3
2
1
Q3303
SOT23
MMBD914XXG
3
1
D3302
25V
603
0.1UF
20%
CERM
NOSTUFF
2
1
C3302
805
MF-LF
1.5K
1/8W
5%
2
1
R3307
MF-LF
805
0
1/8W
5%
21
R3308
0.47UF
10%
X7R
16V
805
2
1
C3304
805
MF-LF
1/8W
5%
3.9K
R3306
1/4W
5%
1.5K
1206
MF-LF
2
1
R3305
SOT-363
2N7002DW-X-F
4
5
3
Q3301
PP12V_RUN
805
1.0K
5%
1/8W
MF-LF
2
1
R3302
SOT-363
2N7002DW-X-F
1
2
6
Q3301
6.3X11-TH-LF
ELEC
16V
20%
120UF
2
1
C3303
MF-LF
5%
1.0K
805
1/8W
NOSTUFF
2
1
R3315
MF-LF
1/8W
5%
805
0
21
R3316
SMB
NOSTUFF
B130LBT01XF
21
D3303
M-RT-SM
53261-0498
CRITICAL
4
3
2
1
6
5
J3302
PP3V3_RUN
53398-0476
CRITICAL
F-ST-SM
4
3
2
1
6
5
J3300
SYNC_MASTER=M33-HS
Fan 2 & HD Temp
SYNC_DATE=08/04/2005
154
33
F
051-6863
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
F2_RCFEEDBK
F2_VOLTAGE8R5
SMU_FAN_TACH2
MIN_LINE_WIDTH=0.5MM
FAN_2_PWR
MIN_NECK_WIDTH=0.25MM
F2_GATESLOWDN
F2_DRV
SMU_FAN_RPM2
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
FAN_2_OUT
I2C_ODD_TEMP_SDA
I2C_ODD_TEMP_SCL
I2C_HD_TEMP_SCL
I2C_HD_TEMP_SDA
28
28
39
39
39
39
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