Samsung M393B1K70DH0-YH9 User Manual

Rev. 1.2, Aug. 2011

M393B5773DH0

M393B5273DH0

M393B5270DH0

M393B1K70DH0

M393B1K73DH0

M393B2K70DM0

240pin Registered DIMM

based on 2Gb D-die	1.35V

78FBGA with Lead-Free & Halogen-Free (RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

2011 Samsung Electronics Co., Ltd. All rights reserved.

- 1 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

Revision History

Revision No.	History	Draft Date	Remark	Editor
1.0	- First Release	Sep. 2010	-	S.H.Kim
1.01	- Corrected typo.	Dec. 2010	-	S.H.Kim
1.1	- Corrected typo.	Feb. 2011	-	J.Y.Lee
1.11	- Corrected typo.	May. 2011	-	J.Y.Lee
1.12	- Corrected typo.	Jun. 2011	-	J.Y.Lee
1.13	- Corrected typo.	Jul. 2011	-	J.Y.Lee
1.2	- Changed input/output capacitance for 1333/1600Mbps of 1.35V	Aug. 2011	-	J.Y.Lee
	- Changed module thickness with Heat Spreader.

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Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

Table Of Contents

240pin Registered DIMM based on 2Gb D-die

1. DDR3L Registered DIMM Ordering Information ...........................................................................................................					5
2. Key Features.................................................................................................................................................................					5
3. Address Configuration ..................................................................................................................................................					5
4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................					6
5. Pin Description .............................................................................................................................................................					7
6. ON DIMM Thermal Sensor ...........................................................................................................................................					7
7. Input/Output Functional Description..............................................................................................................................					8
8. Pinout Comparison Based On Module Type.................................................................................................................					9
9. Registering Clock Driver Specification..........................................................................................................................					10
9.1 Timing & Capacitance values ..................................................................................................................................					10
9.2 Clock driver Characteristics.....................................................................................................................................					10
10.	Function Block Diagram:.............................................................................................................................................				11
10.1		2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ...................................................................			11
10.2		4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) .................................................................			12
10.3		4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ...................................................................			13
10.4		8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) .....................................................................			14
10.5		8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) ....................................................................			16
10.6		16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ...................................................................			17
11.	Absolute Maximum Ratings ........................................................................................................................................				22
11.1		Absolute Maximum DC Ratings.............................................................................................................................			22
11.2		DRAM Component Operating Temperature Range ..............................................................................................			22
12.	AC & DC Operating Conditions...................................................................................................................................				22
12.1		Recommended DC Operating Conditions .............................................................................................................			22
13.	AC & DC Input Measurement Levels ..........................................................................................................................				23
13.1		AC & DC Logic Input Levels for Single-ended Signals..........................................................................................			23
13.2		VREF Tolerances....................................................................................................................................................			25
13.3		AC and DC Logic Input Levels for Differential Signals ..........................................................................................			26
	13.3.1. Differential Signals Definition .........................................................................................................................				26
	13.3.2. Differential Swing Requirement for Clock (CK -		CK)	.............................................and Strobe (DQS - DQS)	26
	13.3.3. Single-ended Requirements for Differential Signals ......................................................................................				28
	13.3.4. Differential Input Cross Point Voltage ............................................................................................................				29
13.4		Slew Rate Definition for Single Ended Input Signals.............................................................................................			30
13.5		Slew rate definition for Differential Input Signals ...................................................................................................			30
14.	AC & DC Output Measurement Levels .......................................................................................................................				30
14.1		Single Ended AC and DC Output Levels...............................................................................................................			30
14.2		Differential AC and DC Output Levels ...................................................................................................................			30
14.3		Single-ended Output Slew Rate ............................................................................................................................			31
14.4		Differential Output Slew Rate ................................................................................................................................			32
15.	IDD specification definition..........................................................................................................................................				33
16.	IDD SPEC Table .........................................................................................................................................................				35
17.	Input/Output Capacitance ...........................................................................................................................................				38
18.	Electrical Characteristics and AC timing .....................................................................................................................				39
18.1		Refresh Parameters by Device Density.................................................................................................................			39
18.2		Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................			39
18.3		Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................			39
	18.3.1. Speed Bin Table Notes ..................................................................................................................................				42
19.	Timing Parameters by Speed Grade ..........................................................................................................................				43
19.1		Jitter Notes ............................................................................................................................................................			46
19.2		Timing Parameter Notes........................................................................................................................................			47
20.	Physical Dimensions...................................................................................................................................................				48
20.1		256Mbx8 based 256Mx72 Module (1 Rank) - M393B5773DH0............................................................................			48
	20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs................................................................				48

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Registered DIMM

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Rev. 1.2

DDR3L SDRAM

20.2	256Mbx8 based 512Mx72 Module (2 Ranks) - M393B5273DH0 ..........................................................................		49
20.2.1. x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs ..............................................................			49
20.3	512Mbx4 based 512Mx72 Module (1 Rank) - M393B5270DH0............................................................................		50
20.3.1. x72		DIMM, populated as one physical rank of x4 DDR3 SDRAMs................................................................	50
20.4	512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70DH0..............................................................................		51
20.4.1. x72		DIMM, populated as two physical ranks of x4 DDR3 SDRAMs ..............................................................	51
20.5	256Mbx8 based 1Gx72 Module (4 Ranks) - M393B1K73DH0..............................................................................		52
20.5.1. x72		DIMM, populated as four physical ranks of x8 DDR3 SDRAMs..............................................................	52
20.6	1Gbx4(DDP) based 2Gx72 Module (4 Ranks) - M393B2K70DM0........................................................................		53
20.6.1. x72		DIMM, populated as four physical ranks of x4 DDR3 SDRAMs..............................................................	53
20.6.2. Heat Spreader Design Guide .........................................................................................................................			54

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Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

1. DDR3L Registered DIMM Ordering Information

	Part Number2	Density	Organization	Component Composition	Number of	Height
					Rank
	M393B5773DH0-YF8/H9/K0	2GB	256Mx72	256Mx8(K4B2G0846D-HY##)*9	1	30mm
	M393B5273DH0-YF8/H9/K0	4GB	512Mx72	256Mx8(K4B2G0846D-HY##)*18	2	30mm
	M393B5270DH0-YF8/H9/K0	4GB	512Mx72	512Mx4(K4B2G0446D-HY##)*18	1	30mm
	M393B1K70DH0-YF8/H9/K0	8GB	1Gx72	512Mx4(K4B2G0446D-HY##)*36	2	30mm
	M393B1K73DH0-YF8/H9	8GB	1Gx72	256Mx8(K4B2G0846D-HY##)*36	4	30mm
	M393B2K70DM0-YF8/H9	16GB	2Gx72	DDP 1Gx4(K4B4G0446D-MY##)*36	4	30mm

NOTE :

1."##" - F8/H9/K0

2.F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11)

-DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

-DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2. Key Features

	Speed	DDR3-800	DDR3-1066	DDR3-1333	DDR3-1600	Unit
		6-6-6	7-7-7	9-9-9	11-11-11
	tCK(min)	2.5	1.875	1.5	1.25	ns
	CAS Latency	6	7	9	11	nCK
	tRCD(min)	15	13.125	13.5	13.75	ns
	tRP(min)	15	13.125	13.5	13.75	ns
	tRAS(min)	37.5	37.5	36	35	ns
	tRC(min)	52.5	50.625	49.5	48.75	ns

•JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply

•VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)

•400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin

•8 independent internal bank

•Programmable CAS Latency: 6,7,8,9,10,11

•Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

•Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) and 8(DDR3-1600)

•8-bit pre-fetch

•Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]

•Bi-directional Differential Data Strobe

•Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

•On Die Termination using ODT pin

•Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C

•Asynchronous Reset

3. Address Configuration

Organization	Row Address	Column Address	Bank Address	Auto Precharge
512Mx4(2Gb) based Module	A0-A14	A0-A9, A11	BA0-BA2	A10/AP
256Mx8(2Gb) based Module	A0-A14	A0-A9	BA0-BA2	A10/AP
1Gx4(4Gb DDP) based Module	A0-A14	A0-A9, A11	BA0-BA2	A10/AP

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Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Pin	Front			Pin	Back	Pin			Front							Pin				Back											Pin	Front			Pin	Back
	VREFDQ				VSS												NC,DQS17														82		DQ33		202	VSS
1				121		42			DQS8							162
																		,TDQS17
2		VSS		122	DQ4	43			DQS8							163					VSS										83		VSS		203	DM4,DQS13
																																				,TDQS13
										VSS																										NC,DQS13
3		DQ0		123	DQ5	44										164		CB6,NC													84	DQS4			204
																																				,TDQS13
4		DQ1		124	VSS	45		CB2,NC								165		CB7,NC													85	DQS4			205	VSS
5		VSS		125	DM0,DQS9	46		CB3,NC								166					VSS										86		VSS		206	DQ38
					,TDQS9
					NC,DQS9	47				VSS
6		DQS0		126												167		NC(TEST)													87		DQ34		207	DQ39
					,TDQS9
7		DQS0		127	VSS	48		VTT, NC								168															88		DQ35		208	VSS
																			RESET
8		VSS		128	DQ6										KEY																89		VSS		209	DQ44
9		DQ2		129	DQ7	49		VTT, NC								169		CKE1, NC													90		DQ40		210	DQ45
10		DQ3		130	VSS	50			CKE0							170					VDD										91		DQ41		211	VSS
11		VSS		131	DQ12	51				VDD						171						NC									92		VSS		212	DM5,DQS14
																																				,TDQS14
																																				NC,DQS14
12		DQ8		132	DQ13	52				BA2						172					A14										93	DQS5			213
																																				,TDQS14
13		DQ9		133	VSS	53										173					VDD										94		DQS5		214	VSS
								Err_Out/NC
		VSS			DM1,DQS10					VDD																							VSS
14				134		54										174		A12/BC													95				215	DQ46
					,TDQS10
					NC,DQS10
15		DQS1		135		55				A11						175						A9									96		DQ42		216	DQ47
					,TDQS10
16		DQS1		136	VSS	56					A7					176					VDD										97		DQ43		217	VSS
17		VSS		137	DQ14	57				VDD						177							A8								98		VSS		218	DQ52
18		DQ10		138	DQ15	58					A5					178						A6									99		DQ48		219	DQ53
19		DQ11		139	VSS	59					A4					179					VDD										100		DQ49		220	VSS
20		VSS		140	DQ20	60				VDD						180							A3								101		VSS		221	DM6,DQS15
																																				,TDQS15
																																				NC,DQS15
21		DQ16		141	DQ21	61					A2					181						A1									102	DQS6			222
																																				,TDQS15
22		DQ17		142	VSS	62				VDD						182					VDD										103	DQS6			223	VSS
23		VSS		143	DM2,DQS11	63		NC, CK1								183					VDD										104		VSS		224	DQ54
					,TDQS11
					NC,DQS11
24		DQS2		144		64		NC, CK1								184					CK0										105		DQ50		225	DQ55
					,TDQS11
25		DQS2		145	VSS	65				VDD						185															106		DQ51		226	VSS
																					CK0
26		VSS		146	DQ22	66				VDD						186					VDD										107		VSS		227	DQ60
27		DQ18		147	DQ23	67		VREFCA								187															108		DQ56		228	DQ61
																		EVENT,NC
28		DQ19		148	VSS	68		NC/Par_In								188							A0								109		DQ57		229	VSS
29		VSS		149	DQ28	69				VDD						189					VDD										110		VSS		230	DM7/DQS16
																																				TDQS16
																																				DM7,DQS16
30		DQ24		150	DQ29	70		A10/AP								190					BA1										111	DQS7			231
																																				,TDQS16
31		DQ25		151	VSS	71				BA0						191					VDD										112		DQS7		232	VSS
		VSS			DM3,DQS12					VDD																							VSS
32				152		72										192					RAS										113				233	DQ62
					,TDQS12
					NC,DQS12
33		DQS3		153		73					WE					193							S0								114		DQ58		234	DQ63
					,TDQS12
34		DQS3		154	VSS	74										194					VDD										115		DQ59		235	VSS
										CAS
35		VSS		155	DQ30	75				VDD						195				ODT0											116		VSS		236	VDDSPD
36		DQ26		156	DQ31	76					S1,NC					196					A13										117		SA0		237	SA1
37		DQ27		157	VSS	77		ODT1,NC								197					VDD										118		SCL		238	SDA
38		VSS		158	CB4,NC	78				VDD						198						S3,NC									119		SA2		239	VSS
39	CB0,NC			159	CB5,NC	79					S2,NC					199					VSS										120		VTT		240	VTT
40	CB1,NC			160	VSS	80				VSS						200				DQ36
41		VSS		161	DM8,DQS17	81			DQ32							201				DQ37
					TDQS17,NC

NOTE : NC = No internal Connection

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

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Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

5. Pin Description

Pin Name

Description

Number

Pin Name

Description

Number

CK0

Clock Input, positive line

1

ODT[1:0]

On Die Termination Inputs

2

Clock Input, negative line

1

DQ[63:0]

Data Input/Output

64

CK0

CKE[1:0]

Clock Enables

2

CB[7:0]

Data check bits Input/Output

8

Row Address Strobe

1

DQS[8:0]

Data strobes

9

RAS

Column Address Strobe

1

Data strobes, negative line

9

CAS

DQS[8:0]

DM[8:0]/

Data Masks/ Data strobes,

9

WE

Write Enable

1

DQS[17:9]

Termination data strobes

TDQS[17:9]

[17:9]

Data strobes, negative line, Termination data

DQS

S[3:0]

Chip Selects

4

9

TDQS[17:9]

strobes

A[9:0],A11,

Address Inputs

2\14

RFU

Reserved for Future Use

2

A[15:13]

Reserved for optional hardware temperature

A10/AP

Address Input/Autoprecharge

1

EVENT

1

sensing

Memory bus test toll (Not Connected and Not

1

A12/BC

Address Input/Burst chop

1

TEST

Usable on DIMMs)

BA[2:0]

SDRAM Bank Addresses

3

Register and SDRAM control pin

1

RESET

SCL

Serial Presence Detect (SPD) Clock Input

1

VDD

Power Supply

22

SDA

SPD Data Input/Output

1

VSS

Ground

59

SA[2:0]

SPD Address Inputs

3

VREFDQ

Reference Voltage for DQ

1

Par_In

Parity bit for the Address and Control bus

1

VREFCA

Reference Voltage for CA

1

Parity error found on the Address and Control

1

VTT

Termination Voltage

4

Err_Out

bus

VDDSPD

SPD Power

1

Total

240

NOTE :

*The VDD and VDDQ pins are tied common to a single power-plane on these designs.

6. ON DIMM Thermal Sensor

SCL

SDA

EVENT WP/EVENT

R1		SA0	SA1		SA2
0 Ω
	R2
	0 Ω SA0
			SA1		SA2

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

2.When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not. When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

	Grade	Range	Temperature Sensor Accuracy			Units	NOTE
			Min.	Typ.	Max.
		75 < Ta < 95	-	+/- 0.5	+/- 1.0		-
	B	40 < Ta < 125	-	+/- 1.0	+/- 2.0	°C	-
		-20 < Ta < 125	-	+/- 2.0	+/- 3.0		-
		Resolution		0.25		°C /LSB	-
			- 7 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

7. Input/Output Functional Description

Symbol

Type

Polarity

Function

CK0

Input

Positive

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.

Edge

Input

Negative

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

CK0

Edge

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers

CKE[1:0]

Input

Active High

and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN

and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

Enables the associated SDRAM command decoder when low and disables decoder when high.

When decoder is disabled, new commands are ignored and previous operations continue.

These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both

S[3:0]

Input

Active Low

inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in

the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg-

ister outputs.

ODT[1:0]

Input

Active High

On-Die Termination control signals

Input

Active Low

When sampled at the positive rising edge of the clock,

CAS,

RAS,

and

WE

define the operation to be exe-

RAS,

CAS,

WE

cuted by the SDRAM.

VREFDQ

Supply

Reference voltage for DQ0-DQ63 and CB0-CB7

VREFCA

Supply

Reference voltage for A0-A15, BA0-BA2,

CKE0, CKE1, Par_In, ODT0 and ODT1.

RAS,

CAS,

WE,

S0,

S1,

Selects which SDRAM bank of eight is activated.

BA[2:0]

Input

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank

address also determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/

A[15:13,

Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur-

ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks

12/BC,11,

Input

(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8

10/AP,9:0]

identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during

Mode Register Set commands.

DQ[63:0],

I/O

Data and Check Bit Input/Output pins

CB[7:0]

Active High Masks write data when high, issued concurrently with input data.

DM[8:0]

VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.

VTT Supply Termination Voltage for Address/Command/Control/Clock nets.

DQS[17:0]

I/O

Positive Edge Positive line of the differential data strobe for input and output data.

DQS[17:0]

I/O

Negative Edge Negative line of the differential data strobe for input and output data.

TDQS/TDQS

is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will

TDQS[17:9],

OUT

enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis-

TDQS[17:9]

abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.

X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1

SA[2:0]

IN

These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM

address range.

SDA

I/O

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be

connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up.

SCL

IN

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected

from the SCL bus time to VDDSPD on the system planar to act as a pull-up.

OUT

This signal indicates that a thermal event has been detected in the thermal sensing device.The system

EVENT

(open

Active Low

should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.

drain)

VDDSPD

Supply

Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from

3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

The

RESET

pin is connected to the

RESET

pin on the register and to the

RESET

pin on the DRAM. When

RESET

IN

low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set

to low level (the Clock Driver will remain synchronized with the input clock)

Par_In

IN

Parity bit for the Address and Control bus. ("1" : Odd, "0" : Even)

OUT

Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out

Err_Out

(open

bus line to VDD on the system planar to act as a pull up.

drain)

TEST

Used by memory bus analysis tools (unused (NC) on memory DIMMs)

- 8 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

8. Pinout Comparison Based On Module Type

RDIMM

UDIMM

Pin

Signal

NOTE

Signal

NOTE

48, 49

VTT

Additional connection for Termination Voltage for

NC

Not used on UDIMMs

Address/Command/Control/Clock nets.

120, 240

VTT

Termination Voltage for Address/Command/Con-

VTT

Termination Voltage for Address/Command/Con-

trol/Clock nets.

trol/Clock nets.

Connected to the register on all RDIMMs NC Not

53

Err_Out

NC

NC Not used on UDIMMs

used on UDIMMs

63

NC

Not used on RDIMMs

CK1

Used for 2 rank UDIMMs, not used on single-rank

UDIMMs, but terminated

64

NC

CK1

68

Par_In

Connected to the register on all RDIMMs

NC

Not used on RDIMMs

Used for dual-rank UDIMMs, not connected

76

S1

Connected to the register on all RDIMMs

S1

on single-rank UDIMMs

77

ODT1, NC

Connected to the register on dualand quadrank

ODT1,NC

Used for dual-rank UDIMMs, not connected

RDIMMs; NC on single-rank RDIMMs

on single-rank UDIMMs

79

Connected to the register on quad-rank

S2, NC

RDIMMs, not connected on single or dual rank

NC

Not used on UDIMMs

RDIMMs

167

NC

TEST input used only on bus analysis probes

NC

TEST input used only on bus analysis

probes

169

CKE1

Connected to the register on dualand quadrank

CKE1,

Used for dual-rank UDIMMs, not connected

RDIMMs; NC on single-rank RDIMMs

NC

on single-rank UDIMMs

171

A15

A15, NC

Depending on device density, may not be

connected to SDRAMs on UDIMMs. However,

172

A14

Connected to the register on all RDIMMs

A14

these signals are terminated on

196

A13

A13

UDIMMs. A15 not routed on some RCs

198

Connected to the register on quad-rank

S3, NC

RDIMMs, not connected on single-or dual-rank

NC

Not used on UDIMMs

RDIMMs

39, 40, 45, 46,

Used on x72 UDIMMs, (n = 0...7); not

158, 159, 164,

CBn

Used on all RDIMMs; (n = 0...7)

NC, CBn

used on x64 UDIMMs

165

125, 134, 143,

DQSn,

Connected to DQS on x4 SDRAMs,

Connected to DM on x8 DRAMs, UDM or

152, 161, 203,

DMn

LDM on x16 DRAMs on UDIMMs;

TDQSn

TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)

212, 221, 230

(n = 0...8)

126, 135, 144,

DQSn,

Connected to DQS on x4 DRAMs, TDQS on x8

153, 162, 204,

NC

Not used on UDIMMs

TDQSn

SDRAMs on RDIMMs; (n=9...17)

213, 222, 231

Connected to optional thermal sensing compo-

187

EVENT

nent.

NC

Not used on UDIMMs

NC

NC on Modules without a thermal sensing

component.

NOTE : NC = No internal Connection

- 9 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

TC = TBD

Symbol

Parameter

Conditions

VDD = 1.35V(1.28V~1.45V)

Units

Notes

& 1.5V(1.425~1.575V)

Min

Max

fclock

Input Clock Frequency

application frequency

300

670

MHz

tCH/tCL

Pulse duration, CK,

HIGH or LOW

0.4

-

tCK

CK

tACT

Inputs active time4 before RESET is taken HIGH

DCKE0/1 = LOW and

8

-

tCK

DCS0/1

= HIGH

tSU

Setup time

Input valid before CK/CK

100

-

ps

tH

Hold time

Input to remain Valid after CK/

175

-

CK

tPDM

Propagation delay, single-bit switching

CK/CK

to output

0.65

1.0

ns

tDIS

output disable time(1/2-Clock pre-launch)

to output float

0.5

-

tCK

CK/CK

output disable time(3/4-Clock pre-launch)

0.25

-

tEN

output enable time(1/2-Clock pre-launch)

to output driving

-

0.5

tCK

CK/CK

output enable time(3/4-Clock pre-launch)

-

0.25

CIN(DATA)

Data Input Capacitance

1.5

2.5

CIN(CLOCK)

Data Input Capacitance

2

3

pF

CIN(RST)

Reset Input Capacitance

-

3

9.2 Clock driver Characteristics

					TC = TBD
	Symbol	Parameter	Conditions	VDD = 1.35V(1.28V~1.45V)			Units	Notes
				& 1.5V(1.425~1.575V)
				Min		Max
	tjit (cc)	Cycle-to-cycle period jitter		0		40	ps
	tSTAB	Stabilization time		-		6	us
	tfdyn	Dynamic phase offset		-50		50	ps
	tCKsk	Clock Output skew				50	ps
	tjit(per)	Yn Clock Period jitter		-40		40	ps
	tjit(hper)	Half period jitter		-50		50	ps
	tQsk1	Qn Output to clock tolerance (Standard 1/2 -Clock	Output Inversion enabled	-100		200	ps
		Pre-Launch)	OUtput Inversion disabled	-100		300
	tQsk1	Output clock tolerance (3/4 Clock Pre-Launch)	Output Inversion enabled	-100		200	ps
			OUtput Inversion disabled	-100		300
	tdynoff	Maximum re-driven dynamic clock off-set		-80		80	ps

- 10 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

10. Function Block Diagram:

10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

DQS8

DQS8 DM8/DQS17

DQS17

CB[7:0]

DQS3

DQS3 DM3/DQS12

DQS12

DQ[31:24]

DQS2 DQS2

DM2/DQS11 DQS11 DQ[23:16]

DQS1 DQS1

DM1/DQS10 DQS10 DQ[15:8]

DQS0

DQS0 DM0/DQS9

DQS9

DQ[7:0]

Vtt

RS0A RRASA RCASA RWEA PCK0A

DQS

DQS

TDQS D8 TDQS

DQ[7:0]

CS RAS CAS WE CK

DQS

DQS

TDQS D3 TDQS

DQ[7:0]

CS RAS CAS WE CK

DQS

DQS

TDQS D2 TDQS

DQ[7:0]

CS RAS CAS WE CK

DQS

DQS

TDQS D1 TDQS

DQ[7:0]

CS RAS CAS WE CK

DQS

DQS

TDQS D0 TDQS

DQ[7:0]

CS RAS CAS WE CK

PCK0ARCLE0ARODT0AA[N:0]A/BA[N:0]A

ZQ CK CKE ODT A[N:0]/BA[N:0]

ZQ CK CKE ODT A[N:0]/BA[N:0]

ZQ CK CKE ODT A[N:0]/BA[N:0]

ZQ CK CKE ODT A[N:0]/BA[N:0]

ZQ CK CKE ODT A[N:0]/BA[N:0]

RS0B

RRASB

RCASB

RWEB PCK0B

PCK0B RCLE0B RODT0B A[N:0]B /BA[N:0]B

DQS4

DQS

ZQ

DQS4

DQS

DM4/DQS13

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

TDQS

D4

DQS13

TDQS

DQ[39:32]

DQ[7:0]

Thermal sensor with SPD

DQS5

DQS

ZQ

SCL

DQS5

DQS

DM5/DQS14

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

SDA

TDQS

D5

EVENT

EVENT

DQS14

TDQS

A0 A1 A2

DQ[47:40]

DQ[7:0]

SA0 SA1 SA2

DQS6

DQS

ZQ

DQS6

DQS

DM6/DQS15

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

TDQS

D6

DQS15

TDQS

DQ[55:48]

DQ[7:0]

VDDSPD

Serial PD

VDD

D0 - D8

DQS7

DQS

ZQ

DQS7

DQS

VTT

DM7/DQS16

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

TDQS

D7

DQS16

TDQS

VREFCA

D0 - D8

DQ[63:56]

DQ[7:0]

VREFDQ

D0 - D8

Vtt

VSS

D0 - D8

NOTE :

1. ZQ resistors are 240 ± 1% For all other resistor values refer to the appropriate wiring diagram.

S0*

RS0A-> CS0 : SDRAMs D[3:0], D8

S1*

RS0B-> CS0 : SDRAMs D[7:4]

BA[N:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8

A[N:0]

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8

1:2

RA[N:0]B -> A[N:0] : SDRAMs D[7:4]

RAS

RRASA ->

: SDRAMs D[3:0], D8

R

RAS

E

RRASB -> RAS : SDRAMs D[7:4]

CAS

G

RCASA -> CAS : SDRAMs D[3:0], D8

I

RCASB -> CAS : SDRAMs D[7:4]

WE

S

RWEA ->

: SDRAMs D[3:0], D8

WE

CKE0

T

RWEB -> WE : SDRAMs D[7:4]

E

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

ODT0

R

RCKE0B -> CKE0 : SDRAMs D[7:4]

RODT0A -> ODT0 : SDRAMs D[3:0], D8

CK0

RODT0B -> ODT0 : SDRAMs D[7:4]

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0A -> CK : SDRAMs D[7:4]

CK0

PCK0A -> CK : SDRAMs D[3:0], D8

PAR_IN

PCK0A -> CK : SDRAMs D[7:4]

QERR

Err_out

RST

RESET**

** : SDRAMs D[8:0]

RST

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)

- 11 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

10.2 4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

DQS8

RS0A

RRASA

RCASA

DQS

DQS8

DQS

DM8/DQS17

TDQS

DQS17

TDQS

CB[7:0]

DQ[7:0]

ZQ

RAS

CAS

CS

RWEAPCK0A

D8 WE CK

CK PCK0A CKE RCKE0A ODT RODT0A A[N:0]/BA[N:0] A[N:0]A /BA[N:0]A

RS1A

DQS

DQS

TDQS TDQS DQ[7:0]

ZQ CS RAS CAS

PCK1APCK1ARCKE1ARODT1A

D17 CKE ODT A[N:0]/BA[N:0] WE CK CK

DQS4

RS0B

RRASB

RCASB

DQS

DQS4

DQS

DM4/DQS13

TDQS

DQS13

TDQS

DQ[39:32]

DQ[7:0]

ZQ

RAS

CAS

CS

RWEBPCK0B

D4 WE CK

CK PCK0B CKE RCKE0B ODT RODT0B A[N:0]/BA[N:0] A[N:0]B /BA[N:0]B

RS1B

DQS

DQS

TDQS TDQS DQ[7:0]

ZQ CS RAS CAS

PCK1BPCK1BRCKE1BRODT1B

D13 CKE ODT A[N:0]/BA[N:0] WE CK CK

DQS3

DQS

DQS3

DQS

DM3/DQS12

TDQS

DQS12

TDQS

DQ[31:24]

DQ[7:0]

ZQ

RAS

CAS

CS

D3 WE CK

CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

TDQS TDQS DQ[7:0]

ZQ CS RAS CAS

D12 WE CK CK

CKE ODT A[N:0]/BA[N:0]

DQS5

DQS

DQS5

DQS

DM5/DQS14

TDQS

DQS14

TDQS

DQ[47:40]

DQ[7:0]

ZQ

RAS

CAS

CS

D5 WE CK

CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

TDQS TDQS DQ[7:0]

ZQ CS RAS CAS

D14 WE CK CK

CKE ODT A[N:0]/BA[N:0]

DQS2

DQS

DQS2

DQS

DM2/DQS11

TDQS

DQS11

TDQS

DQ[23:16]

DQ[7:0]

ZQ

RAS

CAS

CS

D2 WE CK

CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

TDQS TDQS DQ[7:0]

ZQ CS RAS CAS

D11 WE CK CK

CKE ODT A[N:0]/BA[N:0]

DQS6

DQS

DQS6

DQS

DM6/DQS15

TDQS

DQS15

TDQS

DQ[55:48]

DQ[7:0]

ZQ

RAS

CAS

CS

D6 WE CK

CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

TDQS TDQS DQ[7:0]

ZQ CS RAS CAS

D15 WE CK CK

CKE ODT A[N:0]/BA[N:0]

DQS1

DQS7

DQS

DQS

DQS

DQS1

DQS

A[N:0]/BA[N:0]

DQS

A[N:0]/BA[N:0]

DQS7

DQS

DM1/DQS10

CS RAS CAS WE CK CK CKE ODT

CS RAS CAS WE CK CK CKE ODT

DM7/DQS16

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

TDQS

D1

TDQS

D10

TDQS

D7

DQS10

TDQS

TDQS

DQS16

TDQS

DQ[15:8]

DQ[7:0]

DQ[7:0]

DQ[63:56]

DQ[7:0]

ZQ

ZQ

ZQ

DQS0

Vtt

DQS

DQS

DQS0

DQS

A[N:0]/BA[N:0]

DQS

A[N:0]/BA[N:0]

DM0/DQS9

CS RAS CAS WE CK CK CKE ODT

CS RAS CAS WE CK CK CKE ODT

TDQS

D0

TDQS

D9

DQS9

TDQS

TDQS

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

S0*

S1*

Vtt

BA[N:0]

A[N:0]

VDDSPD

Serial PD

Thermal sensor with SPD

RAS

SCL

CAS

VDD

D0 - D17

SDA

WE

EVENT

EVENT

VTT

A0

A1

A2

CKE0

VREFCA

D0 - D17

SA0 SA1 SA2

CKE1

VREFDQ

D0 - D17

ODT0

VSS

D0 - D17

ODT1

CK0

CK0

NOTE :

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

2. RS0 and RS1 alternate between the back and front sides of the DIMM.

PAR_IN

3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate

**

wiring diagram.

RESET

4.See the wiring diagrams for all resistors associated with the command, address and control bus.

DQS
DQS
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
TDQS	D16
TDQS

DQ[7:0]

ZQ

			RS0A-> CS0 : SDRAMs D[3:0], D8
			RS0B-> CS0 : SDRAMs D[7:4]
			RS1A-> CS1 : SDRAMs D[12:9], D17
			RS1B-> CS1 : SDRAMs D[16:13]
			RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
			RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
			RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
			RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]
					->					: SDRAMs D[3:0], D[12:8], D17
			RRASA					RAS
			RRASB -> RAS : SDRAMs D[7:4], D[16:13]
			RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17
1:2			RCASB -> CAS : SDRAMs D[7:4], D[16:13]
R			RWEA ->				WE		: SDRAMs D[3:0], D[12:8], D17
E			RWEB -> WE : SDRAMs D[7:4], D[16:13]
G			RCKE0A -> CKE0 : SDRAMs D[3:0], D8
I			RCKE0B -> CKE0 : SDRAMs D[7:4]
S			RCKE1A -> CKE1 : SDRAMs D[12:9], D17
T			RCKE1B -> CKE1 : SDRAMs D[16:13]
E
			RODT0A -> ODT0 : SDRAMs D[3:0], D8

RRODT0B -> ODT0 : SDRAMs D[7:4] RODT1A -> ODT1 : SDRAMs D[12:9], D17 RODT1A -> ODT1 : SDRAMs D[16:13]

PCK0A -> CK : SDRAMs D[3:0], D8 PCK0B -> CK : SDRAMs D[7:4] PCK1A -> CK : SDRAMs D[12:9], D17 PCK1B -> CK : SDRAMs D[16:13]

PCK0A -> CK : SDRAMs D[3:0], D8 PCK0B -> CK : SDRAMs D[7:4] PCK1A -> CK : SDRAMs D[12:9], D17 PCK1B -> CK : SDRAMs D[16:13]

QERR Err_out

RST

RST** : SDRAMs D[8:0]

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

- 12 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)

RS0A RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[N:0]A /BA[N:0]A

RS0B RRASB RCASB RWEB PCK0B PCK0B RCKE0B RODT0B A[N:0]B /BA[N:0]B

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

VSS

DQS17

DQS

VSS

DQS8

DQS

VSS

DQS17

DQS

VSS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

VSS

DM

D8

VSS

DM

D17

VSS

DM

D4

VSS

DM

D13

CB[3:0]

DQ[3:0]

CB[7:4]

DQ[3:0]

DQ[35:32]

DQ[3:0]

DQ[39:36]

DQ[3:0]

DQS3

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS3

DQS

VSS

DQS17

DQS

VSS

DQS8

DQS

VSS

DQS17

DQS

VSS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

VSS

DM

D3

VSS

DM

D12

VSS

DM

D5

VSS

DM

D14

DQ[27:24]

DQ[3:0]

DQ[31:28]

DQ[3:0]

DQ[43:40]

DQ[3:0]

DQ[47:44]

DQ[3:0]

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

VSS

DQS17

DQS

VSS

DQS8

DQS

VSS

DQS17

DQS

VSS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

VSS

DM

D2

VSS

DM

D11

VSS

DM

D6

VSS

DM

D15

DQ[19:16]

DQ[3:0]

DQ[23:20]

DQ[3:0]

DQ[51:48]

DQ[3:0]

DQ[55:52]

DQ[3:0]

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

ZQ

DQS17

DQS

ZQ

DQS8

DQS

VSS

DQS17

DQS

VSS

DQS8

DQS

VSS

DQS17

DQS

VSS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

VSS

DM

D1

VSS

DM

D10

VSS

DM

D7

VSS

DM

D16

DQ[11:8]

DQ[3:0]

DQ[15:12]

DQ[3:0]

DQ[59:56]

DQ[3:0]

DQ[63:60]

DQ[3:0]

DQS8

DQS

ZQ

DQS17

DQS

ZQ

Vtt

DQS8

DQS

VSS

DQS17

DQS

VSS

VSS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

VSS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

S0*

RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17

DM

D0

DM

D9

DQ[3:0]

DQ[3:0]

DQ[7:4]

DQ[3:0]

RS0B-> CS0 : SDRAMs D[7:4], D[16:13]]

S1*

BA[N:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

A[N:0]

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]

RAS

RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17

Vtt

CAS

RRASB -> RAS : SDRAMs D[7:4], D[16:13]

RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17

WE

1:2

RCASB -> CAS : SDRAMs D[7:4], D[16:13]

Thermal sensor with SPD

VDDSPD

Serial PD

R

RWEA -> WE : SDRAMs D[3:0], D[12:8], D17

SCL

E

RWEB -> WE : SDRAMs D[7:4], D[16:13]

SDA

VDD

D0 - D17

CKE0

G

RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17

EVENT

EVENT

I

A1

A2

RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]

A0

VTT

ODT0

S

RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17

T

RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]

SA0 SA1 SA2

VREFCA

D0 - D17

E

R

VREFDQ

D0 - D17

CK0

PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17

VSS

D0 - D17

CK0

PCK0B -> CK : SDRAMs D[7:4], D[16:13]

PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17

NOTE :

PCK0B -> CK : SDRAMs D[7:4], D[16:13]

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

PAR_IN

QERR

Err_out

2. See the wiring diagrams for all resistors associated with the command, address

RST

and control bus.

RESET**

3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate

RST** : SDRAMs D[17:0]

wiring diagram.

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

(Unused register inputs ODT1 and CKE1 have a 330 Ω resistor to ground)

- 13 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

DQS17

RS0A

RRASA

RCASA

RWEA PCK0A

PCK0A RCKE0A RODT0A A[N:0]A /BA[N:0]A

RS1A

PCK1A

PCK1A RCKE1A RODT1A

DQS17

RS0A

RRASA

RCASA

RWEA PCK0A

PCK0A RCKE0A RODT0A A[N:0]A /BA[N:0]A

DQS

DQS

DQS

DQS17

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS17

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

DQS

VSS

DM

D17

DM

D35

VSS

DM

D8

CB[7:4]

DQ[3:0]

DQ[3:0]

CB[3:0]

DQ[3:0]

DQS12

DQS12

DQS

DQS

DQS

DQS12

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS12

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

DQS

VSS

DM

D12

DM

D30

VSS

DM

D3

DQ[31:28]

DQ[3:0]

DQ[3:0]

DQ[27:24]

DQ[3:0]

DQS11

DQS11

DQS

DQS

DQS

DQS11

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS11

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

DQS

VSS

DM

D11

DM

D29

VSS

DM

D2

DQ[23:20]

DQ[3:0]

DQ[3:0]

DQ[19:16]

DQ[3:0]

DQS10

DQS10

DQS

DQS

DQS

DQS10

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS10

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

DQS

VSS

DM

D10

DM

D28

VSS

DM

D1

DQ[15:12]

DQ[3:0]

DQ[3:0]

DQ[11:8]

DQ[3:0]

RS1A

PCK1A

PCK1A RCKE1A RODT1A

DQS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DM

D26

DQ[3:0]

DQS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DM

D21

DQ[3:0]

DQS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DM

D20

DQ[3:0]

DQS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DM

D19

DQ[3:0]

DQS0	DQS		DQS		DQS0
DQS0	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]		CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]		DQS0
	DQS		DQS
VSS	DM	D0	DM	D18	VSS
DQ[3:0]	DQ[3:0]		DQ[3:0]		DQ[7:4]
Vtt					Vtt

DQS

DQS

DM D9 DQ[3:0]

CS RAS CAS WE CK

CK CKE ODT A[N:0]/BA[N:0]

DQS

DQS

DM D27

DQ[3:0]

CS RAS CAS WE CK CK

CKE ODT A[N:0]/BA[N:0]

- 14 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

DQS14

DQS14

VSS CB[47:44]

DQS4 DQS4

VSS DQ[35:32]

DQS16

DQS16

VSS DQ[63:60]

RS0B RRASB RCASB RWEB PCK0B PCK0B

DQS

DQS

DM D14

DQ[3:0]

CS RAS CAS WE CK CK

DQS

DQS

DM D4 DQ[3:0]

CS RAS CAS WE CK CK

DQS

DQS

DM D16

DQ[3:0]

CS RAS CAS WE CK CK

/BA[N:0]B

CKE CKE CKE RCKE0B ODT ODT ODT RODT0B A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]B

	RS1B				PCK1B		PCK1B RCKE1B RODT1B
DQS
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS
DM				D32
DQ[3:0]
DQS
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS
DM				D22
DQ[3:0]
DQS
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS
DM				D34
DQ[3:0]

DQS13

DQS13

VSS CB[39:36]

DQS5 DQS5

VSS DQ[43:40]

DQS15

DQS15

VSS DQ[55:52]

RS0B RRASB RCASB RWEB PCK0B PCK0B

DQS

DQS

DM D13

DQ[3:0]

CS RAS CAS WE CK CK

DQS

DQS

DM D5 DQ[3:0]

CS RAS CAS WE CK CK

DQS

DQS

DM D15

DQ[3:0]

CS RAS CAS WE CK CK

/BA[N:0]B

CKE CKE CKE RCKE0B ODT ODT ODT RODT0B A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]B

	RS1B				PCK1B		PCK1B RCKE1B RODT1B
DQS
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS
DM				D31
DQ[3:0]
DQS
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS
DM				D23
DQ[3:0]
DQS
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
DQS
DM				D33
DQ[3:0]

DQS10	DQS		DQS
DQS10	DQS		DQS
VSS	DM	D7	DM	D25
DQ[59:56]	DQ[3:0]		DQ[3:0]
	CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]		CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
Vtt

Integrated Thermal sensor in SPD

SCL

SDA

EVENT

EVENT

A0

A1

A2

SA0 SA1 SA2

Serial PD w/ integrated Thermal sensor

VDDSPD

Serial PD

VDD

D0 - D35

VTT

VREFCA

D0 - D35

VREFDQ

D0 - D35

VSS

D0 - D35

DQS6

DQS6 VSS

DQ[51:48]

Vtt

DQS

DQS

DM D6 DQ[3:0]

CS RAS CAS WE CK
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
CK0
CK0	120Ω
CK0	±3%
PAR_IN
RESET

CK CKE ODT A[N:0]/BA[N:0]

DQS

CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]

DQS

DM

D24

DQ[3:0]

			RS0A -> CS0 : SDRAMs D[3:0], D[12:0], D17
			RS0B -> CS0 : SDRAMs D[7:4], D[16:13]
			RS1A -> CS1 : SDRAMs D[21:18], D[30:26], D35
			RS1B -> CS1 : SDRAMs D[25:22], D[34:31]
			RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
			RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
			RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
			RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
										: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
			RRAS			A ->		RAS
			RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
			RCAS				A ->	CAS		: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
1:2			RCASB -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
			RWE		A ->			WE	: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
R			RWEB -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
E			RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17
G			RCKE0B -> CKE0: SDRAMs D[7:4], D[16:13]
I
			RCKE1A -> CKE1: SDRAMs D[21:18], D[30:26], D35

SRCKE1B -> CKE1: SDRAMs D[25:22], D[34:31]

TRODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17

RODT0B -> ODT0: SDRAMs D[7:4], D[16:13]

RRODT1A -> ODT1: SDRAMs D[21:18], D[30:26], D35 RODT1B -> ODT1: SDRAMs D[25:22], D[34:31]

PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17

PCK0B -> CK: SDRAMs D[7:4], D[16:13]

PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35

PCK1B -> CK: SDRAMs D[25:22], D[34:31]

PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17

PCK0B -> CK: SDRAMs D[7:4], D[16:13]

PCK1A -> CK: SDRAMs D[21:18], D[30:26], D35

PCK1B -> CK: SDRAMs D[25:22], D[34:31]

ERR_OUT

RST

RST : SDRAMs D[35:0]

NOTE:

1.See wiring diagrams for resistor values.

2.ZQ pins of each SDRAM are connected to individual RZQ resistors (240 ± 1%)ohms...

- 15 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)

CS0

PCK0

PCK0

WCKE0

WODT0

DQS0

CS

CK

CK

CKE

ODT

DQS

DQS0

DQS

U0

DQ[7:0]

DQ[7:0]

ZQ

DQS1

CS

CK

CK

CKE

ODT

DQS

DQS1

DQS

U1

DQ[15:8]

DQ[7:0]

ZQ

DQS2

CS

CK

CK

CKE

ODT

DQS

DQS2

DQS

U2

DQ[23:16]

DQ[7:0]

ZQ

DQS3

CS

CK

CK

CKE

ODT

DQS

DQS3

DQS

U3

DQ[31:24]

DQ[7:0]

ZQ

DQS8

CS

CK

CK

CKE

ODT

DQS

DQS8

DQS

U4

CB[7:0]

DQ[7:0]

Vtt

ZQ

CS1

PCK0

PCK0

WCKE1

VDD

CS2

PCK2

PCK2

WCKE0

WODT1

CS3

PCK2

PCK2

WCKE1

VDD

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

U9

DQS

U18

DQS

U27

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

U10

DQS

U19

DQS

U28

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

U11

DQS

U20

DQS

U29

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

U12

DQS

U21

DQS

U30

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

U13

DQS

U22

DQS

U31

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

S0

RS0-> CS0 : SDRAMs D[8:0]

S1

RS

1->

CS

1 : SDRAMs D[17:9]

RS2-> CS2 : SDRAMs D[26:18]

S2

RS3-> CS3 : SDRAMs D[35:27]

S3

BA[N:0]

WBA[N:0] -> BA[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

EBA[N:0] -> BA[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

A[N:0]

WA[N:0] -> A[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

EA[N:0] -> A[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

WRAS

->

RAS

RAS

ERAS -> RAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

WCAS

->

CAS

: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

CAS

1:2

ECAS -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

WWE

->

WE

: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

WE

R

EWE -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

CKE0

E

WCKE0 -> CKE0: SDRAMs D[4:0], D[22:18]

G

ECKE0 -> CKE0: SDRAMs D[8:5], D[26:23]

CKE1

I

WCKE1 -> CKE1: SDRAMs D[13:9], D[31:27]

S

ECKE1 -> CKE1: SDRAMs D[17:14], D[35:32]

T

ODT0

WODT0 -> ODT0: SDRAMs D[4:0]

E

EODT0 -> ODT0: SDRAMs D[8:5]

R

ODT1

WODT1 -> ODT1: SDRAMs D[22:18]

EODT1 -> ODT1: SDRAMs D[26:23]

PCK0 -> CK: SDRAMs D[4:0], D[13:9]

CK0

PCK1 -> CK: SDRAMs D[8:5], D[26:23]

PCK2 -> CK: SDRAMs D[22:18], D[31:27]

PCK3 -> CK: SDRAMs D[17:14], D[35:32]

PCK0

->

CK

: SDRAMs D[4:0], D[13:9]

PCK1 -> CK: SDRAMs D[8:5], D[26:23]

PCK2 ->

CK

: SDRAMs D[22:18], D[31:27]

CK0

PCK3 -> CK: SDRAMs D[17:14], D[35:32]

PAR_IN

QERR

Err_out

RST

RESET

RST

: SDRAMs D[35:0]

DQS4

DQS4 DQ[39:32]

DQS5

DQS5 DQ[47:40]

DQS6

DQS6 DQ[55:48]

CS0

PCK1

PCK1

ECKE0

EODT0

CS1

PCK1

PCK1

ECKE1

VDD

CS2

PCK3

PCK3

ECKE0

EODT1

CS3

PCK3

PCK3

ECKE1

VDD

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

DQS

U5

DQS

U14

DQS

U23

DQS

U32

DQ[7:0]

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

ZQ

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

DQS

U6

DQS

U15

DQS

U24

DQS

U33

DQ[7:0]

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

ZQ

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

CS

CK

CK

CKE

ODT

DQS

DQS

DQS

DQS

DQS

U7

DQS

U16

DQS

U25

DQS

U34

DQ[7:0]

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

ZQ

DQS3

CS CK

CK

CKE ODT

CS CK

CK

CKE ODT

CS CK

CK

CKE ODT

CS CK

CK

CKE ODT

DQS

DQS

DQS

DQS

DQS3

DQS

U8

DQS

U17

DQS

U26

DQS

U35

DQ[31:24]

DQ[7:0]

DQ[7:0]

DQ[7:0]

DQ[7:0]

ZQ

ZQ

ZQ

ZQ

Thermal sensor with SPD

SCL

SDA

EVENT

EVENT

A0

A1

A2

SA0 SA1 SA2

VDDSPD

Serial PD

VDD

D0 - D35

VTT

VREFCA

D0 - D35

VREFDQ

D0 - D35

VSS

D0 - D35

NOTE :

1.Unless otherwise noted, resistor values are 15Ω ± 5%.

2.See the wiring diagrams for all resistors associated with the command, address and control bus.

3.ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate wiring diagram.

Vtt

- 16 -

Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs)

VSS DQS8 DQS8

VSS CB[3:0]

ARS0A ARRASA ARCASA ARWEA APCK0A

ZQ

DQS

DQS

DM D9 DQ[3:0]

CS RAS CAS WE CK

	APCK0A			ARCKE0A		ARODT0A		ARA[N:0]A
		CK		CKE		ODT		A[N:0]/BA[N:0]

/ARBA[N:0]A					ARS1A
	VSS			ZQ
				DQS
				DQS
				DM
				DQ[3:0]
					CS			RAS		CAS

ARCKE1AVDD

D8 CKE ODT A[N:0]/BA[N:0] WE CK CK

BRCASA

BRRASA

BRS2A

VSS ZQ DQS DQS DM DQ[3:0]

CAS

RAS

CS

BRWEABPCK0ABPCK0ABRCKE0ABRODT1ABRA[N:0]A

D45 CKE ODT A[N:0]/BA[N:0] WE CK CK

/BRBA[N:0]A

BRS3A

VSS

ZQ

DQS

DQS

D44

DM

DQ[3:0]

CS

RAS

CAS

WE CK

CK

BRCKE1A		VDD
CKE		ODT A[N:0]/BA[N:0]

VSS DQS3 DQS3

VSS DQ[27:24]

ZQ

DQS

DQS

DM D7 DQ[3:0]

CS RAS CAS WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS DM DQ[3:0]

CAS

RAS

CS

D6

WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D47

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D46

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS DQS2 DQS2

VSS DQ[19:16]

ZQ

DQS

DQS

DM D5 DQ[3:0]

CS RAS CAS WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS DM DQ[3:0]

CAS

RAS

CS

D4

WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D49

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D48

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS DQS1 DQS1

VSS DQ[11:8]

ZQ

DQS

DQS

DM D3 DQ[3:0]

CS RAS CAS WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS DM DQ[3:0]

CAS

RAS

CS

D2

WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D51

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D50

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS DQS0 DQS0

VSS DQ[3:0]

Vtt

ZQ

DQS

DQS

DM D1 DQ[3:0]

CS RAS CAS WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS DM DQ[3:0]

CAS

RAS

CS

D0

WE CK

CK CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D53

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

VSS ZQ DQS DQS

DM D52

DQ[3:0]

CK

CK

WE

CAS

RAS

CS

CKE ODT A[N:0]/BA[N:0]

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