SERIAL PRESENCE DETECT
M471A4G43MB1-CTD00
Organization : 1G x 64
Composition : 512M x8 *16ea
Used component part # : K4AAG085WM-BCTDM00
#of rows in module : 2Rows
#of banks in component : 4Banks 4BG
Feature : 30.0mm height & Double sided component
Refresh : 8K/64ms
Bin Sort : TD(DDR4 2666@CL=19)
RCD Vendor and Revision : PCB Rev 1.0
Byte |
Function Described |
Function Supported |
Hex Value |
Note |
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# |
CTD00 |
CTD00 |
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0 |
Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage |
512B Total, 384B Used |
23h |
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1 |
SPD Revision |
Ver 1.1 |
11h |
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2 |
Key Byte / DRAM Device Type |
DDR4 SDRAM |
0Ch |
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3 |
Key Byte / Module Type |
SODIMM |
03h |
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4 |
SDRAM Density and Banks |
16Gb,4BG&4Banks |
86h |
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5 |
SDRAM Addressing |
Row bits 17,Column bits 10 |
29h |
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6 |
SDRAM Device Type |
Monolithinc Device |
00h |
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7 |
SDRAM Optional Features |
Unlimited MAC |
08h |
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8 |
SDRAM Thermal and Refresh Option |
Reserved |
00h |
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9 |
Other SDRAM Optional Features |
sPPR supported |
60h |
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10 |
Reserved |
Reserved |
00h |
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11 |
Module Nominal Voltage, VDD |
1.2V |
03h |
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12 |
Module Organization |
2Rx8 |
09h |
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13 |
Module Memory Bus Width |
64bit, Non-ECC |
03h |
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14 |
Module Thermal Sensor |
without TS |
00h |
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15~16 |
Reserved |
Reserved |
00h |
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17 |
Timebases |
MTB 125ps, FTB 1ps |
00h |
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18 |
SDRAM Minimum Cycle Time(tckavg min) |
0.750ns |
06h |
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19 |
SDRAM Minimum Cycle Time(tckavg max) |
1.6ns |
0Dh |
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20 |
Cas Latency Supported, First Byte |
10,11,12,13,14,15,16,17,18, 19,20 |
F8h |
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21 |
Cas Latency Supported, Second Byte |
10,11,12,13,14,15,16,17,18, 19,20 |
3Fh |
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22 |
Cas Latency Supported, Third Byte |
10,11,12,13,14,15,16,17,18, 19,20 |
00h |
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23 |
Cas Latency Supported, Fourth Byte |
10,11,12,13,14,15,16,17,18, 19,20 |
00h |
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24 |
Minimum Cas Latency Time (tAAmin) |
13.75ns |
6Eh |
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25 |
Minimum RAS to CAS Delay Time(tRCD min) |
13.75ns |
6Eh |
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26 |
Minimum Raw Precharge Delay Time(tRP min) |
13.75ns |
6Eh |
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27 |
Upper Nibbles for tRASmin and tRCmin |
tRAS=32ns, tRC=45.75ns |
11h |
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28 |
Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte |
tRAS=32ns |
00h |
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29 |
Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte |
tRC=45.75ns |
6Eh |
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30 |
Minimum Refresh Recovery Delay Time (tRFC1min), LSB |
550ns |
30h |
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31 |
Minimum Refresh Recovery Delay Time (tRFC1min), MSB |
550ns |
11h |
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32 |
Minimum Refresh Recovery Delay Time (tRFC2min), LSB |
350ns |
F0h |
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33 |
Minimum Refresh Recovery Delay Time (tRFC2min), MSB |
350ns |
0Ah |
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34 |
Minimum Refresh Recovery Delay Time (tRFC4min), LSB |
260ns |
20h |
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35 |
Minimum Refresh Recovery Delay Time (tRFC4min), MSB |
260ns |
08h |
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36 |
Minimum Four Active Window Time (tFAWmin), Most Significant Nibble |
21ns |
00h |
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37 |
Minimum Four Activate Window Time (tFAWmin), Least Significant Byte |
21ns |
A8h |
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38 |
Minimum Active to Active Delay Time (tRRD_smin), different Bank Group |
3.0ns |
18h |
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39 |
Minimum Active to Active Delay Time (tRRD_Lmin), Same Bank Group |
4.9ns |
28h |
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40 |
Minimum CAS to CAS Delay Time(tCCD_Lmin), same bank group |
5ns |
28h |
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JUL. 2018 |
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