Rev. 1.3, Jul. 2010
M471B2873FHS
M471B5673FH0
204pin Unbuffered SODIMM
based on 1Gb F-die |
1.35V |
|
78FBGA with Lead-Free & Halogen-Free (RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
Revision History
Revision No. |
History |
Draft Date |
Remark |
Editor |
1.0 |
- First Release |
Dec. 2009 |
- |
S.H.Kim |
1.1 |
- Changed DIMM IDD Definition |
Jan. 2010 |
- |
S.H.Kim |
|
- Added DIMM IDD Specification |
|
|
|
1.2 |
- Added "CL5" to supported CL setting |
Feb. 2010 |
- |
S.H.Kim |
1.3 |
- Updated the datasheet following JEDEC (JESD79-3E) |
Jul. 2010 |
- |
S.H.Kim |
- 2 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
Table Of Contents |
|
|
204pin Unbuffered SODIMM based on 1Gb F-die |
|
|
1. DDR3L Unbuffered SODIMM Ordering Information...................................................................................................... |
4 |
|
2. Key Features................................................................................................................................................................. |
4 |
|
3. Address Configuration .................................................................................................................................................. |
4 |
|
4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... |
5 |
|
5. Pin Description ............................................................................................................................................................. |
6 |
|
6. Input/Output Functional Description.............................................................................................................................. |
7 |
|
7. Function Block Diagram:............................................................................................................................................... |
8 |
|
7.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................................... |
8 |
|
7.2 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................... |
9 |
|
8. Absolute Maximum Ratings .......................................................................................................................................... |
10 |
|
8.1 Absolute Maximum DC Ratings............................................................................................................................... |
10 |
|
8.2 DRAM Component Operating Temperature Range ................................................................................................ |
10 |
|
9. AC & DC Operating Conditions..................................................................................................................................... |
10 |
|
9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. |
10 |
|
10. AC & DC Input Measurement Levels .......................................................................................................................... |
11 |
|
10.1 |
AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... |
11 |
10.2 |
VREF Tolerances.................................................................................................................................................... |
13 |
10.3 |
AC and DC Logic Input Levels for Differential Signals .......................................................................................... |
14 |
10.3.1. Differential Signals Definition ......................................................................................................................... |
14 |
|
10.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. |
14 |
|
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... |
16 |
|
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ |
17 |
|
10.4 |
Slew Rate Definition for Single Ended Input Signals............................................................................................. |
18 |
10.5 |
Slew rate definition for Differential Input Signals ................................................................................................... |
18 |
11. AC & DC Output Measurement Levels ....................................................................................................................... |
18 |
|
11.1 |
Single Ended AC and DC Output Levels............................................................................................................... |
18 |
11.2 |
Differential AC and DC Output Levels ................................................................................................................... |
18 |
11.3 |
Single-ended Output Slew Rate ............................................................................................................................ |
19 |
11.4 |
Differential Output Slew Rate ................................................................................................................................ |
20 |
12. IDD specification definition.......................................................................................................................................... |
21 |
|
13. IDD SPEC Table ......................................................................................................................................................... |
23 |
|
14. Input/Output Capacitance ........................................................................................................................................... |
24 |
|
14.1 |
1Rx8 1GB SODIMM .............................................................................................................................................. |
24 |
14.2 |
2Rx8 2GB SODIMM .............................................................................................................................................. |
24 |
15. Electrical Characteristics and AC timing ..................................................................................................................... |
25 |
|
15.1 |
Refresh Parameters by Device Density................................................................................................................. |
25 |
15.2 |
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ |
25 |
15.3 |
Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. |
25 |
15.3.1. Speed Bin Table Notes .................................................................................................................................. |
29 |
|
16. Timing Parameters by Speed Grade .......................................................................................................................... |
30 |
|
16.1 |
Jitter Notes ............................................................................................................................................................ |
33 |
16.2 |
Timing Parameter Notes........................................................................................................................................ |
34 |
17. Physical Dimensions :................................................................................................................................................. |
35 |
|
17.1 |
128Mbx8 based 128Mx64 Module (1 Rank) - M471B2873FHS............................................................................ |
35 |
17.2 |
128Mbx8 based 256Mx64 Module (2 Ranks) - M471B5673FH0 .......................................................................... |
36 |
- 3 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
Part Number2 |
Density |
Organization |
Component Composition |
Number of |
Height |
Rank |
|||||
M471B2873FHS-YF8/H9 |
1GB |
128Mx64 |
128Mx8(K4B1G0846F-HY##)*8 |
1 |
30mm |
|
|
|
|
|
|
M471B5673FH0-YF8/H9 |
2GB |
256Mx64 |
128Mx8(K4B1G0846F-HY##)*16 |
2 |
30mm |
|
|
|
|
|
|
NOTE :
1."##" - F8/H9
2.F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
Speed |
DDR3-800 |
DDR3-1066 |
DDR3-1333 |
Unit |
|
6-6-6 |
7-7-7 |
9-9-9 |
|||
|
|
||||
tCK(min) |
2.5 |
1.875 |
1.5 |
ns |
|
|
|
|
|
|
|
CAS Latency |
6 |
7 |
9 |
nCK |
|
|
|
|
|
|
|
tRCD(min) |
15 |
13.125 |
13.5 |
ns |
|
|
|
|
|
|
|
tRP(min) |
15 |
13.125 |
13.5 |
ns |
|
|
|
|
|
|
|
tRAS(min) |
37.5 |
37.5 |
36 |
ns |
|
|
|
|
|
|
|
tRC(min) |
52.5 |
50.625 |
49.5 |
ns |
|
|
|
|
|
|
•JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
•VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
•400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
•8 independent internal bank
•Programmable CAS Latency: 5,6,7,8,9
•Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
•Programmable CAS Write Latency(CWL) = 5 (DDR-800), 6 (DDR3-1066) and 7 (DDR3-1333)
•Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
•Bi-directional Differential Data Strobe
•On Die Termination using ODT pin
•Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
•Asynchronous Reset
Organization |
Row Address |
Column Address |
Bank Address |
Auto Precharge |
128Mx8(1Gb) based Module |
A0-A13 |
A0-A9 |
BA0-BA2 |
A10/AP |
|
|
|
|
|
- 4 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
Pin |
Front |
Pin |
|
Back |
|
Pin |
Front |
|
Pin |
Back |
Pin |
Front |
Pin |
Back |
|||||||||||||||||||||||||
1 |
VREFDQ |
2 |
|
|
VSS |
|
71 |
|
|
|
VSS |
|
72 |
|
|
VSS |
139 |
|
VSS |
140 |
|
DQ38 |
|||||||||||||||||
3 |
|
VSS |
4 |
|
|
DQ4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
KEY |
|
|
|
|
|
|
|
141 |
|
DQ34 |
142 |
|
DQ39 |
||||||
5 |
|
DQ0 |
6 |
|
|
DQ5 |
|
73 |
|
CKE0 |
|
74 |
CKE1 |
143 |
|
DQ35 |
144 |
|
VSS |
||||||||||||||||||||
7 |
|
DQ1 |
8 |
|
|
VSS |
|
75 |
|
|
|
VDD |
|
76 |
|
|
VDD |
145 |
|
VSS |
146 |
|
DQ44 |
||||||||||||||||
9 |
|
VSS |
10 |
|
|
|
|
|
77 |
|
|
|
|
NC |
|
78 |
A153 |
147 |
|
DQ40 |
148 |
|
DQ45 |
||||||||||||||||
|
|
DQS0 |
|||||||||||||||||||||||||||||||||||||
11 |
|
DM0 |
12 |
|
DQS0 |
|
79 |
|
|
|
BA2 |
|
80 |
A143 |
149 |
|
DQ41 |
150 |
|
VSS |
|||||||||||||||||||
13 |
|
VSS |
14 |
|
|
VSS |
|
81 |
|
|
|
VDD |
|
82 |
|
|
VDD |
151 |
|
VSS |
152 |
|
|
|
|
||||||||||||||
|
|
|
DQS5 |
||||||||||||||||||||||||||||||||||||
15 |
|
DQ2 |
16 |
|
|
DQ6 |
|
83 |
|
|
|
|
|
|
|
|
|
|
|
|
84 |
|
|
A11 |
153 |
|
DM5 |
154 |
|
DQS5 |
|||||||||
|
|
A12/BC |
|
|
|
|
|
||||||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
17 |
|
DQ3 |
18 |
|
|
DQ7 |
|
85 |
|
|
|
|
A9 |
|
86 |
|
|
A7 |
155 |
|
VSS |
156 |
|
VSS |
|||||||||||||||
19 |
|
VSS |
20 |
|
|
VSS |
|
87 |
|
|
|
VDD |
|
88 |
|
|
VDD |
157 |
|
DQ42 |
158 |
|
DQ46 |
||||||||||||||||
21 |
|
DQ8 |
22 |
|
|
DQ12 |
|
89 |
|
|
|
|
A8 |
|
90 |
|
|
A6 |
159 |
|
DQ43 |
160 |
|
DQ47 |
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
23 |
|
DQ9 |
24 |
|
|
DQ13 |
|
91 |
|
|
|
|
A5 |
|
92 |
|
|
A4 |
161 |
|
VSS |
162 |
|
VSS |
|||||||||||||||
25 |
|
VSS |
26 |
|
|
VSS |
|
93 |
|
|
|
VDD |
|
94 |
|
|
VDD |
163 |
|
DQ48 |
164 |
|
DQ52 |
||||||||||||||||
27 |
|
|
|
28 |
|
|
DM1 |
|
95 |
|
|
|
|
A3 |
|
96 |
|
|
A2 |
165 |
|
DQ49 |
166 |
|
DQ53 |
||||||||||||||
|
DQS1 |
|
|
|
|||||||||||||||||||||||||||||||||||
29 |
|
DQS1 |
30 |
|
|
|
|
|
97 |
|
|
|
|
A1 |
|
98 |
|
|
|
A0 |
167 |
|
VSS |
168 |
|
VSS |
|||||||||||||
|
RESET |
|
|||||||||||||||||||||||||||||||||||||
31 |
|
VSS |
32 |
|
|
VSS |
|
99 |
|
|
|
VDD |
|
100 |
|
|
VDD |
169 |
|
|
|
170 |
|
DM6 |
|||||||||||||||
|
|
|
|
|
|
DQS6 |
|
||||||||||||||||||||||||||||||||
33 |
|
DQ10 |
34 |
|
|
DQ14 |
|
101 |
|
|
|
CK0 |
|
102 |
|
CK1 |
171 |
|
DQS6 |
172 |
|
VSS |
|||||||||||||||||
35 |
|
DQ11 |
36 |
|
|
DQ15 |
|
103 |
|
|
|
|
|
|
|
|
|
|
|
|
104 |
|
|
|
|
|
|
|
173 |
|
VSS |
174 |
|
DQ54 |
|||||
|
|
|
CK0 |
CK1 |
|
|
|||||||||||||||||||||||||||||||||
37 |
|
VSS |
38 |
|
|
VSS |
|
105 |
|
|
|
VDD |
|
106 |
|
|
VDD |
175 |
|
DQ50 |
176 |
|
DQ55 |
||||||||||||||||
39 |
|
DQ16 |
40 |
|
|
DQ20 |
|
107 |
A10/AP |
|
108 |
|
|
BA1 |
177 |
|
DQ51 |
178 |
|
VSS |
|||||||||||||||||||
41 |
|
DQ17 |
42 |
|
|
DQ21 |
|
109 |
|
|
|
BA0 |
|
110 |
|
|
|
|
|
|
|
179 |
|
VSS |
180 |
|
DQ60 |
||||||||||||
|
|
|
|
|
|
RAS |
|
|
|||||||||||||||||||||||||||||||
43 |
|
VSS |
44 |
|
|
VSS |
|
111 |
|
|
|
VDD |
|
112 |
|
|
VDD |
181 |
|
DQ56 |
182 |
|
DQ61 |
||||||||||||||||
45 |
|
|
|
46 |
|
|
DM2 |
|
113 |
|
|
|
|
|
|
|
|
|
|
|
|
114 |
|
|
|
|
|
|
|
183 |
|
DQ57 |
184 |
|
VSS |
||||
|
DQS2 |
|
|
|
|
|
WE |
|
|
S0 |
|
|
|||||||||||||||||||||||||||
47 |
|
DQS2 |
48 |
|
|
VSS |
|
115 |
|
|
|
|
|
|
|
|
|
|
|
|
116 |
ODT0 |
185 |
|
VSS |
186 |
|
|
|
||||||||||
|
|
|
|
|
CAS |
|
|
DQS7 |
|||||||||||||||||||||||||||||||
49 |
|
VSS |
50 |
|
|
DQ22 |
|
117 |
|
|
|
VDD |
|
118 |
|
|
VDD |
187 |
|
DM7 |
188 |
|
DQS7 |
||||||||||||||||
51 |
|
DQ18 |
52 |
|
|
DQ23 |
|
119 |
|
A133 |
|
120 |
ODT1 |
189 |
|
VSS |
190 |
|
VSS |
||||||||||||||||||||
53 |
|
DQ19 |
54 |
|
|
VSS |
|
121 |
|
|
|
|
|
|
|
|
|
|
|
|
122 |
|
|
NC |
191 |
|
DQ58 |
192 |
|
DQ62 |
|||||||||
|
|
|
|
|
|
|
S1 |
|
|
|
|
||||||||||||||||||||||||||||
55 |
|
VSS |
56 |
|
|
DQ28 |
|
123 |
|
|
|
VDD |
|
124 |
|
|
VDD |
193 |
|
DQ59 |
194 |
|
DQ63 |
||||||||||||||||
57 |
|
DQ24 |
58 |
|
|
DQ29 |
|
125 |
|
TEST |
|
126 |
VREFCA |
195 |
|
VSS |
196 |
|
VSS |
||||||||||||||||||||
59 |
|
DQ25 |
60 |
|
|
VSS |
|
127 |
|
|
|
VSS |
|
128 |
|
|
VSS |
197 |
|
SA0 |
198 |
|
NC |
||||||||||||||||
61 |
|
VSS |
62 |
|
|
|
|
|
129 |
|
DQ32 |
|
130 |
DQ36 |
199 |
VDDSPD |
200 |
|
SDA |
||||||||||||||||||||
|
|
|
DQS3 |
|
|||||||||||||||||||||||||||||||||||
63 |
|
DM3 |
64 |
|
|
DQS3 |
|
131 |
|
DQ33 |
|
132 |
DQ37 |
201 |
|
SA1 |
202 |
|
SCL |
||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||||
65 |
|
VSS |
66 |
|
|
VSS |
|
133 |
|
|
|
VSS |
|
134 |
|
|
VSS |
203 |
|
VTT |
204 |
|
VTT |
||||||||||||||||
67 |
|
DQ26 |
68 |
|
|
DQ30 |
|
135 |
|
|
|
|
|
|
|
|
|
|
|
136 |
DM4 |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
DQS4 |
|
|
|
|
|
|
|
|
|
||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
69 |
|
DQ27 |
70 |
|
|
DQ31 |
|
137 |
|
DQS4 |
|
138 |
|
|
VSS |
|
|
|
|
|
|
|
|
|
NOTE :
1.NC = No Connect, NU = Not Usable, RFU = Reserved Future Use
2.TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3.This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
- 5 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
Pin Name |
Description |
Number |
|
Pin Name |
Description |
Number |
|||||||||||||||
|
CK0, CK1 |
Clock Inputs, positive line |
2 |
|
DQ0-DQ63 |
Data Input/Output |
64 |
||||||||||||||
|
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|
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|
|
|
|
|
|
Data Masks/ Data strobes, |
8 |
|
CK0, CK1 |
Clock Inputs, negative line |
2 |
|
DM0-DM7 |
||||||||||||||||
|
|
Termination data strobes |
|||||||||||||||||||
|
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|
|
||||||||||||||||
CKE0, CKE1 |
Clock Enables |
2 |
DQS0-DQS7 |
Data strobes |
8 |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
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Row Address Strobe |
1 |
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- |
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Data strobes complement |
8 |
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RAS |
DQS0 |
DQS7 |
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Column Address Strobe |
1 |
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Reset Pin |
1 |
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CAS |
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RESET |
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Write Enable |
1 |
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TEST |
Logic Analyzer specific test pin (No connect |
1 |
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WE |
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on SODIMM) |
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Chip Selects |
2 |
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VDD |
Core and I/O Power |
18 |
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S0, S1 |
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A0-A9, A11, |
Address Inputs |
14 |
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VSS |
Ground |
52 |
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A13-A15 |
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A10/AP |
Address Input/Autoprecharge |
1 |
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VREFDQ |
Input/Output Reference |
2 |
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VREFCA |
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Address Input/Burst chop |
1 |
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VDDSPD |
SPD and Temp sensor Power |
1 |
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A12/BC |
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BA0-BA2 |
SDRAM Bank Addresses |
3 |
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VTT |
Termination Voltage |
2 |
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ODT0, ODT1 |
On-die termination control |
2 |
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NC |
Reserved for future use |
3 |
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SCL |
Serial Presence Detect (SPD) Clock Input |
1 |
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Total |
204 |
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SDA |
SPD Data Input/Output |
1 |
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SA0-SA1 |
SPD Address |
2 |
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NOTE:
*The VDD and VDDQ pins are tied common to a single power-plane on these designs.
- 6 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
|
Symbol |
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Type |
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Function |
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CK0-CK1 |
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The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and |
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Input |
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falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera- |
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CK0-CK1 |
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tions is synchronized to the input clock. |
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CKE0-CKE1 |
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Input |
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Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, |
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CKE low initiates the Power Down mode or the Self Refresh mode. |
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Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. |
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S0-S1 |
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Input |
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When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is |
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selected by S0; Rank 1 is selected by S1. |
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When sampled at the cross point of the rising edge of CK and falling edge of |
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signals |
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and |
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define |
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CK, |
CAS, |
RAS, |
WE |
|||||||
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RAS, CAS, WE |
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Input |
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the operation to be executed by the SDRAM. |
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BA0-BA2 |
|
Input |
Selects which DDR3 SDRAM internal bank of eight is activated. |
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ODT0-ODT1 |
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Input |
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Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register. |
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During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of |
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CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the |
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A0-A9, |
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cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke |
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A10/AP, |
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autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0- |
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A11 |
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Input |
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BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, |
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AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre- |
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A12/BC |
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A13-A15 |
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charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre- |
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charge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be |
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performed (HIGH, no burst chop; LOW, burst chopped) |
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DQ0-DQ63 |
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I/O |
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Data Input/Output pins. |
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DM0-DM7 |
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Input |
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The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input |
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data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. |
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DQS0-DQS7 |
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The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is |
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I/O |
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sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 |
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DQS0-DQS7 |
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SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to |
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the crosspoint of respective DQS and DQS. |
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VDD,VDDSPD, |
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Supply |
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. |
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VSS |
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VREFDQ, |
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Supply |
Reference voltage for SSTL15 inputs. |
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VREFCA |
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SDA |
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I/O |
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This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be |
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connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. |
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SCL |
|
Input |
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This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. |
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SA0-SA1 |
|
Input |
Address pins used to select the Serial Presence Detect and Temp sensor base address. |
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TEST |
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I/O |
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The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules |
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Input |
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In Active Low This signal resets the DDR3 SDRAM |
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RESET |
RESET |
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- 7 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
|
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S0 |
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RAS |
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CAS |
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WE CK0 |
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CK0 CKE0 ODT0 A[0:N] /BA[0:N] |
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DQS0 |
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DQS |
240Ω |
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DQS1 |
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DQS |
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240Ω |
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DQS0 |
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DQS |
± 1% |
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DQS1 |
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DQS |
± 1% |
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DM0 |
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DM |
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ZQ |
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DM1 |
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DM |
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ZQ |
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DQ[0:7] |
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DQ[0:7] |
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DQ[8:15] |
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DQ[0:7] |
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D0 |
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D4 |
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CS |
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RAS |
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CAS |
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WE CK |
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CK CKE ODT |
A[0:N]/BA[0:N] |
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CS |
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RAS |
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CAS |
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WE CK |
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CK CKE ODT A[0:N]/BA[0:N] |
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DQS2 |
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DQS |
240Ω |
DQS3 |
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DQS |
240Ω |
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DQS2 |
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DQS |
± 1% |
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DQS3 |
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DQS |
± 1% |
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DM2 |
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DM |
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ZQ |
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DM3 |
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DM |
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ZQ |
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DQ[16:23] |
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DQ[0:7] |
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DQ[24:31] |
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DQ[0:7] |
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D1 |
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D5 |
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CS |
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RAS |
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CAS |
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WE CK |
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CK CKE ODT A[0:N]/BA[0:N] |
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CS |
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RAS |
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CAS |
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WE CK |
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CK CKE ODT A[0:N]/BA[0:N] |
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SCL |
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SCL |
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SA0 |
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A0 |
(SPD) |
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SDA |
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SA1 |
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A1 |
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A2 |
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WP |
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Vtt |
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Vtt |
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VDDSPD |
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SPD |
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VREFCA |
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D0 |
- D7 |
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VREFDQ |
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D0 |
- D7 |
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VDD |
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D0 |
- D7 |
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VSS |
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D0 |
- D7, SPD |
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CK0 |
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D0 |
- D7 |
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D0 |
- D7 |
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CK0 |
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CK1 |
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Terminated near |
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card edge |
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CK1 |
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NC |
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S1 |
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ODT1 |
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NC |
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CKE1 |
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NC |
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D0 |
- D7 |
||||||
RESET |
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DQS4 |
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DQS |
240Ω |
|||||||||||||
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DQS4 |
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DQS |
± 1% |
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DM4 |
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DM |
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ZQ |
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DQ[32:39] |
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DQ[0:7] |
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D2 |
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CS |
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RAS |
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CAS |
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WE CK |
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CK CKE ODT A[0:N]/BA[0:N] |
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DQS6 |
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DQS |
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240Ω |
||||||||||||||||
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DQS6 |
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DQS |
± 1% |
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DM6 |
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DM |
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ZQ |
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DQ[48:55] |
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DQ[0:7] |
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D3 |
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CS |
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RAS |
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CAS |
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WE CK |
|
CK CKE ODT A[0:N]/BA[0:N] |
||||||||||
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Vtt
VDD
DQS5 |
|
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DQS |
|
240Ω |
||||||||||||||
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|||||||||||||||||||
DQS5 |
|
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DQS |
± 1% |
|
||||||||||||||
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DM5 |
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DM |
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ZQ |
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||||||||||
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DQ[40:47] |
|
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DQ[0:7] |
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D6 |
|||||||||||||||||
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CS |
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RAS |
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CAS |
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WE CK |
|
CK CKE ODT A[0:N]/BA[0:N] |
|||||||
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DQS7 |
|
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DQS |
|
240Ω |
|||||||||||||||
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||||||||||||||||||||
DQS7 |
|
|
DQS |
± 1% |
|
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||||||||||||||
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||||||||||||||||||||
DM7 |
|
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DM |
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ZQ |
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||||||||||
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|||||||||||||||||
DQ[56:63] |
|
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DQ[0:7] |
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D7 |
||||||||||||||||||
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||||||||
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CS |
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RAS |
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CAS |
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WE CK |
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CK CKE ODT A[0:N]/BA[0:N] |
||||||||
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Rank0
Vtt
|
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V |
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tt |
V1 |
D4 |
V2 |
D5 |
V3 |
D6 |
V4 |
D7 |
|
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|
V1 |
D0 |
V2 |
D1 |
V3 |
D2 |
V4 |
D3 |
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||||
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tt |
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|
V |
Address and Controllines
NOTE :
1.DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS relationships are maintained as shown
- 8 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
|
|
|
|
|
|
|
|
|
VDD |
|
VDD |
|
|
|
|
S1 RAS CAS WE CK1 CK1 CKE1 ODT1 A[0:N] /BA[0:N] |
|
|
|
|
|
|
Vtt |
|
|
|
|
||
|
S0 |
CK0 CK0 CKE0 ODT0 |
|
|
Vtt |
|
|
|
|
|
Vtt |
|||
DQS3 |
DQS |
240Ω |
|
DQS |
240Ω |
|
|
DQS |
240Ω |
DQS |
240Ω |
|
|
DQS4 |
DQS3 |
DQS |
± 1% |
|
DQS |
± 1% |
|
|
DQS |
± 1% |
DQS |
± 1% |
|
|
DQS4 |
DM3 |
DM |
ZQ |
|
DM |
ZQ |
|
|
DM |
ZQ |
DM |
ZQ |
|
|
DM4 |
DQ[24:31] |
DQ[0:7] |
|
DQ[0:7] |
D3 |
|
|
DQ[0:7] |
D4 |
DQ[0:7] |
|
|
|
DQ[32:39] |
|
|
|
D11 |
|
|
|
|
|
D12 |
|
|
|
|||
|
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
|
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
|
|
|||||
DQS1 |
DQS |
240Ω |
|
DQS |
240Ω |
|
|
DQS |
240Ω |
DQS |
240Ω |
|
|
DQS6 |
DQS1 |
DQS |
± 1% |
|
DQS |
± 1% |
|
|
DQS |
± 1% |
DQS |
± 1% |
|
|
DQS6 |
DM1 |
DM |
ZQ |
|
DM |
ZQ |
|
|
DM |
ZQ |
DM |
ZQ |
|
|
DM6 |
DQ[8:15] |
DQ[0:7] |
|
DQ[0:7] |
D9 |
|
|
DQ[0:7] |
D14 |
DQ[0:7] |
|
|
|
DQ[48:55] |
|
|
|
D1 |
|
|
|
|
|
D6 |
|
|
|
|||
|
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
|
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
|
|
|||||
DQS0 |
DQS |
240Ω |
|
DQS |
240Ω |
|
|
DQS |
240Ω |
DQS |
240Ω |
|
|
DQS7 |
DQS0 |
DQS |
± 1% |
|
DQS |
± 1% |
|
Rank0 |
DQS |
± 1% |
DQS |
± 1% |
|
|
DQS7 |
DM0 |
DM |
ZQ |
|
DM |
ZQ |
|
DM |
ZQ |
DM |
ZQ |
|
|
DM7 |
|
DQ[0:7] |
DQ[0:7] |
|
DQ[0:7] |
|
|
Rank1 |
DQ[0:7] |
|
DQ[0:7] |
|
|
|
DQ[56:63] |
|
|
|
D0 |
|
|
D8 |
|
|
D15 |
D7 |
|
|
|
||
|
|
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|
|
|
|
|
|||||
|
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
|
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
|
|
|||||
DQS2 |
DQS |
240Ω |
|
DQS |
240Ω |
|
|
DQS |
240Ω |
DQS |
240Ω |
|
|
DQS5 |
DQS2 |
DQS |
± 1% |
|
DQS |
± 1% |
|
|
DQS |
± 1% |
DQS |
± 1% |
|
|
DQS5 |
DM2 |
DM |
ZQ |
|
DM |
ZQ |
|
|
DM |
ZQ |
DM |
ZQ |
|
|
DM5 |
DQ[16:23] |
DQ[0:7] |
|
DQ[0:7] |
D10 |
|
|
DQ[0:7] |
D13 |
DQ[0:7] |
|
|
|
DQ[40:47] |
|
|
|
D2 |
|
|
|
|
|
D5 |
|
|
|
|||
|
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT |
A[N:0]/BA[N:0] |
|
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
|
|
|||||
|
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V2 |
V1 |
D12 |
V8 |
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D9 |
D3 |
V9 |
D6 |
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Vtt |
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Vtt |
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V3 |
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V7 |
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VDDSPD |
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SPD |
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D8 |
D10 |
V5 |
D5 |
D7 |
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VREFCA |
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D0 - D15 |
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V4 |
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V6 |
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SCL |
SCL |
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VREFDQ |
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D0 - D15 |
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V4 |
V1 |
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V6 |
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SA0 |
A0 |
(SPD) |
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SDA |
VDD |
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D0 - D15 |
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D13 |
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D0 |
D2 |
V5 |
D15 |
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SA1 |
A1 |
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VSS |
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D0 - D15, SPD |
V3 |
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V7 |
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A2 |
WP |
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Vtt |
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CK0 |
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D0 - D7 |
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D1 |
D11 |
V1 |
D4 |
D14 |
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CK1 |
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D8 - D15 |
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V2 |
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V8 |
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D0 |
- D7 |
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CK0 |
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Address and Controllines |
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D8 |
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CK1 |
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NOTE : |
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D0 |
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RESET |
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1. DQ wiring may differ from that shown how- |
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ever ,DQ, DM, DQS and DQS relationships are maintained as shown
- 9 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
Symbol |
Parameter |
Rating |
Units |
NOTE |
VDD |
Voltage on VDD pin relative to VSS |
-0.4 V ~ 1.975 V |
V |
1,3 |
VDDQ |
Voltage on VDDQ pin relative to VSS |
-0.4 V ~ 1.975 V |
V |
1,3 |
VIN, VOUT |
Voltage on any pin relative to VSS |
-0.4 V ~ 1.975 V |
V |
1 |
TSTG |
Storage Temperature |
-55 to +100 |
°C |
1, 2 |
NOTE :
1.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3.VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Symbol |
Parameter |
rating |
Unit |
NOTE |
TOPER |
Operating Temperature Range |
0 to 95 |
°C |
1, 2, 3 |
NOTE :
1.Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2.The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions
3.Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a)Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b)If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
Symbol |
Parameter |
Operation Voltage |
|
Rating |
|
Units |
NOTE |
|
Min. |
Typ. |
Max. |
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VDD |
Supply Voltage |
1.35V |
1.283 |
1.35 |
1.45 |
V |
1, 2, 3 |
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1.5V |
1.425 |
1.5 |
1.575 |
V |
1, 2, 3 |
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VDDQ |
Supply Voltage for Output |
1.35V |
1.283 |
1.35 |
1.45 |
V |
1, 2, 3 |
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1.5V |
1.425 |
1.5 |
1.575 |
V |
1, 2, 3 |
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NOTE:
1.Under all conditions VDDQ must be less than or equal to VDD.
2.VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3.VDD & VDDQ rating are determinied by operation voltage.
- 10 -
Unbuffered SODIMM
datasheet
Rev. 1.3
DDR3L SDRAM
[ Table 1 ] Single Ended AC and DC input levels for Command and Address
Symbol |
Parameter |
DDR3-800/1066/1333/1600 |
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Unit |
NOTE |
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Min. |
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Max. |
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1.35V |
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VIH.CA(DC90) |
DC input logic high |
VREF + 90 |
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VDD |
mV |
1,5a) |
VIL.CA(DC90) |
DC input logic low |
VSS |
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VREF - 90 |
mV |
1,6a) |
VIH.CA(AC160) |
AC input logic high |
VREF + 160 |
|
Note 2 |
mV |
1,2 |
VIL.CA(AC160) |
AC input logic low |
Note 2 |
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VREF - 160 |
mV |
1,2 |
VIH.CA(AC135) |
AC input logic high |
VREF+135 |
|
Note 2 |
mV |
1,2 |
VIL.CA(AC135) |
AC input logic lowM |
Note 2 |
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VREF-135 |
mV |
1,2 |
VREFCA(DC) |
Reference Voltage for ADD, |
0.49*VDD |
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0.51*VDD |
V |
3,4 |
CMD inputs |
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1.5V |
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VIH.CA(DC100) |
DC input logic high |
VREF + 100 |
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VDD |
mV |
1,5b) |
VIL.CA(DC100) |
DC input logic low |
VSS |
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VREF - 100 |
mV |
1,6b) |
VIH.CA(AC175) |
AC input logic high |
VREF + 175 |
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Note 2 |
mV |
1,2,7 |
VIL.CA(AC175) |
AC input logic low |
Note 2 |
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VREF - 175 |
mV |
1,2,8 |
VIH.CA(AC150) |
AC input logic high |
VREF+150 |
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Note 2 |
mV |
1,2,7 |
VIL.CA(AC150) |
AC input logic low |
Note 2 |
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VREF-150 |
mV |
1,2,8 |
VREFCA(DC) |
Reference Voltage for ADD, |
0.49*VDD |
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0.51*VDD |
V |
3,4 |
CMD inputs |
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NOTE :
1.For input only pins except RESET, VREF = VREFCA(DC)
2.See "Overshoot and Undershoot specifications" section.
3.The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4.For reference : approx. VDD/2 ± 15mV
5.VIH(dc) is used as a simplified symbol for VIH.CA(a) 1.35V : DC90, b) 1.5V : DC100)
6.VIL(dc) is used as a simplified symbol for VIL.CA(a) 1.35V : DC90, b) 1.5V : DC100)
7.VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is used when VREF + 150mV is referenced.
8.VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used when VREF - 150mV is referenced.
- 11 -