Rev. 1.1, Aug. 2013
M393B5173QH0
M393B1G70QH0
M393B2G70QH0
240pin Registered DIMM
based on 4Gb Q-die
78FBGA with Lead-Free & Halogen-Free (RoHS compliant)
datasheet
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Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
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For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2013 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
Revision History
Revision No. |
History |
Draft Date |
Remark |
Editor |
1.0 |
- First Spec. Release |
Jul. 2013 |
- |
S.H.Kim |
1.1 |
- Added by changing line-up 4GB(1Rx8) |
Aug. 2013 |
- |
S.H.Kim |
- 2 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
Table Of Contents |
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240pin Registered DIMM based on 4Gb Q-die |
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1. DDR3 Registered DIMM Ordering Information ............................................................................................................. |
4 |
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2. Key Features................................................................................................................................................................. |
4 |
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3. Address Configuration .................................................................................................................................................. |
4 |
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4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ |
5 |
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5. Pin Description ............................................................................................................................................................. |
6 |
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6. ON DIMM Thermal Sensor ........................................................................................................................................... |
6 |
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7. Input/Output Functional Description.............................................................................................................................. |
7 |
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8. Pinout Comparison Based On Module Type................................................................................................................. |
8 |
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9. Registering Clock Driver Specification.......................................................................................................................... |
9 |
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9.1 Timing & Capacitance values .................................................................................................................................. |
9 |
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9.2 Clock driver Characteristics..................................................................................................................................... |
9 |
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10. Function Block Diagram:............................................................................................................................................. |
10 |
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10.1 |
4GB, 512Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... |
10 |
10.2 |
8GB, 1Gx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ....................................................................... |
11 |
10.3 |
16GB, 2Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ................................................................... |
12 |
11. Absolute Maximum Ratings ........................................................................................................................................ |
14 |
|
11.1 |
Absolute Maximum DC Ratings............................................................................................................................. |
14 |
11.2 |
DRAM Component Operating Temperature Range .............................................................................................. |
14 |
12. AC & DC Operating Conditions................................................................................................................................... |
14 |
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12.1 |
Recommended DC Operating Conditions (SSTL-15)............................................................................................ |
14 |
13. AC & DC Input Measurement Levels .......................................................................................................................... |
15 |
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13.1 |
AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... |
15 |
13.2 |
VREF Tolerances.................................................................................................................................................... |
17 |
13.3 |
AC and DC Logic Input Levels for Differential Signals .......................................................................................... |
18 |
13.3.1. Differential Signals Definition ......................................................................................................................... |
18 |
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13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. |
18 |
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13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... |
20 |
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13.3.4. Differential Input Cross Point Voltage ............................................................................................................ |
21 |
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13.4 |
Slew Rate Definition for Single Ended Input Signals............................................................................................. |
21 |
13.5 |
Slew rate definition for Differential Input Signals ................................................................................................... |
21 |
14. AC & DC Output Measurement Levels ....................................................................................................................... |
22 |
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14.1 |
Single Ended AC and DC Output Levels............................................................................................................... |
22 |
14.2 |
Differential AC and DC Output Levels ................................................................................................................... |
22 |
14.3 |
Single-ended Output Slew Rate ............................................................................................................................ |
22 |
14.4 |
Differential Output Slew Rate ................................................................................................................................ |
23 |
15. DIMM IDD specification definition ............................................................................................................................... |
24 |
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16. IDD SPEC Table ......................................................................................................................................................... |
26 |
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17. Input/Output Capacitance ........................................................................................................................................... |
28 |
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18. Electrical Characteristics and AC timing ..................................................................................................................... |
29 |
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18.1 |
Refresh Parameters by Device Density................................................................................................................. |
29 |
18.2 |
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ |
29 |
18.3 |
Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. |
29 |
18.3.1. Speed Bin Table Notes .................................................................................................................................. |
33 |
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19. Timing Parameters by Speed Grade .......................................................................................................................... |
34 |
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19.1 |
Jitter Notes ............................................................................................................................................................ |
40 |
19.2 |
Timing Parameter Notes........................................................................................................................................ |
41 |
20. Physical Dimensions................................................................................................................................................... |
42 |
|
20.1 |
512Mbx8 based 512Mx72 Module (1 Rank) - M393B5173QH0............................................................................ |
42 |
20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs................................................................ |
42 |
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20.2 |
1Gbx4 based 1Gx72 Module (1 Rank) - M393B1G70QH0 ................................................................................... |
43 |
20.2.1. x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs................................................................ |
43 |
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20.3 |
1Gbx4 based 2Gx72 Module (2 Ranks) - M393B2G70QH0 ................................................................................. |
44 |
20.3.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs .............................................................. |
44 |
- 3 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
Part Number2 |
Density |
Organization |
Component Composition1 |
Number of |
Height |
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Rank |
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M393B5173QH0-CMA |
4GB |
512Mx72 |
512Mx8(K4B4G0846Q-HC##)*9 |
1 |
30mm |
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M393B1G70QH0-CK0/MA |
8GB |
1Gx72 |
1Gx4(K4B4G0446Q-HC##)*18 |
1 |
30mm |
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M393B2G70QH0-CK0/MA |
16GB |
2Gx72 |
1Gx4(K4B4G0446Q-HC##)*36 |
2 |
30mm |
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NOTE :
1."##" - K0/MA
2.K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13)
-DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11)
3.Please contact Samsung for product availability.
Speed |
DDR3-800 |
DDR3-1066 |
DDR3-1333 |
DDR3-1600 |
DDR3-1866 |
Unit |
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6-6-6 |
7-7-7 |
9-9-9 |
11-11-11 |
13-13-13 |
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tCK(min) |
2.5 |
1.875 |
1.5 |
1.25 |
1.071 |
ns |
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CAS Latency |
6 |
7 |
9 |
11 |
13 |
nCK |
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tRCD(min) |
15 |
13.125 |
13.5 |
13.75 |
13.91 |
ns |
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tRP(min) |
15 |
13.125 |
13.5 |
13.75 |
13.91 |
ns |
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tRAS(min) |
37.5 |
37.5 |
36 |
35 |
34 |
ns |
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tRC(min) |
52.5 |
50.625 |
49.5 |
48.75 |
47.91 |
ns |
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•JEDEC standard 1.5V ± 0.075V Power Supply
•VDDQ = 1.5V ± 0.075V
•400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin, 933MHz fCK for 1866Mb/sec/pin
•8 independent internal bank
•Programmable CAS Latency: 6,7,8,9,10,11,13
•Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
•Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333), 8(DDR3-1600) and 9(DDR3-1866)
•Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
•Bi-directional Differential Data Strobe
•On Die Termination using ODT pin
•Average Refresh Period 7.8us at lower then TCASE 85 C, 3.9us at 85 C < TCASE 95 C
•Asynchronous Reset
Organization |
Row Address |
Column Address |
Bank Address |
Auto Precharge |
1Gx4(4Gb) based Module |
A0-A15 |
A0-A9, A11 |
BA0-BA2 |
A10/AP |
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512Mx8(4Gb) based Module |
A0-A15 |
A0-A9 |
BA0-BA2 |
A10/AP |
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- 4 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
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Pin |
Front |
Pin |
Back |
Pin |
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Front |
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Pin |
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Back |
Pin |
Front |
Pin |
Back |
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VREFDQ |
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VSS |
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NC,DQS17 |
82 |
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DQ33 |
202 |
VSS |
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1 |
121 |
42 |
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DQS8 |
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162 |
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,TDQS17 |
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2 |
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VSS |
122 |
DQ4 |
43 |
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DQS8 |
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163 |
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VSS |
83 |
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VSS |
203 |
DM4,DQS13 |
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,TDQS13 |
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VSS |
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NC,DQS13 |
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3 |
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DQ0 |
123 |
DQ5 |
44 |
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164 |
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CB6,NC |
84 |
DQS4 |
204 |
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,TDQS13 |
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4 |
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DQ1 |
124 |
VSS |
45 |
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CB2,NC |
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165 |
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CB7,NC |
85 |
DQS4 |
205 |
VSS |
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5 |
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VSS |
125 |
DM0,DQS9 |
46 |
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CB3,NC |
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166 |
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VSS |
86 |
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VSS |
206 |
DQ38 |
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,TDQS9 |
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NC,DQS9 |
47 |
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VSS |
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6 |
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DQS0 |
126 |
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167 |
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NC(TEST) |
87 |
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DQ34 |
207 |
DQ39 |
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,TDQS9 |
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7 |
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DQS0 |
127 |
VSS |
48 |
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VTT, NC |
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168 |
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88 |
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DQ35 |
208 |
VSS |
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RESET |
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8 |
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VSS |
128 |
DQ6 |
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KEY |
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89 |
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VSS |
209 |
DQ44 |
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9 |
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DQ2 |
129 |
DQ7 |
49 |
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VTT, NC |
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169 |
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CKE1, NC |
90 |
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DQ40 |
210 |
DQ45 |
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10 |
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DQ3 |
130 |
VSS |
50 |
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CKE0 |
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170 |
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VDD |
91 |
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DQ41 |
211 |
VSS |
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11 |
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VSS |
131 |
DQ12 |
51 |
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VDD |
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171 |
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A15 |
92 |
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VSS |
212 |
DM5,DQS14 |
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,TDQS14 |
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NC,DQS14 |
12 |
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DQ8 |
132 |
DQ13 |
52 |
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BA2 |
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172 |
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A14 |
93 |
DQS5 |
213 |
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,TDQS14 |
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13 |
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DQ9 |
133 |
VSS |
53 |
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173 |
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VDD |
94 |
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DQS5 |
214 |
VSS |
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Err_Out/NC |
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VSS |
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DM1,DQS10 |
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VDD |
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VSS |
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14 |
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134 |
54 |
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174 |
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A12/BC |
95 |
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215 |
DQ46 |
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,TDQS10 |
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NC,DQS10 |
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15 |
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DQS1 |
135 |
55 |
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A11 |
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175 |
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A9 |
96 |
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DQ42 |
216 |
DQ47 |
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,TDQS10 |
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16 |
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DQS1 |
136 |
VSS |
56 |
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A7 |
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176 |
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VDD |
97 |
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DQ43 |
217 |
VSS |
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17 |
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VSS |
137 |
DQ14 |
57 |
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VDD |
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177 |
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A8 |
98 |
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VSS |
218 |
DQ52 |
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18 |
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DQ10 |
138 |
DQ15 |
58 |
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A5 |
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178 |
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A6 |
99 |
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DQ48 |
219 |
DQ53 |
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19 |
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DQ11 |
139 |
VSS |
59 |
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A4 |
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179 |
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VDD |
100 |
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DQ49 |
220 |
VSS |
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20 |
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VSS |
140 |
DQ20 |
60 |
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VDD |
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180 |
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A3 |
101 |
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VSS |
221 |
DM6,DQS15 |
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,TDQS15 |
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NC,DQS15 |
21 |
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DQ16 |
141 |
DQ21 |
61 |
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A2 |
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181 |
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A1 |
102 |
DQS6 |
222 |
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,TDQS15 |
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|
|
|
|
|
|
|
|
|
|
|
|
|
22 |
|
DQ17 |
142 |
VSS |
62 |
|
|
|
VDD |
|
182 |
|
|
|
|
VDD |
103 |
DQS6 |
223 |
VSS |
||||||||||||||||
23 |
|
VSS |
143 |
DM2,DQS11 |
63 |
|
NC, CK1 |
|
183 |
|
|
|
|
VDD |
104 |
|
VSS |
224 |
DQ54 |
|||||||||||||||||
|
,TDQS11 |
|
|
|
|
|
|
|
||||||||||||||||||||||||||||
|
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|
|
NC,DQS11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
24 |
|
DQS2 |
144 |
64 |
|
NC, CK1 |
|
184 |
|
|
|
|
CK0 |
105 |
|
DQ50 |
225 |
DQ55 |
||||||||||||||||||
|
,TDQS11 |
|
|
|
|
|
|
|
||||||||||||||||||||||||||||
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
25 |
|
DQS2 |
145 |
VSS |
65 |
|
|
|
VDD |
|
185 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
106 |
|
DQ51 |
226 |
VSS |
||||||
|
|
|
|
|
|
CK0 |
|
|||||||||||||||||||||||||||||
26 |
|
VSS |
146 |
DQ22 |
66 |
|
|
|
VDD |
|
186 |
|
|
|
|
VDD |
107 |
|
VSS |
227 |
DQ60 |
|||||||||||||||
27 |
|
DQ18 |
147 |
DQ23 |
67 |
|
VREFCA |
|
187 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
108 |
|
DQ56 |
228 |
DQ61 |
||||||||
|
|
EVENT,NC |
|
|||||||||||||||||||||||||||||||||
28 |
|
DQ19 |
148 |
VSS |
68 |
|
NC/Par_In |
|
188 |
|
|
|
|
|
|
A0 |
109 |
|
DQ57 |
229 |
VSS |
|||||||||||||||
29 |
|
VSS |
149 |
DQ28 |
69 |
|
|
|
VDD |
|
189 |
|
|
|
|
VDD |
110 |
|
VSS |
230 |
DM7/DQS16 |
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
TDQS16 |
||||||||||||||||||||||||||
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
DM7,DQS16 |
30 |
|
DQ24 |
150 |
DQ29 |
70 |
|
A10/AP |
|
190 |
|
|
|
|
BA1 |
111 |
DQS7 |
231 |
|||||||||||||||||||
|
|
|
|
|
|
|
,TDQS16 |
|||||||||||||||||||||||||||||
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 |
|
DQ25 |
151 |
VSS |
71 |
|
|
|
BA0 |
|
191 |
|
|
|
|
VDD |
112 |
|
DQS7 |
232 |
VSS |
|||||||||||||||
|
|
VSS |
|
DM3,DQS12 |
|
|
|
|
VDD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VSS |
|
|
||||||
32 |
|
152 |
72 |
|
|
|
|
192 |
|
|
|
|
RAS |
113 |
|
233 |
DQ62 |
|||||||||||||||||||
|
,TDQS12 |
|
|
|
|
|
|
|
|
|
||||||||||||||||||||||||||
|
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|
|
|
|
|
NC,DQS12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
33 |
|
DQS3 |
153 |
73 |
|
|
|
|
WE |
|
193 |
|
|
|
|
|
|
S0 |
114 |
|
DQ58 |
234 |
DQ63 |
|||||||||||||
|
,TDQS12 |
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||||||
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
34 |
|
DQS3 |
154 |
VSS |
74 |
|
|
|
|
|
|
|
|
194 |
|
|
|
|
VDD |
115 |
|
DQ59 |
235 |
VSS |
||||||||||||
|
|
|
CAS |
|
|
|
|
|
||||||||||||||||||||||||||||
35 |
|
VSS |
155 |
DQ30 |
75 |
|
|
|
VDD |
|
195 |
|
|
|
ODT0 |
116 |
|
VSS |
236 |
VDDSPD |
||||||||||||||||
36 |
|
DQ26 |
156 |
DQ31 |
76 |
|
|
|
|
S1,NC |
|
196 |
|
|
|
|
A13 |
117 |
|
SA0 |
237 |
SA1 |
||||||||||||||
|
|
|
|
|
|
|
||||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||
37 |
|
DQ27 |
157 |
VSS |
77 |
|
ODT1,NC |
|
197 |
|
|
|
|
VDD |
118 |
|
SCL |
238 |
SDA |
|||||||||||||||||
38 |
|
VSS |
158 |
CB4,NC |
78 |
|
|
|
VDD |
|
198 |
|
|
|
|
|
S3,NC |
119 |
|
SA2 |
239 |
VSS |
||||||||||||||
|
|
|
|
|
|
|
|
|||||||||||||||||||||||||||||
39 |
CB0,NC |
159 |
CB5,NC |
79 |
|
|
|
|
S2,NC |
|
199 |
|
|
|
|
VSS |
120 |
|
VTT |
240 |
VTT |
|||||||||||||||
|
|
|
|
|
|
|||||||||||||||||||||||||||||||
40 |
CB1,NC |
160 |
VSS |
80 |
|
|
|
VSS |
|
200 |
|
|
|
DQ36 |
|
|
|
|
|
|
||||||||||||||||
41 |
|
VSS |
161 |
DM8,DQS17 |
81 |
|
|
DQ32 |
|
201 |
|
|
|
DQ37 |
|
|
|
|
|
|
||||||||||||||||
|
TDQS17,NC |
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||||||
|
|
|
|
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|
|
|
|
|
NOTE : NC = No internal Connection
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
- 5 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
Pin Name |
Description |
Number |
|
Pin Name |
Description |
Number |
|||||||||||||||
|
|
|
CK0 |
Clock Input, positive line |
1 |
|
|
ODT[1:0] |
On Die Termination Inputs |
2 |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
Clock Input, negative line |
1 |
|
|
DQ[63:0] |
Data Input/Output |
64 |
||||
|
|
|
CK0 |
||||||||||||||||||
|
|
|
|
|
|
|
|
||||||||||||||
CKE[1:0] |
Clock Enables |
2 |
|
|
CB[7:0] |
Data check bits Input/Output |
8 |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
Row Address Strobe |
1 |
|
|
DQS[8:0] |
Data strobes |
9 |
||||
|
|
|
RAS |
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
Column Address Strobe |
1 |
|
|
|
|
|
|
|
Data strobes, negative line |
9 |
|
|
|
CAS |
DQS[8:0] |
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DM[8:0]/ |
Data Masks/ Data strobes, |
9 |
||||
|
|
|
|
WE |
Write Enable |
1 |
|
DQS[17:9] |
|||||||||||||
|
|
|
|
|
Termination data strobes |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
TDQS[17:9] |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
[17:9] |
Data strobes, negative line, Termination data |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DQS |
|
||||||
|
|
S[3:0] |
Chip Selects |
4 |
9 |
||||||||||||||||
|
|
TDQS[17:9] |
strobes |
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
A[9:0],A11, |
Address Inputs |
2\14 |
|
|
|
RFU |
Reserved for Future Use |
2 |
|||||||||||||
A[15:13] |
|
|
|
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Reserved for optional hardware temperature |
|
|
A10/AP |
Address Input/Autoprecharge |
1 |
|
|
|
EVENT |
1 |
|||||||||||||
|
|
|
|
sensing |
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Memory bus test toll (Not Connected and Not |
1 |
|
A12/BC |
Address Input/Burst chop |
1 |
|
|
|
TEST |
||||||||||||||
|
|
|
|
Usable on DIMMs) |
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||
|
BA[2:0] |
SDRAM Bank Addresses |
3 |
|
|
|
|
|
|
|
Register and SDRAM control pin |
1 |
|||||||||
|
|
|
RESET |
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
SCL |
Serial Presence Detect (SPD) Clock Input |
1 |
|
|
|
VDD |
Power Supply |
22 |
||||||||||
|
|
|
SDA |
SPD Data Input/Output |
1 |
|
|
|
VSS |
Ground |
59 |
||||||||||
|
SA[2:0] |
SPD Address Inputs |
3 |
|
|
VREFDQ |
Reference Voltage for DQ |
1 |
|||||||||||||
|
Par_In |
Parity bit for the Address and Control bus |
1 |
|
|
VREFCA |
Reference Voltage for CA |
1 |
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
Parity error found on the Address and Control |
1 |
|
|
|
VTT |
Termination Voltage |
4 |
|||
|
Err_Out |
|
|
|
|||||||||||||||||
|
bus |
|
|
|
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VDDSPD |
SPD Power |
1 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Total |
240 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NOTE :
*The VDD and VDDQ pins are tied common to a single power-plane on these designs.
SCL |
|
|
|
|
|
SDA |
EVENT WP/EVENT
R1 |
|
SA0 |
SA1 |
SA2 |
|||
0 |
|
||||||
R2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0 |
|
|
|
|
|
|
|
SA0 |
SA1 |
SA2 |
||||
|
|||||||
|
|
||||||
|
|
|
|
|
|
|
|
NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM
2.When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not. When only the SPD is placed on the module, R2 is placed but R1 is not.
[ Table 1 ] Temperature Sensor Characteristics
Grade |
Range |
Temperature Sensor Accuracy |
Units |
NOTE |
|||
Min. |
Typ. |
Max. |
|||||
|
|
|
|
||||
|
75 < Ta < 95 |
- |
+/- 0.5 |
+/- 1.0 |
|
- |
|
|
|
|
|
|
C |
|
|
B |
40 < Ta < 125 |
- |
+/- 1.0 |
+/- 2.0 |
- |
||
|
|
|
|
|
|
|
|
|
-20 < Ta < 125 |
- |
+/- 2.0 |
+/- 3.0 |
|
- |
|
|
|
|
|
|
|
|
|
|
Resolution |
|
0.25 |
|
C /LSB |
- |
|
|
|
|
|
|
|
|
|
|
|
- 6 - |
|
|
|
|
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
|
|
Symbol |
Type |
Polarity |
|
|
|
|
|
|
|
|
|
Function |
||||||||||||||||||||||||||||||
|
|
|
|
|
|
CK0 |
Input |
Positive |
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver. |
|||||||||||||||||||||||||||||||||||
|
|
|
|
|
|
Edge |
||||||||||||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input |
Negative |
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. |
||||||||||||||||||||||||||
|
|
|
|
|
|
CK0 |
||||||||||||||||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Edge |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers |
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CKE[1:0] |
Input |
Active High |
and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN |
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and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) |
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Enables the associated SDRAM command decoder when low and disables decoder when high. |
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When decoder is disabled, new commands are ignored and previous operations continue. |
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These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both |
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S[3:0] |
Input |
Active Low |
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inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in |
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the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg- |
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ister outputs. |
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ODT[1:0] |
Input |
Active High |
On-Die Termination control signals |
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Input |
Active Low |
When sampled at the positive rising edge of the clock, |
CAS, |
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RAS, |
and |
WE |
define the operation to be exe- |
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RAS, |
CAS, |
WE |
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cuted by the SDRAM. |
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VREFDQ |
Supply |
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Reference voltage for DQ0-DQ63 and CB0-CB7 |
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VREFCA |
Supply |
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Reference voltage for A0-A15, BA0-BA2, |
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CKE0, CKE1, Par_In, ODT0 and ODT1. |
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RAS, |
CAS, |
WE, |
S0, |
S1, |
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Selects which SDRAM bank of eight is activated. |
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BA[2:0] |
Input |
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BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank |
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address also determines mode register is to be accessed during an MRS cycle. |
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Provided the row address for Active commands and the column address and Auto Precharge bit for Read/ |
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A[15:13, |
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Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur- |
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ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks |
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12/BC,11, |
Input |
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(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 |
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10/AP,9:0] |
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identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during |
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Mode Register Set commands. |
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DQ[63:0], |
I/O |
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Data and Check Bit Input/Output pins |
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CB[7:0] |
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Active High Masks write data when high, issued concurrently with input data. |
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DM[8:0] |
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VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic. |
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VTT Supply Termination Voltage for Address/Command/Control/Clock nets. |
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DQS[17:0] |
I/O |
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Positive Edge Positive line of the differential data strobe for input and output data. |
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DQS[17:0] |
I/O |
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Negative Edge Negative line of the differential data strobe for input and output data. |
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TDQS[17:9], |
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TDQS/TDQS |
is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will |
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enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis- |
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TDQS[17:9] |
OUT |
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abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. |
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X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1 |
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SA[2:0] |
IN |
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These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM |
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address range. |
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SDA |
I/O |
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This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be |
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connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up. |
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SCL |
IN |
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This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected |
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from the SCL bus time to VDDSPD on the system planar to act as a pull-up. |
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OUT |
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This signal indicates that a thermal event has been detected in the thermal sensing device.The system |
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EVENT |
(open |
Active Low |
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should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. |
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drain) |
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VDDSPD |
Supply |
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Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from |
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3.0 Volt to 3.6 Volt (nominal 3.3V) operation. |
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The |
RESET |
pin is connected to the |
RESET |
pin on the register and to the |
RESET |
pin on the DRAM. When |
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RESET |
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IN |
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low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set |
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to low level (the Clock Driver will remain synchronized with the input clock) |
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Par_In |
IN |
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Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even) |
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OUT |
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Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out |
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Err_Out |
(open |
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bus line to VDD on the system planar to act as a pull up. |
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drain) |
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TEST |
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Used by memory bus analysis tools (unused (NC) on memory DIMMs) |
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- 7 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
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RDIMM |
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UDIMM |
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Pin |
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Signal |
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NOTE |
Signal |
NOTE |
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48, 49 |
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VTT |
Additional connection for Termination Voltage for |
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NC |
Not used on UDIMMs |
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Address/Command/Control/Clock nets. |
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120, 240 |
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VTT |
Termination Voltage for Address/Command/Con- |
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VTT |
Termination Voltage for Address/Command/Con- |
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trol/Clock nets. |
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trol/Clock nets. |
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Connected to the register on all RDIMMs NC Not |
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53 |
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Err_Out |
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NC |
NC Not used on UDIMMs |
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used on UDIMMs |
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63 |
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NC |
Not used on RDIMMs |
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CK1 |
Used for 2 rank UDIMMs, not used on single-rank |
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UDIMMs, but terminated |
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64 |
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NC |
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CK1 |
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68 |
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Par_In |
Connected to the register on all RDIMMs |
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NC |
Not used on RDIMMs |
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Used for dual-rank UDIMMs, not connected |
76 |
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S1 |
Connected to the register on all RDIMMs |
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S1 |
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on single-rank UDIMMs |
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77 |
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ODT1, NC |
Connected to the register on dualand quadrank |
ODT1,NC |
Used for dual-rank UDIMMs, not connected |
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RDIMMs; NC on single-rank RDIMMs |
on single-rank UDIMMs |
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79 |
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Connected to the register on quad-rank |
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S2, NC |
RDIMMs, not connected on single or dual rank |
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NC |
Not used on UDIMMs |
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RDIMMs |
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167 |
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NC |
TEST input used only on bus analysis probes |
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NC |
TEST input used only on bus analysis |
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probes |
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169 |
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CKE1 |
Connected to the register on dualand quadrank |
CKE1, |
Used for dual-rank UDIMMs, not connected |
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RDIMMs; NC on single-rank RDIMMs |
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NC |
on single-rank UDIMMs |
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171 |
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A15 |
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A15, NC |
Depending on device density, may not be |
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connected to SDRAMs on UDIMMs. However, |
172 |
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A14 |
Connected to the register on all RDIMMs |
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A14 |
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these signals are terminated on |
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196 |
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A13 |
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A13 |
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UDIMMs. A15 not routed on some RCs |
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198 |
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Connected to the register on quad-rank |
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S3, NC |
RDIMMs, not connected on single-or dual-rank |
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NC |
Not used on UDIMMs |
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RDIMMs |
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39, 40, 45, 46, |
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Used on x72 UDIMMs, (n = 0...7); not |
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158, 159, 164, |
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CBn |
Used on all RDIMMs; (n = 0...7) |
NC, CBn |
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used on x64 UDIMMs |
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165 |
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125, 134, 143, |
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DQSn, |
Connected to DQS on x4 SDRAMs, |
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Connected to DM on x8 DRAMs, UDM or |
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152, 161, 203, |
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DMn |
LDM on x16 DRAMs on UDIMMs; |
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TDQSn |
TDQS on x8 SDRAMs on RDIMMs; (n = 9...17) |
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212, 221, 230 |
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(n = 0...8) |
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126, 135, 144, |
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DQSn, |
Connected to DQS on x4 DRAMs, TDQS on x8 |
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153, 162, 204, |
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NC |
Not used on UDIMMs |
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TDQSn |
SDRAMs on RDIMMs; (n=9...17) |
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213, 222, 231 |
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Connected to optional thermal sensing compo- |
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187 |
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EVENT |
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nent. |
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NC |
Not used on UDIMMs |
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NC |
NC on Modules without a thermal sensing |
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component. |
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||||||||||
NOTE : NC = No internal Connection |
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- 8 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
|
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TC = TBD |
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Symbol |
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Parameter |
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Conditions |
VDD = 1.5 0.075V |
Units |
Notes |
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Min |
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Max |
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fclock |
Input Clock Frequency |
application frequency |
300 |
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670 |
MHz |
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tCH/tCL |
Pulse duration, CK, |
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HIGH or LOW |
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0.4 |
|
- |
tCK |
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CK |
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tACT |
Inputs active time4 before RESET is taken HIGH |
DCKE0/1 = LOW and |
8 |
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- |
tCK |
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DCS0/1 = HIGH |
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tSU |
Setup time |
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Input valid before CK/CK |
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100 |
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- |
ps |
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tH |
Hold time |
Input to remain Valid after CK/ |
175 |
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- |
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CK |
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tPDM |
Propagation delay, single-bit switching |
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CK/CK |
to output |
0.65 |
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1.0 |
ns |
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tDIS |
output disable time(1/2-Clock pre-launch) |
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0.5 |
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- |
tCK |
|
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CK/CK |
to output float |
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output disable time(3/4-Clock pre-launch) |
0.25 |
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- |
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tEN |
output enable time(1/2-Clock pre-launch) |
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to output driving |
- |
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0.5 |
tCK |
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CK/CK |
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output enable time(3/4-Clock pre-launch) |
- |
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0.25 |
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CIN(DATA) |
Data Input Capacitance |
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1.5 |
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2.5 |
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CIN(CLOCK) |
Data Input Capacitance |
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2 |
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3 |
pF |
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CIN(RST) |
Reset Input Capacitance |
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- |
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3 |
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TC = TBD |
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Symbol |
Parameter |
Conditions |
VDD = 1.5 0.075V |
Units |
Notes |
||
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Min |
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Max |
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tjit (cc) |
Cycle-to-cycle period jitter |
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0 |
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40 |
ps |
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tSTAB |
Stabilization time |
|
- |
|
6 |
us |
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tfdyn |
Dynamic phase offset |
|
-50 |
|
50 |
ps |
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tCKsk |
Clock Output skew |
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50 |
ps |
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tjit(per) |
Yn Clock Period jitter |
|
-40 |
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40 |
ps |
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tjit(hper) |
Half period jitter |
|
-50 |
|
50 |
ps |
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tQsk1 |
Qn Output to clock tolerance (Standard 1/2 -Clock |
Output Inversion enabled |
-100 |
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200 |
ps |
|
Pre-Launch) |
OUtput Inversion disabled |
-100 |
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300 |
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tQsk1 |
Output clock tolerance (3/4 Clock Pre-Launch) |
Output Inversion enabled |
-100 |
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200 |
ps |
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OUtput Inversion disabled |
-100 |
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300 |
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tdynoff |
Maximum re-driven dynamic clock off-set |
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-80 |
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80 |
ps |
|
- 9 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
DQS8
DQS8 DM8/DQS17 DQS17 CB[7:0]
DQS3
DQS3 DM3/DQS12 DQS12 DQ[31:24]
DQS2
DQS2 DM2/DQS11 DQS11 DQ[23:16]
DQS1
DQS1 DM1/DQS10 DQS10 DQ[15:8]
DQS0
DQS0 DM0/DQS9 DQS9 DQ[7:0]
Vtt
|
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RS0A |
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RRASA |
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RCASA |
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RWEA PCK0A |
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PCK0A RCLE0A RODT0A A[N:0]A /BA[N:0]A |
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DQS |
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ZQ |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D8 |
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TDQS |
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DQ[7:0] |
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DQS |
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ZQ |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D3 |
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TDQS |
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DQ[7:0] |
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DQS |
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ZQ |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D2 |
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TDQS |
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DQ[7:0] |
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DQS |
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ZQ |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D1 |
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TDQS |
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DQ[7:0] |
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DQS |
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ZQ |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D0 |
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TDQS |
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DQ[7:0] |
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RS0B |
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RRASB |
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RCASB |
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RWEB PCK0B |
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PCK0B RCLE0B RODT0B A[N:0]B /BA[N:0]B |
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DQS4 |
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DQS |
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ZQ |
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DQS4 |
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DQS |
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DM4/DQS13 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D4 |
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DQS13 |
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TDQS |
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DQ[39:32] |
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DQ[7:0] |
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Thermal sensor with SPD |
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DQS5 |
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DQS |
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ZQ |
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SCL |
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DQS5 |
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DQS |
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DM5/DQS14 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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SDA |
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TDQS |
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D5 |
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EVENT |
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EVENT |
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DQS14 |
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TDQS |
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A0 A1 A2 |
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DQ[47:40] |
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DQ[7:0] |
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SA0 SA1 SA2 |
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DQS6 |
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DQS |
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ZQ |
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DQS6 |
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DQS |
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DM6/DQS15 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D6 |
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DQS15 |
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TDQS |
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DQ[55:48] |
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DQ[7:0] |
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VDDSPD |
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Serial PD |
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VDD |
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D0 - D8 |
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DQS7 |
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DQS |
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ZQ |
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DQS7 |
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DQS |
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VTT |
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DM7/DQS16 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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TDQS |
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D7 |
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DQS16 |
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TDQS |
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VREFCA |
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D0 - D8 |
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DQ[63:56] |
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DQ[7:0] |
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VREFDQ |
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D0 - D8 |
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Vtt |
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VSS |
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D0 - D8 |
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NOTE :
1. ZQ resistors are 240 1% For all other resistor values refer to the appropriate wiring diagram.
S0 |
* |
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RS |
0A-> |
CS |
0 : SDRAMs D[3:0], D8 |
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S1* |
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RS0B-> CS0 : SDRAMs D[7:4] |
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BA[N:0] |
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RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8 |
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A[N:0] |
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RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4] |
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RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8 |
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1:2 |
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RA[N:0]B -> A[N:0] : SDRAMs D[7:4] |
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RAS |
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RRASA -> |
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: SDRAMs D[3:0], D8 |
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R |
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RAS |
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E |
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RRASB -> RAS : SDRAMs D[7:4] |
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CAS |
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G |
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RCASA -> CAS : SDRAMs D[3:0], D8 |
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I |
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RCASB -> CAS : SDRAMs D[7:4] |
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WE |
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S |
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RWEA -> |
WE |
: SDRAMs D[3:0], D8 |
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CKE0 |
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T |
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RWEB -> WE : SDRAMs D[7:4] |
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E |
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RCKE0A -> CKE0 : SDRAMs D[3:0], D8 |
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ODT0 |
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R |
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RCKE0B -> CKE0 : SDRAMs D[7:4] |
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RODT0A -> ODT0 : SDRAMs D[3:0], D8 |
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CK0 |
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RODT0B -> ODT0 : SDRAMs D[7:4] |
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PCK0A -> CK : SDRAMs D[3:0], D8 |
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PCK0A -> CK : SDRAMs D[7:4] |
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CK0 |
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PCK0A -> CK : SDRAMs D[3:0], D8 |
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PAR_IN |
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PCK0A -> CK : SDRAMs D[7:4] |
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QERR |
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Err_out |
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RST |
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RESET** |
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** : SDRAMs D[8:0] |
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RST |
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*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)
- 10 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
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RS0A RRASA RCASA RWEA PCK0A PCK0A RCKE0A RODT0A A[N:0]A /BA[N:0]A |
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RS0B RRASB RCASB RWEB PCK0B PCK0B RCKE0B RODT0B A[N:0]B /BA[N:0]B |
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DQS8 |
DQS |
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ZQ |
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DQS17 |
DQS |
ZQ |
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DQS4 |
DQS |
ZQ |
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DQS13 |
DQS |
ZQ |
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DQS8 |
DQS |
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VSS |
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DQS17 |
DQS |
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VSS |
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DQS4 |
DQS |
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VSS |
DQS13 |
DQS |
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VSS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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VSS |
DM |
D8 |
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VSS |
DM |
D17 |
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VSS |
DM |
D4 |
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VSS |
DM |
D13 |
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CB[3:0] |
DQ[3:0] |
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CB[7:4] |
DQ[3:0] |
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DQ[35:32] |
DQ[3:0] |
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DQ[39:36] |
DQ[3:0] |
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DQS3 |
DQS |
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ZQ |
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DQS12 |
DQS |
ZQ |
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DQS5 |
DQS |
ZQ |
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DQS14 |
DQS |
ZQ |
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DQS3 |
DQS |
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VSS |
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DQS12 |
DQS |
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VSS |
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DQS5 |
DQS |
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VSS |
DQS14 |
DQS |
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VSS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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VSS |
DM |
D3 |
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VSS |
DM |
D12 |
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VSS |
DM |
D5 |
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VSS |
DM |
D14 |
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DQ[27:24] |
DQ[3:0] |
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DQ[31:28] |
DQ[3:0] |
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DQ[43:40] |
DQ[3:0] |
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DQ[47:44] |
DQ[3:0] |
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DQS8 |
DQS |
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ZQ |
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DQS11 |
DQS |
ZQ |
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DQS6 |
DQS |
ZQ |
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DQS15 |
DQS |
ZQ |
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DQS2 |
DQS |
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VSS |
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DQS11 |
DQS |
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VSS |
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DQS6 |
DQS |
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VSS |
DQS15 |
DQS |
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VSS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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VSS |
DM |
D2 |
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VSS |
DM |
D11 |
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VSS |
DM |
D6 |
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VSS |
DM |
D15 |
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DQ[19:16] |
DQ[3:0] |
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DQ[23:20] |
DQ[3:0] |
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DQ[51:48] |
DQ[3:0] |
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DQ[55:52] |
DQ[3:0] |
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DQS1 |
DQS |
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ZQ |
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DQS10 |
DQS |
ZQ |
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DQS7 |
DQS |
ZQ |
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DQS16 |
DQS |
ZQ |
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DQS1 |
DQS |
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VSS |
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DQS10 |
DQS |
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VSS |
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DQS7 |
DQS |
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VSS |
DQS16 |
DQS |
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VSS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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VSS |
DM |
D1 |
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VSS |
DM |
D10 |
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VSS |
DM |
D7 |
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VSS |
DM |
D16 |
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DQ[11:8] |
DQ[3:0] |
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DQ[15:12] |
DQ[3:0] |
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DQ[59:56] |
DQ[3:0] |
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DQ[63:60] |
DQ[3:0] |
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DQS0 |
DQS |
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ZQ |
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DQS9 |
DQS |
ZQ |
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Vtt |
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DQS0 |
DQS |
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VSS |
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DQS9 |
DQS |
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VSS |
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VSS |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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VSS |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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S0* |
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RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17 |
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DM |
D0 |
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DM |
D9 |
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DQ[3:0] |
DQ[3:0] |
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DQ[7:4] |
DQ[3:0] |
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RS0B-> CS0 : SDRAMs D[7:4], D[16:13] |
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S1* |
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S[3:2] NC |
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BA[N:0] |
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RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17 |
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RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13] |
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A[N:0] |
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RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17 |
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RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13] |
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RAS |
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RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17 |
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Vtt |
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CAS |
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RRASB -> RAS : SDRAMs D[7:4], D[16:13] |
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RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17 |
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WE |
1:2 |
RCASB -> CAS : SDRAMs D[7:4], D[16:13] |
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Thermal sensor with SPD |
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VDDSPD |
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Serial PD |
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R |
RWEA -> WE : SDRAMs D[3:0], D[12:8], D17 |
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SCL |
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E |
RWEB -> WE : SDRAMs D[7:4], D[16:13] |
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SDA |
VDD |
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D0 - D17 |
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CKE0 |
G |
RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17 |
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EVENT |
EVENT |
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I |
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A1 |
A2 |
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RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13] |
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A0 |
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VTT |
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ODT0 |
S |
RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17 |
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T |
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RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13] |
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SA0 SA1 SA2 |
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VREFCA |
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D0 - D17 |
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E |
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CK0 |
R |
PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17 |
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VREFDQ |
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D0 - D17 |
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120 |
PCK0B -> CK : SDRAMs D[7:4], D[16:13] |
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VSS |
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D0 - D17 |
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CK0 |
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PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17 |
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PCK0B -> CK : SDRAMs D[7:4], D[16:13] |
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CK1 |
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NOTE : |
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120 |
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CK1 |
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1. Unless otherwise noted, resistor values are 15 5%. |
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PAR_IN |
Err_out |
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2. See the wiring diagrams for all resistors associated with the command, address |
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and control bus. |
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RESET** |
RST |
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3. ZQ resistors are 240 1% . For all other resistor values refer to the appropriate |
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RST** : SDRAMs D[17:0] |
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wiring diagram. |
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- 11 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
DQS17 |
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RS0A |
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RRASA |
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RCASA |
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RWEA PCK0A |
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PCK0A RCKE0A RODT0A A[N:0]A /BA[N:0]A |
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RS1A |
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PCK1A |
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PCK1A RCKE1A RODT1A |
DQS8 |
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RS0A |
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RRASA |
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RCASA |
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RWEA PCK0A |
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PCK0A RCKE0A RODT0A A[N:0]A /BA[N:0]A |
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DQS |
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DQS |
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DQS |
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DQS17 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
DQS8 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DQS |
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DQS |
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VSS |
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DM |
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D17 |
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DM |
D17B |
VSS |
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DM |
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D8 |
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CB[7:4] |
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DQ[3:0] |
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DQ[3:0] |
CB[3:0] |
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DQ[3:0] |
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DQS12 |
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DQS3 |
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DQS |
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DQS |
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DQS |
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DQS12 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
DQS3 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DQS |
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DQS |
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VSS |
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DM |
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D12 |
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DM |
D12B |
VSS |
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DM |
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D3 |
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DQ[31:28] |
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DQ[3:0] |
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DQ[3:0] |
DQ[27:24] |
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DQ[3:0] |
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DQS11 |
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DQS2 |
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DQS |
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DQS |
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DQS |
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DQS11 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
DQS2 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DQS |
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DQS |
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VSS |
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DM |
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D11 |
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DM |
D11B |
VSS |
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DM |
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D2 |
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DQ[23:20] |
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DQ[3:0] |
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DQ[3:0] |
DQ[19:16] |
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DQ[3:0] |
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DQS10 |
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DQS1 |
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DQS |
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DQS |
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DQS |
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DQS10 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
|
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
DQS1 |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DQS |
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DQS |
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VSS |
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DM |
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D10 |
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DM |
D10B |
VSS |
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DM |
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D1 |
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DQ[15:12] |
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DQ[3:0] |
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DQ[3:0] |
DQ[11:8] |
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DQ[3:0] |
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RS1A |
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PCK1A |
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PCK1A RCKE1A RODT1A |
||||||||
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DQS |
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||||||
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
||||||||||||||
DQS |
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DM |
D8B |
|||||||||||||
DQ[3:0] |
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DQS |
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||||||
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
||||||||||||||
DQS |
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||||||
DM |
D3B |
|||||||||||||
DQ[3:0] |
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DQS |
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||||||
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
||||||||||||||
DQS |
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||||||
DM |
D2B |
|||||||||||||
DQ[3:0] |
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DQS |
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||||||
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
||||||||||||||
DQS |
|
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||||||
DM |
D1B |
|||||||||||||
DQ[3:0] |
DQS0 |
DQS |
|
DQS |
|
DQS9 |
DQS0 |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
DQS9 |
||
DQS |
|
DQS |
|
||
VSS |
DM |
D0 |
DM |
D0B |
VSS |
DQ[3:0] |
DQ[3:0] |
DQ[3:0] |
DQ[7:4] |
||
Vtt |
|
|
|
|
Vtt |
DQS
DQS
DM D9 DQ[3:0]
CS RAS CAS WE CK
CK CKE ODT A[N:0]/BA[N:0]
DQS
DQS
DM D9B
DQ[3:0]
CS RAS CAS WE CK CK
CKE ODT A[N:0]/BA[N:0]
- 12 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
DQS4
DQS4
VSS CB[35:32]
DQS5
DQS5
VSS DQ[43:40]
DQS6
DQS6
VSS DQ[51:48]
RS0B RRASB RCASB RWEB PCK0B
DQS
DQS
DM D4 DQ[3:0]
CS RAS CAS WE CK
DQS
DQS
DM D5 DQ[3:0]
CS RAS CAS WE CK
DQS
DQS
DM D6 DQ[3:0]
CS RAS CAS WE CK
/BA[N:0]B
CK CK CK PCK0B CKE CKE CKE RCKE0B ODT ODT ODT RODT0B A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]B
|
|
RS1B |
|
PCK1B |
|
PCK1B RCKE1B RODT1B |
||||||
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DQS |
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|
||||
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
||||||||||||
DQS |
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|
||||
DM |
D4B |
|||||||||||
DQ[3:0] |
||||||||||||
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DM |
D5B |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DM |
D6B |
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DQ[3:0] |
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DQS13
DQS13 VSS CB[39:36]
DQS14
DQS14 VSS DQ[47:44]
DQS15
DQS15 VSS DQ[55:52]
RS0B RRASB RCASB RWEB PCK0B PCK0B
DQS
DQS
DM D13
DQ[3:0]
CS RAS CAS WE CK CK
DQS
DQS
DM D14
DQ[3:0]
CS RAS CAS WE CK CK
DQS
DQS
DM D15
DQ[3:0]
CS RAS CAS WE CK CK
/BA[N:0]B
CKE CKE CKE RCKE0B ODT ODT ODT RODT0B A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]/BA[N:0] A[N:0]B
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RS1B |
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PCK1B |
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PCK1B RCKE1B RODT1B |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DM |
D13B |
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DQ[3:0] |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DM |
D14B |
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DQ[3:0] |
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DQS |
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CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
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DQS |
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DM |
D15B |
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DQ[3:0] |
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DQS7 |
DQS |
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DQS |
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DQS16 |
DQS7 |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0] |
DQS16 |
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DQS |
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DQS |
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VSS |
DM |
D7 |
DM |
D7B |
VSS |
DQ[59:56] |
DQ[3:0] |
DQ[3:0] |
DQ[63:60] |
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Vtt |
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Vtt |
DQS
DQS
DM D16
DQ[3:0]
CS RAS CAS WE CK CK
CKE ODT A[N:0]/BA[N:0]
DQS
DQS
DM D16B
DQ[3:0]
CS RAS CAS WE CK CK CKE
ODT A[N:0]/BA[N:0]
Integrated Thermal sensor in SPD
SCL
EVENT |
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EVENT |
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SDA |
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A0 A1 A2
SA0 SA1 SA2
Serial PD w/ integrated Thermal sensor
VDDSPD |
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Serial PD |
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VDD |
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D0 - D35 |
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VTT |
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VREFCA |
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D0 - D35 |
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VREFDQ |
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D0 - D35 |
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VSS |
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D0 - D35 |
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NOTE:
1.See wiring diagrams for resistor values.
2.ZQ pins of each SDRAM are connected to individual RZQ resistors (240 +/-1%)ohms...
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
CK0
CK1
CK1
PAR_IN
RESET
1:2 R E G I S T E R
120
RST
RS0A -> CS0 : SDRAMs D[3:0], D[12:8], D17
RS0B -> CS0 : SDRAMs D[7:4]B, D[16:13] B
RS1A -> CS1 : SDRAMs D[3:0]B, D[12:8]B, D17B RS1B -> CS1 : SDRAMs D[7:4], D[16:13]
RBA[N:0]A -> BA[N:0]: SDRAMs D[3:0], D[12:8], D17,D[3:0]B, D[12:8]B, D17B RBA[N:0]B -> BA[N:0]: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
RA[N:0]A -> A[N:0]: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B RA[N:0]B -> A[N:0]: SDRAMs D[7:4], D[16:13], D[7:4], D[16:13]B
RRASA -> RAS: SDRAMs D[3:0], D[12:8],D17, D[3:0]B, D[12:8]B, D17B RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
RCASA -> CAS: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B RCASB -> CAS: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B
RWEA -> WE: SDRAMs D[3:0], D[12:8], D17, D[3:0]B, D[12:8]B, D17B RWEB -> WE: SDRAMs D[7:4], D[16:13], D[7:4]B, D[16:13]B RCKE0A -> CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B -> CKE0: SDRAMs D[7:4]B, D[16:13]B RCKE1A -> CKE1: SDRAMs D[3:0], D[12:8]B, D17B RCKE1B -> CKE1: SDRAMs D[7:4], D[16:13] RODT0A -> ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B -> ODT0: SDRAMs D[7:4]B, D[16:13]B RODT1A -> ODT1: SDRAMs D[3:0]B, D[12:8]B, D17B RODT1B -> ODT1: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B
PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]
PCK0A -> CK: SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK: SDRAMs D[7:4]B, D[16:13]B
PCK1A -> CK: SDRAMs D[3:0]B, D[12:8]B, D17B
PCK1B -> CK: SDRAMs D[7:4], D[16:13]
ERR_OUT
RST : SDRAMs D[17:0], D[17:0]B
- 13 -
Registered DIMM
datasheet
Rev. 1.1
DDR3 SDRAM
Symbol |
Parameter |
Rating |
Units |
NOTE |
VDD |
Voltage on VDD pin relative to VSS |
-0.4 V ~ 1.975 V |
V |
1,3 |
VDDQ |
Voltage on VDDQ pin relative to VSS |
-0.4 V ~ 1.975 V |
V |
1,3 |
VIN, VOUT |
Voltage on any pin relative to VSS |
-0.4 V ~ 1.975 V |
V |
1 |
TSTG |
Storage Temperature |
-55 to +100 |
C |
1, 2 |
NOTE :
1.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3.VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Symbol |
Parameter |
rating |
Unit |
NOTE |
TOPER |
Operating Temperature Range |
0 to 95 |
C |
1, 2, 3 |
NOTE :
1.Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2.The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85 C under all operating conditions
3.Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a)Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b)If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
Symbol |
Parameter |
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Rating |
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Units |
NOTE |
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Min. |
Typ. |
Max. |
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VDD |
Supply Voltage |
1.425 |
1.5 |
1.575 |
V |
1,2 |
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VDDQ |
Supply Voltage for Output |
1.425 |
1.5 |
1.575 |
V |
1,2 |
NOTE:
1.Under all conditions VDDQ must be less than or equal to VDD.
2.VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
- 14 -