Philips SAA7201H-B-C2, SAA7201H-C1, SAA7201H-C1-S1, SAA7201H-C2, SAA7201H-C2-R1 Datasheet

INTEGRATED CIRCUITS

SAA7201

Integrated MPEG2 AVG decoder

Objective specification			1997 Jan 29
File under Integrated Circuits, IC02

Philips Semiconductors	Objective specification
Integrated MPEG2 AVG decoder	SAA7201

FEATURES

General

∙Uses single external Synchronous DRAM (SDRAM) organized as 1M × 16 interfacing at 81 MHz; compatible with the SDRAM ‘lite’ or ‘PC’

∙Fast external CPU interface; 16-bit data + 8-bit address

∙Dedicated input for audio and video data in PES or ES format; data input rate: ≤9 Mbytes/s in byte mode; ≤20 Mbit/s in bit serial mode; audio and/or video data can also serve as input via CPU interface

∙Single 27 MHz external clock for time base reference and internal processing; all required decoding and presentation clocks are generated internally

∙Internal system time base at 90 kHz can be synchronized via CPU port

∙Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks

∙Boundary scan (JTAG) plus external SDRAM self test implemented

∙Supply voltage 3.3 V

∙Package 160 QFP.

CPU relation

∙16-bit data, 8-bit address, or 16-bit multiplexed bus; Motorola and Intel mode supported

∙Support for fast DMA transfer to either internal registers or external SDRAM

∙Maximum sustained rate to the external SDRAM is 9 Mbytes/s.

MPEG2 system

∙Parsing of MPEG2 PES and MPEG1 packet streams

∙Double System Time Clock (STC) counters for discontinuity handling

∙Time stamps or CPU controlled audio/video synchronization

∙Support for seamless time base change (edition)

∙Processing of errors flagged by channel decoding or demux section

∙Support for retrieval of PES header and PES private data.

MPEG2 audio

∙Decoding of 2 channel, layer I and II MPEG audio; support for mono, stereo, intensity stereo and dual channel mode

∙Constant and variable bit rates up to 448 kbit/s

∙Audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 kHz

∙CRC error detection

∙Selectable output channel in dual channel mode

∙Independent volume control for both channels and programmable inter-channel crosstalk control through a baseband audio processing unit

∙Storage ancillary data up to 54 bytes

∙Dynamic range control at output

∙Muting possibility via external controller; automatic muting in case of errors

∙Generation of ‘beeps’ with programmable tone height, duration and amplitude

∙Serial two channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible with either I2S or Japanese formats

∙Serial SPDIF audio output

∙Clock output 256 or 384 × fs for external D/A converter

∙Audio input buffer in external SDRAM with programmable size (default is 64 kbit)

∙Programmable processing delay compensation

∙Software controlled stop, pause, restricted skip, and restart functions.

MPEG2 video

∙Decoding of MPEG2 video up to main level, main profile

∙Nominal video input buffer size equals 2.6 Mbit for Video Main Profile and Main Level (MP@ML)

∙Output picture format: CCIR-601 4 : 2 : 2 interlaced pictures; picture format 720 × 576 at 50 Hz or 720 × 480 at 60 Hz

∙3 : 2 pull-down supported with 24 and 30 Hz sequences

∙Support of constant and variable bit rates up to 15 Mbit/s

∙Output interface at 8-bit wide, 27 MHz UYVY multiplexed bus

∙Horizontal and vertical pan and scan allows the extraction of a window from the coded picture

1997 Jan 29

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Philips Semiconductors	Objective specification
Integrated MPEG2 AVG decoder	SAA7201

∙Flexible horizontal continuous scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies

∙Vertical scaling with fixed factors 0.5, 1 or 2 to support picture scaling and up-sampling

∙Scaling of incoming pictures to 25% of their original size with anti-aliasing filtering to free screen space for graphics applications like electronic program guides

∙Non-full screen MPEG pictures will be displayed in a box of which position and background colour are adjustable by the external CPU

∙Video output may be slaved to internally (master) generated or externally (slave) supplied HV synchronization signals; the position of active video is programmable; MPEG timebase changes do not affected the display phase

∙Video output direct connectable to SAA718X encoder family

∙Various trick modes under control of external CPU:

–Freeze I or P pictures; restart on I picture

–Freeze on B pictures; restart at any moment

–Scanning and decoding of I or I and P pictures

–Single step mode

–Repeat/Skip field for time base correction.

Graphics

∙Graphics is region based and presented in boxes independent of video format

∙Screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling and fading of regions

∙Support of 2, 4, 8 bits/pixel bit-maps in fixed bit-maps or coded in accordance to the DVB variable/run length standard for region bases graphics

∙Optimized memory control in MPEG video decoding allows for storage of graphical bit-maps up to 1.2 Mbit in

50Hz and 2.0 Mbit in 60 Hz systems

∙VL/RL encoding enables full screen graphics at

8bit/pixel in 50 Hz

∙Fast CPU access enables full bit-map updates within a display field period

∙Display colours are obtained via colour look-up tables; CLUT output is YUVT at 8-bit for each signal component thus enabling 16M different colours and 6-bit for T (transparency) which gives 64 mixing levels with video

∙Bit-map table mechanism to specify a sub-set of entries if the CLUT is larger than required by the coded bit pattern; supported bit-map tables are 16 to 256,

4to 256 and 4 to 16

∙Graphics boxes may not overlap vertically; if 256 entry CLUT has to be down loaded, a vertical separation of

1field line is mandatory

∙Internal support for fast block moves in the external SDRAM during MPEG decoding

∙Graphics mechanism can be used for signal generation in the vertical blanking interval; useful for teletext, wide screen signalling, closed caption etc.

∙Support for a single down-loadable cursor of 1 kpixel with programmable shape; supported shapes are

8× 128, 16 × 64, 32 × 32, 64 × 16 and 128 × 8

∙Cursor colours are determined via a 4-entry CLUT with YUVT at 6, 4, 4 respectively 2 bits; mixing of cursor with video + graphics in 4 levels

∙Cursor can be moved freely across the screen without overlapping restrictions.

1997 Jan 29

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Philips Semiconductors	Objective specification
Integrated MPEG2 AVG decoder	SAA7201

GENERAL DESCRIPTION

The SAA7201 is an MPEG2 decoder which combines audio decoding and video decoding. Additionally to these basic MPEG functions it also provides means for enhanced graphics and/or on-screen display.

QUICK REFERENCE DATA

Due to an optimized architecture for audio and video decoding, maximum capacity in the external memory and processing power from the external CPU is available for the support for graphics.

SYMBOL	PARAMETER	MIN.	TYP.	MAX.	UNIT
VDD	functional supply voltage	3.0	3.3	3.6	V
VCC	pad supply voltage	3.0	3.3	3.6	V
IDD(tot)	total supply current at VDD = 3.3 V	−	tbf	−	mA
fCLK	clock frequency	−	27.0	−	MHz
fCLK	frequency deviation	−30 × 10−6	−	+30 × 10−6

ORDERING INFORMATION

TYPE			PACKAGE
NUMBER		NAME	DESCRIPTION	VERSION
SAA7201H		QFP160	plastic quad flat package; 160 leads (lead length 1.95 mm);	SOT322-4
			body 28 × 28 × 3.4 mm; high stand-off height

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Philips Semiconductors	Objective specification
Integrated MPEG2 AVG decoder	SAA7201
BLOCK DIAGRAM

handbook, full pagewidth	VDDCO1 to		SDRAM_WE	SDRAM_DATA			READI	VDDA
	VDDCO4	SDRAM_CAS SDRAM_UDQ			(15 to 0)		CP81MEXT
								VDD1 to
			SDRAM_ADDR
	SDRAM_RAS					CP81M READO		VDD16
				(11 to 0)

	4	77	75	74	78	16	84	83	81	80	121
					12						16
					MEMORY
					INTERFACE
A_STROBE	159								VIDEO INPUT
	148
V_STROBE
								BUFFER & SYNC
	8	AUDIO/VIDEO
AV_DATA(0 to 7)		INTERFACE
ERROR	147
									VIDEO
		SYSTEM TIME							DECODER
		BASE UNIT
CPU_TYPE	2			SAA7201
	1
MUX
	8										106	HS
CS	9								DISPLAY		107
DS
										UNIT		VS
	10
AS
	11
R/W
	12
DTACK
	8	HOST
ADDRESS(8 to 1)
	16	INTERFACE
DATA(15 to 0)
											8
	4
IRQ(3 to 0)									GRAPHICS			YUV(7 to 0)
	4										119
DMA_REQ										UNIT		GRPH
	3
DMA_ACK
	6										143	SD
DMA_RDY
											142
	5											SCLK
DMA_DONE
									AUDIO		145
												WS
	124								DECODER		146
CLK												SPDIF
		CLOCK
											139
	138											FSCLK
		GENERATION
RESET
		JTAG							AUDIO INPUT
								BUFFER & SYNC
		4			16
							122
	VSSCO1 to VSSCO4			VSS1 to VSS16		VSSA					MGD322

Fig.1 Block diagram.

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Philips Semiconductors					Objective specification
Integrated MPEG2 AVG decoder						SAA7201
PINNING
		SYMBOL	PIN	DESCRIPTION		V	I/O
MUX			1	multiplexed/non-multiplexed (active LOW) bus input		5.0	I
CPU_TYPE			2	Intel/Motorola (active LOW) selection input		5.0	I
DMA_ACK			3	DMA acknowledge input		3.3	I
DMA_REQ			4	DMA request input and output		3.3	I/O
DMA_DONE			5	DMA end input		3.3	I
DMA_RDY			6	DMA ready output		3.3	O/Z
VSS1			7	ground for pad ring		3.3	−
CS			8	chip select input		5.0	I
DS			9	data strobe input		5.0	I
AS			10	address strobe input		5.0	I
			11	read/write (active LOW) input		5.0	I
R/W
DTACK			12	data acknowledge output		5.0	O/Z
VDD1			13	supply for pad ring		3.3	−
IRQ0			14	individually maskable interrupts		3.3	O/Z
IRQ1			15	individually maskable interrupts		3.3	O/Z
IRQ2			16	individually maskable interrupts		3.3	O/Z
IRQ3			17	individually maskable interrupts		3.3	O/Z
VSS2			18	ground for pad ring		−	−
VSSCO1			19	ground for core logic		−	−
VDDCO1			20	supply for core logic		3.3	−
DATA0			21	CPU data interface		5.0	I/O
DATA1			22	CPU data interface		5.0	I/O
DATA2			23	CPU data interface		5.0	I/O
DATA3			24	CPU data interface		5.0	I/O
VDD2			25	supply for pad ring		3.3	−
DATA4			26	CPU data interface		5.0	I/O
DATA5			27	CPU data interface		5.0	I/O
DATA6			28	CPU data interface		5.0	I/O
DATA7			29	CPU data interface		5.0	I/O
VSS3			30	ground for pad ring		−	−
DATA8			31	CPU data interface		5.0	I/O
DATA9			32	CPU data interface		5.0	I/O
DATA10			33	CPU data interface		5.0	I/O
DATA11			34	CPU data interface		5.0	I/O
VDD3			35	supply for pad ring		−	−
DATA12			36	CPU data interface		5.0	I/O
DATA13			37	CPU data interface		5.0	I/O
DATA14			38	CPU data interface		5.0	I/O
DATA15			39	CPU data interface		5.0	I/O
VSS4			40	ground for pad ring		−	−

1997 Jan 29

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Philips Semiconductors			Objective specification
Integrated MPEG2 AVG decoder				SAA7201
SYMBOL	PIN	DESCRIPTION		V	I/O
ADDRESS1	41	CPU address interface		5.0	I
ADDRESS2	42	CPU address interface		5.0	I
ADDRESS3	43	CPU address interface		5.0	I
ADDRESS4	44	CPU address interface		5.0	I
VDD4	45	supply for pad ring		3.3	−
ADDRESS5	46	CPU address interface		5.0	I
ADDRESS6	47	CPU address interface		5.0	I
ADDRESS7	48	CPU address interface		5.0	I
ADDRESS8	49	CPU address interface		5.0	I
VSS5	50	ground for pad ring		−	−
VSSCO2	51	ground for core logic		−	−
VDDCO2	52	supply for core logic		3.3	−
SDRAM_DATA0	53	memory data interface		3.3	I/O
SDRAM_DATA15	54	memory data interface		3.3	I/O
SDRAM_DATA1	55	memory data interface		3.3	I/O
VDD5	56	supply for pad ring		3.3	−
SDRAM_DATA14	57	memory data interface		3.3	I/O
SDRAM_DATA2	58	memory data interface		3.3	I/O
SDRAM_DATA13	59	memory data interface		3.3	I/O
VSS6	60	ground for pad ring		−	−
SDRAM_DATA3	61	memory data interface		3.3	I/O
SDRAM_DATA12	62	memory data interface		3.3	I/O
SDRAM_DATA4	63	memory data interface		3.3	I/O
VDD6	64	supply for pad ring		3.3	−
SDRAM_DATA11	65	memory data interface		3.3	I/O
SDRAM_DATA5	66	memory data interface		3.3	I/O
SDRAM_DATA10	67	memory data interface		3.3	I/O
VSS7	68	ground for pad ring		−	−
SDRAM_DATA6	69	memory data interface		3.3	I/O
SDRAM_DATA9	70	memory data interface		3.3	I/O
SDRAM_DATA7	71	memory data interface		3.3	I/O
VDD7	72	supply for pad ring		3.3	−
SDRAM_DATA8	73	memory data interface		3.3	I/O
SDRAM_WE	74	SDRAM write enable output		3.3	O
SDRAM_CAS	75	SDRAM column address strobe output		3.3	O
VSS8	76	ground for pad ring		−	−
SDRAM_RAS	77	SDRAM row address strobe output		3.3	O
SDRAM_UDQ	78	SDRAM write mask output		3.3	O
VDD8	79	supply for pad ring		3.3	−
READI	80	read command input		3.3	I

1997 Jan 29

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Philips Semiconductors			Objective specification
Integrated MPEG2 AVG decoder				SAA7201
SYMBOL	PIN	DESCRIPTION		V	I/O
READO	81	read command output		3.3	O
VSS9	82	ground for pad ring		−	−
CP81MEXT	83	81 MHz clock return path input		3.3	I
CP81M	84	81 MHz memory clock output		3.3	O
VDD9	85	supply for pad ring		3.3	−
SDRAM_ADDR8	86	memory address		3.3	O
SDRAM_ADDR9	87	memory address		3.3	O
SDRAM_ADDR11	88	memory address		3.3	O
VSS10	89	ground for pad ring		−	−
SDRAM_ADDR7	90	memory address		3.3	O
SDRAM_ADDR10	91	memory address		3.3	O
SDRAM_ADDR6	92	memory address		3.3	O
VDD10	93	supply for pad ring		3.3	−
SDRAM_ADDR0	94	memory address		3.3	O
SDRAM_ADDR5	95	memory address		3.3	O
SDRAM_ADDR1	96	memory address		3.3	O
VSS11	97	ground for pad ring		−	−
SDRAM_ADDR4	98	memory address		3.3	O
SDRAM_ADDR2	99	memory address		3.3	O
SDRAM_ADDR3	100	memory address		3.3	O
VSSCO3	101	ground for core logic		−	−
VDDCO3	102	supply for core logic		3.3	−
VDD11	103	supply for pad ring		3.3	−
TEST8	104	IC test interface		3.3	I/O
TEST7	105	IC test interface		3.3	I/O
HS	106	horizontal synchronization input and output		3.3	I/O
VS	107	vertical synchronization input and output		3.3	I/O
VSS12	108	ground for pad ring		−	−
YUV0	109	YUV video output at 27 MHz		3.3	O/Z
YUV1	110	YUV video output at 27 MHz		3.3	O/Z
YUV2	111	YUV video output at 27 MHz		3.3	O/Z
YUV3	112	YUV video output at 27 MHz		3.3	O/Z
VDD12	113	supply for pad ring		3.3	−
YUV4	114	YUV video output at 27 MHz		3.3	O/Z
YUV5	115	YUV video output at 27 MHz		3.3	O/Z
YUV6	116	YUV video output at 27 MHz		3.3	O/Z
YUV7	117	YUV video output at 27 MHz		3.3	O/Z
TEST6	118	IC test interface		3.3	I/O
GRPH	119	indicator for graphics information output		3.3	O
TEST5	120	IC test interface		3.3	I/O

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Philips Semiconductors					Objective specification
	Integrated MPEG2 AVG decoder					SAA7201
	SYMBOL		PIN	DESCRIPTION		V	I/O
	VDDA		121	supply for analogue blocks		3.3	−
	VSSA		122	ground for analogue blocks		−	−
	VSS13		123	ground for pad ring		−	−
	CLK		124	27 MHz clock input		3.3	I
	VSS14		125	ground for pad ring		−	−
	TCLK		126	boundary scan test clock input		3.3	I
	TRST		127	boundary scan test reset input		3.3	I
	TMS		128	boundary scan test mode select input		3.3	I
	TDO		129	boundary scan test data output		3.3	O
	TDI		130	boundary scan test data input		3.3	I
	VDD13		131	supply for pad ring		3.3	−
	TEST4		132	IC test interface		3.3	I/O
	TEST3		133	IC test interface		3.3	I/O
	TEST2		134	IC test interface		3.3	I/O
	TEST1		135	IC test interface		3.3	I/O
	TEST0		136	IC test interface		3.3	I/O
	VDD14		137	supply for pad ring		3.3	−
			138	hard reset input (active LOW)		3.3	I
	RESET
	FSCLK		139	256 or 384 fs (audio sampling) output		3.3	O/Z
	VDDCO4		140	supply for core logic		3.3	−
	VSSCO4		141	ground for core logic		−	−
	SCLK		142	serial audio clock output		3.3	O/Z
	SD		143	serial audio data output		3.3	O/Z
	VSS15		144	ground for pad ring		−	−
	WS		145	word select output		3.3	O/Z
	SPDIF		146	digital audio output		3.3	O/Z
	ERROR		147	flag for bitstream error input		5.0	I
	V_STROBE		148	video strobe input		5.0	I
	VDD15		149	supply for pad ring		3.3	−
	AV_DATA0		150	MPEG input port for PES data		5.0	I
	AV_DATA1		151	MPEG input port for PES data		5.0	I
	AV_DATA2		152	MPEG input port for PES data		5.0	I
	AV_DATA3		153	MPEG input port for PES data		5.0	I
	VSS16		154	ground for pad ring		−	−
	AV_DATA4		155	MPEG input port for PES data		5.0	I
	AV_DATA5		156	MPEG input port for PES data		5.0	I
	AV_DATA6		157	MPEG input port for PES data		5.0	I
	AV_DATA7		158	MPEG input port for PES data		5.0	I
	A_STROBE		159	audio strobe input		5.0	I
	VDD16		160	supply for pad ring		3.3	−

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Philips Semiconductors	Objective specification
Integrated MPEG2 AVG decoder	SAA7201

handbook, full pagewidth		DD16	STROBEA	DATA7AV	DATA6AV	DATA5AV	DATA4AV	SS16	DATA3AV	DATA2AV	DATA1AV	DATA0AV	DD15	STROBEV	ERROR	SPDIF	WS	SS15		SCLK	SSCO4	DDCO4	FSCLK	RESET	DD14	TEST0	TEST1	TEST2	TEST3	TEST4	DD13	I	O	TMS	TRST	TCLK	SS14	CLK	SS13	SSA	DDA
																			SD
		V						V					V					V			V	V			V						V	TD	TD				V		V	V	V
		160	159	158	157	156	155	154	153	152	151	150	149	148	147	146	145	144	143	142	141	140	139	138	137	136	135	134	133	132	131	130	129	128	127	126	125	124	123	122	121
MUX	1																																								120	TEST5
CPU_TYPE	2																																								119	GRPH
DMA_ACK	3																																								118	TEST6
DMA_REQ	4																																								117	YUV7
DMA_DONE	5																																								116	YUV6
DMA_RDY	6																																								115	YUV5
VSS1	7																																								114	YUV4
CS	8																																								113	VDD12
DS	9																																								112	YUV3
AS	10																																								111	YUV2
R/W	11																																								110	YUV1
DTACK	12																																								109	YUV0
VDD1	13																																								108	VSS12
IRQ0	14																																								107	VS
IRQ1	15																																								106	HS
IRQ2	16																																								105	TEST7
IRQ3	17																																								104	TEST8
VSS2	18																																								103	VDD11
VSSCO1	19																																								102	VDDCO3
VDDCO1	20																		SAA7201																						101	VSSCO3
DATA0	21																																								100	SDRAM_ADDR3
DATA1	22																																								99	SDRAM_ADDR2
DATA2	23																																								98	SDRAM_ADDR4
DATA3	24																																								97	VSS11
VDD2	25																																								96	SDRAM_ADDR1
DATA4	26																																								95	SDRAM_ADDR5
DATA5	27																																								94	SDRAM_ADDR0
DATA6	28																																								93	VDD10
DATA7	29																																								92	SDRAM_ADDR6
VSS3	30																																								91	SDRAM_ADDR10
DATA8	31																																								90	SDRAM_ADDR7
DATA9	32																																								89	VSS10
DATA10	33																																								88	SDRAM_ADDR11
DATA11	34																																								87	SDRAM_ADDR9
VDD3	35																																								86	SDRAM_ADDR8
DATA12	36																																								85	VDD9
DATA13	37																																								84	CP81M
DATA14	38																																								83	CP81MEXT
DATA15	39																																								82	VSS9
VSS4	40																																								81	READO
		41	42	43	44	45	46	47	48	49	50	51	52	53	54	55	56	57	58	59	60	61	62	63	64	65	66	67	68	69	70	71	72	73	74	75	76	77	78	79	80
																																									MGD321
		ADDRESS1	ADDRESS2	ADDRESS3	ADDRESS4	DD4	ADDRESS5	ADDRESS6	ADDRESS7	ADDRESS8	SS5	SSCO2	DDCO2	SDRAM DATA0	SDRAM DATA15	SDRAM DATA1	DD5	SDRAM DATA14	SDRAM DATA2	SDRAM DATA13	SS6	SDRAM DATA3	SDRAM DATA12	SDRAM DATA4	DD6	SDRAM DATA11	SDRAM DATA5	SDRAM DATA10	SS7	SDRAM DATA6	SDRAM DATA9	SDRAM DATA7	DD7	SDRAM DATA8	SDRAM WE	SDRAM CAS	SS8	SDRAM RAS	SDRAM UDQ	DD8	I
						V					V	V	V				V				V				V				V				V				V			V	READ
																	Fig.2			Pin configuration.
1997 Jan 29																						10

Philips Semiconductors	Objective specification
Integrated MPEG2 AVG decoder	SAA7201

FUNCTIONAL DESCRIPTION

General

The SAA7201 is an MPEG2 decoder which combines audio decoding, video decoding and enhanced region based graphics. The decoder operates with a single 16 Mbit external synchronous dynamic random access

memory (SDRAM) and runs from a single external 27 MHz clock. Due to the optimized memory control for MPEG2 decoding, more than 1 Mbit is available for graphics in 50 Hz systems.

MPEG2 data can be accepted up to 9 Mbytes/s through a dedicated byte wide interface. The data on this interface can be either in PES (Packetized Elementary Stream), MPEG1 packet or ES (Elementary Stream) format as described in Chapter “References”. Two additional strobe signals distinguish between audio and video data.

The internal video decoder is capable of decoding all MPEG compliant streams up to main level main profile as specified in Chapter “References”. The audio decoder implements 2 channel audio decoding according to the standards in Chapter “References”.

All real time audio/video decoding and synchronization tasks are performed autonomously, so the external microcontroller only needs to perform high-level tasks like initialization, status monitoring and trick mode control.

The main support task of the external microcontroller concerns the control of the graphical unit. This unit should

be supplied with bit-maps, determining the contents of the graphical regions and by a simple set of instructions determining the appearance of the graphical data on the screen. Most graphical information should be stored in the external memory which implies multiple data transfers between CPU and the external memory. By performing these data transfers on a direct memory access (DMA) basis, full bit-maps can be transferred within one video frame period.

The video output, containing a mix of MPEG video and graphical data, is at a YUV multiplexed format which can be directly connected to an external composite video encoder. The audio output, containing a mix of MPEG audio and programmable ‘beeps’, is in a serial, I2S or Japanese format which can be directly supplied to most commercially available up-sampling audio DA converters.

A functional block diagram of the decoder is given in Fig.1. Its application environment is depicted in Fig.24. In the following sections, a brief description of the individual internal blocks of the MPEG2 decoder will be given.

Audio/video interface

In a basic set-top box application the SAA7201 receives audio and video PES data in a byte wide format at rates up to 9 Mbytes/s. A timing diagram is shown in Fig.3. Next to the 8-bit wide data bus an audio and video strobe is expected at the input. Erroneous data may be flagged via the error indicator.

handbook,AVfullDATApagewidth

(0 to 7)

video byte (n) video byte (n + 1) audio byte (m)

³25 ns ³25 ns

V_STROBE

³111 ns

A_STROBE

ERROR

MGD323

Fig.3 Timing diagram of parallel input mode.

1997 Jan 29

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