PHILIPS EM1.2U Service Manual

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Circuit Descriptions and Abbreviation List

Index of this chapter

1. Introduction

2. Block diagram

3. Power supply

4. Control

5. Tuner and IF

6. Video: HD jack interface

7. Video: High-end Input Processor

8. Video: Feature box

9. Video: High-end Output Processor

10. Video: 3D Comb Filter

11. Video: PIP/DW Panel

12. Synchronization

13. Horizontal deflection

14. Vertical deflection

15. Audio

16. CRT Panel / Rotation / Scavem

17. Software related features

18. Abbreviation list

19. IC Data Sheets

For a good understanding of the following circuit descriptions, please use the Block Diagram LSP

Supply and Deflection, Block Diagram Video + DVI and DW, Block Diagram Video without DVI
and DW, Block Diagram Audio, I2C Overview, Supply Lines Overview and Testpoints Overview

(LSP (Copper Track Side)

WITHOUT DW + DVI), DW Panel, SSB) and Wiring Diagram. Where necessary, you will find a

separate drawing for clarification.

, CRT Panel (FOR SETS WITH DW + DVI), CRT Panel (FOR SETS

Introduction

The EM1.2U is a low end R8 chassis, with the same LSP, but with a Painter
microprocessor (instead of the OTC).
The user interface and micro controller are the same as used in H8 sets. In the EM1.2U
however, a HIP, PICNIC, and HOP are used for the '100 Hz' function instead of the
BOCMA in the H8.
The HIP and HOP have about the same functionality as the BOCMA. This chip set insures
that line frequency and YUV-signals are doubled (2 fH), while the vertical frequency stay 60
Hz (1fH). The set runs in progressive scan (an interlaced picture at 60 Hz, instead of at 30
Hz in normal NTSC).

The EM1.2U architecture consists of a full sized LSP/SSP combination, a smaller sized

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SSB (mounted on the SSP via a SIMM connector), a PIP/DW panel, and a 3D Comb Filter
panel.
The main functionalities of these boards are:

z

LSP: supply, deflection, and sound amplification.

z

SSP: tuner input, SIMM interface, I/O and interface provisions for extended functions
such as PIP.

z

SSB: core TV functionalities, such as set control, video and audio decoding, feature
box, video featuring, and sync/geometry control.

The LSP (single sided) is designed very conventionally, with hardly any surface mounted
components on the copper side.

Warning: be aware that the LSP has a very large 'hot' area, including both deflection coils.

The SSB is a high tech module (four layer, 2 sides reflow technology, full SMC) with very
high component density and complete shielding for EMC reasons. Despite this, it is
designed so that repair on component level still is possible. To achieve this, attention was
paid to:

z

The position of service test lands: most of them are at the Tuner side.

z

Accessibility (Tuner side). If there are still problems with the accessibility, one can
order an extension board (12 NC: 9965 000 05769).

z

Clearance around surface mounted ICs (for replacing).

z

Detailed diagnostics and fault finding is possible via ComPair.

Caution: Always be sure that the set is 'off' (disconnected from the AC Power) when you
remove or replace the SSB panel!

Block Diagram

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Figure: Block diagram

The Tuner/splitter (item 1200) is a PLL tuner and delivers the IF-signal, via audio and video
SAW-filters, to the HIP (High-end Input Processor). The HIP has the following functions:

z

IF modulation.

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z

Video source select and record select.

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Color decoder.

z

Synchronization.

Several video input/output connections (with audio connections) are available:

1. Side I/O: interfaces CVBS, SVSH.

2. AV1: interfaces CVBS, RGB-input and YUV-input (1fH)

3. AV2: interfaces CVBS and Y/C (meant for VCR-connection).

4. AV4: interfaces YPbPr/RGB (HD) inputs (2fH).

5. Monitor out: interfaces CVBS out.

6. Audio out: interfaces external front and surround speakers.

The HIP delivers YUV and sync signals to the PICNIC. This IC takes care of:

z

Analog to Digital conversion and vice versa.

z

Interlaced to progressive scan conversion.

z

Panorama mode.

z

Noise reduction.

z

Dynamic contrast.

For Digital Scan, the PROZONIC is required, which can be connected to the PICNIC.

After the PICNIC, the YUV signals and sync signals are fed to the HOP (High-end Output
Processor). This IC handles the video control and geometry part. The RGB-signals for
CC/OSD (from the uP) are also inserted via the HOP. The video part delivers the RGB
signals to the CRT-panel and the geometry part delivers the H-drive, V-drive, E/W-drive,
and TILT-drive signals.

Both deflection circuits are 'hot' and located on the LSP. The HOP drives them. To make a
galvanic separation, the Line Drive is driven via transformer 5410 and the Frame Drive via
transformer 5621.The horizontal output stage generates some supply voltages and the EHT
voltage, focus voltage and Vg2 voltage.

The RGB amplifiers on the CRT-panel are integrated in one IC, and are supplied with 200 V
from the LOT.
The Scavem circuit modulates transitions of the Luminance (Y) signal on the horizontal
deflection current, giving a sharper picture.

The sound part is built around the MSP34xx (Multi-channel Sound Processor) for IF sound
detection, sound control and source selection. Dolby decoding is also done by the MSP.
Amplification is done via a 'class B' integrated power amplifier IC, the TDA7497.

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The microprocessor ('Painter') takes care of the analog CC input processing and output
processing. The μP, ROM, and RAM are supplied with 3.3 V, which is derived from the
+5V2.
The NVM (Non Volatile Memory) is used to store the settings, the Painter is an OTP (One
Time Programmable) chip with integrated set software.

There is a separate Standby Supply, in order to reduce the Standby power consumption.
During Standby, the Main Supply is switched 'off' (via TS7529). A relay (1550) is used to
switch the Degaussing circuit. It is switched 'on' after set start-up and switched 'off' by the
μP after 12 s.
The Main Supply, a SMPS based on the 'boost converter' principle, generates the 141 V
(VBAT) and the +28V for the audio part.
Note: Voltage VBAT is not mains isolated ('hot'), but is alignment free.

Power Supply (Diagram A1 and A2)

The power supply has a number of main functions:

1. Mains harmonic filter.

2. Degaussing picture tube.

3. Standby power supply.

4. Main supply.

Mains Harmonic Filter (Diagram A1A)

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Figure: Mains harmonic filter

The mains harmonic filter has two functions: to prevent high frequency signals (harmonics)
from being transferred into the mains and to protect the set from lightning damage.
Capacitor C2507 prevents the high frequency signals (generated by the set), from being
conveyed into the mains (it forms a short-circuit).
In case of a lightning surge between the 2 phases (differential mode), the energy is
immediately bled away through the VDR (R3509) to the other phase.
In case of a lightning surge on both phases of the mains in relation to the aerial ground
(common mode), the filter acts as a high resistance (U

= L * dI/dt), as a result of which

EMK

the voltage across coil L5503/04 increases. A spark gap (1590) prevents the voltage from
increasing too much, which would lead to a damaged coil. When ignited, the current will be
discharged via this spark gap.
Resistor R3500 is used for limiting the inrush-current.

Degaussing (Diagram A1A)

As soon as the set is connected with the AC Power, the 5V2 is present. When the
'DEGAUSSING' signal from the processor (Painter) is 'low,' transistor 7528 will conduct,
and relay 1550 is activated. Initially a considerable current will flow, via PTC 3516, through
the degaussing coil. The PTC will heat up, resistance will rise, and the current will decay
rapidly. The Painter makes the 'DEGAUSSING' signal 'high' after 12 seconds, which will
switch 'off' the relay.

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Standby power supply (Diagram A2)

Principle

This power supply is not only delivering the standby voltage, but also the main voltages for
the small signal part. It is a SOPS type (Self-Oscillating Power Supply) and is regulated by
the controlled switching of an oscillator. It uses the 'Flyback' principle:

Figure: Flyback principle

After closing switch 'S,' the current ID will increase linearly in time. The magnetic energy in
the primary coil is directly proportional with the self-inductance of the coil and current ID
(thus with the time the switch is closed).
The voltage polarity at the secondary winding is negative (due to different winding
direction), meaning that diode D will block. Capacitor C will discharge via R

, and U

L

OUT

will decrease.
Opening switch 'S' will generate a counter-e.m.f. in the primary winding, trying to maintain
current I D . Through this the polarity of the secondary voltage will inverse. The magnetic

energy stored in the coil will now be transformed to the secondary side. Diode D will now
conduct, capacitor C will be charged, and U

will increase.

OUT

Implementation

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Figure: Standby supply circuitry

To apply this on the EM1.2U (diagram A2): replace switch 'S' by FET TS7102, coil L by
L5100, diode D by D6111, and C by C2104.

z

Time interval t0-t1: After switching 'on' the TV-set, the gate of MOSFET TS7102 will
be high (max. 15 V due to zener diode D6105). This will drive the FET into saturation
(UDS = 0 V). The DC-voltage UMAINS will be transposed across the primary winding
of L5100 (3, 5), resulting in a linear increasing current through this coil. The voltage
across the co-coupled coil (1, 2) is also positive and will keep the FET in conductivity
via C2101, R3103/3105/3102 and R3117 for some time. The self-induction of the coil
and the magnitude of the supply voltage (+375 V) determine the slope of the primary
current. The maximum current is determined by the time the FET stays in
conductance (t0-t1). This time is directly determined by the voltage across
R3108//R3118 (0.7 Ω). This voltage is a measure of the current, and if it exceeds 1.4
V, TS7101 will be driven into conductivity and consequently connects the gate of

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TS7102 to earth. The FET will block. The current is: 1.4 V / 0.7 Ω = 2 A. The voltage
across the secondary winding (8, 9) will be negative, diodes D6111 and D6107 will
block.

z

Time interval t1-t2: The sudden current interruption in the primary coil will induce a
counter-e.m.f. that tries to maintain the current. The voltage on the drain of the FET
will increase. The secondary voltage (8, 10) will become positive and will charge
C2104 via D6111. All energy that was stored in L5100 during t0-t1 will be transferred
into the load. Due to the transformer principle, a voltage will now be induced in the
primary winding (3, 5) and the co-coupled winding (1, 2). This voltage will be N* U

(N= winding ratio). The voltage across the co-coupled coil will be negative, keeping
the FET blocked.

z

Time t2: At t2, the current through the secondary coil will be reduced to zero, as
C2104 is no longer charged. Consequently, the voltages will decay and will change
polarity. The gate of the FET will be again made positive, is driven into conductivity,
and the cycle starts again.

SEC

5V2 Stabilization and Feedback

The Standby Power Supply always oscillates at maximum power. The only limiting factor is
the maximum primary current, which has been preset with R3108//3118.
R3113, zener diode D6122, R3124, and R3114 determine U

. If the voltage across

OUT

R3114 exceeds the threshold voltage of the diode of the optocoupler 7104 (± 1 V) or, in
other words, UOUT exceeds 5.2 V, the transistor of the optocoupler will conduct.
Transistor TS7100 is now driven, and a negative voltage will be transposed to the emitter of
TS7101. When TS7101 conducts, the gate of the FET is at earth potential, forcing the
oscillator to stop. Due to the load, the secondary voltage U

will decrease. At a certain

OUT

voltage, optocoupler TS7104 will block and the oscillator will start again.
Since there are no capacitors, and there is a high amplification factor in the feedback
circuit, the feedback is ultra-fast. This is why the ripple on U

is minimal. The negative

OUT

supply voltage (-20 V) used in the feedback circuit originates from the co-coupling coil, and
is rectified through D6103.
Stabilization is not effected through duty-cycle control, but through the burst-mode of
TS7100.
Burst-mode is load dependent. If the power supply is less loaded, the secondary voltage
will have the tendency to increase more rapidly. If the load on the power supply increases,
then the oscillator stops less often, right up to the moment that the oscillator is operating
continuously: maximum load. If the power supply is now loaded even more, the output
voltage will decay. The maximum primary current set by R3108//3118 determines the
maximum load.

8V6 Stabilization and Feedback

In general, with a flyback supply with multiple outputs, as used in the former chassis, one of

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the output voltages is controlled via the primary feedback loop. The additional secondary
output voltages are determined via the turn-ratio of the transformer.
It is often seen that a linear voltage regulator is used for post regulation of the non-primary
regulated secondary voltages. The disadvantage of this approach is the power loss in the
linear voltage regulator.

For this chassis, a power economic solution is achieved, by implementing a kind of
secondary down-converter. The advantage, compared to a conventional down-converter, is
that no extra coil is required. It is using the inductance of the main transformer. This way
one large current coil, a power diode, and one elcap are saved.

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Figure: Circuit principle

A basic flyback converter is used, with a MOSFET Q1, transformer L1, and a primary
feedback circuit. The output of the primary controlled voltage is U1.
The additional secondary controlled supply consists of D2 and Q2, with output voltage U2.
The main flyback supply is working independently, where the duty cycle is controlled via the
primary feedback, and the MOSFET Q1 is switching at a certain frequency. MOSFET Q2 is
also switching at the same frequency, as it is synchronized with Q1.

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Figure: Timing diagram

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Time interval t0-t1: The primary MOSFET Q1 is switched 'on,' both diodes D1 and D2
are blocked.

z

Time interval t1-t2: MOSFET Q1 is switched 'off' and Q2 is switched 'on.' During this
period, the energy is transferred to output U2 of the supply. Diode D1 is blocked,
because U3 is lower than U1.

z

Time t2: Q2 is switched 'off.'

z

Time interval t2-t3: During this period, the rest of the energy will be transferred to
output U1.

The two controllers, the primary feedback for U1, and the secondary feedback for U2, all
work independently.
The secondary voltage U2 is controlled by the 'on' time of Q2.
As soon as the load on U2 increases, the 'on' time of Q2 (the period t1-t2) is automatically
increased by the secondary feedback. More energy will be taken by the output U2, and less
energy will be transferred to U1. Voltage U1 will drop automatically. The primary feedback

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loop will change the primary drive to enlarge the total amount of energy to be transferred,
from the primary side, and U1 will rise again.

Protection

If the optocoupler fails, the secondary voltage will increase. This would have disastrous
consequences since many ICs (for example, Painter, Flash-RAM and DRAM) are fed with
this 5.2 V. In other words, very expensive repairs would be required.
We already know that the negative supply is directly dependent upon the secondary 5.2 V,
because of which the negative supply will increase proportionally as the secondary voltage
increases.
If the negative supply, in the mean time, reaches -25 V, D6106 will start to zener and
TS7101 will start conducting. D6106 will take over the stabilization task of the optocoupler,
however, with a considerable spread: from -20 to -25 V is a 25 % increase, thus UOUT will
increase from 5.2 V to a maximum of 6.5 V.

Tuner Supply

The Standby supply produces the +33V (V

) voltage for the tuner. The +33V is the

TUN

tuning voltage for the Tuner. The +5VT voltage is derived from the +8V with stabilizer 7912
(see diagram A8). It is used to supply the tuner only.

SSB Supply

There are several voltages going to the SSB: +8V6, +5V2 and +3V3.
The +5V2 and +8V6 (always present) come directly from the Standby power supply.
The +3V3 is derived from the +5V with stabilizer 7910 (diagram A8).

Main Supply (Diagram A1)

The main power supply is able to deliver continuous power between 100 W and 160 W.
Some important notes:

z

V

z

V

is not isolated from the main supply ('hot').

BAT

is alignment free.

BAT

Principle

The Main Power Supply generates the 141 V (V

based on the 'buck booster' principle. A booster converter produces an output voltage,
which is greater than its input voltage. This is necessary in order to get a stable V

the 110 V AC power input voltage.

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) and the +28V for the audio part. It is

BAT

BAT

out of

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Figure: 'Buck boost' principle

1. After closing switch 'S', a linear in time increasing current IT will flow through inductor
L.

2. Opening switch 'S' will generate a counter-e.m.f. in coil L, trying to maintain the
current. This is possible via diode D (this diode is also called the 'freewheel diode').
Therefore, after opening 'S', the magnetic energy stored in coil L will be transferred to

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electrostatic energy in capacitor C.

3. So, by changing the duty cycle, it will be possible to control V

BAT

.

Implementation

At start-up of the main supply, C2515 (diagram A1B) can be assumed to be a short-circuit.
UAB will be 15 V (R3513, D6510) and UGS of the FET will be +5.4 V (via D6515). The FET
will be driven into saturation (same as closing switch 'S'). The drain-current will increase
linearly in time. With other words: resistors R3513 and R3518 will start the oscillator. The
voltage across the co-coupled coil (5, 6) will keep the FET in conductivity.

The TS7502 is a low-voltage semiconductor, which drives the MOSFET TS7504. To bridge
the different voltage levels, an opto-coupler (item 7507) is used. Via this opto-coupler, the
DC-current through R3504 is influenced. The changed current through R3504 changes the
VBE of TS7502, which will influence the drive of MOSFET TS7504 (= switch 'S' in figure
'Buck boost principle').

The sudden current interruption in the primary coil will induce a counter-e.m.f. that tries to
maintain the current via the 'freewheel' diode D6534. This current is linearly decreasing in
time and, as it is also flowing through R3514//R3515, TS7502 will be blocked after a certain
period. The gate of the FET will be made positive again, is driven into conductivity, and the
cycle starts again.

For safety reasons, transistor TS7530 is added as a back-up solution for TS7502. If B-E of
TS7502 is shorted, TS7530 takes over its function.

Stabilization of V BAT

The output voltage VBAT is determined by: V

BAT

= V

IN

* (T

ON

/ (T

ON

+ T

OFF

)) = V

IN

*

duty-cycle.
To stabilize the output voltage, a feedback loop is implemented, which will reduce T

when V

increases and vice versa.

BAT

ON

Via a voltage divider, existing of (1 %) resistors R3507, R3510, and R3527//3549, a voltage
of 2.5 V (when VBAT = 141 V) is fed to the input of precision shunt regulator 7506. This
regulator will conduct, and a current will flow through the diode part of the opto-coupler

7507. The base of TS7502 will now be set at a certain positive voltage. As this transistor
switches the FET TS7504 'on' and 'off,' this circuit can determine the duty-cycle.
For example, when the load increases, V

will decrease. Consequently, the input

BAT

voltage of regulator 7506 will decrease, resulting in a lower current. Via opto-coupler 7505
and transistor TS7502, T

will rise.

BAT

of the FET is changed (will increase). The output voltage V

ON

If the load continues to increase, the regulator will block at a certain moment. TON is now

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at maximum value. This is the point where V

will go below 141 V and, at further

BAT

increasing load, is switched 'off.' The voltage across the co-coupled coil (L5506, pin 4 and

5) will decrease, due to the increasing load. Therefore, the voltage on the gate of TS7504
comes below the threshold voltage. The supply switches 'off,' and an audible hiccupping
can be heard.
On the other hand, when the load decreases, V

will rise. Consequently, the input

BAT

voltage of TS7506 will also rise, resulting in a higher current. This changes the base
voltage of TS7502, and through that the T

V

will be reduced.

BAT

If, for instance, V

decreases (for example, U

IN

of the FET will decrease. The output voltage

ON

MAINS

is 90 V instead of 120 V), the slope of

the drain-current will be flattened, through which the FET will be in conductance longer,
keeping V

If, for any reason, the stabilization circuit fails, the output voltage V

200 V (via D6514). D6514 will form a short-circuit, V

constant.

OUT

can never exceed

BAT

will drop and the set will switch

BAT

'off' (this will also result in an audible hiccupping of the supply).

Switch to 'Standby' (via RC)

When the set is switched to 'Standby' mode via the Remote Control, the Main supply is
switched 'off' by the circuit around TS7529 (see diagram A1).
During 'on'-state, the Main supply is fed with line pulses via the 'SUP-ENABLE' line. They
are rectified and smoothed via D6517, D6516, and C2530, and fed to TS7529. Because
they are less than -20 V, this transistor is blocked. When these pulses are stopped, TS7529
will be saturated and TS7502 will switch 'on.' This will switch 'off' the Main supply.

It is important, that the Main supply is switched 'off' before the Standby supply. This is in
order to prevent several unwanted phenomena, such as audible plops and visible switch off
spots. Without an extra circuit to force this, this cannot be achieved. Therefore, the circuit
around TS7505 and TS7508 (diagram A1A) is implemented.
This circuit compares the Main DC voltage (+375 V) and a reference voltage (V

BAT

) via

resistors R3554, R3555, R3560, and R3556. Elcap C2539 serves as voltage source for the
two transistors.
When the Main DC voltage will decrease w.r.t. the reference voltage VBAT, the
'SUP_ENABLE' line will be activated via TS7505, TS7508 and R3559. This will switch 'off'
the Main supply via TS7529.

Switch to 'On' (via 'SUP-ENABLE')

Via the 'STANDBY' command from the Painter, the MOSFETS 7141 and 7131 (diagram
A2) are switched 'on.' When the Painter senses the +5V and +8V, a command is given to

2

the HOP to start the drive (via I

C).
When this is sensed via the 'SUP-ENABLE' line (at the base of line transistor TS7421,
diagram A3), the main supply is switched 'on' via TS7529 (diagram A1).

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Protection

When, for any reason (interruptions or defective components), the feedback loop of the
Main supply fails, the V

will rise. This is detected via zener diodes D6507, D6508, and

BAT

D6513. This will 'ignite' thyristor T7503, which will result in the blowing of fuse 1503.

Audio Supply

The pulses on the secondary winding of L5506 (or L5512) are rectified by D6535 (+16 V)
and D6536 (-16V), and smoothed by C2542 and C2543.

Control (Diagram B7)

Painter

Introduction

The SAA5667 (IC7001) is called the Painter. The microprocessor and the CC/OSD-decoder
are integrated in this IC. Some of its functions are:

z

Set control.

z

CC/OSD acquisition.

z

RGB-outputs to the HOP

z

Menu blending; for blending the contrast, software controlled.

z

I/O-ports for I 2 C, RC5, LED, and service modes.

z

Error code generation.

Data Storage

z

The set software is integrated in the Painter.

z

The Non Volatile Memory IC7001 is a 4 kB version M24C32, and is used to store data
of a working set.

Power Supply

The Painter is supplied with 3V3. For this voltage, a 3V3 stabilizer is used (IC7005).
With the circuitry around TS7003 and 7004 (diagram B7), a reset is generated to wake up
the Painter (pin 74). During this reset, all I/O pins of the Painter are made 'high.'

CC/OSD

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The horizontal (H D ) and vertical (V

SYNC

) sync pulses are also fed to the Painter for

stable OSD and CC.
This IC gets its video signal directly (from the HIP) on pin 31. The RGB-outputs (46/47/48)
together with the fast blanking signal (pin 52) are fed to the HOP.

I 2 C Bus

There are two I 2 C busses used:

z

Slow (max. 100 kHz) hardware I 2 C-bus (called SDA_S/SCL_S), used for all ICs.

z

Separate short bus (called SDA_NVM/SCL_NVM) for the Non Volatile Memory
(NVM), to avoid data corruption.

Note: In the diagrams you can also find a bus called SDA_F/SCL_F (F= fast), but in this
chassis it is connected to the 'slow' bus.

NVM

The Non Volatile Memory contains all set related data that must be kept permanently, such
as:

z

Software identification.

z

Operational hours.

z

Error codes.

z

Option codes.

z

All factory alignments.

z

Last Status items for the customer + a complete factory recall.

Tuner and IF (Diagram A8 and B2)

The tuner/splitter is I 2 C controlled, and is capable of receiving off-air and cable channels.

Tuning is done via I 2 C. The reference voltage on pin 9 is 33 V. This voltage (V

derived from the secondary side of the standby supply, via D6110 and R3116//R3115 and a
33 V zener diode (D6200). The Painter, together with the HIP, controls the tuning
procedure. There is also automatic switching for the different video systems.

The IF-filter is integrated in a SAW (Surface Acoustic Wave) filter. The type of this filter
depends on the received standard(s). There are two SAW filters: one for filtering picture-IF
and a second one for sound-IF.

The output of the tuner is controlled via an IF-amplifier with AGC-control. This is a voltage

TUN

) is

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feedback from pin 62 of the HIP to pin 1 of the tuner. AGC take-over point is adjusted via
the service alignment mode 'Tuner - AGC.' Service tip: If there is too much noise in the
picture, it is possible that the AGC setting is wrong. It is also possible that the AGC setting
is misaligned if the picture is deformed with a perfect signal. Then the IF-circuit is amplifying
too much.

The video IF-signal is fed to pins 2 and 3 of the PLL-controlled IF-demodulator. The
voltage-controlled oscillator of the PLL is adjusted via the service menu 'IF PLL OFFSET.' If
the alignment is correct, the frequency displayed in the installation menu is the same as the
applied frequency from a generator. The external coil L5408 connected between pins 7 and
8 is used as reference.
The demodulated IF-video signal is available at pin 10 of the HIP. In this video signal, there
is a rest of the sound carrier, which is filtered out by the sound trap 1407.
Via TS7322, the signal is supplied to AV1 (monitor out) and again back into the HIP (pin 14)
to the source/record selection.

To achieve Quasi Split Sound (QSS), the IF-signal is fed to the HIP on pin 63/64 via SAW­filter 1405. The FM- modulated signal is available on pin 5 and is fed to the audio
demodulator MSP34xx (7651, diagram B6).

Video: HD Jack Interface (Diagram N)

The Jack High Definition module covers the following functions:

1. RGB input/output selection.

2. Matrix circuit to convert YPbPr to RGB.

3. Sync slicer for YPbPr sync on Y, RGB sync on Green.

4. Sync selection.

5. Control Function.

6. Audio feed-through of signal source.

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Figure: Source selection

RGB in/output selection

The module has two video inputs and one RGB output (going into the set).
The inputs can also handle 1080i-signals and 480p-signals (both in RGB format and YPbPr
format).
(This selection circuitry is also needed to cope with the various formats of the non­standardized HD set top box business.)

Video-input (3 cinches, reference number 1993-A-B-C):

z

YPbPr with sync on Y.

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z

RGB with sync on green. Note: cinch-inputs are normally used for YPbPr input.

Video-input (D-sub, reference number 1990):

z

YPbPr with sync on Y. Note: D-sub input is normally used for RGB-inputs only.

z

RGB with sync on Green.

z

RGB with separate H and V Sync (called VGA in 480p).

RGB output:
This RGB output of the board is signaled into the set (HOP-section of SSB, diagram B4).

Matrix

The YPbPr-signal format is converted to RGB via the matrix function. In 480p-format, the
PAL matrix is used, otherwise the ATSC matrix is used.

The matrix choice is made with TDA8601 (SW1, 7107).
This switch is controlled via the command IO-1 (called MATRIX SELECT in the figure).

Sync Slicer

The sync slicer extracts the horizontal and vertical synchronization signals for the HOP (in
the set):

z

From the 3-level sync pulses Y of the 1080i YPbPr.

z

From the 3-level sync pulses Green of the 1080i RGB.

z

From the normal sync pulses of the 480p signal.

Explanation of 3-level sync shown in picture:

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Figure: 3-level sync signal

Example of a 2-level sync pulse: CVBS-signal with two levels of sync (-300 mV, 0 mV).
Example of a 3-level sync pulse: ATSC-signal with three levels of sync (-300 mV, 0 mV,
+300 mV).
The amplitudes of the Y, R, G, and B signals are 700 mV; amplitudes of the Pb and Pr
signals are 350 mV.

Sync Selection

If the synchronization is derived from Y or Green, the H and V sync from the sync-slicer
must be selected.

z

When YPbPr-signal or RGB-signal is 480p-format: sync signals will be V-770 and H­770-2 sync.

z

When YPbPr-signal or RGB-signal is 1080i-format: sync signals will be V-770 and H­770-3 sync.

When the sync is separate (H and V), the sync of the source must be selected.
The IO-4, IO-5 control-lines select the sync-inputs of the HEF4052 (7102).
In the figure, these control-lines are named SYNC_SELECT_2 and SYNC_SELECT_1.
Via IO-6 line (TRISTATE_SYNC), the sync output can be put in tri-state.

Control Function

The I/O expander, controlled by I 2 C, makes the different selections.
These selections can be made with the user interface.

Audio

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Audio left and audio right are connected via the two cinches and passed through the
module.

Video: High-end Input Processor (HIP, Diagram B2)

The HIP TDA932xH contains the following functions:

z

IF demodulation.

z

AFC signal generation, used to track drifting transmitters.

z

Sound carrier re-generation (SIF).

z

Sync acquisition, delivering H A , and V A .

Inputs

The HIP has various inputs:

z

Full matrix switch with:



Two CVBS inputs.



Two Y/C (or additional CVBS) inputs.



One CVBS front-end input.

z

Two RGB inputs.

Outputs

One can select three separate, switchable outputs:

z

One YUV-output, which is fed to the PICNIC.

z

Two CVBS outputs, one for CC-decoding (CVBS-TXT) and the other for MONITOR
out to have WYSIWYR (What you see is what you record).

Video Processing

The HOP will generate synchronization signals derived from the feature box (PICNIC, pin
60 and 61) signals.
If a VCR is connected, there is also an automatic correction for MacroVision (r). This is
active for the external sources.
The HIP itself (no external voltage) controls the Y/C switch in the HIP.
The chrominance decoder in the HIP is full multi-standard, but only NTSC is decoded.
A sync separation circuit is integrated in the HIP; the HIP delivers the HA50 and VA50 to
the PICNIC and DW-panel.

The quartz crystals can be connected without any alignment. They are also used as a
reference for the synchronization. A digital control circuit that is locked to the reference

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signal of the color decoder determines the start-up of the sync.
Note: If the crystal must be replaced, you must use only the genuine replacement part. This
crystal is very precise: if it is replaced by another type of crystal, there may be no color,
because of a different capacity.

Video: Feature Box (Diagram B3)

Introduction

The basic function of the Feature box (FBX6) is picture improvement, and depending on the
version, several scan conversion methods are possible. The feature box is integrated on
the SSB, and the PICNIC (SAA4978H) is the key component.
The PICNIC is used for the 60 Hz (prog. Scan) conversion. It has the following functions:

z

The ADC/DAC conversion.

z

Interlaced to progressive scan conversion.

z

Dual screen compression

z

The Panorama mode.

z

Automatic Aspect Ratio Adaptation (AARA)

z

Color Transient Improvement (CTI)

z

The contrast improvement (Dynamic Contrast).

All these functions are integrated in one IC: SAA4978H, 160 pins QFP.

The 60 Hz YUV signals, coming from the HIP, are fed to the PICNIC via an anti-aliasing
filter.
The (AABB) frame frequency doubling is done by the PICNIC (SAA4978, 160 pins QFP)
together with a field memory (MEM1).
This IC has an internal CPU and a (small) integrated ROM. The actual FBX software is
located in an external ROM (item 7711). In order to limit the number of connections
between the PICNIC and the external ROM, a number of lines are used twice. The lines A8
to A15 are fixed lines, while the lines A0 to A7 are made switchable with the eight data lines
of the ROM. This is done via a Latch (item 7712) that is controlled by pin 139 of the PICNIC
(the 'ALE' signal). Via bus 'C,' a digitalized signal is presented to FM1 (Field Memory 1),
which is used for the 60 to 120 Hz conversion.

ADC/DAC conversion

z

Analog to Digital conversion is done with three identical 9-bit ADCs.

z

Digital to Analog conversion uses three identical 10-bit DACs.

In the PICNIC there are three nine-bit ADCs present for Y, U, and V. For digitizing the Y
(luminance), nine bits are used (to realize a more detailed picture). These nine bits are only

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internally used. Via dithering, the nine bits are reduced to eight bits and this data is stored
into memory. The data in the memory is fed back to the PICNIC and via un-dithering the
data is again reproduced to nine bits for processing.
U/V (color difference signals) is also sampled with nine bits. These two nine bit data
streams are multiplexed to four bit data streams. As the perception of colors by the human
eye is less sensitive to luminance, this reduction is allowed.

Interlaced to progressive scan conversion

The main task of the PICNIC is the conversion from interlaced to progressive scan (60 Hz)
for YUV and HV-sync. In order to remove 'large area flicker' (especially visible in a white
picture), the field-rate of the video is doubled by the FBX6. The 16 kHz line frequency is
doubled. When the video input contains fields A, B, etc, the conversion provides an AABB
sequence on the display. The actual conversion is done in the first Field Memory by reading
it twice at double speed, while writing it once.

Dual Screen Compression.

The PICNIC can provide horizontal video compression up to 50 %. The compress mode
can be used to display dual screens.

The Panorama Mode.

To fit 4:3 pictures into a 16:9 display, it is possible to apply a panoramic horizontal
distortion, to make a screen-fitting picture without black sidebars or lost video. The center
horizontal gain is programmable and the side gain is automatically adapted to make a
screen-fit.

Automatic Aspect Ratio Adaptation (AARA)

This feature uses data from the 'black bar detection circuit' to adapt the vertical and
horizontal amplitude to an aspect ratio belonging to the display without showing the black
bars.

CTI

At CVBS video signals, the bandwidth of color signals is limited to 1/4 of the luminance
bandwidth. Transients between areas of different color are therefore not very sharp. The
PICNIC can increase these transients artificially with a time manipulation algorithm.

Dynamic Contrast

To make the contrast (black/white) range wider, Philips has invented Dynamic Contrast. It
uses the digital memory used in digital scan sets. It measures every A-field (25 x/s) and
digitally analyzes where on the grayscale most of the image is located. If it is a relatively
dark image, the lighter part of that image is stretched towards white, so that more contrast

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will become visible in that picture. If it is a relatively light image, the darker part of that
image is stretched towards black, so that these darker parts will have more contrast. When
the image is in the middle of the grayscale, both dark and light parts are stretched.

PROZONIC

Figure: Digital Scan principle

External ICs are connected to the PICNIC depending of the set features.
For EM1.2U sets with Digital Scan, the PROZONIC (IC7708, SAA4990H) is placed with two
memory ICs (IC7714 and 7715). It is an abbreviation for PROgressive scan ZOom and
Noise reduction IC. When applying this IC, a second Field Memory is necessary.
The following functions are available:

z

Line flicker reduction (Digital Scan): this is a feature to reduce the 30 Hz interlace line
flicker.

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z

Dynamic Noise Reduction: noise affected signals can be improved by combining the
pixel values of the current and past video fields. This is however only possible in
areas without movement.

z

Variable Vertical Sample Rate Conversion.

z

Synchronous No Parity Eight bit Reception and Transmission interface (SNERT-bus).

Video: High-end Output Processor (HOP) and TOPIC
(diagram B4)

General

The YUV-signals from the PICNIC are fed to the HOP (High-end Output Processor,
TDA9330). The video and geometry control parts are integrated in the HOP. The RGB­signals for CC/OSD (from the μP) are also inserted via the HOP. The geometry part
delivers the H-drive, EW-drive, V-drive, and also a drive signal for rotation.

The main functions of the HOP are:

z

Video control (contrast, brightness, saturation, etc).

z

Second RGB interface for OSD/CC.

z

Peak White Limiting.

z

Cut-off control and White Drive (RGB outputs).

z

Geometry control.

z

Deflection control.

The TOPIC (The most Outstanding Picture improvement IC, item 7302, type TDA9178) is
an optional IC between the PICNIC and the HOP. It has the following (picture improvement)
functions:

z

Luminance Transient Processor (LTP), for detail enhancement.

z

Chrominance delay circuitry, to compensate timing differences between Y and C.

z

Spectral processor, for improved sharpness and color transient improvement (CTI).

z

Color vector processor, for skin tone correction, green enhancement and blue stretch.

z

Measure and detection circuitry, for AutoTV.

The sandcastle pulse from the HOP is fed to pin 1 of the TOPIC, which is used as a
reference for timing.

Video Control

After source selection, the HOP controls the signals for Saturation, Contrast, and

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Brightness. Output is RGB again.

OSD/CC Control

On pins 35 to 38, the RGB and fast blanking from the Painter (OSD and CC) are inserted.
The sync signal V

SYNC

is derived from the 'FRAMEDRIVE-' signal.

Peak White Limiting

On pin 43 there is a Peak White Limiting signal line (PWL). If the beam current increases,
the 'EHT-info' voltage will decrease. Average limiting via R3343/C2333 controls PWL.

Cut-off Control

The following occurs when you switch the TV to Standby:

1. The vertical scan is completed.

2. The vertical flyback is completed (the horizontal output is gated with the flyback pulse,
so that the horizontal output transistor cannot be switched 'on' during the flyback
pulse).

3. The 'slow stop' of the horizontal output is started, by gradually reducing the 'on' time
at the horizontal output from nominal to zero (this will take 50 ms).

4. At the same time, the fixed beam current is forced via the black-current-loop for 25
ms. This is done by setting the RGB outputs to a maximum voltage of 5.6V.

A 'one-point' cut-off control is used: A current of 8 μA (for cut-off) is fed to pin 44 of the
HOP. This is done with a measurement pulse during the frame flyback. During the first
frame, three pulses are generated to adjust the cut-off voltage at a current of 8 μA. With this
measurement, the black level at the RGB-outputs is adjusted. Therefore, at start-up there is
no monitor pulse anymore. At start-up, the HOP measures the pulses, which come back via
pin 44. The RGB-outputs have to be between 1.5 V and 3.5 V. If one of the outputs is
higher than 3.5 V or one of them lower than 1.5 V, the RGB-outputs will be blanked.

Geometry control

All geometry control is performed via I 2C and the data is stored in the NVM (IC7011) of the
SSB.

Deflection Control

Line Drive

The Line drive is derived from an internal VCO. As a reference, an external resonator is

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used (1301). The internal VCO is locked with the H

PICNIC.
The 'PHI-2' part of the HOP receives the HFB_X-RAY_PROT (pin 13) to correct the phase
of the Line drive. The EHT-info is supplied to pin 14 (DYN-PHASE-CORR) to compensate
picture breathing depending on the beam current.
Note: This is not used in this chassis, therefore EHT-compensation in the SAM menu is set
to zero.

-pulse, which comes from the

D100

Frame Drive

At pins 1 and 2, the symmetrical frame drive signals are available. The V

synchronization of the OSD/CC, is derived from the 'FRAMEDRIVE-' signal.

SYNC

signal, for

East/West Drive

At pin 3, the E/W drive signal is available. Pin 4 is a feedback input for the EHT-info, and is
used to prevent pumping of the picture. The EHT also varies dependent on the beam
current. For example, for wide-screen without load this is 31.5 kV and with load (1.5 mA)

29.5 kV.

Frame Rotation

For frame rotation, a control voltage from pin 25 of the HOP is used. Frame rotation is only
used in wide-screen sets.

Guarding protections

Flash detection

When a flash occurs, the EHT-info will become negative very quickly. Via R3316, D6304,
and D6303, TS7303 starts to conduct. This makes pin 5 of HOP 'high.' The output (pin 8) is
immediately stopped.
If the H-drive stops, then pin 5 will also become 'low' again, which will reset the flash
detection.

bit (FLS) is set in an output status register, so that the Painter can detect that there was a

flash. This FLS-bit will be reset when the Painter has read that register.

HFB protection

If the HFB is not present, this is detected via the HOP. The Painter puts the set into
protection and reads a register in the HOP. An error code is generated.

Video: 3D Comb Filter (Diagram CO)

Conventional Comb filters separate the luminance (black and white picture information)

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from the chroma (color picture information), by comparing horizontal scanning lines within
one video frame.
The 3D Comb Filter takes this idea two steps further by acting upon not only consecutive
lines within the frame, but in the frames before as well. The added analysis and correction
result in far sharper pictures with less noise, as well as an enhanced purity of color. The
filter also compensates for any motion that occurs between fields.
Image movements are detected per pixel, and each still image is processed in 3D YC
separation, while each moving image is processed in 2D (line) YC separation automatically.
A non-standard NTSC signal (e.g.: NTSC VCR signal) will be processed in 2D YC
separation.
The 3D Comb filter is integrated in one IC (type μPD64083).

Short description

Figure: Block diagram of a 3D Comb filter

z

Sync separation: This block separates horizontal and vertical sync. Depending on
these syncs the input signal will be judged as standard or non-standard. In case of
standard signal, 3D Y/C separation is possible. In case of non-standard signal, 2D
Y/C separation is performed.

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z

Motion detector: In case we have standard signals, the Motion detector will determine
the position of the switch. In case motion is detected between two fields (on pixel
base), the switch will be forced into the 2D position. If there is no motion detected, the
switch will be set in the 3D-separation position.

z

3D Y/C separation: The phase of the present NTSC Chrominance signal is reversed
from that of the NTSC Chrominance signal of two fields before. By making use of this
characteristic, Y/C separation is performed with these fields. The Y/C separation will
not be possible when any moving portions that vary between the two fields are
processed. On these signals, 2D Y/C separation is performed.

z

2D Y/C separation: The phase of the present line Chrominance signal is reversed
from the signal at the same place, one line above and one line below. Making use of
this characteristic can perform Y/C separation. A 3-line Y/C separation will be
performed.

z

SDRAM: The SDRAM is a 2-field memory needed for 3D/2D Y/C separation.

z

Switch: The standard, non-standard detection block and the motion detector control
this switch.

The video inputs and outputs are protected from temporary overload conditions and are

ESD protected for improved reliability. The module is controlled via I 2 C commands.
The red LED on the panel indicates proper sync and color burst timing. When they are
detected, the LED must be 'off.'
The input currents for the 5 V (280 mA) and 9 V (120 mA) supply are self-limiting due to the
use of a PTC (R3103 and R3104).

Video: PIP/DW Panel (Diagram C)

This panel provides the option for the viewer to see two pictures or programs on the
displayed area of a TV screen. The displayed pictures can be in PIP mode or DW mode.
The viewer can also select the size and position of the 'second' picture.
Key components:

z

Tuner (item 7201).

z

SAW Filter (item 1352).

z

IF + Video processor (item 7301).

z

PIP processor (item 7801).

z

Switching ICs: TDA8601 (item 7803) and HEF4053 (items 7401 and 7402).

z

IO expander (item 7403).

z

V-chip (item 7501).

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Figure: Double Window circuitry

IF and Video section

The IF and Video processing in the PIP/DW module is performed by a BOCMA IC, and in
the set by the HIP IC. There is also a PIP processor.
'IF-TER' from the tuner is fed to pin 1 and 2, IF circuits of TDA8887H IC7301 via SAW filter

1352. The AGC voltage for the tuner can be adjusted in the SAM tuner menu (2nd AGC).
In order to display the external AV sources by the DW panel, a source selection circuit is
incorporated on the panel. Three external AV sources are possible (AV1-YUV, AV2­SVHS2, AV-FRONT). IC7401 HEF4053 performs the selection between these sources.
The YUV is fed directly to video processor IC7301. The IC performs this source selection
internally.
The video processor IC7301 decodes the CVBS at pin 24 or pin 29 into YC signal and
further process it into YUV signal and output at pin 40, 45, and 46. 'PIP-AUDIO' is fed to pin
47 of the audio demodulator MSP34x2 on the SSB.

PIP/DW processing

IC7801 SAB9081 is a multi-standard PIP controller, which can be used in double window or
PIP applications. The YUV from the video processor IC7301 is fed to pin 79, 81, and 83.
IC7801 will insert YUV from the IC7301 with reduced size into the main picture YUV source
in a PIP environment. The main picture YUV is fed to pins 100, 2, and 98, respectively.
These signals are mainly used during the DW mode.

Inside IC7801, the conversion to the digital environment is done on a chip with ADCs.
Processing and storage (1 MB DRAM) of the video data is performed entirely in the digital
domain. The conversion back to the analog domain is performed by DACs. Internal clocks
are generated by PLLs, which lock on to the applied horizontal and vertical syncs from the
main and sub pictures. The main picture syncs are applied to pin 70 (vertical) and pin 94
(horizontal), and the sub picture syncs are applied to pin 72 (vertical) and pin 87
(horizontal).
For DW mode, the main picture is compressed horizontally by a factor of two and fed
directly to the output. After compression, a horizontal expansion of two is possible for the
main picture. The sub picture is also compressed horizontally by a factor of two but stored
in memory before it is fed to the outputs.

Post-processed YUV signals are fed to fast switching IC7803 TDA8601 pins 6, 7, and 8. In
normal operation (without DW), the main picture YUV signals (at pins 2, 3 and 4) are
bypassed by IC7803, and returned back to the main video processor. When DW mode is
active, the compressed YUV signals (main and sub pictures) are used and fed to the main
video processor. During the PIP mode, only sub-picture YUV signals are used. The

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insertion control is made possible by a fast blanking signal from pin 68 of IC7801.

V-Chip

For the movie rating blocking requirements, a data-slicer is built on the DW panel. IC7501
Z86130 will decode the V-Chip coding for the DW picture. The source for decoding is made
possible by the 'SEL_PIP_CVBS' signal at the IO port of IC7301 pin 60. When this signal is
'low,' Tuner 1, Tuner 2, or AV CVBS is selected. When this signal is 'high,' the external YUV
is selected.

Power supplies

The power supplies used by the DW panel are from the main board 5 V, 8 V, and 33 V (for
tuner only). IC7802 LM317T regulates the 5V to +3.3V, +3V, and +3VD. These voltages are
mainly used by the DW processor circuitry. The 8V is mainly supplied to IC7301 TDA8887H
IF + video processing circuitry, and to fast switching IC7803.

Synchronization (Diagram B2, B3 & B4)

The HIP video processor provides the vertical and horizontal sync pulses V

They are synchronized with the incoming CVBS signal. These pulses are then fed to the
PICNIC, where they are doubled to be synchronous with the 120 Hz picture. The outgoing
pulses, V

drive pulses.

The V

synchronized on the HFB pulse from the CRT and on the VSYNC from the HOP, for the
synchronization of CC/OSD/EPG.

When no CVBS is offered to the video processor, the HIP switches 'off' the VA50 and HA50
pulses, and the pulses are generated by the PICNIC (to assure a stable OSD).

D100

and H

D100

pulse from the PICNIC is inverted by TS7304 to the V D signal. The Painter is

, are fed to the HOP, which supplies the vertical and horizontal

D100

A50

and H

A50

.

Horizontal (Line) Deflection (Diagram A3)

Principle

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Figure: Line deflection circuitry

The HOP (located on the SSB) generates the line-drive pulses (LINEDRIVE1), which have
a frequency of 31468 Hz (T = 31,77 s).

When the LINEDRIVE1 signal is high, TS7409 and TS7408 will conduct. A constant DC
voltage will be applied across L5410, causing a linearly increasing current through this coil.
The secondary voltage of L5410 has a negative polarity so that TS7421 will block.
When the set is switched 'on,' the current through L5410 is supplied by the 5V2 Standby
supply (via D6407), and taken over by the +11D voltage (via D6408) of the main supply.

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When the LINEDRIVE1 signal becomes low, TS7409 and TS7408 will block. The voltage
polarity across the primary winding of L5410 will invert. The positive voltage on the
secondary winding will now drive TS7421 into conductivity. Because of the storage time of
the line transistor (TS7421), L5410 cannot transfer its energy immediately to the secondary
side. This may result in high voltage peaks on the collector of TS7409 and TS7408. To
prevent these peaks from damaging the transistors, a 'snubber' circuit (C2414, C2412 and
R3411) will suppress them.

When the LINEDRIVE1 signal is high again, the sequence described above starts again.
Circuit L5411 and R3409 will increase the switch 'off' time of the line transistor.

The line stage is started via a 'slow start' principle. During start-up, the HOP generates line
drive pulses with a small TON and a high frequency (50 kHz). TOFF is constant and TON is
gradually increased until the frequency is 31468 Hz (normal condition).
The time interval from start to normal condition takes about 150 ms.
When switching off, the same procedure is followed, but in reverse order.

Implementation

To explain the operation of the line output stage, we use the following start conditions:

z

C2433 is charged to max. 141 V (V

z

TS7421 is driven into conductivity.

BAT

)

Figure: Line deflection part 1

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z

Period t1-t2: When TS7421 is driven into conductivity, the capacitor voltage of 141 V
will be divided across bridge-coil L5422 and the deflection coil (connector 1417). Due
to the chosen inductance values, there will be 100 V across the deflection coil and 41
V across L5422. The linearly increasing current in the deflection coil will result in a
spot moving from the center of the picture tube to the right. The voltage across L5422
will also charge C2421 (41 V - 0.7 V).

z

Period t2-t3: At the moment the LINEDRIVE signal becomes high, TS7421 will stop
conducting. A voltage will be induced in the coils, trying to maintain the current. The
current through the line deflection coils continues to flow through C2425 and C2421
and the current through L5422 continues to flow through C2426 and C2421. The
energy stored in the line deflection coil is passed to C2425, and the energy of L5422
to C2426. The resonance-frequencies of these two LC-circuits define the flyback time
of the spot from the right side of the picture tube to the left. On average, no current
flows through C2421, and thus the voltage across this capacitor remains constant.

Figure: Line deflection part 2

z

Period t3-t4: The same as period t2-t3; but now the current flows in the opposite
direction, since the voltage across C2425 and C2426 is higher than the voltage
across C2433 and C2421.

z

Period t4-t5: The coils try to maintain the negative current and will negatively charge
the capacitors. Because of this, D6422 and D6423 will conduct. The voltage is 100 V
across the deflection coil and 41 V across L5422. Since both diodes conduct, we may
consider the voltage constant. A linear current flows with the same changing
characteristics as in period t1-t2. The spot now moves from the extreme left of the
picture tube to the center. Before the current becomes zero, and the spot is located in

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the center of the frame, TS7421 reverts into conductivity. A short negative current will
flow. Then the cycle starts again.

Corrections

Several corrections are necessary to obtain a proper picture.

Linearity Correction

A constant voltage across the horizontal deflection coil should result in a linearly increasing
saw-tooth current. This is not the case, however, as the resistance of the coil is not
negligible. In order to compensate for this, a remagnetized coil L5421 in series with the
deflection coil is used. This coil ensures that during time interval t1-t3 the circuit resistance
will be higher than during t4-t5.
Item L5421 is the linearity coil. To avoid self-oscillation, R3431 and C2431 are placed
parallel to L5421.
See diagram “Line deflection circuitry” item [*1].

S-correction

Since the sides of the picture are further away from the point of deflection than the center, a
linear saw-tooth current would result in a non-linear image (the center would be scanned
slower than the sides).
To solve this, the deflection current for the right side and left side is reduced.
C2433 is quadratically charged during time interval t1-t2. The left and right voltage across
the deflection coil decreases, causing the deflection to slow down. In the center, the voltage
increases and the deflection will be faster.
An S-shaped current is superimposed on the saw-tooth current. This correction is called
'finger-length correction' or 'S-Correction.'
C2433 is relatively small, and as a result, the saw-tooth current will generate a parabolic
voltage with negative voltage peaks. The current also results in a parabolic voltage across
C2421, resulting in the finger-length correction, proportionally increasing with the picture
width.
The EW-DRIVE signal will ensure the largest picture width in the center of the frame. The
largest correction is applied here. The larger the picture width, the higher the deflection
current through C2433.
See diagram “Line deflection circuitry” item [*2].

E/W-correction

line written at the upper side or lower side of the screen will be larger at the screen center
when a fixed deflection current is used. Therefore, the amplitude of the deflection current
must be increased when the spot approaches the screen center. This is called East/West
correction.

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The EW drive signal originates in the HOP and is supplied to TS7480 via OpAmp 7450-B
and optocoupler TS7482. The shape of this signal determines the various geometric
correction parameters:

z

H amplitude

z

EW-parabola

z

EW-corner

z

EW-trapezium

z

Horizontal parallelogram

z

Horizontal bow

TS7480 will charge capacitor C2421 more or less, increasing the deflection current when
reaching the center of the screen.
The moment TS7480 is driven into saturation, C2421 will discharge during the flyback. As a
consequence of this, C2421 must be charged again during the scan via the conduction
diode D6422 (as long as C2421 is not charged to the voltage across L5422, D6422 will
conduct).
The current in the deflection coil is therefore larger than the current flowing in L5422 (1-2).
The voltage across the deflection coil increases, so the picture width increases. When
TS7480 blocks, C2421 will not discharge anymore, and the voltage across C2421 will
remain constant.
The result is that the voltage across the deflection coil is minimal. The voltage across coil
L5422, however, is maximal. This coil (L5422) consists of a transformer with the following
properties:
As the current through the coil 1-2 increases (smaller picture width), the current through coil
3-4 decreases. Because of the transformer characteristic a higher voltage will be subjected
to coil 3-4, which will counteract the current. The current will diminish even further.
When the current through coil 1-2 diminishes (larger picture width), the current through coil
3-4 increases.

Beam-current Correction

The 'EHT-info' signal at point 10 of the LOT depends on the value of the beam-current and
the voltage from divider R3450, R3451, and C2450. This signal is fed to the HOP to trim the
contrast, and to compensate for the changes in picture-width as a function of the EHT-info,
when EHT is decreased.
The 'EHT-info' is also used to correct the EW-current.

The 'DYN-FASE-CORR' signal, derived from the 'EHT-info' signal, is fed to the HOP via
C2455 (see diagram A8) and drives a dynamic phase correction necessary because of
beam-current variations. Regulating T

of the line transistor TS7421 does this.

ON

Secondary Line Voltages

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During the blocking time of TS7421, the magnetic energy of coil 1-5 of the LOT is
transferred to electrical energy in the secondary winding. Via rectifying and smoothing,
several secondary supply voltages are generated, such as:

z

EHT, Focus and Vg2-voltage

z

+200V for the CRT panel (pin 8 LOT)

z

+11D for the line deflection (pin 12 LOT)

z

+13V-LOT for the frame deflection (pin 6 LOT)

z

-15V-LOT for the frame deflection (pin 3 LOT)

z

Filament voltage (pin 9 LOT)

Vertical (Frame) Deflection (Diagram A4)

Frame Stage Drive

Figure: Frame deflection circuitry

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The HOP drives the frame output stage with a symmetrical saw-tooth voltage. Since the
HOP is 'cold' and the frame output stage is 'hot,' they are galvanically isolated. This is done
via a transformer (5621). The HOP generates three signals needed for the frame output
stage: FRAMEDRIVE+, FRAMEDRIVE- and TILT (for rotation).
The rotation circuit is kept on the 'cold' side of the chassis, to avoid the cost of an extra
optocoupler.
The circuit around IC7440 will amplify the frame drive signals and the vertical deflection
current will flow through the vertical deflection coil via the output stage IC7620.

Flyback Generator

The frame output stage is supplied via the +13 V and -15 V coming from the LOT. The
output of the amplifier is 0 V

During the (forward) scan, a supply of +13 V and -15 V is sufficient to respond to the slowly
changing current. The internal flyback generator puts a voltage of -15 V on pin 3. Because
of the voltage drop over zener diode D6622 (8.2 V), C2622 will be charged to 19 V: 13 +
(15 - 8.2 - 0.7) V.
During the flyback scan, the change in current-per-time is much larger, so a higher voltage
is required. The flyback generator will now generate a voltage of +13 V on pin 3. Added to
the charge on C2622 this will give a flyback voltage of 32 V (depending on the CRT size,
this value can differ).

The amplifier IC (IC7620, pin 5) supplies the saw-tooth current to the frame deflection coil.
The current through this coil is measured via R3620//R3621//R3622 and fed back to the
inverting input of the amplifier.
R3624 and C2624 on the output of the amplifier form a filter for high frequencies, and, in
this way, prevent oscillations.
Peak voltages on the output, as a result of a possible flash, for example, are damped by the
clamp circuit consisting of D6619, C2627, and R3627. The network consisting of R3625,
R3626, R3629, and C2629 forms an extra damping circuit.

, so a coupling capacitor is not required.

DC

Protection circuits

Bridge Coil Protection (see Diagram A3)

The secondary voltage of the bridge coil L5422 is guarded at the diode modulator
(D6421/6422) via a 10 V zener diode (6499 on diagram A4). When the bridge-coil is
working properly, the average voltage on D6422 is such that this zener diode will conduct. It
will drive TS7652 into saturation.
When, for any reason, the secondary side of the bridge coil is shorted, the average voltage
on D6422 will drop below the zener-voltage, and TS7652 will block. Now capacitor C2642
is charged. Transistor TS7443 starts conducting and the SUP-ENABLE signal is grounded
via R3403. This will switch 'off' the main supply (see diagram A1).

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Frame Output Protection

The frame output stage is guarded by the circuit built around TS7641. If the frame output
stage is working properly, TS7641 and TS7652 will both conduct, and thereby discharge
C2642. TS7443 is blocked, so the SUP-ENABLE signal is 'high.'
If there are frame pulses missing, TS7641 will block and capacitor C2642 is charged.
Transistor TS7443 starts conducting and the SUP-ENABLE signal is grounded via R3403.
This will switch 'off' the main supply (see diagram A1).

ARC Protection

If there are 'open' connections (for example, bad solder joints) in the high-energy deflection
circuitry, this can lead to damaging effects (fire). For that reason, the E/W current is sensed
(via 3479//3480). If this current becomes too high, the 'thyristor' circuit (TS7653 and
TS7654) is triggered. TS7442 is switched 'on' and TS7443 is forced into conduction. The
'SUP-ENABLE' signal is now shorted to ground level, which will force the Main Power
Supply into Standby mode.

Audio (Diagram B6, B10, and A6)

The EM1.2U chassis contains ITT's Multi-standard Sound Processing (MSP IC, type
MSP34xx) for sound decoding.
This IC takes care of the main FM sound decoding. All MSP versions contain digital audio
processing used for the basic left/right stereo sound, such as bass, treble, balance,
incredible sound, and spatial. In addition to that, the MSP3451 is also able to perform
'Virtual Dolby;' a Dolby approved sound mode for surround sound reproduction with
left/right speakers only.
The MSP3451 is capable of supporting four stereo inputs. Therefore, an extra input selector
(HEF4052) is not needed. It has a separate headphone output, so sound control can be
performed separately from the speakers.

Inputs / Outputs

Inputs: The MSP can cover four stereo inputs and one mono input.
Outputs: CVBS/decoder out, record select/WYSIWYR (What You See Is What You
Record), and headphone.

Audio Decoding

The incoming signal is fed to the AGC. After this, an ADC converts the IF-signal to a digital
signal.
Two demodulation channels process this digital signal. The first one is able to handle FM.
This channel contains a mixer to shift the incoming signal in the frequency domain. This
shift is determined by the value of a DCO (Digital Controlled Oscillator).

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After the down-mix, the signal is fed, via a filter, to a discriminator. From here the FM
(BTSC) demodulation can be performed.
Both channels contain an 'automatic carrier mute' function, which automatically mutes the
output of the analog section when no carrier is detected.

After demodulation, the FM-signals are subjected to a deemphasis operation. After that, the
matrix of the stereo system is applied.

Explanation of BTSC Stereo system (USA)

The standard for TV stereo audio in the USA was set by the Broadcast Television Systems
Committee (BTSC). The BTSC system was designed to:

z

Be compatible with then current monaural TV receivers,

z

Present good stereo separation and signal to noise ratio,

z

Make a Second Audio Program available as a separate audio channel,

z

Provide a technical voice/data channel to communicate within the TV stations system.

In a transmitted TV signal in the USA, the FM Audio signal is placed 4.5 MHz above the AM
Video Carrier. The audio FM has a nominal deviation of +/-50 kHz. With the BTSC system
this signal separation and FM deviation is maintained.

Figure: BTSC signal spectrum

The figure above shows the detected base band audio signal spectrum. The 'L+R' signal
maintains compatibility with the original (and current) monaural receivers. With Double
Sideband Suppressed Carrier (DSSC) for the 'L-R' signal, there is a need for an exact re­insertion of the missing carrier. This is to assure good detection in the receiver. This is the
main purpose of the pilot carrier at 1f H (15.743 kHz). It also serves to alert the TV set (and

the customer) to the fact that the signal is in stereo. As the pilot is at the exact horizontal
scan frequency, this can lead to false indication from such sources as VCRs, Signal
Amplifiers, etc., where both sound and video are present with RF energy.

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The figure also shows the Second Audio Program (SAP) frequency, which is a constant
carrier of an audio tone of 5fH (78.670 kHz), FM modulated by the SAP program content.
SAP is always monaural.
The material on the SAP audio may, in some cases, not be related to the video content.
Alternatively, it may contain a verbal description of the action in the video for those who
cannot view the picture.
Some stations use it to transmit background music or book reading for the blind.

Figure: Audio decoder block diagram

In the figure above, a simplified block diagram of a stereo sound system in a TV set shows
the 'L+R' audio signal combined with the detected 'L-R' audio signal to develop stereo 'L'
and 'R' audio.
The 'pilot' signal is doubled in frequency (to 2fH) and re-inserted into the detection of the 'L­R'. This completes the detection.
The pilot signal also tells the control circuit when a pilot frequency is present. The 'L-R' and
'L+R' audio are supplied to the stereo matrix. There, by addition and subtraction, the single
'R' and 'L' audio signals are output. The SAP audio is detected and made available. In
addition, the indication of a SAP signal is given to the control circuit.

Audio Processing

The sound processing is performed completely by the MSP:

z

Volume control is performed by the user via the 'SOUND' menu.

z

Tone control in 'Stereo' sets is performed via the 'BASS/TREBLE' control.

z

Headphone control: the MSP has a separate Headphone output so separate sound
control is possible.

Automatic Volume Leveling (AVL)

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One of the features of the MSP-family is Automatic Volume Leveling (AVL). If used, AVL
limits large volume differences in the broadcast between television programs and
commercials, or within a movie.
To be able to get a Dolby approval (for the Virtual Dolby sets), the AVL feature must be
switchable. Therefore, the AVL feature is customer switchable via the menu.

Audio Amplifier (Diagram A6)

The audio amplifier part is very straightforward. It uses an integrated class B power
amplifiers (TDA7497). It delivers an output of 2 x 10WRMS to two full range speakers
and/or subwoofer.
The supply voltage is +35 V, generated by the main supply via L5506.
Muting is done via the 'SOUND-ENABLE' line connected to pin 9 of the amplifier IC and
coming from the Painter. This signal is inverted by TS7730, as a result of which at a high
level of the 'SOUND-ENABLE' signal, current is sinked from pin 9, and the IC mutes.

Headphone Amplifier (Diagram B10)

The headphone amplifier is a straightforward OpAmp amplifier (IC7681, NJM4556). It is
supplied with +8 V.

CRT Panel / Rotation / Scavem (diagram F)

RGB Amplifiers

The integrated RGB amplifier (TDA6108, IC7307) is located on the CRT panel. The
cathodes of the picture tube are driven by the outputs 9, 8, and 7.

Rotation (Diagram A5)

In sets with a rotation coil (wide screen sets), the amount of frame rotation is adjusted with
the 'TILT' DAC-output of the HOP pin 25 (see 'Vertical Deflection').

Scavem

The Scavem-circuitry is implemented in the layout of the picture tube panel. It is thus not an
extra module. Scavem means SCAn VElocity Modulation. This means that the picture
content influences the horizontal deflection. In an ideal square wave, the sides are limited in
slope by a limited bandwidth (5 MHz).
Scavem will improve the slope as follows: At a positive slope, a Scavem-current is
generated, which supports the deflection current. During the first half of the slope, the spot
is accelerated and the picture is darker, while at the second half of the slope, the spot is
delayed and the slope becomes steeper.
At the end of the slope, the Scavem-current decays to zero, and the spot is at the original

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position. An overshoot occurs which improves the impression of sharpness. At the negative
slope, the Scavem-current counteracts the deflection.

The Y-Scavem signal comes from diagram B4 and is the input-signal for the Scavem­circuitry on the CRT-panel (it enters the CRT-panel on pin 5 of connector 1940). The Y­Scavem circuitry has: a RGB (2fH) input via the AV4-input, or a CVBS input for the other
signal sources.
Via TS7300 this signal is fed to emitter follower TS7304.The signal is conveyed to the
differentiator C2330, R3324, and R3318. Only the high frequencies are differentiated (small
RC-time).
The positive and negative pulses of this signal drive TS7309/7303 and TS7310/7302,
respectively, into conductivity. The DC setting of the output stage is set by R3421, R3423,
R3424, and R3426. The working voltage of the transistors is settled at half the supply
voltage.
At the positive section of the pulse, the current flows through R3318, C2307, the Scavem­coil, and TS7309/7303. At the negative section of the pulse, the current flows through
R3318, C2409, the Scavem-coil, and TS7310/7302.

Software Related Features

The following features are described:

z

Auto TV

z

'Switch On' Behavior

AutoTV

The AutoTV (or 'Automatic Picture Control' or 'Active Control') aims at giving the customer
the best possible picture performance at any time. It is a collection of algorithms that control
the image processing parameters, depending on the picture properties retrieved from
meters or information in the main software.

The following sub-systems are defined for AutoTV. They are present or absent according to
the hardware configuration of the set.

z

Auto Noise Reduction. This algorithm measures the amount of noise in the incoming
video signal (this is done by the LIMERIC part of the PICNIC). As a result of this
measurement, the amount of noise in the picture is corrected, starting from the noise
level that is unpleasant to the customer. Which parameters can be used depends on
the hardware.

z

Auto Sharpness. This algorithm measures the amount of sharpness via the bandwidth
of the incoming video signal and adapts the peaking frequency in the PICNIC
according to this info. If the 'sharpness meter' sees the video content as 'sharp,' high
frequency peaking will be used. If the picture content is seen as 'not sharp,' a low/mid

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frequency peaking is used.

Notes:

z

There is a coupling between the Auto Noise and the Auto Sharpness algorithm: if
noise is present in the video content, then in general the sharpness will be made less
aggressive. Special care has to be taken to the interaction of the LIMERIC and the
vertical peaking of the PICNIC: an overly large amount of vertical peaking increases
the visibility of the 2DNR artifacts.

z

Most algorithms are located in the embedded processor of the PICNIC, because of
time-critical calculations, and because most picture analyzing and correction circuits
are present in the PICNIC. Some parts of the algorithms are located in the main

software, because the outcome needs to be sent to other I

2

C devices.

'Switch On' Behavior

This is the start up sequence:

1. After the power is applied, the 'Standby supply' starts oscillating, generating the +5V2
(and +3V3). A reset (POR) is generated and the Painter is awakened.

2. Next step is the check whether the set needs to be in 'Standby' mode or not.
Therefore, the NVM content is read and the Standby-bit is checked. If the set is to
stay in Standby, there is no further action.

3. If the set switches 'on', first the degaussing will be activated (12 seconds).

4. Meanwhile the MSP is reset and the Standby line is pulled low, leading to a full semi
standby mode (5 V and 8V switched on).

5. The Painter waits until the +5V and the +8 V are fully present. Checking the AD-input

of the Painter does this. The +5V, +8V, and I 2 C protection-algorithms are activated.

6. The HOP is instructed via the I 2 C-bus to start the drive.

7. The main supply is activated via the SUP-ENABLE signal. The Line Deflection
circuitry is now supplied with the V

, and the EHT generation can start.

BAT

8. During start-up of the deflection, I 2C traffic must be disabled for 250 ms to avoid data

corruption. If flashes or spikes are generated during EHT start-up, I

2

C data could be

disturbed or corrupted.

9. After deflection is powered up completely, all the other protection-algorithms are
activated.

10. The black current stabilization loop in the HOP is switched on. Some extra checking is
done to ensure that the loops are completely stabilized.

11. The Painter sets all the necessary parameters for correct sound and image and
unblanks the picture.

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Abbreviation list

Abbreviation Description

2DNR

3DNR

AARA

ACI

ADC

AFC

AGC

AM

ANR

Spatial (2D) Noise Reduction

Temporal (3D) Noise Reduction

Automatic Aspect Ratio Adaptation: algorithm that adapts
aspect ratio to remove horizontal black bars; keeps the
original aspect ratio

Automatic Channel Installation: algorithm that installs TV
channels directly from a cable network by means of a
predefined TXT page

Analog to Digital Converter

Automatic Frequency Control: control signal used to tune
to the correct frequency

Automatic Gain Control: algorithm that controls the video
input of the feature box

Amplitude Modulation

Automatic Noise Reduction: one of the algorithms of Auto
TV

AR

ASF

ATV

AUDIO_C

AUDIO_L

AUDIO_R

AUDIO_SL

AUDIO-SR

AUDIO_SW

Auto TV

Aspect Ratio: 4 by 3 or 16 by 9

Auto Screen Fit: algorithm that adapts aspect ratio to
remove horizontal black bars without discarding video
information

See Auto TV

AUDIO Center

AUDIO Left

AUDIO Right

AUDIO Surround Left

AUDIO Surround Right

AUDIO SubWoofer

A hardware and software control system that measures
picture content, and adapts image parameters in a
dynamic way

BC-PROT

BG

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PROTection signal to the μP for a too high Beam Current.

System B and G

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BLC-INFO

B-SC1-IN

B-SC2-IN

B-TXT

CBA

CC

CL

ComPair

CRT

CSM

CTI

BLack Current INFO

Blue SCART1 IN

Blue SCART2 IN

Blue TeleteXT

Circuit Board Assembly (PCB)

Closed Caption

Constant Level: audio output to connect with an external
amplifier

Computer aided rePair

Cathode Ray Tube or picture tube

Customer Service Mode

Color Transient Improvement: manipulates steepness of
chroma transients

CVBS

CVBS-TER

DAC

DBE

DC-filament

DFU

DNR

DSP

DST

DVD

DYN-FASE-COR

Composite Video Blanking and Synchronization

CVBS TERrestrial

Digital to Analog Converter

Dynamic Bass Enhancement: extra low frequency
amplification

Filament supply voltage

Directions For Use: owner's manual

Digital Noise Reduction: noise reduction feature of the set

Digital Signal Processing

Dealer Service Tool: special remote control designed for
service technicians

Digital Video Disc

DYNamic phASE CORrection: corrects the phase of the
H-drive

EHT

EHT-INFO

EW

EW-DRIVE

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Extra High Tension

Extra High Tension INFOrmation, used for contrast
reduction, vertical and horizontal amplitude correction,
beam current protection, and flash detection.

East West, related to horizontal deflection of the set

The drive signal for the EW transistor

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EXT

FBL

FBL-PIP

FBL-TXT

FBSCO

FBX

FDS

FILAMENT

FLASH

EXTernal (source), entering the set by SCART or by
cinches (jacks)

Fast BLanking: DC signal accompanying RGB signals

The Fast BLanking signal for PIP

The Fast BLanking signal for TXT. It has a higher priority
than FBL-PIP

Fixed Beam Current Switch Off, a 140 V dip detection to
activate the black switch off circuit

Feature BoX: part of the small signal board /separate
module which contains 100 Hz processing, extra features
and AutoTV algorithms (FBX6= based on PICNIC, FBX7=
based on PICNIC and Eagle)

Full Dual Screen

Filament of CRT

FLASH memory

FM

G-TXT

GND-DRIVE

HA50

HD100

HD@HOME

HFB

HIP

HOP

Field Memory or Frequency Modulation

Green TeleteXT

A separate ground for the line-drive toward the line driver

Horizontal Acquisition 1fh: horizontal sync pulse coming
out of the HIP

Horizontal Drive 2fH: horizontal sync pulse coming out of
the feature-box

A signal from the Painter, to switch the HOP to the Pixel
Plus standard (60 Hz frame)

Horizontal Flyback Pulse: horizontal sync pulse from
large signal deflection

High-end video Input Processor (TDA9320): video and
chroma decoder.

High-end video Output Processor (TDA9330): video,
sync, and geometry controller

HP

Interlaced

Last Status

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HeadPhone

Scan mode where two fields are used to form one frame.
Each field contains half the number of the total amount of
lines. The fields are written in 'pairs,' causing line flicker

The settings last chosen by the customer and read and

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stored in RAM or in the NVM. They are called at start-up
of the set to configure it according to the customer's
preferences

LDP

LED

LINE-DRIVE

LNA

LSP

MSP

MUTE

NC

NVM

O/C

ON/OFF_LED

Line Deflection Protection signal, derived from the EW
current and voltage

Light Emitting Diode

LINE DRIVE signal (for the Line transistor)

Low Noise Adapter

Large Signal Panel

Multi-standard Sound Processor: ITT sound decoder

MUTE Line

Not Connected

Non Volatile Memory: IC containing TV related data such
as alignments

Open Circuit

ON/OFF control signal for the LED

OSD

OTC

P50

PCB

PICNIC

PIP

Progressive Scan

PTP

RAM

On Screen Display

On screen display Teletext and Control; also called
Artistic (SAA5800)

Project 50 communication: protocol between TV and
peripherals

Printed Circuit Board

Peripheral Integrated Combined Network IC (SAA4978):
main IC for 100 Hz features and feature processing

Picture In Picture

Scan mode where all scan lines are displayed in one
frame at the same time, creating double vertical
resolution.

Picture Tube Panel

Random Access Memory

R-TXT

RC

RC5

RESET

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Red TeleteXT

Remote Control

Signal protocol from the remote control receiver

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RESET signal

RGB-PIP

RGB-TXT

RGB-VC

ROM

SAM

SC

S/C

SCAVEM

SCL-F

SD

SDA-F

SIF

SIMM

RGB-input for PIP

RGB-input for TeleteXT and OSD

RGB-input to the Picture Tube Panel

Read Only Memory

Service Alignment Mode

SandCastle: two-level pulse derived from sync signals

Short Circuit

SCAn VElocity Modulation

CLock Signal on Fast I2C bus

Standard Definition

DAta Signal on Fast I2C bus

Sound Intermediate Frequency

80-fold connector between LSP and SSB

SNERT

SSB

STBY

SW

TXT

uP

U100

V100

VA50

VBAT

VD100

VDPOS

Synchronous No parity Eight bit Reception and Transmit

Small Signal Board

STandBY

SubWoofer

TeleteXT

MicroProcessor

U from Feature Box

V from Feature Box

Vertical Acquisition 1fH

Main supply for deflection (usually 141 V)

Vertical Drive 2fH: vertical sync pulse from deflection

One of the symmetrical drive signals for the DC frame
output stage.

VDNEG

VFB

VL

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One of the symmetrical drive signals for the DC frame
output stage.

Vertical Flyback Pulse: vertical sync pulse coming from
the feature box

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Variable Level out: processed audio output toward
external amplifier

WYSIWYR

X-RAY-PROT

XTAL

Y100

Y-OUT

YUV-Feat

What You See Is What You Record: record selection that
follows main picture and sound

A PROTection signal against excessive X-RAY radiation

Quartz crystal

Y from Feature Box

Luminance-signal to HOP IC

The YUV input for the main picture, coming from the
Feature box or the HIP

IC Data Sheets

This section shows the internal block diagrams and pin layouts of ICs that are drawn as
'black boxes' in the electrical diagrams (with the exception of 'memory' and 'logic' ICs).

Diagram B7, SAA5667HL (IC7001)

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Figure: Diagram and Pin Layout 'Painter'

Diagram CO, μPD64083 (IC7015)

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Figure: Internal Block Diagram and Pin Layout '3D Comb filter'

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