MOTOROLA MC10EP33D, MC10EP33DR2 Datasheet
MC10EP33
B
4 Divider
The MC10EP33 is an integrated B4 divider. The differential clock
inputs and the VBB allow a differential, single–ended or AC coupled
interface to the device. If used, the VBB output should be bypassed to
ground with a 0.01µF capacitor.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power–up, the internal flip–flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
• 320ps Propagation Delay
• 3 GHz T ypical Toggle Frequency
• PECL mode: 3.0V to 5.5V V
• ECL mode: 0V V
with VEE = –3.0V to –5.5V
CC
• Internal Input Resistors: Pulldown on D, D
• Q Output will default LOW with inputs open or at V
• ESD Protection: >4KV HBM, >200V MM
• V
BB
Output
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 91 devices
CLK
1
2
3
RESET
with VEE = 0V
CC
R
B
4
EE
78Q
6
V
CC
QCLK
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1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
HEP33
ALYW
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
CLK, CLK
Reset ECL Asynchronous Reset
V
BB
Q, Q ECL Data Outputs
V
CC
V
EE
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
FUNCTION
ECL Clock Inputs
Reference Voltage Output
Positive Supply
Negative, 0 Supply
V
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 1
45
BB
V
EE
CLK
X
Z
Z = LOW to HIGH Transition
Z
= HIGH to LOW Transition
F = Divide by 4 Function
Device Package Shipping
MC10EP33D SOIC 98 Units/Rail
MC10EP33DR2 SOIC 2500 Tape & Reel
1 Publication Order Number:
TRUTH TABLE
CLK
ORDERING INFORMATION
RESET
X
Z
Z
L
Q
L
F
Q
H
F
MC10EP33/D
MC10EP33
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
EE
V
CC
V
I
V
I
I
out
I
BB
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
{
Use for inputs of same package only.
Power Supply (VCC = 0V) –6.0 to 0 VDC
Power Supply (VEE = 0V) 6.0 to 0 VDC
Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC
Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC
Output Current Continuous
VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Thermal Resistance (Junction–to–Ambient) Still Air
Thermal Resistance (Junction–to–Case) 41 to 44 ± 5% °C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
CLK
{
t
RR
Surge
500lfpm
50
100
± 0.5 mA
190
130
mA
°C/W
RESET
Q
Figure 2. Timing Diagram
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MC10EP33
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –5.5V to –3.0V) (Note 4.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC–2.0 volts.
3. V
4. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 1.)
Output HIGH Voltage
(Note 2.)
Output LOW Voltage
(Note 2.)
Input HIGH Voltage
Single Ended
Input LOW Voltage
Single Ended
Output Voltage Reference –1510 –1410 –1310 –1445 –1345 –1245 –1385 –1285 –1 185 mV
Input HIGH Voltage Common Mode
Range (Note 3.)
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with VEE, max varies 1:1 with VCC.
IHCMR
EEmin
to V
CLK
, all other pins floating.
EEmax
18 26 34 18 26 34 18 26 34 mA
–1135 –1060 –885 –1070 –945 –820 –1010 –885 –760 mV
–1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV
–1210 –885 –1145 –820 –1085 –760 mV
–1935 –1610 –1870 –1545 –1810 –1485 mV
VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
0.5
–150
0.5
–150
0.5
–150
µA
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 8.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
5. VCC = 3.3V, VEE = 0V, all other pins floating.
6. All loading with 50 ohms to VCC–2.0 volts.
7. V
8. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 5.)
Output HIGH Voltage
(Note 6.)
Output LOW Voltage
(Note 6.)
Input HIGH Voltage
Single Ended
Input LOW Voltage
Single Ended
Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 21 15 mV
Input HIGH Voltage Common Mode
Range (Note 7.)
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with VEE, max varies 1:1 with VCC.
IHCMR
CLK
18 26 34 18 26 34 18 26 34 mA
2165 2240 2415 2230 2355 2480 2290 2415 2540 mV
1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
2090 2415 2155 2480 2215 2540 mV
1365 1690 1430 1755 1490 1815 mV
2.0 3.3 2.0 3.3 2.0 3.3 V
0.5
–150
0.5
–150
0.5
–150
µA
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