MOTOROLA HC05J5AGRS, HC05J5AGRH User Manual

68HC05J5A

HC05J5AGRS/H REV 2.1

68HC05J5A

68HRC05J5A

68HC705J5A

68HRC705J5A

SPECIFICATION

(General Release)

July 16, 1999

Semiconductor Products Sector

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola, Inc., 1999

				July 16, 1999	GENERAL RELEASE SPECIFICATION
				TABLE OF CONTENTS
Section						Page
				SECTION 1
				GENERAL DESCRIPTION
1.1	FEATURES ......................................................................................................					1-1
1.2	MASK OPTIONS..............................................................................................					1-2
1.3	MCU STRUCTURE..........................................................................................					1-2
1.4	PIN ASSIGNMENTS ........................................................................................					1-4
1.5	FUNCTIONAL PIN DESCRIPTION..................................................................					1-4
1.5.1		VDD AND VSS ..............................................................................................				1-4
1.5.2		OSC1, OSC2/R............................................................................................				1-4
1.5.3						1-6
		RESET
1.5.4		IRQ	................................................(MASKABLE INTERRUPT REQUEST)			1-6
1.5.5		PA0-PA7 ......................................................................................................				1-6
1.5.6		PB0-PB5 ......................................................................................................				1-7
				SECTION 2
				MEMORY
2.1	I/O AND CONTROL REGISTERS ...................................................................					2-2
2.2	RAM .................................................................................................................					2-2
2.3	ROM.................................................................................................................					2-2
2.4	I/O REGISTERS SUMMARY ...........................................................................					2-3
				SECTION 3
				CENTRAL PROCESSING UNIT
3.1	REGISTERS ....................................................................................................					3-1
3.2	ACCUMULATOR (A)........................................................................................					3-2
3.3	INDEX REGISTER (X) .....................................................................................					3-2
3.4	STACK POINTER (SP) ....................................................................................					3-2
3.5	PROGRAM COUNTER (PC) ...........................................................................					3-2
3.6	CONDITION CODE REGISTER (CCR) ...........................................................					3-3
3.6.1 Half Carry Bit (H-Bit) ....................................................................................						3-3
3.6.2		Interrupt Mask (I-Bit) ....................................................................................				3-3
3.6.3		Negative Bit (N-Bit) ......................................................................................				3-3
3.6.4		Zero Bit (Z-Bit) .............................................................................................				3-3
3.6.5		Carry/Borrow Bit (C-Bit) ...............................................................................				3-4
				SECTION 4
				INTERRUPTS
4.1	CPU INTERRUPT PROCESSING ...................................................................					4-1
4.2	RESET INTERRUPT SEQUENCE ..................................................................					4-2
4.3	SOFTWARE INTERRUPT (SWI) .....................................................................					4-3
4.4	HARDWARE INTERRUPTS ............................................................................					4-3
4.5	EXTERNAL INTERRUPT (IRQ).......................................................................					4-3
4.5.1 IRQ CONTROL/STATUS REGISTER (ICSR) $0A......................................						4-5

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Section				Page
4.5.2 OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) ....................................				4-6
4.5.3		TIMER INTERRUPT (MFT) .........................................................................		4-7
4.5.4 TIMER1 INTERRUPT (16-BIT TIMER)........................................................				4-7
			SECTION 5
			RESETS
5.1		EXTERNAL RESET (RESET)..........................................................................		5-2
5.2		INTERNAL RESETS ........................................................................................		5-2
5.2.1		POWER-ON RESET (POR) ........................................................................		5-2
5.2.2 COMPUTER OPERATING PROPERLY RESET (COPR)...........................				5-2
5.2.3 LOW VOLTAGE RESET (LVR) ...................................................................				5-3
5.2.4 ILLEGAL ADDRESS RESET (ILADR).........................................................				5-3
			SECTION 6
		LOW POWER MODES
6.1		STOP INSTRUCTION......................................................................................		6-2
6.1.1		STOP Mode .................................................................................................		6-3
6.1.2		HALT Mode..................................................................................................		6-3
6.2		WAIT INSTRUCTION.......................................................................................		6-4
6.3		DATA-RETENTION MODE..............................................................................		6-4
6.4	COP WATCHDOG TIMER CONSIDERATIONS .............................................			6-4
			SECTION 7
		INPUT/OUTPUT PORTS
7.1	SLOW OUTPUT FALLING-EDGE TRANSITION.............................................			7-1
7.2		PORT A............................................................................................................		7-1
7.2.1 Port A Data Register....................................................................................				7-2
7.2.2 Port A Data Direction Register.....................................................................				7-2
7.2.3 Port A Pulldown/up Register........................................................................				7-3
7.2.4 Port A Drive Capability.................................................................................				7-3
7.2.5 Port A I/O Pin Interrupts...............................................................................				7-3
7.3		PORT B............................................................................................................		7-4
7.3.1 Port B Data Register....................................................................................				7-4
7.3.2 Port B Data Direction Register.....................................................................				7-5
7.3.3 Port B Pulldown/up Register........................................................................				7-5
7.4		I/O PORT PROGRAMMING ............................................................................		7-6
7.4.1		Pin Data Direction........................................................................................		7-6
7.4.2		Output Pin....................................................................................................		7-6
7.4.3		Input Pin.......................................................................................................		7-6
7.4.4		I/O Pin Transitions .......................................................................................		7-7
7.4.5 I/O Pin Truth Tables.....................................................................................				7-7

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		TABLE OF CONTENTS
Section				Page
		SECTION 8
		MULTI-FUNCTION TIMER
8.1	OVERVIEW......................................................................................................			8-2
8.2	COMPUTER OPERATING PROPERLY (COP) WATCHDOG			........................ 8-2
8.3	MFT REGISTERS ............................................................................................			8-2
8.3.1		Timer Counter Register (TCR) $09..............................................................		8-3
8.3.2		Timer Control/Status Register (TCSR) $08 .................................................		8-3
8.4	OPERATION DURING STOP MODE ..............................................................			8-5
8.5	OPERATION DURING WAIT/HALT MODE.....................................................			8-5
		SECTION 9
		16-BIT TIMER
9.1	TIMER1 COUNTER REGISTERS (TCNTH, TCNTL) ......................................			9-2
9.2	ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)..............................			9-3
9.3	INPUT CAPTURE REGISTERS ......................................................................			9-5
9.4	TIMER1 CONTROL REGISTER (T1CR) .........................................................			9-8
9.5	TIMER1 STATUS REGISTER (T1SR).............................................................			9-9
9.6	TIMER1 OPERATION DURING WAIT MODE.................................................			9-9
9.7	TIMER1 OPERATION DURING STOP MODE ................................................			9-9
		SECTION 10
		INSTRUCTION SET
10.1	ADDRESSING MODES .................................................................................			10-1
10.1.1		Inherent......................................................................................................		10-1
10.1.2		Immediate ..................................................................................................		10-1
10.1.3		Direct .........................................................................................................		10-2
10.1.4		Extended....................................................................................................		10-2
10.1.5		Indexed, No Offset.....................................................................................		10-2
10.1.6		Indexed, 8-Bit Offset ..................................................................................		10-2
10.1.7		Indexed, 16-Bit Offset ................................................................................		10-3
10.1.8		Relative......................................................................................................		10-3
10.1.9		Instruction Types .......................................................................................		10-3
10.1.10		Register/Memory Instructions ....................................................................		10-4
10.1.11		Read-Modify-Write Instructions .................................................................		10-5
10.1.12		Jump/Branch Instructions ..........................................................................		10-5
10.1.13		Bit Manipulation Instructions......................................................................		10-7
10.1.14		Control Instructions....................................................................................		10-7
10.1.15		Instruction Set Summary ...........................................................................		10-8

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	TABLE OF CONTENTS
Section			Page
		SECTION 11
	ELECTRICAL SPECIFICATIONS
11.1	MAXIMUM RATINGS.....................................................................................		11-1
11.2	THERMAL CHARACTERISTICS ...................................................................		11-1
11.3	FUNCTIONAL OPERATING RANGE ............................................................		11-1
11.4	DC ELECTRICAL CHARACTERISTICS........................................................		11-2
11.5	CONTROL TIMING ........................................................................................		11-5
		SECTION 12
	MECHANICAL SPECIFICATIONS
12.1	16-PIN PDIP (CASE #648) ............................................................................		12-1
12.2	16-PIN SOIC (CASE #751G) .........................................................................		12-1
12.3	20-PIN PDIP (CASE #738) ............................................................................		12-2
12.4	20-PIN SOIC (CASE #751D) .........................................................................		12-2
		APPENDIX A
		MC68HRC05J5A
A.1	INTRODUCTION..............................................................................................		A-1
A.2	RC OSCILLATOR CONNECTIONS.................................................................		A-1
A.3	ELECTRICAL CHARACTERISTICS ................................................................		A-2
		APPENDIX B
		MC68HC705J5A
B.1	INTRODUCTION..............................................................................................		B-1
B.2	MEMORY .........................................................................................................		B-1
B.3	MASK OPTION REGISTERS (MOR)...............................................................		B-1
B.4	BOOTSTRAP MODE .......................................................................................		B-4
B.5	EPROM PROGRAMMING ...............................................................................		B-4
B.5.1 EPROM Program Control Register (PCR)...................................................			B-4
B.5.2	Programming Sequence ..............................................................................		B-5
B.6	ELECTRICAL CHARACTERISTICS ................................................................		B-6
		APPENDIX C
		MC68HRC705J5A
C.1	INTRODUCTION..............................................................................................		C-1
C.2	RC OSCILLATOR CONNECTIONS.................................................................		C-1
C.3	ELECTRICAL CHARACTERISTICS ................................................................		C-2
		APPENDIX D
	ORDERING INFORMATION
D.1	MC ORDER NUMBERS...................................................................................		D-1

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	July 16, 1999		GENERAL RELEASE SPECIFICATION
	LIST OF FIGURES
Figure		Title		Page
1-1	MC68HC05J5A Block Diagram........................................................................			1-3
1-2	Pin Assignments for 16-Pin and 20-Pin Packages...........................................			1-4
1-3	Oscillator Connections .....................................................................................			1-5
2-1	MC68HC05J5A Memory Map ..........................................................................			2-1
2-2	I/O Registers Memory Map ..............................................................................			2-2
2-3	I/O Registers $0000-$000F..............................................................................			2-3
2-4	I/O Registers $0010-$001F..............................................................................			2-4
3-1	MC68HC05 Programming Model .....................................................................			3-1
4-1	Interrupt Processing Flowchart ........................................................................			4-2
4-2	IRQ Function Block Diagram............................................................................			4-3
4-3	IRQ Status & Control Register .........................................................................			4-5
5-1	Reset Block Diagram .......................................................................................			5-1
6-1	STOP/HALT/WAIT Flowcharts.........................................................................			6-2
7-1	Port B Data Direction Register .........................................................................			7-1
7-2	Port A I/O Circuitry ...........................................................................................			7-2
7-3	Port B I/O Circuitry ...........................................................................................			7-4
8-1	Multi-Function Timer Block Diagram ................................................................			8-1
8-2	COP Watchdog Timer Location .......................................................................			8-2
8-3	Timer Counter Register....................................................................................			8-3
8-4	Timer Control/Status Register (TCSR).............................................................			8-3
9-1	16-Bit Timer Block Diagram .............................................................................			9-1
9-2	16-Bit Timer Counter Block Diagram ...............................................................			9-2
9-3	16-Bit Timer Counter Registers (TCNTH, TCNTL) ..........................................			9-3
9-4	Alternate Counter Block Diagram.....................................................................			9-4
9-5	Alternate Counter Registers (ACNTH, ACNTL) ...............................................			9-4
9-6	Timer Input Capture Block Diagram.................................................................			9-5
9-7	Timer1 Capture Control Register .....................................................................			9-6
9-8	TCAP Input Signal Conditioning.......................................................................			9-6
9-9	TCAP Input Comparator Output.......................................................................			9-7
9-10	Input Capture Registers (ICH, ICL) ..................................................................			9-7
9-11	Timer Control Register (T1CR) ........................................................................			9-8
9-12	Timer Status Registers (T1SR) ........................................................................			9-9
12-1	16-Pin PDIP Mechanical Dimensions ............................................................			12-1
12-2	16-Pin SOIC Mechanical Dimensions ............................................................			12-1
12-3	20-Pin PDIP Mechanical Dimensions ............................................................			12-2
12-4	20-Pin SOIC Mechanical Dimensions ............................................................			12-2
A-1	RC Oscillator Connections ...............................................................................			A-1
A-2	Typical Internal Operating Frequency for RC Oscillator Connections..............			A-2
B-1	MC68HC705J5A Memory Map ........................................................................			B-3
B-2	EPROM Programming Sequence ....................................................................			B-5
C-1	RC Oscillator Connections ...............................................................................			C-1
C-2	Typical Internal Operating Frequency for RC Oscillator Connections..............			C-2

MC68HC05J5A	MOTOROLA
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	LIST OF FIGURES
Figure	Title	Page

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	LIST OF TABLES
Table	Title	Page
4-1	Vector Address for Interrupts and Reset..........................................................	4-1
6-1	COP Watchdog Timer Recommendations .......................................................	6-5
7-1	Port A I/O Pin Functions...................................................................................	7-7
7-2	Port B I/O Pin Functions...................................................................................	7-7
8-1	RTI Rates and COP Reset Times ....................................................................	8-5
10-1	Register/Memory Instructions ........................................................................	10-4
10-2	Read-Modify-Write Instructions .....................................................................	10-5
10-3	Jump and Branch Instructions........................................................................	10-6
10-4	Bit Manipulation Instructions ..........................................................................	10-7
10-5	Control Instructions ........................................................................................	10-7
10-6	Instruction Set Summary ...............................................................................	10-8
10-7	Opcode Map.................................................................................................	10-14
11-1	DC Electrical Characteristics, VDD=5 V ........................................................	11-2
11-2	DC Electrical Characteristics, VDD=2.2V .....................................................	11-3
11-3	Control Timing, VDD=5V...............................................................................	11-5
11-4	Control Timing, VDD=2.2V............................................................................	11-5
A-1	Functional Operating Range ............................................................................	A-2
A-2	DC Electrical Characteristics, VDD=5V...........................................................	A-2
B-1	Functional Operating Range ............................................................................	B-6
B-2	EPROM Programming Electrical Characteristics .............................................	B-6
B-3	DC Electrical Characteristics, VDD=5 V ..........................................................	B-6
C-1	Functional Operating Range ............................................................................	C-2
C-2	DC Electrical Characteristics, VDD=5 V ..........................................................	C-2
D-1	MC Order Numbers..........................................................................................	D-1

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	LIST OF TABLES
Table	Title	Page

MOTOROLA	MC68HC05J5A
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July 16, 1999 GENERAL RELEASE SPECIFICATION

SECTION 1

GENERAL DESCRIPTION

The MC68HC05J5A is a member of the low-cost high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit design strategy. All MCUs in the family use the popular M68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types.

The MC68HC05J5A is an enhanced version of the MC68HC05J5, with expanded

RAM, ROM sizes, and an additional 16-bit timer with TCAP. This MCU is available in 20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages. The 16-pin version has four less I/O lines.

Three variation on the MC68HC05J5A device are available; a summary of their differences are listed in the following table:

DEVICE	ROM TYPE	OSCILLATOR OPTION	REFERENCE
MC68HC05J5A	2560 bytes ROM	Crystal/resonator or external clock oscillator	—
MC68HRC05J5A	2560 bytes ROM	RC oscillator	Appendix A
MC68HC705J5A	2560 bytes EPROM	Crystal/resonator or external clock oscillator	Appendix B
MC68HRC705J5A	2560 bytes EPROM	RC oscillator	Appendix C

1.1FEATURES

The features of the MC68HC05J5A include the following:

•Industry standard M68HC05 CPU core

•Fully static operation with no minimum clock speed

•Power-saving STOP and WAIT modes

•Memory-Mapped Input/Output (I/O) registers

•2560 Bytes of user ROM with security feature

•128 Bytes of user RAM

•On-Chip Oscillator:

–Crystal/Resonator oscillator

–External clock oscillator

•15-Bit Multi-function Timer

•16-Bit Programmable Timer with Input Capture

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•14 Bidirectional I/O pins (10 I/O pins on 16-pin package)

–PA0-PA5, PB0, and PB3-PB5: with software programmable input pulldown devices

–PB1, PB2, PA6 and PA7: open-drained I/O pins with software programmable pull-up devices

–PA6, PA7, and PB1: with slow output falling transition feature

–PA7: with falling-edge interrupt capability

–PA0-PA3: with maskable rising-edge only or rising-edge and high level interrupt capability

–20-pin package: PB1 and PB2, each with 25mA current sink capability

–16-pin package: PB1 with 50mA current sink capability

•Computer Operation Properly (COP) Watchdog

•Low Voltage Reset Circuit

•Illegal Address Reset

•20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages

1.2MASK OPTIONS

The following mask options are available on the MC68HC05J5A:

MASK			OPTION
STOP instruction convert to WAIT			[Enabled] or [Disabled]
External interrupt pins		PA0-PA3)	[Edge-triggered] or [Edge and level triggered]
	(IRQ,
Port A and Port B pull-down/pull-up resistors			[Enabled] or [Disabled]
PA0-PA3 external interrupt capability			[Enabled] or [Disabled]
Oscillator Delay Option (internal clock cycles)			[224] or [4064]
Low Voltage Reset			[Enabled] or [Disabled]
COP Watchdog Timer			[Enabled] or [Disabled]

1.3MCU STRUCTURE

Figure 1-1 shows the structure of MC68HC05J5A MCU.

MOTOROLA	GENERAL DESCRIPTION	MC68HC05J5A
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July 16, 1999 GENERAL RELEASE SPECIFICATION

	PA0
	PA1
	PA2	PORT	DATA
	PA3
		A	DIR
	PA4	REG	REG
	PA5
	PA6
	PA7
	PB0
	PB1
	PB2	PORT	DATA
		B	DIR
	PB3
		REG	REG
	PB4
	PB5

: External edge interrupt capability

: 8 mA current sink

: Open-drained with internal pull-up and

8 mA current sink

: External interrupt capability, open-drained with internal pull-up and 8 mA current sink

: Shared pin: PB0/TCAP

: 25 mA current sink open-drained with internal pull-up

: not bonded out in 16-pin package

	OSC1	OSC2/R		RESET
				IRQ
	OSCILLATOR		CORE
	AND DIVIDE		TIMER	LOW
	BY 2		(COP)
				VOLTAGE
				RESET
			16-BIT	TCAP
			TIMER
		CPU CONTROL		ALU
		68HC05 CPU		VDD
				VSS
			ACCUM
		CPU REGISERS
			INDEX REG
		0 0 0 0 0 0 0 0 1 1		STK PTR
		PROGRAM COUNTER
		COND CODE REG 1 1 1 H I N Z C
		2560 BYTES	128 BYTES
		ROM		RAM

Figure 1-1. MC68HC05J5A Block Diagram

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1.4PIN ASSIGNMENTS

	OSC2/R				1	16		PB1			PB3		1	20		PB2
			OSC1		2	15		VDD		OSC2/R			2	19		PB1
					3	14		VSS					3	18		VDD
		RESET									OSC1
			PA7		4	13							4	17		VSS
								IRQ/VPP
											RESET
			PA6		5	12		PA0					5	16
											PA7					IRQ/VPP
			PA5		6	11		PA1			PA6		6	15		PA0
			PA4		7	10		PA2			PA5		7	14		PA1
PB0/TCAP					8	9		PA3			PA4		8	13		PA2
										PB0/TCAP			9	12		PA3
											PB4		10	11		PB5
	IRQ/VPP: VPP is only available on EPROM parts

Figure 1-2. Pin Assignments for 16-Pin and 20-Pin Packages

1.5FUNCTIONAL PIN DESCRIPTION

The following paragraphs give a description of the general function of each pin assigned in Figure 1-2.

1.5.1VDD AND VSS

Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply.

Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded.

1.5.2OSC1, OSC2/R

The OSC1 and OSC2/R pins are the connections for the on-chip oscillator. The

OSC1 and OSC2/R pins can accept the following sets of components:

MOTOROLA	GENERAL DESCRIPTION	MC68HC05J5A
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July 16, 1999 GENERAL RELEASE SPECIFICATION

1.A crystal as shown in Figure 1-3(a)

2.A ceramic resonator as shown in Figure 1-3(a)

3.An external clock signal as shown in Figure 1-3(b)

The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP.

Crystal Oscillator

The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor is provided between OSC1 and OSC2/R for the crystal type oscillator.

MCU

MCU

ROSC
OSC1	OSC2/R	OSC1	OSC2/R

									unconnected
				37 pF			37pF
									External Clock
(a) Crystal or ceramic									(b) External clock source
			resonator connection						connection

ROSC : see Section 11. Electrical Specifications.

Figure 1-3. Oscillator Connections

Ceramic Resonator Oscillator

In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The resonator manufacturer’s recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor is provided between OSC1 and OSC2/R for the ceramic resonator type oscillator.

External Clock

An external clock from another CMOS-compatible device can be connected to the

OSC1 input, with the OSC2/R input not connected, as shown in Figure 1-3(b).

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1.5.3RESET

This is an I/O pin. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering

diode to discharge any voltage on the pin to VDD, when the power is removed. An internal pull-up is also connected between this pin and VDD. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. This pin is an output pin if LVR triggers an internal reset.

1.5.4IRQ (MASKABLE INTERRUPT REQUEST)

This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the option is selected to include level-sensitive triggering, the IRQ input requires an

external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.

Each of the PA0 through PA3 I/O pins may be connected as an OR function with the IRQ interrupt function by a mask option. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ pin, except for the inverted phase. The edge or level sensitivity selected by a separate mask option for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal. Besides, PA7 also has falling-edge only interrupt capability whose functionality is controlled by another set of register bits.

1.5.5PA0-PA7

These eight I/O lines comprise Port A. PA6 and PA7 are open-drained pins with pull-up devices whereas PA0 to PA5 are push-pull pins with pull-down devices. PA4 to PA7 are also capable of sinking 8mA.

The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset. The lower four I/O pins (PA0 to PA3) can be connected via an internal OR gate to the IRQ interrupt function enabled by a mask option. Another independent interrupt source comes from the falling-edge on PA7. PA7 interrupt source is associated with a second set of interrupt control/status bits. All Port A pins except PA6 and PA7 have software programmable pull-down devices also provided by a mask option. PA6 and PA7 pins have software programmable pull-up devices also provided by the same mask option. Pull-up devices on PA6 and PA7 once enabled are always enabled regardless of pin direction configuration, unlike pull-down devices on PA0 to PA5 which are activated only when these pins are configured as input pins.

PA6 and PA7 pins, when configured as output pins, also have slow output fallingedge transition feature to reduce EMI. The falling-edge transition time is set at 250ns typical at a specified load of 500pF, assuming the bus rate is 2MHz. The slow transition output feature of PA6 and PA7, along with that of PB1 and PB2,

MOTOROLA	GENERAL DESCRIPTION	MC68HC05J5A
1-6		REV 2.1

July 16, 1999 GENERAL RELEASE SPECIFICATION

can be enabled or disabled by software. Both PA6 and PA7 pins have Schmitt trigger input for better noise immunity. VIH and VIL are specified at 2.4V and 0.8V, respectively.

The slow transition feature of PA6 and PA7 pins can be enabled or disabled by software. Once enabled, slow transition feature is applied to both pins while in output mode.

1.5.6 PB0-PB5

NOTE

I/O lines PB2 to PB5 are not available on the 16-pin package.

These six I/O lines comprise Port B. PB0, PB3 to PB5 are push-pull I/O lines with pull-down resistor. PB1 and PB2 are open-drain I/O lines with pull-up resistor.

The state of any line is software programmable and is configured as an input during power-on or reset. I/O lines PB1 and PB2 have software programmable pull-up device, whereas PB0, PB3 to PB5 have software programmable pull-down device, provided by mask option. Pull-up devices on PB1 and PB2 lines once enabled are always enabled regardless of pin direction configuration; unlike pulldown devices on PB0, PB3-PB5 lines, which are activated only when the pin is configured as input pin.

Similar to PA6 and PA7, PB1 also has a slow output falling transition feature when

configured as an output line. PB1 has 25mA sink capability at 0.5V V .

OL

PB2 output is one clock cycle (250ns if bus rate is 2MHz) late than other I/O pins if slow output transition feature is enabled. PB2 has 25mA sink capability at 0.5V

VOL.

NOTE

For the 16-pin package, PB1 and PB2 are bonded to the same pin and is labelled PB1. This PB1 pin has 50mA sink capability if PB1 and PB2 data register bits they are written with the same value at the same write cycle. The falling transition time of PB1 is set at 250ns typical at a specified load of 50pF, assuming that the bus rate is 2MHz. The slow transition feature on this PB1 pin is longer than PB1 pin for the 20-pin package.

NOTE

If Port Data Register PB1 and PB2 are not written with the same value, PB1 pin on the 16-pin package will sink 25mA only and the output transition time will be shorter.

MC68HC05J5A	GENERAL DESCRIPTION	MOTOROLA
REV 2.1		1-7

GENERAL RELEASE SPECIFICATION

July 16, 1999

MOTOROLA	GENERAL DESCRIPTION	MC68HC05J5A
1-8		REV 2.1

July 16, 1999 GENERAL RELEASE SPECIFICATION

SECTION 2

MEMORY

The MC68HC05J5A has 4K-bytes of addressable memory consisting 32 bytes of

I/O, 128 bytes of user RAM, and 2560 bytes of user ROM, as shown in

Figure 2-1.

$0000

$001F $0020

$007F $0080

$00C0 $00FF $0100

$02FF $0300

$0CFF $0D00

$0DFF $0E00

$0FEF $0FF0

$0FF5 $0FF6 $0FFF

I/O

32 Bytes

unimplemented 96 Bytes

User RAM 128 Bytes

Stack

unimplemented 512 Bytes

User ROM

2560 Bytes

unimplemented 256 Bytes

Internal Test & Vectors

496 Bytes ROM

ROM Reserved

6 Bytes

User Vectors ROM

10 Bytes

0000

0031

0032

0127

0128

0192

0255

0256

0767

0768

3327

3328

3583

3584

4079

4080

4085

4086

4095

				$0000
		I/O
		Registers
		32 bytes
		(see Figure 2-2)
				$001F
	COP Watchdog Timer*			$0FF0
		Reserved		$0FF1
		Reserved		$0FF2
		Reserved		$0FF3
		Reserved		$0FF4
		Reserved		$0FF5
	Timer1 Vector (High Byte)			$0FF6
	Timer1 Vector (Low Byte)			$0FF7
	MFT Vector (High Byte)			$0FF8
	MFT Vector (Low Byte)			$0FF9
	IRQ Vector (High Byte)			$0FFA
	IRQ Vector (Low Byte)			$0FFB
	SWI Vector (High Byte)			$0FFC
	SWI Vector (Low Byte)			$0FFD
	Reset Vector (High Byte)			$0FFE
	Reset Vector (Low Byte)			$0FFF

* Writing a 0 to bit 0 of $0FF0 clears the COP Timer. Reading $0FF0 returns ROM data.

Figure 2-1. MC68HC05J5A Memory Map

MC68HC05J5A	MEMORY	MOTOROLA
REV 2.1		2-1

GENERAL RELEASE SPECIFICATION

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2.1I/O AND CONTROL REGISTERS

The I/O and Control Registers reside in locations $0000-$001F. The overall organization of these registers is shown in Figure 2-2. The bit assignments for each register are shown in Figure 2-3 and Figure 2-4. Reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored.

	Port A Data Register	$0000
	Port B Data Register	$0001
	Timer1 Capture Control Register	$0002
		$0003
	unimplemented (1)
		$0004
	Port A Data Direction Register
		$0005
	Port B Data Direction Register
	unimplemented (2)
	MFT Control & Status Register	$0008
	MFT Counter Register	$0009
	IRQ Control & Status Register	$000A
	unimplemented (5)
	Port A Pulldown/up Register	$0010
	Port B Pulldown/up Register	$0011
		$0012
	Timer1 Registers (4)
		$0015
	unimplemented (2)
		$0018
	Timer1 Registers (4)
		$001B
	unimplemented (3)
		$001E
	Reserved
	Reserved for Test	$001F

Figure 2-2. I/O Registers Memory Map

2.2RAM

The total RAM consists of 128 bytes (including the stack) at locations $0080 through $00FF. The stack begins at address $00FF and proceeds down to $00C0. Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.

2.3ROM

There are a total of 2570 bytes of user ROM on-chip. This includes 2560 bytes of user ROM from locations $0300 to $0CFF for user program storage and 10 bytes for user vectors from locations $0FF6 to $0FFF.

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2.4I/O REGISTERS SUMMARY

	ADDR	REGISTER	R/W	BIT 7	BIT 6	BIT 5	BIT 4	BIT 3	BIT 2	BIT 1	BIT 0
	$0000	Port A Data	R	PA7	PA6	PA5	PA4	PA3	PA2	PA1	PA0
		PORTA	W
	$0001	Port B Data	R	0	0	PB5	PB4	PB3	PB2	PB1	PB0
		PORTB	W
	$0002	Timer1 Capture Control	R	TCAPS
		T1CC	W
	$0003	Unimplemented	R
			W
	$0004	Port A Data Direction	R	DDRA7	DDRA6	DDRA5	DDRA4	DDRA3	DDRA2	DDRA1	DDRA0
		DDRA	W
	$0005	Port B Data Direction	R	SLOWE	0	DDRB5	DDRB4	DDRB3	DDRB2	DDRB1	DDRB0
		DDRB	W
	$0006	Unimplemented	R
			W
	$0007	Unimplemented	R
			W
	$0008	MFT Ctrl/Status	R	TOF	RTIF	TOFE	RTIE	0	0	RT1	RT0
		TCSR	W					TOFR	RTIFR
	$0009	MFT Counter	R	TMR7	TMR6	TMR5	TMR4	TMR3	TMR2	TMR1	TMR0
		TCR	W
	$000A	IRQ Control/Status	R	IRQE	IRQE1	0	0	IRQF	IRQF1	0	0
		ICSR	W				R			IRQR	IRQR1
	$000B	Unimplemented	R
			W
	$000C	Unimplemented	R
			W
	$000D	Unimplemented	R
			W
	$000E	Unimplemented	R
			W
	$000F	Unimplemented	R
			W
				unimplemented bits					reserved bits		R

Figure 2-3. I/O Registers $0000-$000F

MC68HC05J5A	MEMORY	MOTOROLA
REV 2.1		2-3

GENERAL RELEASE SPECIFICATION

July 16, 1999

	ADDR	REGISTER	R/W	BIT 7	BIT 6	BIT 5	BIT 4	BIT 3	BIT 2	BIT 1	BIT 0
	$0010	Port A Pull-down/up	R
		PDURA	W	PURA7	PURA6	PDRA5	PDRA4	PDRA3	PDRA2	PDRA1	PDRA0
	$0011	Port B Pull-down/up	R
		PDURB	W			PDRB5	PDRB4	PDRB3	PURB2	PURB1	PDRB0
	$0012	Timer1 Control	R	ICIE	0	T1OIE	0	0	0	IEDGE	0
		T1CR	W
	$0013	Timer1 Status	R	ICF	0	T1OF	0	0	0	0	0
		T1SR	W
	$0014	Input Capture High	R	BIT15	BIT14	BIT13	BIT12	BIT11	BIT10	BIT9	BIT8
		ICH	W
	$0015	Input Capture Low	R	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
		ICL	W
	$0016	Unimplemented	R
			W
	$0017	Unimplemented	R
			W
	$0018	Timer1 Counter High	R	BIT15	BIT14	BIT13	BIT12	BIT11	BIT10	BIT9	BIT8
		TCNTH	W
	$0019	Timer1 Counter Low	R	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
		TCNTL	W
	$001A	Alt. Counter High	R	BIT15	BIT14	BIT13	BIT12	BIT11	BIT10	BIT9	BIT8
		ACNTH	W
	$001B	Alt. Counter Low	R	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
		ACNTL	W
	$001C	Unimplemented	R
			W
	$001D	Unimplemented	R
			W
	$001E	Reserved	R	R	R	R	R	R	R	R	R
			W
	$001F	Reserved	R	R	R	R	R	R	R	R	R
			W
				unimplemented bits					reserved bits		R

Figure 2-4. I/O Registers $0010-$001F

MOTOROLA	MEMORY	MC68HC05J5A
2-4		REV 2.1

July 16, 1999 GENERAL RELEASE SPECIFICATION

SECTION 3

CENTRAL PROCESSING UNIT

The MC68HC05J5A has an 4k-bytes memory map. The stack has only 64 bytes.

Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter.

3.1REGISTERS

The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown inFigure 3-1 and are described in the following paragraphs.

										7		6		5					4		3		2			1		0
																ACCUMULATOR																A
15	14	13	12	11	10			9	8					INDEX REGISTER																		X
0	0	0	0	0	0			0	0	1			1						STACK POINTER													SP
								PROGRAM COUNTER																								PC
		CONDITION CODE REGISTER								1			1	1					H		I		N			Z		C				CC
					HALF-CARRY BIT (FROM BIT 3)
									INTERRUPT MASK
										NEGATIVE BIT
												ZERO BIT
												CARRY BIT

Figure 3-1. MC68HC05 Programming Model

MC68HC05J5A	CENTRAL PROCESSING UNIT	MOTOROLA
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GENERAL RELEASE SPECIFICATION

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3.2ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The

CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device.

3.3INDEX REGISTER (X)

The index register shown in Figure 3-1 is an 8-bit register that can perform two functions:

•Indexed addressing

•Temporary storage

In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register content to an 8-bit immediate value. In indexed addressing with a

16-bit offset, the CPU finds the operand address by adding the index register content to a 16-bit immediate value.

The index register can also serve as an auxiliary accumulator for temporary storage. The index register is not affected by a reset of the device.

3.4STACK POINTER (SP)

The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack.

When accessing memory, the ten most significant bits are permanently set to 0000000011. The six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses five locations.

3.5PROGRAM COUNTER (PC)

The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched.

MOTOROLA	CENTRAL PROCESSING UNIT	MC68HC05J5A
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Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

3.6CONDITION CODE REGISTER (CCR)

The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a program, and specific actions can be taken as a result of their states. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register.

3.6.1Half Carry Bit (H-Bit)

When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.

3.6.2Interrupt Mask (I-Bit)

When the interrupt mask is set, the internal and external interrupts are disabled.

Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared.

A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions.

3.6.3Negative Bit (N-Bit)

The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.)

The negative bit can also be used to check an often tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag.

3.6.4Zero Bit (Z-Bit)

The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero.

MC68HC05J5A	CENTRAL PROCESSING UNIT	MOTOROLA
REV 2.1		3-3

GENERAL RELEASE SPECIFICATION

July 16, 1999

3.6.5Carry/Borrow Bit (C-Bit)

The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.

MOTOROLA	CENTRAL PROCESSING UNIT	MC68HC05J5A
3-4		REV 2.1

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SECTION 4

INTERRUPTS

The MCU can be interrupted in six different ways:

•Non-maskable Software Interrupt Instruction (SWI)

•External Asynchronous Interrupt (IRQ)

•Optional External Interrupt via IRQ on PA0-PA3 (by a mask option)

•External Interrupt via IRQ on PA7

•Multi-Function Timer (MFT)

•16-Bit Timer Interrupt (Timer1)

4.1CPU INTERRUPT PROCESSING

Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete.

If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs the processor completes the current instruction, then stacks the current CPU register states, sets the I-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state.

When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $0FF6 thru $0FFF as defined inTable 4-1.

Table 4-1. Vector Address for Interrupts and Reset

	Flag		CPU
Register	Name	Interrupts	Interrupt	Vector Address
N/A	N/A	Reset	RESET	$0FFE-$0FFF
N/A	N/A	Software	SWI	$0FFC-$0FFD
ICSR	IRQF/IRQF1	External Interrupt	IRQ	$0FFA-$0FFB
TCSR	TOF	MFT Overflow	MFT	$0FF8-$0FF9
TCSR	RTIF	Real Time Interrupt	MFT	$0FF8-$0FF9
T1SR	T1OF, ICF	Timer1 Interrupt	TIMER1	$0FF6-$0FF7

MC68HC05J5A	INTERRUPTS	MOTOROLA
REV 2.1		4-1

GENERAL RELEASE SPECIFICATION

July 16, 1999

An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing.

From

RESET

Y

Is

I-Bit

Set?

N

IRQ

Y

Clear IRQ

External

Request

Interrupt?

Latch if IRQE1 is

N

cleared

TIMER

Y

Internal

Interrupt?

N

Stack PC, X, A, CC

Fetch Next

Set I-Bit in CCR

Instruction

SWI

Load PC From:

Y

SWI: $0FFC, $0FFD

Instruction

IRQ: $0FFA-$0FFB

?

TIMER: $0FF8-$0FF9

N

TIMER1: $0FF6-$0FF7

RTI

Y

Instruction

?

Restore Registers

from stack

N

CC, A, X, PC

Execute

Instruction

Figure 4-1. Interrupt Processing Flowchart

4.2RESET INTERRUPT SEQUENCE

The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $0FFE and $0FFF. The I-bit in the condition code register is also set.

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4.3SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. As with any instruction, interrupts pending during the previous instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address is specified by the contents of memory locations $0FFC and $0FFD.

4.4HARDWARE INTERRUPTS

All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are two types of hardware interrupts which are explained in the following sections.

4.5EXTERNAL INTERRUPT (IRQ)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2.

IRQ Pin		to BIH & BIL
VDD		instruction
PA0		sensing
PA1
	IRQ
PA2	LATCH
PA3	R	IRQF

Mask Option

(Port A External Int.)

RST

IRQR

Mask Option

(IRQ Level)

IRQ Fetch Vector

IRQE1

to IRQ IRQE processing

in CPU

IRQE1

VDD
IRQ1	IRQF1
LATCH
PA7
R

RST

IRQR1

Figure 4-2. IRQ Function Block Diagram

MC68HC05J5A	INTERRUPTS	MOTOROLA
REV 2.1		4-3

GENERAL RELEASE SPECIFICATION

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The IRQ pin is a source of IRQ interrupts and a mask option can also enable the other four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.

The last source of IRQ interrupt comes from PA7 whenever there is a falling edge on PA7 and IRQE1 is enabled. There is no mask option associated with PA7 interrupt.

Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes from IRQ and IRQ1 latches. The IRQ latch will be set on the falling edge of the IRQ pin or on any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled.

The IRQ1 latch will be set on the falling edge of PA7 if PA7 interrupt has been enabled. If "edge-only" sensitivity is chosen by a mask option, only the IRQ latch output can activate an IRQF flag which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases:

1.Falling edge on the IRQ pin.

2.Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).

If level sensitivity is chosen, the rising edge signal on the clock input of the IRQ latch can also activate an IRQF flag which creates an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases:

1.Low level on the IRQ pin.

2.Falling edge on the IRQ pin.

3.High level on any PA0PA3 pin with IRQ enabled (via mask option).

4.Rising edge on any PA0PA3 pin with IRQ enabled (via mask option).

The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $0FFA and $0FFB.

The IRQ latch is automatically cleared by entering the interrupt service routine IF IRQE1 enable bit is cleared. If IRQE1 enable bit is also set, the only way of clearing IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one to the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF flag, regardless of the status of the IRQE1 bit, besides IRQ vector fetch. This conditional reset of IRQF flag provides a way for the user to differentiate the interrupt sources from IRQ and IRQ1 latches and also to make it J1A compatible if PA7 interrupt is not used. As long as the output state of the IRQF flag bit is active the CPU will continuously re-enter the IRQ interrupt sequence until the active state is removed or the IRQE enable bit is cleared.

PA7 interrupt source, if enabled by IRQE1 enable bit, triggers IRQ interrupt on PA7 falling edge only. The IRQ1 latch (IRQF1 flag) can ONLY be cleared by writing a logic one to the IRQR1 acknowledge bit in the ICSR. IRQ vector fetch can NOT clear IRQF1 flag. IRQ interrupt caused by PA7 falling edge also vectors to $0FFA and $0FFB.

MOTOROLA	INTERRUPTS	MC68HC05J5A
4-4		REV 2.1