INTEL 80C186EB, 80C188EB, 80L188EB, 80L186EB User Manual

TS80C186EB20

80C186EB/80C188EB AND 80L186EB/80L188EB

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

X Full Static Operation

X True CMOS Inputs and Outputs

YIntegrated Feature Set

ÐLow-Power Static CPU Core

ÐTwo Independent UARTs each with an Integral Baud Rate Generator

ÐTwo 8-Bit Multiplexed I/O Ports

ÐProgrammable Interrupt Controller

ÐThree Programmable 16-Bit Timer/Counters

ÐClock Generator

ÐTen Programmable Chip Selects with Integral Wait-State Generator

ÐMemory Refresh Control Unit

ÐSystem Level Testing Support (ONCE Mode)

YDirect Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O

YSpeed Versions Available (5V):

Ð25 MHz (80C186EB25/80C188EB25)

Ð20 MHz (80C186EB20/80C188EB20)

Ð13 MHz (80C186EB13/80C188EB13)

YAvailable in Extended Temperature Range (b40§C to a85§C)

YSpeed Versions Available (3V):

Ð16 MHz (80L186EB16/80L188EB16)

Ð13 MHz (80L186EB13/80L188EB13)

YLow-Power Operating Modes:

ÐIdle Mode Freezes CPU Clocks but keeps Peripherals Active

ÐPowerdown Mode Freezes All Internal Clocks

YSupports 80C187 Numeric Coprocessor Interface (80C186EB PLCC Only)

YAvailable In:

Ð80-Pin Quad Flat Pack (QFP)

Ð84-Pin Plastic Leaded Chip Carrier (PLCC)

Ð80-Pin Shrink Quad Flat Pack (SQFP)

The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.

272433 ± 1

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

June, 2002

Order Number: 272433-005

COPYRIGHT © INTEL CORPORATION, 2002

80C186EB/80C188EB and 80L186EB/80L188EB 16-Bit High-Integration Embedded Processors

CONTENTS

PAGE

INTRODUCTION ААААААААААААААААААААААААААА 4

CORE ARCHITECTURE ААААААААААААААААААА 4

Bus Interface Unit АААААААААААААААААААААААААА 4

Clock Generator ААААААААААААААААААААААААААА 4

80C186EC PERIPHERAL

ARCHITECTURE АААААААААААААААААААААААА 5

Interrupt Control Unit ААААААААААААААААААААААА 5

Timer/Counter Unit АААААААААААААААААААААААА 5

Serial Communications Unit АААААААААААААААА 7

Chip-Select Unit АААААААААААААААААААААААААААА 7

I/O Port Unit ААААААААААААААААААААААААААААААА 7

Refresh Control Unit ААААААААААААААААААААААА 7

Power Management Unit ААААААААААААААААААА 7

80C187 Interface (80C186EB Only) ААААААААА 7

ONCE Test Mode АААААААААААААААААААААААААА 7

PACKAGE INFORMATION АААААААААААААААА 8

Prefix Identification ААААААААААААААААААААААААА 8

Pin Descriptions АААААААААААААААААААААААААААА 8

80C186EB PINOUT ААААААААААААААААААААААА 14

PACKAGE THERMAL

SPECIFICATIONS АААААААААААААААААААААА 22

ELECTRICAL SPECIFICATIONS ААААААААА 23

Absolute Maximum Ratings ААААААААААААААА 23

CONTENTS

PAGE

Recommended Connections АААААААААААААА 23

DC SPECIFICATIONS АААААААААААААААААААА 24

ICC versus Frequency and Voltage ААААААААА 27

PDTMR Pin Delay Calculation ААААААААААААА 27

AC SPECIFICATIONS АААААААААААААААААААА 28

AC CharacteristicsÐ80C186EB25 ААААААААА 28

AC CharacteristicsÐ80C186EB20/13 ААААА 30

AC CharacteristicsÐ80L186EB16 ААААААААА 32

Relative Timings АААААААААААААААААААААААААА 36

Serial Port Mode 0 Timings АААААААААААААААА 37

AC TEST CONDITIONS АААААААААААААААААА 38

AC TIMING WAVEFORMS ААААААААААААААА 38

DERATING CURVES ААААААААААААААААААААА 41

RESET ААААААААААААААААААААААААААААААААААА 42

BUS CYCLE WAVEFORMS АААААААААААААА 45

EXECUTION TIMINGS ААААААААААААААААААА 52

INSTRUCTION SET SUMMARY АААААААААА 53

ERRATA ААААААААААААААААААААААААААААААААА 59

REVISION HISTORY ААААААААААААААААААААА 59

2

80C186EB/80C188EB, 80L186EB/80L188EB

272433 ± 2

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB

Figure 1. 80C186EB/80C188EB Block Diagram

3

80C186EB/80C188EB, 80L186EB/80L188EB

INTRODUCTION

Unless specifically noted, all references to the 80C186EB apply to the 80C188EB, 80L186EB, and 80L188EB. References to pins that differ between the 80C186EB/80L186EB and the 80C188EB/ 80L188EB are given in parentheses. The ``L'' in the part number denotes low voltage operation. Physically and functionally, the ``C'' and ``L'' devices are identical.

The 80C186EB is the first product in a new generation of low-power, high-integration microprocessors. It enhances the existing 186 family by offering new features and new operating modes. The 80C186EB is object code compatible with the 80C186XL/ 80C188XL microprocessors.

The 80L186EB is the 3V version of the 80C186EB. The 80L186EB is functionally identical to the 80C186EB embedded processor. Current 80C186EB users can easily upgrade their designs to use the 80L186EB and benefit from the reduced power consumption inherent in 3V operation.

The feature set of the 80C186EB meets the needs of low power, space critical applications. Low-Power applications benefit from the static design of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a Powerdown mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space critical applications benefit from the integration of commonly used system peripherals. Two serial channels are provided for services such as diagnostics, inter-processor communication, modem interface, terminal display interface, and many others. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 129 external interrupts and will prioritize these interrupts with those generated from the on-chip peripherals. Three general purpose timer/counters and sixteen multiplexed I/O port pins round out the feature set of the 80C186EB.

Figure 1 shows a block diagram of the 80C186EB/ 80C188EB. The Execution Unit (EU) is an enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instruction, and fully static operation. The Bus Interface Unit (BIU) is the same as that found on the original 186 family products, ex-

cept the queue status mode has been deleted and buffer interface control has been changed to ease system design timings. An independent internal bus is used to allow communication between the BIU and internal peripherals.

CORE ARCHITECTURE

Bus Interface Unit

The 80C186EB core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information, and data (for write operations) information. It is also responsible for reading data off the local bus during a read operation. A READY input pin is provided to extend a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates two control signals (DEN and DT/R) when interfacing to external transceiver chips. (Both DEN and DT/R are available on the PLCC devices, only DEN is available on the QFP and SQFP devices.) This capability allows the addition of transceivers for simple buffering of the multiplexed address/data bus.

Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-over- tone mode crystal network. Alternatively, the oscillator circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components. All AC timings are referenced to CLKOUT.

4

80C186EB/80C188EB, 80L186EB/80L188EB

272433 ± 4

	272433 ± 3
(A) Crystal Connection	(B) Clock Connection

NOTE:

The L1C1 network is only required when using a thirdovertone crystal.

Figure 2. Clock Configurations

The following parameters are recommended when choosing a crystal:

Temperature Range:	Application Specific
ESR (Equivalent Series Resistance):		40X max
C0 (Shunt Capacitance of Crystal):		7.0 pF max
CL (Load Capacitance):		20 pF g 2 pF
Drive Level:		1 mW max

80C186EB PERIPHERAL ARCHITECTURE

The 80C186EB has integrated several common system peripherals with a CPU core to create a compact, yet powerful system. The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or serial channels).

The list of integrated peripherals includes:

#7-Input Interrupt Control Unit

#3-Channel Timer/Counter Unit

#2-Channel Serial Communications Unit

#10-Output Chip-Select Unit

#I/O Port Unit

#Refresh Control Unit

#Power Management Unit

The registers associated with each integrated periheral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O space on any 256 Byte address boundary.

Figure 3 provides a list of the registers associated with the PCB. The Register Bit Summary at the end of this specification individually lists all of the registers and identifies each of their programming attributes.

Interrupt Control Unit

The 80C186EB can receive interrupts from a number of sources, both internal and external. The interrupt control unit serves to merge these requests on a priority basis, for individual service by the CPU. Each interrupt source can be independently masked by the Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU.

Internal interrupt sources include the Timers and Serial channel 0. External interrupt sources come from the five input pins INT4:0. The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU. Although the Timer and Serial channel each have only one request input to the ICU, separate vector types are generated to service individual interrupts within the Timer and Serial channel units.

Timer/Counter Unit

The 80C186EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of these are highly flexible and are connected to external pins for control or clocking. A third timer is not connected to any external pins and can only be clocked internally. However, it can be used to clock the other two timer channels. The TCU can be used to count external events, time external events, generate non-repeti- tive waveforms, generate timed interrupts. etc.

5

80C186EB/80C188EB, 80L186EB/80L188EB

PCB	Function		PCB	Function		PCB	Function		PCB	Function
Offset			Offset			Offset			Offset
00H	Reserved		40H	Timer2 Count		80H	GCS0 Start		C0H	Reserved
02H	End Of Interrupt		42H	Timer2 Compare		82H	GCS0 Stop		C2H	Reserved
04H	Poll		44H	Reserved		84H	GCS1 Start		C4H	Reserved
06H	Poll Status		46H	Timer2 Control		86H	GCS1 Stop		C6H	Reserved
08H	Interrupt Mask		48H	Reserved		88H	GCS2 Start		C8H	Reserved
0AH	Priority Mask		4AH	Reserved		8AH	GCS2 Stop		CAH	Reserved
0CH	In-Service		4CH	Reserved		8CH	GCS3 Start		CCH	Reserved
0EH	Interrupt Request		4EH	Reserved		8EH	GCS3 Stop		CEH	Reserved
10H	Interrupt Status		50H	Port 1 Direction		90H	GCS4 Start		D0H	Reserved
12H	Timer Control		52H	Port 1 Pin		92H	GCS4 Stop		D2H	Reserved
14H	Serial Control		54H	Port 1 Control		94H	GCS5 Start		D4H	Reserved
16H	INT4 Control		56H	Port 1 Latch		96H	GCS5 Stop		D6H	Reserved
18H	INT0 Control		58H	Port 2 Direction		98H	GCS6 Start		D8H	Reserved
1AH	INT1 Control		5AH	Port 2 Pin		9AH	GCS6 Stop		DAH	Reserved
1CH	INT2 Control		5CH	Port 2 Control		9CH	GCS7 Start		DCH	Reserved
1EH	INT3 Control		5EH	Port 2 Latch		9EH	GCS7 Stop		DEH	Reserved
20H	Reserved		60H	Serial0 Baud		A0H	LCS Start		E0H	Reserved
22H	Reserved		62H	Serial0 Count		A2H	LCS Stop		E2H	Reserved
24H	Reserved		64H	Serial0 Control		A4H	UCS Start		E4H	Reserved
26H	Reserved		66H	Serial0 Status		A6H	UCS Stop		E6H	Reserved
28H	Reserved		68H	Serial0 RBUF		A8H	Relocation		E8H	Reserved
2AH	Reserved		6AH	Serial0 TBUF		AAH	Reserved		EAH	Reserved
2CH	Reserved		6CH	Reserved		ACH	Reserved		ECH	Reserved
2EH	Reserved		6EH	Reserved		AEH	Reserved		EEH	Reserved
30H	Timer0 Count		70H	Serial1 Baud		B0H	Refresh Base		F0H	Reserved
32H	Timer0 Compare A		72H	Serial1 Count		B2H	Refresh Time		F2H	Reserved
34H	Timer0 Compare B		74H	Serial1 Control		B4H	Refresh Control		F4H	Reserved
36H	Timer0 Control		76H	Serial1 Status		B6H	Reserved		F6H	Reserved
38H	Timer1 Count		78H	Serial1 RBUF		B8H	Power Control		F8H	Reserved
3AH	Timer1 Compare A		7AH	Serial1 TBUF		BAH	Reserved		FAH	Reserved
3CH	Timer1 Compare B		7CH	Reserved		BCH	Step ID		FCH	Reserved
3EH	Timer1 Control		7EH	Reserved		BEH	Reserved		FEH	Reserved

Figure 3. Peripheral Control Block Registers

6

Serial Communications Unit

The Serial Control Unit (SCU) of the 80C186EB contains two independent channels. Each channel is identical in operation except that only channel 0 is supported by the integrated interrupt controller (channel 1 has an external interrupt pin). Each channel has its own baud rate generator that is independent of the Timer/Counter Unit, and can be internally or externally clocked at up to one half the 80C186EB operating frequency.

Independent baud rate generators are provided for each of the serial channels. For the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. A 1x baud clock is provided in the synchronous mode.

Chip-Select Unit

The 80C186EB Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chipselects to access both memories and peripherals. In addition, each chip-select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically terminate a bus cycle independent of the condition of the READY input pin.

I/O Port Unit

The I/O Port Unit (IPU) on the 80C186EB supports two 8-bit channels of input, output, or input/output operation. Port 1 is multiplexed with the chip select pins and is output only. Most of Port 2 is multiplexed with the serial channel pins. Port 2 pins are limited to either an output or input function depending on the operation of the serial pin it is multiplexed with.

Refresh Control Unit

The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between refresh requests.

80C186EB/80C188EB, 80L186EB/80L188EB

A 12-bit address generator is maintained by the RCU and is presented on the A12:1 address lines during the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary.

Power Management Unit

The 80C186EB Power Management Unit (PMU) is provided to control the power consumption of the device. The PMU provides three power modes: Active, Idle, and Powerdown.

Active Mode indicates that all units on the 80C186EB are functional and the device consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals continue to operate normally).

The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. All internal registers hold their values provided VCC is maintained. Current consumption is reduced to just transistor junction leakage.

80C187 Interface (80C186EB Only)

The 80C186EB (PLCC package only) supports the direct connection of the 80C187 Numerics Coprocessor.

ONCE Test Mode

To facilitate testing and inspection of devices when fixed into a target system, the 80C186EB has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ``ON Circuit Emulation''. The ONCE mode is selected by forcing the A19/ONCE pin LOW (0) during a processor reset (this pin is weakly held to a HIGH (1) level) while RESIN is active.

7

80C186EB/80C188EB, 80L186EB/80L188EB

PACKAGE INFORMATION

This section describes the pins, pinouts, and thermal characteristics for the 80C186EB in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) package. For complete package specifications and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369).

Prefix Identification

With the extended temperature range, operational characteristics are guaranteed over the temperature range corresponding to b40§C to a85§C ambient. Package types are identified by a two-letter prefix to the part number. The prefixes are listed in Table 1.

Table 1. Prefix Identification

	Prefix	Note	Package	Temperature
			Type	Type
	TN		PLCC	Extended
	TS		QFP (EIAJ)	Extended
	SB	1	SQFP	Extended/Commercial
	N	1	PLCC	Commercial
	S	1	QFP (EIAJ)	Commercial

NOTE:

1.The 5V 25 MHz and 3V 16 MHz versions are only available in commercial temperature range corresponding to 0§C to a70§C ambient.

Pin Descriptions

Each pin or logical set of pins is described in Table 3. There are three columns for each entry in the Pin Description Table.

The Pin Name column contains a mnemonic that describes the pin function. Negation of the signal name (for example, RESIN) denotes a signal that is active low.

The Pin Type column contains two kinds of information. The first symbol indicates whether a pin is power (P), ground (G), input only (I), output only (O) or input/output (I/O). Some pins have multiplexed functions (for example, A19/S6). Additional symbols indicate additional characteristics for each pin. Table 2 lists all the possible symbols for this column.

The Input Type column indicates the type of input (Asynchronous or Synchronous).

Asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge. Synchronous pins require that setup and hold times be met to guarantee proper operation. For example, missing the setup or hold time for the SRDY pin (a synchronous input) will result in a system failure or lockup. Input pins may also be edgeor level-sensitive. The possible characteristics for input pins are S(E), S(L), A(E) and A(L).

The Output States column indicates the output state as a function of the device operating mode. Output states are dependent upon the current activity of the processor. There are four operational states that are different from regular operation: bus hold, reset, Idle Mode and Powerdown Mode. Appropriate characteristics for these states are also indicated in this column, with the legend for all possible characteristics in Table 2.

The Pin Description column contains a text description of each pin.

As an example, consider AD15:0. I/O signifies the pins are bidirectional. S(L) signifies that the input function is synchronous and level-sensitive. H(Z) signifies that, as outputs, the pins are high-imped- ance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X) signifies that the pins retain their states during Powerdown Mode.

8

	80C186EB/80C188EB, 80L186EB/80L188EB
	Table 2. Pin Description Nomenclature
Symbol	Description
P	Power Pin (Apply aVCC Voltage)
G	Ground (Connect to VSS)
I	Input Only Pin
O	Output Only Pin
I/O	Input/Output Pin
S(E)	Synchronous, Edge Sensitive
S(L)	Synchronous, Level Sensitive
A(E)	Asynchronous, Edge Sensitive
A(L)	Asynchronous, Level Sensitive
H(1)	Output Driven to VCC during Bus Hold
H(0)	Output Driven to VSS during Bus Hold
H(Z)	Output Floats during Bus Hold
H(Q)	Output Remains Active during Bus Hold
H(X)	Output Retains Current State during Bus Hold
R(WH)	Output Weakly Held at VCC during Reset
R(1)	Output Driven to VCC during Reset
R(0)	Output Driven to VSS during Reset
R(Z)	Output Floats during Reset
R(Q)	Output Remains Active during Reset
R(X)	Output Retains Current State during Reset
I(1)	Output Driven to VCC during Idle Mode
I(0)	Output Driven to VSS during Idle Mode
I(Z)	Output Floats during Idle Mode
I(Q)	Output Remains Active during Idle Mode
I(X)	Output Retains Current State during Idle Mode
P(1)	Output Driven to VCC during Powerdown Mode
P(0)	Output Driven to VSS during Powerdown Mode
P(Z)	Output Floats during Powerdown Mode
P(Q)	Output Remains Active during Powerdown Mode
P(X)	Output Retains Current State during Powerdown Mode

9

80C186EB/80C188EB, 80L186EB/80L188EB

								Table 3. Pin Descriptions
		Pin				Pin	Input	Output	Description
		Name				Type	Type	States
	VCC					P	Ð	Ð	POWER connections consist of four pins which must be
									shorted externally to a VCC board plane.
	VSS					G	Ð	Ð	GROUND connections consist of six pins which must be
									shorted externally to a VSS board plane.
	CLKIN					I	A(E)	Ð	CLocK INput is an input for an external clock. An external
									oscillator operating at two times the required processor
									operating frequency can be connected to CLKIN. For crystal
									operation, CLKIN (along with OSCOUT) are the crystal
									connections to an internal Pierce oscillator.
	OSCOUT					O	Ð	H(Q)	OSCillator OUTput is only used when using a crystal to
								R(Q)	generate the external clock. OSCOUT (along with CLKIN)
								P(Q)	are the crystal connections to an internal Pierce oscillator.
									This pin is not to be used as 2X clock output for non-crystal
									applications (i.e., this pin is N.C. for non-crystal applications).
									OSCOUT does not float in ONCE mode.
	CLKOUT					O	Ð	H(Q)	CLocK OUTput provides a timing reference for inputs and
								R(Q)	outputs of the processor, and is one-half the input clock
								P(Q)	(CLKIN) frequency. CLKOUT has a 50% duty cycle and
									transistions every falling edge of CLKIN.
	RESIN					I	A(L)	Ð	RESet IN causes the processor to immediately terminate
									any bus cycle in progress and assume an initialized state. All
									pins will be driven to a known state, and RESOUT will also
									be driven active. The rising edge (low-to-high) transition
									synchronizes CLKOUT with CLKIN before the processor
									begins fetching opcodes at memory location 0FFFF0H.
	RESOUT					O	Ð	H(0)	RESet OUTput that indicates the processor is currently in
								R(1)	the reset state. RESOUT will remain active as long as RESIN
								P(0)	remains active.
	PDTMR					I/O	A(L)	H(WH)	Power-Down TiMeR pin (normally connected to an external
								R(Z)	capacitor) that determines the amount of time the processor
								P(1)	waits after an exit from power down before resuming normal
									operation. The duration of time required will depend on the
									startup characteristics of the crystal oscillator.
	NMI					I	A(E)	Ð	Non-Maskable Interrupt input causes a TYPE-2 interrupt to
									be serviced by the CPU. NMI is latched internally.
	TEST/BUSY					I	A(E)	Ð	TEST is used during the execution of the WAIT instruction to
									suspend CPU operation until the pin is sampled active
	(TEST)
									(LOW). TEST is alternately known as BUSY when interfacing
									with an 80C187 numerics coprocessor (80C186EB only).
	AD15:0					I/O	S(L)	H(Z)	These pins provide a multiplexed Address and Data bus.
	(AD7:0)							R(Z)	During the address phase of the bus cycle, address bits 0
								P(X)	through 15 (0 through 7 on the 80C188EB) are presented on
									the bus and can be latched using ALE. 8- or 16-bit data
									information is transferred during the data phase of the bus
									cycle.

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

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80C186EB/80C188EB, 80L186EB/80L188EB

Table 3. Pin Descriptions (Continued)

Pin

Pin

Input

Output

Description

Name

Type

Type

States

A18:16

I/O

A(L)

H(Z)

These pins provide multiplexed Address during the address

R(WH)

phase of the bus cycle. Address bits 16 through 19 are presented

A19/ONCE

(A15:A8)

P(X)

on these pins and can be latched using ALE. These pins are

driven to a logic 0 during the data phase of the bus cycle. On the

(A18:16)

80C188EB, A15 ± A8 provide valid address information for the

(A19/ONCE)

entire bus cycle. During a processor reset (RESIN active), A19/

ONCE is used to enable ONCE mode. A18:16 must not be driven

low during reset or improper operation may result.

S2:0

O

Ð

H(Z)

Bus cycle Status are encoded on these pins to provide bus

R(Z)

transaction information. S2:0 are encoded as follows:

P(1)

S2

S1

S0

Bus Cycle Initiated

0

0

0

Interrupt Acknowledge

0

0

1

Read I/O

0

1

0

Write I/O

0

1

1

Processor HALT

1

0

0

Queue Instruction Fetch

1

0

1

Read Memory

1

1

0

Write Memory

1

1

1

Passive (no bus activity)

ALE

O

Ð

H(0)

Address Latch Enable output is used to strobe address

R(0)

information into a transparent type latch during the address phase

P(0)

of the bus cycle.

BHE

O

Ð

H(Z)

Byte High Enable output to indicate that the bus cycle in progress

(RFSH)

R(Z)

is transferring data over the upper half of the data bus. BHE and

P(X)

A0 have the following logical encoding

A0

BHE

Encoding (for the 80C186EB/80L186EB only)

0

0

Word Transfer

0

1

Even Byte Transfer

1

0

Odd Byte Transfer

1

1

Refresh Operation

On the 80C188EB/80L188EB, RFSH is asserted low to indicate a

refresh bus cycle.

RD

O

Ð

H(Z)

ReaD output signals that the accessed memory or I/O device

R(Z)

must drive data information onto the data bus.

P(1)

WR

O

Ð

H(Z)

WRite output signals that data available on the data bus are to be

R(Z)

written into the accessed memory or I/O device.

P(1)

READY

I

A(L)

Ð

READY input to signal the completion of a bus cycle. READY

S(L)

must be active to terminate any bus cycle, unless it is ignored by

correctly programming the Chip-Select Unit.

DEN

O

Ð

H(Z)

Data ENable output to control the enable of bi-directional

R(Z)

transceivers in a buffered system. DEN is active only when data is

P(1)

to be transferred on the bus.

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

11

80C186EB/80C188EB, 80L186EB/80L188EB

Table 3. Pin Descriptions (Continued)

Pin

Pin

Input

Output

Description

Name

Type

Type

States

DT/R

O

Ð

H(Z)

Data Transmit/Receive output controls the direction of a

R(Z)

bi-directional buffer in a buffered system. DT/R is only

P(X)

available for the PLCC package.

LOCK

O

Ð

H(Z)

LOCK output indicates that the bus cycle in progress is not

R(WH)

to be interrupted. The processor will not service other bus

P(1)

requests (such as HOLD) while LOCK is active. This pin is

configured as a weakly held high input while RESIN is

active and must not be driven low.

HOLD

I

A(L)

Ð

HOLD request input to signal that an external bus master

wishes to gain control of the local bus. The processor will

relinquish control of the local bus between instruction

boundaries not conditioned by a LOCK prefix.

HLDA

O

Ð

H(1)

HoLD Acknowledge output to indicate that the processor

R(0)

has relinquished control of the local bus. When HLDA is

P(0)

asserted, the processor will (or has) floated its data bus

and control signals allowing another bus master to drive the

signals directly.

NCS

O

Ð

H(1)

Numerics Coprocessor Select output is generated when

(N.C.)

R(1)

accessing a numerics coprocessor. NCS is not provided on

P(1)

the QFP or SQFP packages. This signal does not exist on

the 80C188EB/80L188EB.

ERROR

I

A(L)

Ð

ERROR input that indicates the last numerics coprocessor

(N.C.)

operation resulted in an exception condition. An interrupt

TYPE 16 is generated if ERROR is sampled active at the

beginning of a numerics operation. ERROR is not provided

on the QFP or SQFP packages. This signal does not exist

on the 80C188EB/80L188EB.

PEREQ

I

A(L)

Ð

CoProcessor REQuest signals that a data transfer

(N.C.)

between an External Numerics Coprocessor and Memory is

pending. PEREQ is not provided on the QFP or SQFP

packages. This signal does not exist on the 80C188EB/

80L188EB.

UCS

O

Ð

H(1)

Upper Chip Select will go active whenever the address of

R(1)

a memory or I/O bus cycle is within the address limitations

P(1)

programmed by the user. After reset, UCS is configured to

be active for memory accesses between 0FFC00H and

0FFFFFH.

LCS

O

Ð

H(1)

Lower Chip Select will go active whenever the address of

R(1)

a memory bus cycle is within the address limitations

P(1)

programmed by the user. LCS is inactive after a reset.

P1.0/GCS0

O

Ð

H(X)/H(1)

These pins provide a multiplexed function. If enabled, each

R(1)

pin can provide a Generic Chip Select output which will go

P1.1/GCS1

active whenever the address of a memory or I/O bus cycle

P1.2/GCS2

P(X)/P(1)

is within the address limitations programmed by the user.

P1.3/GCS3

When not programmed as a Chip-Select, each pin may be

P1.4/GCS4

used as a general purpose output Port. As an output port

P1.5/GCS5

pin, the value of the pin can be read internally.

P1.6/GCS6

P1.7/GCS7

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

12

										80C186EB/80C188EB, 80L186EB/80L188EB
								Table 3. Pin Descriptions (Continued)
	Pin						Pin	Input	Output	Description
	Name						Type	Type	States
	T0OUT						O	Ð	H(Q)	Timer OUTput pins can be programmed to provide a
	T1OUT								R(1)	single clock or continuous waveform generation,
									P(Q)	depending on the timer mode selected.
	T0IN						I	A(L)	Ð	Timer INput is used either as clock or control signals,
	T1IN							A(E)		depending on the timer mode selected.
	INT0						I	A(E,L)	Ð	Maskable INTerrupt input will cause a vector to a
	INT1									specific Type interrupt routine. To allow interrupt
	INT4									expansion, INT0 and/or INT1 can be used with
										INTA0 and INTA1 to interface with an external slave
										controller.
	INT2/INTA0						I/O	A(E,L)	H(1)	These pins provide a multiplexed function. As inputs,
										they provide a maskable INTerrupt that will cause
	INT3/INTA1								R(Z)
									P(1)	the CPU to vector to a specific Type interrupt routine.
										As outputs, each is programmatically controlled to
										provide an INTERRUPT ACKNOWLEDGE
										handshake signal to allow interrupt expansion.
	P2.7						I/O	A(L)	H(X)	BI-DIRECTIONAL, open-drain Port pins.
	P2.6								R(Z)
									P(X)
	CTSO						I	A(L)	Ð	Clear-To-Send input is used to prevent the
										transmission of serial data on their respective TXD
	P2.4/CTS1
										signal pin. CTS1 is multiplexed with an input only port
										function.
	TXD0						O	Ð	H(X)/H(Q)	Transmit Data output provides serial data
	P2.1/TXD1								R(1)	information. TXD1 is multiplexed with an output only
									P(X)/P(Q)	Port function. During synchronous serial
										communications, TXD will function as a clock output.
	RXD0						I/O	A(L)	R(Z)	Receive Data input accepts serial data information.
	P2.0/RXD1								H(Q)	RXD1 is multiplexed with an input only Port function.
									P(X)	During synchronous serial communications, RXD is
										bi-directional and will become an output for
										transmission or data (TXD becomes the clock).
	P2.5/BCLK0						I	A(L)/A(E)	Ð	Baud CLocK input can be used as an alternate clock
	P2.2/BCLK1									source for each of the integrated serial channels.
										BCLKx is multiplexed with an input only Port function,
										and cannot exceed a clock rate greater than one-half
										the operating frequency of the processor.
	P2.3/SINT1						O	Ð	H(X)/H(Q)	Serial INTerrupt output will go active to indicate
									R(0)	serial channel 1 requires service. SINT1 is
									P(X)/P(X)	multiplexed with an output only Port function.

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

13

80C186EB/80C188EB, 80L186EB/80L188EB

80C186EB PINOUT

Tables 4 and 5 list the 80C186EB/80C188EB pin names with package location for the 84-pin Plastic Leaded Chip Carrier (PLCC) component. Figure 5 depicts the complete 80C186EB/80C188EB pinout (PLCC package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 6 and 7 list the 80C186EB/80C188EB pin names with package location for the 80-pin Quad Flat Pack (QFP) component. Figure 6 depicts the complete 80C186EB/80C188EB (QFP package) as viewed from the top side of the component (i.e., contacts facing down).

Tables 8 and 9 list the 80186EB/80188EB pin names with package location for the 80-pin Shrink Quad Flat Pack (SQFP) component. Figure 7 depicts the complete 80C186EB/80C188EB (SQFP package) as viewed from the top side of the component (i.e., contacts facing down).

Table 4. PLCC Pin Names with Package Location

Address/Data Bus												Bus Control								Processor Control
Name			Location					Name									Location			Name							Location
AD0			61			ALE											6		RESIN								37
AD1			66			BHE (RFSH)											7		RESOUT								38
AD2			68														10		CLKIN								41
						S0
AD3			70																OSCOUT								40
						S1											9
AD4			72
						S2											8		CLKOUT								44
AD5			74
						RD											4		TEST/BUSY								14
AD6			76
						WR											5
																			NCS (N.C.)								60
AD7			78
						READY											18		PEREQ (N.C.)								39
AD8 (A8)			62
																	11		ERROR (N.C.)								3
AD9 (A9)			67			DEN
AD10 (A10)			69			DT/R											16		PDTMR								36
AD11 (A11)			71			LOCK											15		NMI								17
AD12 (A12)			73			HOLD											13		INT0								31
AD13 (A13)			75			HLDA											12		INT1								32
AD14 (A14)			77																INT2/INTA0								33
AD15 (A15)			79
													Power						INT3/INTA1								34
A16			80																INT4								35
						Name										Location
A17			81
A18			82			VSS										2, 22, 43
A19/ONCE			83													63, 65, 84
						VCC										1, 23
																42, 64
NOTE:
Pin names in parentheses apply to the 80C188EB/80L188EB.

I/O

	Name							Location
	UCS							30
	LCS							29
	P1.0/GCS0							28
	P1.1/GCS1							27
	P1.2/GCS2							26
	P1.3/GCS3							25
	P1.4/GCS4							24
	P1.5/GCS5							21
	P1.6/GCS6							20
	P1.7/GCS7							19
	T0OUT							45
	T0IN							46
	T1OUT							47
	T1IN							48
	RXD0							53
	TXD0							52
	P2.5/BCLK0							54
	CTS0							51
	P2.0/RXD1							57
	P2.1/TXD1							58
	P2.2/BCLK1							59
	P2.3/SINT1							55
	P2.4/CTS1							56
	P2.6							50
	P2.7							49

14

80C186EB/80C188EB, 80L186EB/80L188EB

Table 5. PLCC Package Locations with Pin Name

Location						Name									Location		Name									Location		Name					Location	Name
1		VCC													22	VSS										43		VSS					64	VCC
2		VSS													23	VCC										44		CLKOUT					65	VSS
3		ERROR (N.C.)													24	P1.4/GCS4										45		T0OUT					66	AD1
																										46		T0IN
4		RD													25	P1.3/GCS3																	67	AD9 (A9)
																										47		T1OUT					68	AD2
5		WR													26	P1.2/GCS2
6		ALE													27	P1.1/GCS1										48		T1IN					69	AD10 (A10)
7		BHE (RFSH)													28	P1.0/GCS0										49		P2.7					70	AD3
																										50		P2.6					71	AD11 (A11)
8		S2													29	LCS
9		S1													30	UCS										51		CTS0					72	AD4
																																	73	AD12 (A12)
10		S0													31	INT0										52		TXD0
															32	INT1										53		RXD0					74	AD5
11		DEN
																																	75	AD13 (A13)
12		HLDA													33	INT2/INTA0										54		P2.5/BCLK0
13		HOLD													34	INT3/INTA1										55		P2.3/SINT1					76	AD6
14		TEST/BUSY													35	INT4										56		P2.4/CTS1					77	AD14 (A14)
																																	78	AD7
15		LOCK													36	PDTMR										57		P2.0/RXD1
																																	79	AD15 (A15)
16		DT/R													37	RESIN										58		P2.1/TXD1
17		NMI													38	RESOUT										59		P2.2/BCLK1					80	A16
																																	81	A17
18		READY													39	PEREQ (N.C.)										60		NCS (N.C.)
																																	82	A18
19		P1.7/GCS7													40	OSCOUT										61		AD0
20		P1.6/GCS6													41	CLKIN										62		AD8 (A8)					83	A19/ONCE
21		P1.5/GCS5													42	VCC										63		VSS					84	VSS

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

15

80C186EB/80C188EB, 80L186EB/80L188EB

272433 ± 5

NOTE:

This is the FPO number location (indicated by X's).

Pin names in parentheses apply to the 80C188EB/80L188EB.

Figure 4. 84-Pin Plastic Leaded Chip Carrier Pinout Diagram

16

80C186EB/80C188EB, 80L186EB/80L188EB

Table 6. QFP Pin Name with Package Location

Address/Data Bus											Bus Control								Processor Control												I/O
Name			Location					Name								Location			Name					Location			Name								Location
AD0			10			ALE										38		RESIN						68		UCS									61
AD1			15			BHE (RFSH)										39		RESOUT						69			LCS								60
AD2			17															CLKIN						71
																42											P1.0/GCS0								59
						S0
AD3			19															OSCOUT						70			P1.1/GCS1								58
						S1										41
AD4			21															CLKOUT						74		P1.2/GCS2									57
						S2										40
AD5			23															TEST						46		P1.3/GCS3									56
						RD										36
AD6			25															PDTMR						67			P1.4/GCS4								55
						WR										37
AD7			27															NMI						48
																											P1.5/GCS5								52
						READY										49
AD8 (A8)			11															INT0						62
																											P1.6/GCS6								51
						DEN										43
AD9 (A9)			16															INT1						63
																											P1.7/GCS7								50
						LOCK										47
AD10 (A10)			18															INT2/INTA0						64			T0OUT								75
AD11 (A11)			20			HOLD										45		INT3/INTA1						65		T0IN									76
AD12 (A12)			22			HLDA										44		INT4						66		T1OUT									77
AD13 (A13)			24																							T1IN									78
AD14 (A14)			26									Power														RXD0									3
AD15 (A15)			28																							TXD0									2
						Name									Location
A16			29																							P2.5/BCLK0									4
						VSS									12, 14, 33
A17			30																							CTS0									1
A18			31												35, 53, 73											P2.0/RXD1									7
						VCC									13, 34
A19/ONCE			32																							P2.1/TXD1									8
															54, 72											P2.2/BCLK1									9
																										P2.3/SINT1									5
																										P2.4/CTS1									6
																										P2.6									80
																										P2.7									79

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

17

80C186EB/80C188EB, 80L186EB/80L188EB

Table 7. QFP Package Location with Pin Names

Location		Name				Location			Name								Location			Name							Location		Name
1	CTS0					21		AD4									41		S1								61		UCS
						22		AD12 (A12)
2	TXD0																42		S0								62		INT0
3	RXD0					23		AD5																			63		INT1
																	43		DEN
						24		AD13 (A13)
4	P2.5/BCLK0																44		HLDA								64		INT2/INTA0
5	P2.3/SINT1					25		AD6									45		HOLD
																											65		INT3/INTA1
6	P2.4/CTS1					26		AD14 (A14)									46		TEST								66		INT4
						27		AD7																			67		PDTMR
7	P2.0/RXD1																47		LOCK
8	P2.1/TXD1					28		AD15 (A15)									48		NMI								68		RESIN
9	P2.2/BCLK1					29		A16									49		READY								69		RESOUT
10	AD0					30		A17
																	50		P1.7/GCS7								70		OSCOUT
11	AD8 (A8)					31		A18																			71		CLKIN
																	51		P1.6/GCS6
12	VSS					32		A19/ONCE									52		P1.5/GCS5								72		VCC
13	VCC					33		VSS									53		VSS								73		VSS
14	VSS					34		VCC									54		VCC								74		CLKOUT
15	AD1					35		VSS									55		P1.4/GCS4								75		T0OUT
16	AD9 (A9)																										76		T0IN
						36		RD									56		P1.3/GCS3
17	AD2																										77		T1OUT
						37		WR									57		P1.2/GCS2
18	AD10 (A10)																										78		T1IN
						38		ALE									58		P1.1/GCS1
19	AD3																										79		P2.7
						39		BHE (RFSH)									59		P1.0/GCS0
20	AD11 (A11)																										80		P2.6
						40		S2									60		LCS

NOTE:

Pin names in parentheses apply to the 80C188EB/80L188EB.

18