Intel 8086, 8086-1, 8086-2 User Manual

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8086

16-BIT HMOS MICROPROCESSOR 8086/8086-2/8086-1

YDirect Addressing Capability 1 MByte of Memory

YArchitecture Designed for Powerful Assembly Language and Efficient High Level Languages

Y14 Word, by 16-Bit Register Set with Symmetrical Operations

Y24 Operand Addressing Modes

YBit, Byte, Word, and Block Operations

Y8 and 16-Bit Signed and Unsigned Arithmetic in Binary or Decimal Including Multiply and Divide

YRange of Clock Rates: 5 MHz for 8086,

8 MHz for 8086-2,

10 MHz for 8086-1

YMULTIBUS System Compatible Interface

YAvailable in EXPRESS

ÐStandard Temperature Range

ÐExtended Temperature Range

YAvailable in 40-Lead Cerdip and Plastic

Package

(See Packaging Spec. Order Ý231369)

The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations to achieve high performance levels.

231455 ± 2

40 Lead

Figure 2. 8086 Pin

Configuration

Figure 1. 8086 CPU Block Diagram

231455 ± 1

 

September 1990

Order Number: 231455-005

8086

Table 1. Pin Description

The following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ``Local Bus'' in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to additional bus buffers).

 

Symbol

Pin No.

Type

 

 

 

Name and Function

 

 

 

 

 

 

 

 

 

 

 

AD15 ± AD0

2 ± 16, 39

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed

 

 

 

 

 

 

memory/IO address (T1), and data (T2, T3, TW, T4) bus. A0 is

 

 

 

 

 

 

analogous to BHE for the lower byte of the data bus, pins D7 ± D0. It is

 

 

 

 

 

 

LOW during T1 when a byte is to be transferred on the lower portion

 

 

 

 

 

 

of the bus in memory or I/O operations. Eight-bit oriented devices tied

 

 

 

 

 

 

to the lower half would normally use A0 to condition chip select

 

 

 

 

 

 

functions. (See BHE.) These lines are active HIGH and float to 3-state

 

 

 

 

 

 

OFF during interrupt acknowledge and local bus ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

A19/S6,

35 ± 38

O

ADDRESS/STATUS: During T1 these are the four most significant

 

A18/S5,

 

 

address lines for memory operations. During I/O operations these

A17/S4,

 

 

lines are LOW. During memory and I/O operations, status information

 

 

is available on these lines during T2, T3, TW, T4. The status of the

A16/S3

 

 

 

 

 

 

 

 

interrupt enable FLAG bit (S5) is updated at the beginning of each

 

 

 

 

 

 

CLK cycle. A17/S4 and A16/S3 are encoded as shown.

 

 

 

 

 

 

This information indicates which relocation register is presently being

 

 

 

 

 

 

used for data accessing.

 

 

 

 

 

 

 

These lines float to 3-state OFF during local bus ``hold acknowledge.''

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A17/S4

A16/S3

Characteristics

 

 

 

 

 

 

0 (LOW)

0

Alternate Data

 

 

 

 

 

 

0

 

 

1

Stack

 

 

 

 

 

 

1 (HIGH)

0

Code or None

 

 

 

 

 

 

1

 

 

1

Data

 

 

 

 

 

 

S6 is 0

 

 

 

 

 

 

 

 

(LOW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BHE/S7

34

O

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal

 

 

 

 

 

 

(BHE) should be used to enable data onto the most significant half of

 

 

 

 

 

 

the data bus, pins D15 ± D8. Eight-bit oriented devices tied to the upper

 

 

 

 

 

 

half of the bus would normally use BHE to condition chip select

 

 

 

 

 

 

functions. BHE is LOW during T1 for read, write, and interrupt

 

 

 

 

 

 

acknowledge cycles when a byte is to be transferred on the high

 

 

 

 

 

 

portion of the bus. The S7 status information is available during T2,

 

 

 

 

 

 

T3, and T4. The signal is active LOW, and floats to 3-state OFF in

 

 

 

 

 

 

``hold''. It is LOW during T1 for the first interrupt acknowledge cycle.

 

 

 

 

 

 

BHE

A0

Characteristics

 

 

 

 

 

 

0

 

0

Whole word

 

 

 

 

 

 

0

 

1

Upper byte from/to odd address

 

 

 

 

 

 

1

 

0

Lower byte from/to even address

 

 

 

 

 

 

1

 

1

None

 

 

 

 

 

 

 

 

 

 

 

 

 

RD

32

O

READ: Read strobe indicates that the processor is performing a

 

 

 

 

 

 

memory or I/O read cycle, depending on the state of the S2 pin. This

 

 

 

 

 

 

signal is used to read devices which reside on the 8086 local bus. RD

 

 

 

 

 

 

is active LOW during T2, T3 and TW of any read cycle, and is

 

 

 

 

 

 

guaranteed to remain HIGH in T2 until the 8086 local bus has floated.

 

 

 

 

 

 

This signal floats to 3-state OFF in ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

8086

 

 

 

 

 

 

 

Table 1. Pin Description (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Pin No.

Type

 

 

Name and Function

 

 

 

 

 

 

 

 

 

 

 

 

 

READY

22

I

 

READY: is the acknowledgement from the addressed memory or I/O

 

 

 

 

 

 

 

 

device that it will complete the data transfer. The READY signal from

 

 

 

 

 

 

 

 

memory/IO is synchronized by the 8284A Clock Generator to form

 

 

 

 

 

 

 

 

READY. This signal is active HIGH. The 8086 READY input is not

 

 

 

 

 

 

 

 

synchronized. Correct operation is not guaranteed if the setup and hold

 

 

 

 

 

 

 

 

times are not met.

 

 

 

 

 

 

 

 

 

 

 

 

 

INTR

18

I

 

INTERRUPT REQUEST: is a level triggered input which is sampled

 

 

 

 

 

 

 

 

during the last clock cycle of each instruction to determine if the

 

 

 

 

 

 

 

 

processor should enter into an interrupt acknowledge operation. A

 

 

 

 

 

 

 

 

subroutine is vectored to via an interrupt vector lookup table located in

 

 

 

 

 

 

 

 

system memory. It can be internally masked by software resetting the

 

 

 

 

 

 

 

 

interrupt enable bit. INTR is internally synchronized. This signal is

 

 

 

 

 

 

 

 

active HIGH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEST

23

I

 

TEST: input is examined by the ``Wait'' instruction. If the TEST input is

 

 

 

 

 

 

 

 

LOW execution continues, otherwise the processor waits in an ``Idle''

 

 

 

 

 

 

 

 

state. This input is synchronized internally during each clock cycle on

 

 

 

 

 

 

 

 

the leading edge of CLK.

 

 

 

 

 

 

 

 

 

NMI

17

I

 

NON-MASKABLE INTERRUPT: an edge triggered input which causes

 

 

 

 

 

 

 

 

a type 2 interrupt. A subroutine is vectored to via an interrupt vector

 

 

 

 

 

 

 

 

lookup table located in system memory. NMI is not maskable internally

 

 

 

 

 

 

 

 

by software. A transition from LOW to HIGH initiates the interrupt at the

 

 

 

 

 

 

 

 

end of the current instruction. This input is internally synchronized.

 

 

 

 

 

 

 

 

 

RESET

21

I

 

RESET: causes the processor to immediately terminate its present

 

 

 

 

 

 

 

 

activity. The signal must be active HIGH for at least four clock cycles. It

 

 

 

 

 

 

 

 

restarts execution, as described in the Instruction Set description, when

 

 

 

 

 

 

 

 

RESET returns LOW. RESET is internally synchronized.

 

 

 

 

 

 

 

 

 

CLK

19

I

 

CLOCK: provides the basic timing for the processor and bus controller.

 

 

 

 

 

 

 

 

It is asymmetric with a 33% duty cycle to provide optimized internal

 

 

 

 

 

 

 

 

timing.

 

 

 

 

 

 

 

 

 

VCC

40

 

 

VCC: a5V power supply pin.

 

GND

1, 20

 

 

GROUND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MN/MX

33

I

 

MINIMUM/MAXIMUM: indicates what mode the processor is to

 

 

 

 

 

 

 

 

operate in. The two modes are discussed in the following sections.

 

 

 

 

 

 

 

 

 

 

 

 

The following pin function descriptions are for the 8086/8288 system in maximum mode (i.e., MN/MX e VSS). Only the pin functions which are unique to maximum mode are described; all other pin functions are as described above.

 

 

 

 

 

 

 

 

 

 

 

S2, S1, S0

 

26 ± 28

O

STATUS: active during T4, T1, and T2 and is returned to the passive state

 

 

 

 

 

 

 

 

 

(1, 1, 1) during T3 or during TW when READY is HIGH. This status is used

 

 

 

 

 

 

 

 

 

by the 8288 Bus Controller to generate all memory and I/O access control

 

 

 

 

 

 

 

 

 

signals. Any change by S2, S1, or S0 during T4 is used to indicate the

 

 

 

 

 

 

 

 

 

beginning of a bus cycle, and the return to the passive state in T3 or TW is

 

 

 

 

 

 

 

 

 

used to indicate the end of a bus cycle.

 

 

 

 

 

 

 

 

 

 

3

8086

Table 1. Pin Description (Continued)

 

Symbol

Pin No.

Type

 

 

 

 

 

 

 

 

 

 

Name and Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2, S1, S0

26 ± 28

O

These signals float to 3-state OFF in ``hold acknowledge''. These status

 

(Continued)

 

 

lines are encoded as shown.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S2

 

 

S1

 

 

 

S0

 

Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

0 (LOW)

 

 

0

 

 

0

 

 

Interrupt Acknowledge

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

0

 

 

1

 

 

Read I/O Port

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

1

 

 

0

 

 

Write I/O Port

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

1

 

 

1

 

 

Halt

 

 

 

 

 

 

 

 

 

 

 

 

 

1 (HIGH)

 

 

0

 

 

0

 

 

Code Access

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

0

 

 

1

 

 

Read Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

1

 

 

0

 

 

Write Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

1

 

 

1

 

 

Passive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RQ/GT0,

30, 31

I/O

REQUEST/GRANT: pins are used by other local bus masters to force

 

 

 

 

 

 

 

 

the processor to release the local bus at the end of the processor's

 

RQ/GT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

current bus cycle. Each pin is bidirectional with RQ/GT0 having higher

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and

 

 

 

 

 

 

 

 

 

 

 

 

 

may be left unconnected. The request/grant sequence is as follows

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Page 2-24):

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. A pulse of 1 CLK wide from another local bus master indicates a local

 

 

 

 

 

 

 

 

 

 

 

 

 

bus request (``hold'') to the 8086 (pulse 1).

 

 

 

 

 

 

 

 

 

 

 

 

 

2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the 8086 to

 

 

 

 

 

 

 

 

 

 

 

 

 

the requesting master (pulse 2), indicates that the 8086 has allowed the

 

 

 

 

 

 

 

 

 

 

 

 

 

local bus to float and that it will enter the ``hold acknowledge'' state at

 

 

 

 

 

 

 

 

 

 

 

 

 

the next CLK. The CPU's bus interface unit is disconnected logically

 

 

 

 

 

 

 

 

 

 

 

 

 

from the local bus during ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

 

 

3. A pulse 1 CLK wide from the requesting master indicates to the 8086

 

 

 

 

 

 

 

 

 

 

 

 

 

(pulse 3) that the ``hold'' request is about to end and that the 8086 can

 

 

 

 

 

 

 

 

 

 

 

 

 

reclaim the local bus at the next CLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Each master-master exchange of the local bus is a sequence of 3

 

 

 

 

 

 

 

 

 

 

 

 

 

pulses. There must be one dead CLK cycle after each bus exchange.

 

 

 

 

 

 

 

 

 

 

 

 

 

Pulses are active LOW.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If the request is made while the CPU is performing a memory cycle, it

 

 

 

 

 

 

 

 

 

 

 

 

 

will release the local bus during T4 of the cycle when all the following

 

 

 

 

 

 

 

 

 

 

 

 

 

conditions are met:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. Request occurs on or before T2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2. Current cycle is not the low byte of a word (on an odd address).

 

 

 

 

 

 

 

 

 

 

 

 

 

3. Current cycle is not the first acknowledge of an interrupt acknowledge

 

 

 

 

 

 

 

 

 

 

 

 

 

sequence.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4. A locked instruction is not currently executing.

 

 

 

 

 

 

 

 

 

 

 

 

 

If the local bus is idle when the request is made the two possible events

 

 

 

 

 

 

 

 

 

 

 

 

 

will follow:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. Local bus will be released during the next clock.

 

 

 

 

 

 

 

 

 

 

 

 

 

2. A memory cycle will start within 3 clocks. Now the four rules for a

 

 

 

 

 

 

 

 

 

 

 

 

 

currently active memory cycle apply with condition number 1 already

 

 

 

 

 

 

 

 

 

 

 

 

 

satisfied.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOCK

29

O

LOCK: output indicates that other system bus masters are not to gain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

control of the system bus while LOCK is active LOW. The LOCK signal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is activated by the ``LOCK'' prefix instruction and remains active until the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

completion of the next instruction. This signal is active LOW, and floats

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to 3-state OFF in ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

8086

 

 

 

Table 1. Pin Description (Continued)

 

 

 

 

 

 

 

 

Symbol

Pin No.

Type

 

 

Name and Function

 

 

 

 

 

 

QS1, QS0

24, 25

O

QUEUE STATUS: The queue status is valid during the CLK cycle after

 

 

 

which the queue operation is performed.

 

 

 

QS1 and QS0 provide status to allow external tracking of the internal

 

 

 

8086 instruction queue.

 

 

 

 

 

 

 

 

 

 

 

 

 

QS1

QS0

 

Characteristics

 

 

 

0

(LOW)

0

 

No Operation

 

 

 

0

 

1

 

First Byte of Op Code from Queue

 

 

 

1

(HIGH)

0

 

Empty the Queue

 

 

 

1

 

1

 

Subsequent Byte from Queue

 

 

 

 

 

 

 

 

The following pin function descriptions are for the 8086 in minimum mode (i.e., MN/MX e VCC). Only the pin functions which are unique to minimum mode are described; all other pin functions are as described above.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M/IO

28

O

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to

 

 

 

 

 

 

 

 

 

 

distinguish a memory access from an I/O access. M/IO becomes valid in

 

 

 

 

 

 

 

 

 

 

the T4 preceding a bus cycle and remains valid until the final T4 of the cycle

 

 

 

 

 

 

 

 

 

 

(M e HIGH, IO e LOW). M/IO floats to 3-state OFF in local bus ``hold

 

 

 

 

 

 

 

 

 

 

acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WR

29

O

WRITE: indicates that the processor is performing a write memory or write

 

 

 

 

 

 

 

 

 

 

I/O cycle, depending on the state of the M/IO signal. WR is active for T2, T3

 

 

 

 

 

 

 

 

 

 

and TW of any write cycle. It is active LOW, and floats to 3-state OFF in

 

 

 

 

 

 

 

 

 

 

local bus ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTA

24

O

INTA: is used as a read strobe for interrupt acknowledge cycles. It is active

 

 

 

 

 

 

 

 

 

 

LOW during T2, T3 and TW of each interrupt acknowledge cycle.

 

ALE

25

O

ADDRESS LATCH ENABLE: provided by the processor to latch the

 

 

 

 

 

 

 

 

 

 

address into the 8282/8283 address latch. It is a HIGH pulse active during

 

 

 

 

 

 

 

 

 

 

T1 of any bus cycle. Note that ALE is never floated.

 

 

 

 

 

 

 

 

 

 

 

 

 

DT/R

27

O

DATA TRANSMIT/RECEIVE: needed in minimum system that desires to

 

 

 

 

 

 

 

 

 

 

use an 8286/8287 data bus transceiver. It is used to control the direction of

 

 

 

 

 

 

 

 

 

 

data flow through the transceiver. Logically DT/R is equivalent to S1 in the

 

 

 

 

 

 

 

 

 

 

maximum mode, and its timing is the same as for M/IO. (T e HIGH, R e

 

 

 

 

 

 

 

 

 

 

LOW.) This signal floats to 3-state OFF in local bus ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEN

26

O

DATA ENABLE: provided as an output enable for the 8286/8287 in a

 

 

 

 

 

 

 

 

 

 

minimum system which uses the transceiver. DEN is active LOW during

 

 

 

 

 

 

 

 

 

 

each memory and I/O access and for INTA cycles. For a read or INTA cycle

 

 

 

 

 

 

 

 

 

 

it is active from the middle of T2 until the middle of T4, while for a write cycle

 

 

 

 

 

 

 

 

 

 

it is active from the beginning of T2 until the middle of T4. DEN floats to 3-

 

 

 

 

 

 

 

 

 

 

state OFF in local bus ``hold acknowledge''.

 

 

 

 

 

 

 

 

 

 

HOLD,

31, 30

I/O

HOLD: indicates that another master is requesting a local bus ``hold.'' To be

 

HLDA

 

 

acknowledged, HOLD must be active HIGH. The processor receiving the

 

 

 

 

 

 

 

 

 

 

``hold'' request will issue HLDA (HIGH) as an acknowledgement in the

 

 

 

 

 

 

 

 

 

 

middle of a T4 or Ti clock cycle. Simultaneous with the issuance of HLDA

 

 

 

 

 

 

 

 

 

 

the processor will float the local bus and control lines. After HOLD is

 

 

 

 

 

 

 

 

 

 

detected as being LOW, the processor will LOWer the HLDA, and when the

 

 

 

 

 

 

 

 

 

 

processor needs to run another cycle, it will again drive the local bus and

 

 

 

 

 

 

 

 

 

 

control lines. Hold acknowledge (HLDA) and HOLD have internal pull-up

 

 

 

 

 

 

 

 

 

 

resistors.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The same rules as for RQ/GT apply regarding when the local bus will be

 

 

 

 

 

 

 

 

 

 

released.

 

 

 

 

 

 

 

 

 

 

HOLD is not an asynchronous input. External synchronization should be

 

 

 

 

 

 

 

 

 

 

provided if the system cannot otherwise guarantee the setup time.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

8086

FUNCTIONAL DESCRIPTION

General Operation

The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure 1.

These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.

The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the BIU will attempt a word fetch memory cycle. This greatly reduces ``dead time'' on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

The execution unit receives pre-fetched instructions from the BIU queue and provides un-relocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage. See the Instruction Set description for further register set and architectural descriptions.

MEMORY ORGANIZATION

The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million

bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each, with each segment falling on 16-byte boundaries. (See Figure 3a.)

All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to the rules of the following table. All information in one segment type share the same logical attributes (e.g. code or data). By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured.

Word (16-bit) operands can be located on even or odd address boundaries and are thus not constrained to even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location. The BIU automatically performs the proper number of memory accesses, one if the word operand is on an even byte boundary and two if it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the software. This performance penalty does not occur for instruction fetches, only word operands.

Physically, the memory is organized as a high bank

(D15 ± D8) and a low bank (D7 ± D0) of 512K 8-bit bytes addressed in parallel by the processor's ad-

dress lines A19 ± A1. Byte data with even addresses is transferred on the D7 ± D0 bus lines while odd addressed byte data (A0 HIGH) is transferred on the D15 ± D8 bus lines. The processor provides two enable signals, BHE and A0, to selectively allow reading from or writing into either an odd byte location, even byte location, or both. The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary.

Memory

Segment Register

Segment

Reference Need

Used

Selection Rule

 

 

 

Instructions

CODE (CS)

Automatic with all instruction prefetch.

 

 

 

Stack

STACK (SS)

All stack pushes and pops. Memory references relative to BP

 

 

base register except data references.

 

 

 

Local Data

DATA (DS)

Data references when: relative to stack, destination of string

 

 

operation, or explicitly overridden.

 

 

 

External (Global) Data

EXTRA (ES)

Destination of string operations: explicitly selected using a

 

 

segment override.

 

 

 

6

231455 ± 3

Figure 3a. Memory Organization

In referencing word data the BIU requires one or two memory cycles depending on whether or not the starting byte of the word is on an even or odd address, respectively. Consequently, in referencing word operands performance can be optimized by locating data on even address boundaries. This is an especially useful technique for using the stack, since odd address references to the stack may adversely affect the context switching time for interrupt processing or task multiplexing.

231455 ± 4

Figure 3b. Reserved Memory Locations

Certain locations in memory are reserved for specific CPU operations (see Figure 3b). Locations from

8086

address FFFF0H through FFFFFH are reserved for operations including a jump to the initial program loading routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt types has its service routine pointed to by a 4-byte pointer element consisting of a 16-bit segment address and a 16-bit offset address. The pointer elements are assumed to have been stored at the respective places in reserved memory prior to occurrence of interrupts.

MINIMUM AND MAXIMUM MODES

The requirements for supporting minimum and maximum 8086 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins. Consequently, the 8086 is equipped with a strap pin (MN/MX) which defines the system configuration. The definition of a certain subset of the pins changes dependent on the condition of the strap pin. When MN/MX pin is strapped to GND, the 8086 treats pins 24 through 31 in maximum mode. An 8288 bus controller interprets status information coded into S0, S2, S2 to generate bus timing and control signals compatible with the MULTIBUS architecture. When the MN/MX pin is strapped to VCC, the 8086 generates bus control signals itself on pins 24 through 31, as shown in parentheses in Figure 2. Examples of minimum mode and maximum mode systems are shown in Figure 4.

BUS OPERATION

The 8086 has a combined address and data bus commonly referred to as a time multiplexed bus. This technique provides the most efficient use of pins on the processor while permitting the use of a standard 40-lead package. This ``local bus'' can be buffered directly and used throughout the system with address latching provided on memory and I/O modules. In addition, the bus can also be demultiplexed at the processor with a single set of address latches if a standard non-multiplexed bus is desired for the system.

Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4 (see Figure 5). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a ``NOT READY'' indication is given by the addressed device, ``Wait'' states (TW) are inserted between T3 and T4. Each inserted ``Wait'' state is of the same duration as a CLK cycle. Periods

7

8086

231455 ± 5

Figure 4a. Minimum Mode 8086 Typical Configuration

231455 ± 6

Figure 4b. Maximum Mode 8086 Typical Configuration

8

can occur between 8086 bus cycles. These are referred to as ``Idle'' states (Ti) or inactive CLK cycles. The processor uses these cycles for internal housekeeping.

During T1 of any bus cycle the ALE (Address Latch Enable) signal is emitted (by either the processor or the 8288 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched.

Status bits S0, S1, and S2 are used, in maximum mode, by the bus controller to identify the type of bus transaction according to the following table:

 

 

 

 

 

 

 

 

 

 

8086

 

 

 

 

 

 

 

 

 

 

 

 

S2

S1

S0

Characteristics

0

(LOW)

0

 

0

 

Interrupt Acknowledge

 

 

 

 

 

 

 

 

 

0

 

 

 

0

 

1

 

Read I/O

 

 

 

 

 

 

 

 

 

0

 

 

 

1

 

0

 

Write I/O

 

 

 

 

 

 

 

 

 

0

 

 

 

1

 

1

 

Halt

 

 

 

 

 

 

 

1

(HIGH)

0

 

0

 

Instruction Fetch

 

 

 

 

 

 

 

 

 

1

 

 

 

0

 

1

 

Read Data from Memory

 

 

 

 

 

 

 

 

 

1

 

 

 

1

 

0

 

Write Data to Memory

 

 

 

 

 

 

 

 

 

1

 

 

 

1

 

1

 

Passive (no bus cycle)

 

 

 

 

 

 

 

 

 

 

 

231455 ± 8

Figure 5. Basic System Timing

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