Intel 80286, 80287 User Manual

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Customer Support is Intel's complete support service that provides Intel customers with hardware support, software support, customer training, and consulting services. For more information contact your local sales offices.

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80286 AND 80287 PROGRAMMER'S REFERENCE MANUAL

1987

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PREFACE

This manual describes the 80286, the most powerful 16-bit microprocessor in the 8086 family, and the 80287 Numeric Processor Extension (NPX).

ORGANIZATION OF THIS MANUAL

This manual is, essentially, two books in one. The first book describes the 80286, the second the 80287 NPX.

80286

The 80286 contains a table of contents, eleven chapters, four appendices, and an index. For more information on the 80286 book's organization, see its first chapter, Chapter 1, "Introduction to the 80286." Section 1.4 in that chapter explains the organization in detail.

80287 NPX

The 80287 NPX contains a preface, table of contents, four chapters, three appendices, and a glossary. For more information on the 80287 NPX book's organization, see its preface.

iii

TABLE OF CONTENTS
CHAPTER 1		Page
INTRODUCTION TO THE 80286
General Attributes ... ......................................................	.................................................	1-1
Modes of Operation ........................................................................	...............................	1-2
Advanced Features ........................................................................................................		1-2
Memory Management .................................................................................................		1-2
Task Management ......................................................................................................		1-3
Protection Mechanisms ..............................................................................................		1-3
Support for Operating Systems .................................................................................		1-4
Organization of This Book .............................................................................................		1-4
Related Publications .......................................................................	................................	1-6
CHAPTER 2
80286 BASE ARCHITECTURE
Memory Organization and Segmentation ......................................................................		2-1
Data Types ........................................................................................................	.............	2-1
Registers .........................................................................................................................		2-7
General Registers .......................................................................................................		2-7
Memory Segmentation and Segment Registers ..........	, .............................................	2-8
Index, Pointer, and Base Registers ...........................................................................		2-9
Status and Control Registers .....................................................................................		2-14
Addressing Modes .........................................................................................................		2-16
Operands .........................................................................................	...........................	2-16
Register and Immediate Modes ................................................................	.................	2-17
Memory Addressing Modes .......................................................................................		2-17
Segment Selection ....................................................................................	..............	2-18
Offset Computation .................................................................................................		2-19
Memory Mode .........................................................................................................		2-20
Input/Output ...................................................................................................................		2-21
I/O Address Space ...................................................................	..................................	2-23
Memory-Mapped I/O ..................................................................................................		2-23
Interrupts and Exceptions ..............................................................................................		2-24
Hierarchy of Instruction Sets .........................................................................................		2-25
CHAPTER 3
BASIC INSTRUCTION SET
Data Movement Instructions ..........................................................................................		3-1
General-Purpose Data Movement Instructions .........................................................		3-1
Stack Manipulation Instructions .................................................................................		3-2
Flag Operation with the Basic Instruction Set ...............................................................		3-4
Status Flags ................................................................................................................		3-4
Control Flags ...............................................................................................................		3-4
Arithmetic Instructions ...................................................................................................		3-5
Addition Instructions ...................................................................................................		3-7
Subtraction Instructions .............................................................................................		3-7
Multiplication Instructions ...........................................................................................		3-8
Division Instructions ...................................................................................................		3-9
Logical Instructions ........................................................................................................		3-9
Boolean Operation Instructions .................................................................................		3-9
Shift and Rotate Instructions ......................................................................................		3-10
Shift Instructions .....................................................................................................		3-10

v

TABLE OF CONTENTS
	Page
Rotate Instructions ..................................................................................................	3-13
Type Conversion and No-Operation Instructions ......................................................	3-16
Test and Compare Instructions .....................................................................................	3-16
Control Transfer Instructions .........................................................................................	3-16
Unconditional Transfer Instructions ...........................................................................	3-17
Jump Instruction .....................................................................................................	3-17
Call Instruction ........................................................................................................	3-18
Return and Return from Interrupt Instruction ........................................................	3-19
Conditional Transfer Instructions ...............................................................................	3-19
Conditional Jump Instructions ................................................................................	3-20
Loop Instructions ....................................................................................................	3-20
Executing a Loop or Repeat Zero Times ...............................................................	3.-21
Software-Generated Interrupts ..................................................................................	3-21
Software Interrupt Instruction .................................................................................	3-21
Character Translation and String Instructions ..............................................................	3-22
Translate Instruction ...................................................................................................	3-22
String Manipulation Instructions and Repeat Prefixes ..............................................	3-22
String Movement Instructions ................................................................................	3-23
Other String Operations ..........................................................................................	3-23
Address Manipulation Instructions ................................................................................	3-24
Flag Control Instructions ................................................................................................	3-25
Carry Flag Control Instructions ..................................................................................	3-25
Direction Flag Control Instructions ............................................................................	3-25
Flag Transfer Instructions ..........................................................................................	3-26
Binary-Coded Decimal Arithmetic Instructions .............................................................	3-27
Packed BCD Adjustment Instructions ........................................................................	3-27
Unpacked BCD Adjustment Instructions ...................................................................	3-27
Trusted Instructions ... ....................................................................................................	3-28
Trusted and Privileged Restrictions on POPF and IRET ..........................................	3-28
Machine State Instructions .........................................................................................	3-28
Input and Output Instructions ....................................................................................	3-29
Processor Extension Instructions ..................................................................................	3-29
Processor Extension Synchronization Instructions ..................................................	3-30
Numeric Data Processor Instructions ........................................................................	3-30
Arithmetic Instructions ............................................................................................	3-30
Comparison Instructions .........................................................................................	3-30
Transcendental Instructions ...................................................................................	3-30
Data Transfer Instructions ......................................................................................	3-31
Constant Instructions ..............................................................................................	3-31
CHAPTER 4
EXTENDED INSTRUCTION SET
Block I/O Instructions ......................................................................................................	4-1
High-Level Instructions ....................................................................................................	4-2
CHAPTER 5
REAL ADDRESS MODE
Addressing and Segmentation .......................................................................................	5-1
Interrupt Handling ...........................................................................................................	5-3
Interrupt Vector Table .................................................................................................	5-3
Interrupt Priorities ...................................................................................................	5-4
Interrupt Procedures ...................................................................................................	5-5

vi

TABLE OF CONTENTS

	Page
Reserved and Dedicated Interrupt Vectors ...............................................................	5-5
System Initialization ........................................................................................................	5-7
CHAPTER 6
MEMORY MANAGEMENT AND VIRTUAL ADDRESSING
Memory Management Overview ....................................................................................	6-1
Virtual Addresses ...........................................................................................................	6-2
Descriptor Tables ...........................................................................................................	6-4
Virtual-to-Physical Address Translation ........................................................................	6-6
Segments and Segment Descriptors .............................................................................	6-7
Memory Management Registers ...................................................................................	6-9
Segment Address Translation Registers ...................................................................	6-9
System Address Registers .........................................................................................	6-12
CHAPTER 7
PROTECTION
Introduction .....................................................................................................................	7-1
Types of Protection ....................................................................................................	7-1
Protection Implementation .........................................................................................	7-2
Memory Management and Protection ...........................................................................	7-4
Separation of Address Spaces ..................................................................................	7-5
LDT and GDT Access Checks ...................................................................................	7-5
Type Validation ...........................................................................................................	7-6
Privilege Levels and Protection .....................................................................................	7-8
Example of Using Four Privilege Levels ....................................................................	7-8
Privilege Usage ...........................................................................................................	7-9
Segment Descriptor .......................................................................................................	7-10
Data Accesses ............................................................................................................	7-12
Code Segment Access ...............................................................................................	7-13
Data Access Restriction by Privilege Level ...............................................................	7-13
POinter Privilege Stamping via ARPL .........................................................................	7-14
Control Transfers ...........................................................................................................	7-15
Gates ...........................................................................................................................	7-16
Call Gates ................................................................................................................	7-17
Intra-Level Transfers via Call Gate .........................................................................	7-18
Inter-Level Control Transfer via Call Gates ............................................................	7-19
Stack Changes Caused by Call Gates ...................................................................	7-20
Inter-Level Returns .....................................................................................................	7-20
CHAPTERS
TASKS AND STATE TRANSITIONS
Introduction .....................................................................................................................	8-1
Task State Segments and Descriptors ..........................................................................	8-1
Task State Segment Descriptors ...............................................................................	8-3
Task Switching ...............................................................................................................	8·4
Task Linking ...................................................................................................................	8-7
Task Gates .....................................................................................................................	8-8
CHAPTER 9
INTERRUPTS AND EXCEPTIONS
Interrupt Descriptor Table ..............................................................................................	9-1
Hardware Initiated Interrupts .........................................................................................	9-2

vii

TABLE OF CONTENTS
		Page
Software Initiated Interrupts ..........................................................................................		9-3
Interrupt Gates and Trap Gates .....................................................................................		9-3
Task Gates and Interrupt Tasks ....................................................................................		9-7
Scheduling Considerations ................................................................	.........................	9-8
Deciding Between Task, Trap, and Interrupt Gates ................................	..................	9-8
Protection Exceptions and Reserved Vectors ..............................................................		9-9
Invalid OP-Code (Interrupt 6) ......................................................................................		9-10
Double Fault (Interrupt 8) ............................................................................................		9-10
Processor Extension Segment Overrun (Interrupt 9) ................................................		9-10
Invalid Task State Segment (Interrupt 10) .................................................................		9-11
Not Present (Interrupt 11) ...........................................................................................		9-11
Stack Fault (Interrupt 12) ............................................................................................		9-12
General Protection Fault (Interrupt 13) ......................................................................		9-13
Additional Exceptions and Interrupts ............................................................................		9-13
Single Step Interrupt (Interrupt 1) ..............................................................................		9-14
CHAPTER 10
SYSTEM CONTROL AND INITIALIZATION
System Flags and Registers ............................................................................	............	10-1
Descriptor Table Registers .......................................................................................		10-1
System Control Instructions ........................................................................................		10-3
Machine Status Word ...............................................................................................		10-4
Other Instructions .....................................................................................................		10-5
Privileged and Trusted Instructions .............................................................................		10-5
Initialization ...................................................................................................................		10-6
Real Address Mode ..................................................................................................		10-7
Protected Mode ........................................................................................................		10-7
CHAPTER 11
ADVANCED TOPICS
Virtual Memory Management ..............................................................................	.........	11-1
Special Segment Attributes ...................................... ....................................................		11-1
Conforming Code Segments ....................................................................................		11-1
Expand-Down Data Segments .........................................................................	........	11-2
Pointer Validation .........................................................................................................		11-3
Descriptor Validation ................................................................................................		11-4
Pointer Integrity: RPL and the "Trojan Horse Problem" ........................................		11-4
NPX Context Switching ................................................................................................		11-5
Multiprocessor Considerations .............................................................	.......................	11-5
Shutdown .............................................................................................	;........................	11-7

APPENDIX A

80286 SYSTEM INITIALIZATION

APPENDIX B

THE 80286 INSTRUCTION SET

APPENDIX C

8086/8088 COMPATIBILITY CONSIDERATIONS

APPENDIX D

80286/80386 SOFTWARE COMPATIBILITY CONSIDERATIONS

INDEX

viii

TABLE OF CONTENTS

Figures

Figure		Title				Page
1-1	Four Privilege Levels	.....................................	........................	..............	....................	1-4
2-1	Segmented Virtual Memory ..........................................		.................	..........................		2-2
2-2	Bytes and Words in Memory...................................................................................					2-3
2-3	80286/80287 Supported Data Types ............................		..............	............................		2-5
2-4	80286 Base Architecture Register Set ...................................................................					2-7
2-5	Real Address Mode Segment Selector Interpretation ...........................................					2-9
2-6	Protected Mode Segment Selector Interpretation .................................................					2-10
2-7	80286 Stack .............................................................................................................					2-11
2-8	Stack Operation .......................................................................................................					2-12
2-9	BP Usage as a Stack Frame Base Pointer .............................................................					2-13
2-10	Flags Register ..........................................................................................................					2-15
2-11	Two-Component Address .......................................................................................					2-18
2-12	Use of Memory Segmentation ......................		:.........................................................			2-20
2-13	Complex Addressing Modes ...................................................................................					2-22
2-14	Memory-Mapped I/O	................................................................................................				2-24
2-15	Hierarchy of Instructions .........................................................................................					2-27
3-1	PUSH .......................	:...............................................................................................				3-2
3-2	PUSHA......................................................	....................	........................	...................		3-3
3-3	POP ..........................................................................................................................					3-4
3-4	POPA ........................................................................................................................					3-5
3-5	Flag Word Contents ..................................	.......................................		........................		3-6
3-6	SAL and SHL ...........................................................................................................					3-11
3-7	SHR ..........................................................................................................................					3-12
3-8	SAR ..........................................................................................................................					3-12
3-9	ROL ..........................................................................................................................					3-13
3-10	ROR .........................................................................................................................					3-14
3-11	RCL ..........................................................................................................................					3-15
3-12	RCR ..........................................................................................................................					3-15
3-13	LAHF and SAHF ......................................................................................................					3-26
3-14	PUSHF and POPF ...................................................................................................					3-27
4-1	Formal Definition of the ENTER Instruction ...........................................................					4-3
4-2	Variable Access in Nested Procedures ..................................................................					4-4
4-2a	Stack Frame for MAIN at Level 1 ............................................................................					4-4
4-2b	Stack Frame for Procedure A .....................................		..................	..........................		4-5
4-2c	Stack Frame for Procedure B at Level 3 Called from A ....... ................................			:		4-5
4-2d	Stack Frame for Procedure C at Level 3 Called from B ........................................					4-6
5-1 a	Forming the Segment Base Address ..........................		........................	....................		5-2
5-1 b	Forming the 20-Bit Physical Address in the Real Address Mode .........................					5-2
5-2	Overlapping Segments to Save Physical Memory ........................			.........................		5-3
5-3	Interrupt Vector Table for Real Address Mode ......................................................					5-4
5-4	Stack Structure after Interrupt (Real Address Mode) .......................................			....	:	5-5
6-1	Format of the Segment Selector Component		........................................................			6-2
6-2	Address Spaces and Task Isolation .......................................................................					6-3
6-3	Segment Descriptor (S = 1) ..............................		............................	...........................		6-5
6-4	Special Purpose Descriptors or System Segment Descriptors (S=O) .................					6-6
6-5	LDT Descriptor ........................................................................................................					6-7
6-6	Virtual-to-Physical Address Translation ............		........................	.............................		6-8
6-7	Segment Descriptor Access Bytes .........................................................................					6-9
6-8	Memory Management Registers .............................................................................					6-10
6-9	Descriptor Loading ..................................................................................................					6-11

ix

	TABLE OF CONTENTS
Figure	Title		Page
7-1	Addressing Segments of a Module within a Task ..................................................		7-3
7-2	Descriptor Cache Registers .............................................................	'"....................	7-4
7-3	80286 Virtual Address Space ........................................................	..........................	7-6
7-4	Local and Global Descriptor Table Definitions .......................................................		7-7
7-5	Error Code Format (on the stack) ...........................................................................		7-7
7-6	Code and Data Segments Assigned to a Privilege Level ...............	........................	7-9
7-7	Selector Fields .........................................................................................................		7-11
7-8	Access Byte Examples ..............................................................................................		7-12
7-9	Pointer Privilege Stamping ......................................................................................		7-15
7-10	Gate Descriptor Format ...........................................................................................		7-17
7-11	Call Gate ..................................................................................................................		7-19
7-12	Stack Contents after an Inter-Level Call .................................................................		7-21
8-1	Task State Segment and TSS Registers ................................................................		8-2
8-2	TSS Descriptor ............................................................................................	............	8-4
8-3	Task Gate Descriptor ..............................................................................................		8-8
8-4	Task Switch Through a Task Gate .........................................................................		8-9
9-1	Interrupt Descriptor Table Definition ......................................................................		9-1
9-2	IDT Selector Error Code ..........................................................................................		9-2
9-3	Trap/Interrupt Gate Descriptors .............................................................................		9-4
9-4	Stack Layout after an Exception with an Error Code ..................	..........................	9-5
10-1	Local and Global Descriptor Table Definition .........................................................		10-2
10-2	Interrupt Descriptor Table Definition ......................................................................		10-2
10-3	Data Type for Global Descriptor Table and Interrupt Descriptor Table ................		10-3
11-1	Expand-Down Segment .....................................................................	.....................	11-2
11-2	Dynamic Segment Relocation and Expansion of Segment Limit	..........................	11-3
11-3	Example of NPX Context Switching .......................................................................		11-6
B-1	In Instruction Byte Format ......................................................................................		B-2
B-2	Ir Instruction Byte Format .......................................................................................		B-4
	Tables
Table	Title		Page
2-1	Implied Segment Usage by Index, Pointer, and Base Registers ...........................		2-14
2-2	Segment Register Selection Rules ..................................................	.......................	2-19
2-3	Memory Operand Addressing Modes ....................................................................		2-21
2-4	80286 Interrupt Vector Assignments (Real Address Mode) ..................................		2-26
3-1	Status Flags'Functions ...........................................................................................		3-6
3-2	Control Flags'Functions .........................................................................................		3-7
3-3	Interpretation of Conditional Transfers ..................................................................		3-20
5-1	Interrupt Processing Order .....................................................................................		5-4
5-2	Dedicated and Reserved Interrupt Vectors in Real Address Mode ......................		5-6
5-3	Processor State after RESET ......................................................	:..........................	5-7
7-1	Segment Access Rights Byte Format '"..............................................	....................	7-11
7-2	Allowed Segment Types in Segment Registers ..........................	;..........................	7-12
7-3	Call Gate Checks .....................................................................................................		7-18
7-4	Inter-Level Return Checks ......................................................................................		7-22
8-1	Checks Made during a Task Switch .......................................................................		8-6
8-2	Effect of a Task Switch on BUSY and NT Bits and the Link Word .......................		8-7
9-1	Trap and Interrupt Gate Checks .............................................................................		9-6
9-2	Interrupt and Gate Interactions ...............................................................................		9-7

x

	TABLE OF CONTENTS
Table	Title	Page
9-3	Reserved Exceptions and Interrupts ......................................................................	9-9
9-4	Interrupt Processing Order ... ..................................................................................	9-9
9-5	Conditions That Invalidate the TSS ........................................................................	9-12
10-1	MSW 8it Functions ..................................................................................................	10-4
10-2	Recommended MSW Encodings for Processor Extension Control......................	10-5
11-1	NPXContextSwitching ...........................................................................................	11-7
8-1	ModRM Values ........................................................................................................	8-3
8-2	Protection Exceptions of the 80286 .............. ....................... ....................... ............	8-8
8-3	Hexadecimal Values for the Access Rights 8yte ...................................................	8-14
C-1	New 80286 Interrupts ..............................................................................................	C-1

xi

inter

CUSTOMER SUPPORT

CUSTOMER SUPPORT

Customer Support is Intel's complete support service that provides Intel customers with hardware support, software support, customer training, and consulting services. For more information contact your local sales offices.

After a customer purchases any system hardware or software product, service and support become major factors in determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. As you might expect, Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices providing hardware repair services, software support services, customer training classes, and consulting services.

HARDWARE SUPPORT SERVICES

Intel is committed to providing an international service support package through a wide variety of service offerings available from Intel Hardware Support.

SOFfWARE SUPPORT SERVICES

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Introduction to the 80286

1

CHAPTER 1

INTRODUCTION TO THE 80286

The 80286 is the most powerful 16-bit processor in the 8086 series of microprocessors, which includes the 8086, the 8088, the 80186, the 80188, and the 80286. It is designed for applications that require very high performance. It is also an excellent choice for sophisticated "high end" applications that will benefit from its advanced architectural features: memory management, protection mechanisms, task management, and virtual memory support. The 80286 provides, on a single VLSI chip, computational and architectural characteristics normally associated with much larger minicomputers.

Sections 1.1, 1.2, and 1.3 of this chapter provide an overview of the 80286 architecture. Because the 80286 represents an extension of the 8086 architecture, some of this overview material may be new and unfamiliar to previous users of the 8086 and similar microprocessors. But the 80286 is also an evolutionary development, with the new architecture superimposed upon the industry standard 8086 in such a way as to affect only the design and programming of operating systems and other such system softwar~. Section 1.4 of this chapter provides a guide to the organization of this manual, suggesting which chapters are relevant to the needs of particular readers.

1.1 GENERAL ATTRIBUTES

The 80286 base architecture has many features in common with the architecture of other members of the 8086 family, such as byte addressable memory, I/O interfacing hardware, interrupt vectoring, and support for both multiprocessing and processor extensions. The entire family has a common set of addressing modes and basic instructions. The 80286 base architecture also includes a number of extensions which add to the versatility of the computer.

The 80286 processor can function in two modes of operation (see section 1.2 of this chapter, Modes of Operation). In one of these modes only the base architecture is available to programmers, whereas in the other mode a number of very powerful advanced features have been added, including support for virtual memory, multitasking, and a sophisticated protection mechanism. These advanced features are described in section 1.3 of this chapter.

The 80286 base architecture was designed to support programming in high-level languages, such as Pascal, C or PL/M. The register set and instructions are well suited to compiler-generated code. The addressing modes (see section 2.6.3 in Chapter 2) allow efficient addressing of complex data structures, such as static and dynamic arrays, records, and arrays within records, which are commonly supported by high-level languages. The data types supported by the architecture include, along with bytes and words, high level language constructs such as strings, BCD, and floating point.

The memory architecture of the 80286 was designed to support modular programming techniques. Memory is divided into segments, which may be of arbitrary size, that can be used to contain procedures and data structures. Segmentation has several advantages over more conventional linear memory architectures. It supports structured software, since segments can contain meaningful program units and data, and more compact code, since references within a segment can be shorter (and locality of reference usually insures that the next few references will be within the same segment). Segmentation also lends itself to efficient implementation of sophisticated memory management, virtual memory, and memory protection.

In addition, new instructions have been added to the base architecture to give hardware support for procedure invocations, parameter passing, and array bounds checking.

1-1

INTRODUCTION TO THE 80286

1.2 MODES OF OPERATION

The 80286 can be operated in either of two different modes: Real Address Mode or Protected Virtual Address Mode (also referred to as Protected Mode). In either mode of operation, the 80286 represents an upwardly compatible addition to the 8086 family of processors.

In Real Address Mode, the 80286 operates essentially as a very high-performance 8086. Programs written for the 8086 or the 80186 can be executed in this mode without any modification (the few exceptions are described in Appendix C, "Compatibility Considerations"). Such upward compatibility extends even to the object code level; for example, an 8086 program stored in read-only memory will execute successfully in 80286 Real Address Mode. An 80286 operating in Real Address Mode provides a number of instructions not found on the 8086. These additional instructions, also present with the 80186, allow for efficient subroutine linkage, parameter validation, index calculations, and block 1/0 transfers.

The advanced architectural features and full capabilities of the 80286 are realized in its native Protected Mode. Among these features are sophisticated mechanisms to support data protection, system integrity, task concurrency, and memory management, including virtual storage. Nevertheless, even in Protected Mode, the 80286 remains upwardly compatible with most 8086 and 80186 application programs. Most 8086 applications programs can be re-compiled or re-assembled and executed on the 80286 in Protected Mode.

1.3 ADVANCED FEATURES

The architectural features described in section 1.1 of this chaper are common to both operating modes of the processor. In addition to these common features, Protected Mode provides a number of advanced features, including a greatly extended physical and logical address space, new instructions, and support for additional hardware-recognized data structures. The Protected Mode 80286 includes a sophisticated memory management and multilevel protection mechanism. Full hardware support is included for multitasking and task switching operations.

1.3.1 Memory Management

The memory architecture of the Protected Mode 80286 represents a significant advance over that of the 8086. The physical address space has been increased froml megabyte to 16 megabytes (224 byies), while the virtual address space (i.e., the address space visible to a program) has been increased from 1 megabyte to 1 gigabyte (230 bytes). Moreover, separate virtual address spaces are provided for each task in a multi-tasking system (see the next section, 1.3.2, "Task Management").

The 80286 supports on-chip memory management instead of relying on an external memory management unit. The one-chip solution is preferable because no software is required to manage an external memory management unit, performance is much better, and hardware designs are significantly simpler.

Mechanisms have been included in the 80286 architecture to allow the efficient implementation of virtual memory systems. (In virtual memory systems, the user regards the combination of main and external storage as a single large memory. The user can write large programs without worrying about the physical memory limitations of the system. To accomplish this, the operating system places some of the user programs and data in external storage and brings them into main memory only as they are needed.) All instructions that can cause a segment-riot-present fault are fully restartable. Thus, a notpresent segment can be loaded from external storage, and the task can be restarted at the point where the fault occurred.

1-2

INTRODUCTION TO THE 80286

The 80286, like all members of the 8086 series, supports a segmented memory architecture. The 80286 also fully integrates memory segmentation into a comprehensive protection scheme. This protection scheme includes hardware-enforced length and type checking to protect segments from inadvertent misuse.

1.3.2 Task Management

The 80286 is designed to support multi-tasking systems. The architecture provides direct support for the concept of a task. For example, task state segments (see section 8.2 in Chapter 8) are hardwarerecognized and hardware-manipulated structures that contain information on the current state of all tasks in the system.

Very efficient context-switching (task-switching) can be invoked with a single instruction. Separate logical address spaces are provided for each task in the system. Finally, mechanisms exist to support intertask communication, synchronization, memory sharing, and task scheduling. Task Management is described in Chapter 8.

1.3.3 Protection Mechanisms

The 80286 allows the system designer to define a comprehensive protection policy to be applied, uniformly and continuously, to all ongoing operations of the system. Such a policy may be desirable to ensure system reliability, privacy of data, rapid error recovery, and separation of multiple users.

The 80286 protection mechanisms are based on the notion of a "hierarchy of trust." Four privilege levels are distinguished, ranging from Level 0 (most trusted) to Level 3 (least trusted). Level 0 is usually reserved for the operating system kernel. The four levels may be visualized as concentric rings, with the most privileged level in the center (see figure 1-1).

This four-level scheme offers system reliability, flexibility, and design options not possible with the typical two-level (supervisorluser) separation provided by other processors. A four-level division is capable of separating kernel, executive, system services, and application software, each with different privileges.

At anyone time, a task executes at one of the four levels. Moreover, all data segments and code segments are also assigned to privilege levels. A task executing at one level cannot access data at a more privileged level, nor can it call a procedure at a less privileged level (i.e., trust a less privileged procedure to do work for it). Thus, both access to data and transfer of control are restricted in appropriate ways.

A complete separation can exist between the logical address spaces local to different tasks, providing users with automatic protection against accidental or malicious interference by other users. The hardware also provides immediate detection of a number of fault and error conditions, a feature that can be useful in the development and maintenance of software.

Finally, these protection mechanisms require relatively little system overhead because they are integrated into the memory management and protection hardware of the processor itself.

1-3

INTRODUCTION TO THE 80286

LEAST TRUSTED

MOST TRUSTED

G30108

Figure 1-1. Four Privilege Levels

1.3.4 Support for Operating Systems

Most operating systems involve some degree of concurrency, with multiple tasks vying for system resources. The task management mechanisms described above provide the 80286 with inherent support for such multi-tasking systems. Moreover, the advanced memory management features of the 80286 allow the implementation of sophisticated virtual memory systems.

Operating system implementors have found that a multi-level approach to system services provides better security and more reliable systems. For example, a very secure kernel might implement critical functions such as task scheduling and resource aiiocation, while less fundamenlal [ulictions (such as I/O) are built around the kernel. This layered approach also makes program development and enhancement simpler and facilitates error detection and debugging. The 80286 supports the layered approach through its four-level privilege scheme.

1.4 ORGANIZATION OF THIS BOOK

To facilitate the use of this book both as an introduction to the 80286 architecture and as a reference guide, the remaining chapters are divided into three major parts.

Part I, comprising chapters 2 through 4, should be read by all those who wish to acquire a basic familiarity with the 80286 architecture. These chapters provide detailed information on memory segmentation, registers, addressing modes and the general (application level) 80286 instruction set. In conjunction with the 80286 Assembly Language Reference Manual, these chapters provide sufficient information for an assembly language programmer to design and write application programs.

1-4

INTRODUCTION TO THE 80286

The chapters in Part I are:

Chapter 2, "Architectural Features." This chapter discusses those features of the 80286 architecture that are significant for application programmers. The information presented can also function as an introduction to the machine for system programmers. Memory organization and segmentation, processor registers, addressing modes, and instruction formats are all discussed.

Chapter 3, "Basic Instruction Set." This chapter presents the core instructions of the 8086 family.

Chapter 4, "Extended Instruction Set." This chapter presents the extended instructions shared by the 80186 and 80286 processors.

Part II of the book consists of a single chapter:

Chapter 5, "Real Address Mode." This chapter presents the system programmer's view of the 80286 when the processor is operated in Real Address Mode.

Part III of the book comprises chapters 6 through 11. Aimed primarily at system programmers, these chapters discuss the more advanced architectural features of the 80286, which are available when the processor is. in Protected Mode. Details on memory management, protection mechanisms, and task switching are provided.

The chapters in Part III are:

Chapter 6, "Virtual Memory." This chapter describes the 80286 address translation mechanisms that support virtual memory. Segment descriptors, global and local descriptor tables, and descriptor caches are discussed.

Chapter 7, "Protection." This chapter describes the protection features of the 80286. Privilege levels, segment attributes, access restrictions, and call gates are discussed.

Chapter 8, "Tasks and State Transitions." This chapter describes the 80286 mechanisms that support concurrent tasks. Context-switching, task state segments, task gates, and interrupt tasks are discussed.

Chapter 9, "Interrupts, Traps and Faults." This chapter describes interrupt and trap handling. Special attention is paid to the exception traps, or faults, which may occur in Protected Mode. Interrupt gates, trap gates, and the interrupt descriptor table are discussed.

Chapter 10, "System Control and Initialization." This chapter describes the actual instructions used to implement the memory management, protection, and task support features of the 80286. System registers, privileged instructions, and the initial machine state are discussed.

Chapter 11, "Advanced Topics." This chapter completes Part III with a description of several advanced topics, including special segment attributes and pointer validation.

1.5 RELATED PUBLICATIONS

The following manuals also contain information of interest to programmers of 80287 systems:

Introduction to the 80286, order number 210308

ASM286 Assembly Language Reference Manual, order number 121924

80286 Operating System Writer's Guide, order number 121960

1-5

inter

INTRODUCTION TO THE 80286

80286 Hardware Reference Manual, order number 210760

Microprocessor and Peripheral Handbook, order number 230843

PL/M-286 User's Guide, order number 121945

80287 Support Library Reference Manual, order number 122129

8086 Software Toolbox Manual, order number 122203 (includes information about 80287 Emulator Software)

1-6

80286 Base Architecture

2

CHAPTER 2

80286 BASE ARCHITECTURE

This chapter describes the 80286 application programming environment as seen by assembly language programmers. It is intended to introduce the programmer to those features of the 80286 architecture that directly affect the design and implementation of 80286 application programs.

2.1 MEMORY ORGANIZATION AND SEGMENTATION

The main memory of an 80286 system makes up its physical address space. This address space is organized as a sequence of 8-bit quantities, called bytes. Each byte is assigned a unique address ranging from 0 up to a maximum of 220 (1 megabyte) in Real Address Mode, and up to 224 (16 megabytes) in Protected Mode. .

A virtual address space is the organization of memory as viewed by a program. Virtual address space is also organized in units of bytes. (Other addressable units such as words, strings, and BCD digits are described below in section 2.2, "Data Types.") In Real Address Mode, as with the 8086 itself, programs view physical memory directly, inasmuch as they manipulate pure physical addresses. Thus, the virtual address space is identical to the physical address space (1 megabyte).

In Protected Mode, however, programs have no direct access to physical addresses. Instead, memory is viewed as a much larger virtual address space of 230 bytes (1 gigabyte). This 1 gigabyte virtual address is mapped onto the Protected Mode's 16-megabyte physical address space by the address translation mechanisms described in Chapter 6.

The programmer views the virtual address space on the 80286 as a collection of up to sixteen thousand linear subspaces, each with a specified size or length. Each of these linear address spaces is called a segment. A segment is a logical unit of contiguous memory. Segment sizes may range from one byte up to 64K (65,536) bytes.

80286 memory segmentation supports the logical structure of programs and data iq memory. Programs are not written as single linear sequences of instructions and data, but rather as modules of code and data. For example, program code may include a main routine and several separate procedures. Data may also be organized into various data structures, some private and some shared with other programs in the system. Run-time stacks constitute yet another data requirement. Each of these several modules of code and data, moreover, may be very different in size or vary dynamically with program execution.

Segmentation supports this logical structure (see figure 2-1). Each meaningful module of a program may be separately contained in individual segments. The degree of modularization, of course, depends on the requirements of a particular application. Use of segmentation benefits almost all applications. Programs execute faster and require less space. Segmentation also simplifies the design of structured software.

2.2 DATA TYPES

Bytes and words are the fundamental units in which the 80286 manipulates data, i.e., the fundamental data types.

2-1

80286 BASE ARCHITECTURE

	r--------	,
	20000 CS	8000 r-----..,
	MAIN		8600 r-----.,
		PROCEDURE
	PROCEDURE	A
	0 _____...
		_____I	0'"-____..1
		7253051	DATA (B)
		DATA (A)
	0 _____...	L..-__-- I	0 I..____--1
	2000 ~----..,
	o ___ ...

O~""';""';_ __I

L _______ ...J

CURRENTLY

ACCESSIBLE

G3010B

Figure 2-1. Segmented Virtual Memory

A byte is 8 contiguous bits starting on an addressable byte boundary. The bits are numbered 0 through 7, starting from the right. Bit 7 is the most significant bit:

o

I I i

BYTE

,I

A word is defined as two contiguous bytes starting on an arbitrary byte boundary; a word thus contains 16 bits. The bits are numbered 0 through 15, starting from the right. Bit 15 is the most significant bit. The byte containing bit 0 of the word is called the low byte; the byte containing bit 15 is called the high byte.

15	0
I : :~IGH:B+: : I : :+W:BY+: : I
LOCATION N+1	LOCATION N

2-2

80286 BASE ARCHITECTURE

Each byte within a word has its own particular address, and the smaller of the two addresses is used as the address of the word. The byte at this lower address contains the eight least significant bits of the word, while the byte at the higher address contains the eight most significant bits. The arrangement of bytes within words is illustrated in figure 2-2.

Note that a word need not be aligned at an even-numbered byte address. This allows maximum flexibility in data structures (e.g., records containing mixed byte and word entries) and efficiency in memory utilization. Although actual transfers of data between the processor and memory take place at physically aligned word boundaries, the 80286 converts requests for unaligned words into the appropriate sequences of requests acceptable to the memory interface. Such odd aligned word transfers, however, may impact performance by requiring t'Yo memory cycles to transfer the word rather than one. Data structures (e.g., stacks) should therefore be designed in such a way that word operands are aligned on word boundaries whenever possible for maximum system performance. Due to instruction prefetching and queueing within the CPU, there is no requirement for instructions to be aligned on word boundaries and no performance loss if they are not.

Although bytes and words are the fundamental data types of operands, the processor also supports additional interpretations on these bytes or words. Depending on the instruction referencing the operand, the following additional data types can be recognized:

Integer:

A signed binary numeric value contained in an 8-bit byte or a 16-bit word. All operations assume a 2's complement representation. (Signed 32and 64-bit integers are supported using the 80287 Numeric Data Processor.)

BYTE	MEMORY
ADDRESS'	VALUES
'r		"
E
D
C	FE	WORD AT ADDRESS B
B	06	CONTAINS FE06
		I
A
		BYTE AT ADDRESS 9
9	1F	) CONTAINS 1F
8
7	23	WORD AT ADDRESS 6
6	OB	CONTAINS 230B
		I
5
4
3	74	WORD AT ADDRESS 2
	31
		I
		CONTAINS 74CB
2	CB	IWORD AT ADDRESS 1
		CONTAINS CB31
o		'NOTE:
		ALL VALUES IN HEXADECIMAL

G30108

Figure 2-2. Bytes and Words in Memory

2-3

80286 BASE ARCHITECTURE

Ordinal:

An unsigned binary numeric value contained in an 8-bit byte or 16-bit word.

Pointer:

A 32-bit address quantity composed of a segment selector component and an offset component. Each component is a 16-bit word.

String:

A contiguous sequence of bytes or words. A string may contain from 1 byte to 64K bytes.

ASCII:

A byte representation of alphanumeric and control characters using the. ASCII standard of character representation.

BCD:

A byte (unpacked) representation of the decimal digits (0-9).

Packed BCD:

A byte (packed) representation of two decimal digits (0-9). One digit is stored in each nibble of the byte.

Floating Point:

A signed 32-, 64-, or 80-bit real number representation. (Floating operands are supported using the 80287 Numeric Processor Configuration.)

Figure 2-3 graphically represents the data types supported by the 80286. 80286 arithmetic operations may be performed on five types of numbers: unsigned binary, signed binary (integers), unsigned pflcked decimal, unsigned unpacked decimal, and floating point. Binary numbers may be 8 or 16 bits long. Decimal numbers are stored in bytes; two digits per byte for packed decimal, one digit per byte for unpacked decimal. The processor always assumes that the operands specified in arithmetic instructions contain data that represent valid numbers for the type of instruction being performed. Invalid data may produce unpredictable results.

Unsigned binary numbers may be either 8 or 16 bits long; all bits are considered in determining a number's magnitude. The value range of an 8-bit unsigned binary number is 0-255; 16 bits can represent values from 0 through 65,535. Addition, subtraction, multiplication and division operations are available for unsigned binary numbers.

Signed binary numbers (integers) may be either 8 or 16 bits long. The high-order (leftmost) bit is interpreted as the number's sign: O=positive and 1= negative. Negative numbers are represented in standard two's complement notation. Since the high-order bit is used for a sign, the range of an 8-bit integer is -128 through +127; 16-bit integers may range from -.32,768 through +32,767. The value zero has a positive sign.

2-4