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Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH)
Datasheet
May 2014
328904-003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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Copyright © 2013–2014, Intel Corporation. All rights reserved.
2 |
Datasheet |
Contents
1 |
Introduction |
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41 |
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1.1 |
About This Manual............................................................................................. |
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41 |
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1.2 |
1.1.1 ............................................................................. |
Chapter Descriptions |
42 |
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Overview ......................................................................................................... |
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44 |
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1.3 |
1.2.1 ............................................................................... |
Capability Overview |
45 |
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Intel® 8 ...............................Series/C220 Series Chipset Family PCH SKU Definition |
52 |
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1.4 |
Device and ..............................................................................Revision ID Table |
57 |
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2 |
Signal Description ................................................................................................... |
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60 |
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2.1 |
Flexible ......................................................................................................I/O |
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62 |
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2.2 |
USB Interface ................................................................................................... |
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63 |
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2.3 |
PCI Express* .................................................................................................... |
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66 |
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2.4 |
Serial ATA ...........................................................................................Interface |
67 |
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2.5 |
Clock Signals .................................................................................................... |
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69 |
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2.6 |
Real Time ...................................................................................Clock Interface |
70 |
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2.7 |
External ........................................................................................RTC Circuitry |
71 |
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2.8 |
Interrupt ............................................................................................Interface |
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71 |
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2.9 |
Processor ............................................................................................Interface |
72 |
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2.10 |
Direct Media .....................................................Interface (DMI) to Host Controller |
72 |
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2.11 |
Intel® Flexible ........................................................Display Interface (Intel® FDI) |
73 |
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2.12 |
Analog .........................................................................Display/VGA DAC Signals |
73 |
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2.13 |
Digital Display ........................................................................................Signals |
73 |
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2.14 |
Embedded .......................................DisplayPort* (eDP*) Backlight Control Signals |
74 |
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2.15 |
Intel® High ...............................................Definition Audio (Intel® HD Audio) Link |
74 |
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2.16 |
Low Pin .............................................................................Count (LPC) Interface |
75 |
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2.17 |
General ...............................................................................Purpose I/O Signals |
75 |
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2.18 |
Functional ..............................................................................................Straps |
|
81 |
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2.19 |
SMBus Interface................................................................................................ |
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84 |
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2.20 |
System ............................................................................Management Interface |
85 |
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2.21 |
Controller ..................................................................................................Link |
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85 |
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2.22 |
Serial Peripheral ..........................................................................Interface (SPI) |
85 |
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2.23 |
Manageability ........................................................................................Signals |
86 |
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2.24 |
Power Management ..............................................................................Interface |
87 |
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2.25 |
Power and ..................................................................................Ground Signals |
90 |
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2.26 |
Thermal ................................................................................................Signals |
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91 |
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2.27 |
Miscellaneous ........................................................................................Signals |
92 |
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2.28 |
Testability .............................................................................................Signals |
|
93 |
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2.29 |
Reserved ........................................................................................../ Test Pins |
93 |
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3 |
PCH Pin States......................................................................................................... |
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95 |
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3.1 |
Integrated .....................................................................Pull-Ups and Pull-Downs |
95 |
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3.2 |
Output ........................................................................Signals Planes and States |
97 |
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3.3 |
Input and .............................................................I/O Signals Planes and States |
102 |
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4 |
PCH and System .........................................................................................Clocks |
107 |
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4.1 |
Straps Related ................................................................to Clock Configuration |
107 |
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4.2 |
Platform ........................................................................Clocking Requirements |
107 |
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4.3 |
Functional ............................................................................................Blocks |
|
109 |
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4.4 |
Clock Configuration .................................................................Access Overview |
111 |
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5 |
Functional Description........................................................................................... |
|
112 |
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5.1 |
Flexible ....................................................................................................I/O |
|
112 |
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5.2 |
PCI-to-PCI ............................................................................................Bridge |
|
113 |
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5.2.1 ................................................................................ |
PCI Bus Interface |
113 |
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5.3 |
5.2.2 ................................................................................. |
PCI Legacy Mode |
113 |
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PCI Express* ................................................................Root Ports (D28:F0~F7) |
113 |
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5.3.1 ................................Supported PCI Express* (PCIe*) Port Configurations |
114 |
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5.3.2 ........................................................................... |
Interrupt Generation |
114 |
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5.3.3 ............................................................................. |
Power Management |
115 |
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................................................................. |
5.3.3.1 |
S3/S4/S5 Support |
115 |
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............................................. |
5.3.3.2 |
Resuming from Suspended State |
115 |
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........................................... |
5.3.3.3 |
Device Initiated PM_PME Message |
115 |
Datasheet |
3 |
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5.3.3.4 |
...............................................................SMI/SCI Generation |
116 |
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5.3.3.5 |
Latency Tolerance Reporting (LTR) .......................................... |
116 |
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5.3.4 |
5.3.3.6 |
Opportunistic Buffer Flush/Fill (OBFF) ....................................... |
116 |
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SERR# Generation............................................................................... |
116 |
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5.3.5 |
Hot-Plug |
.............................................................................................Presence Detection |
117 |
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5.3.5.1 |
117 |
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5.3.5.2 ............................................................... |
SMI/SCI Generation |
117 |
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5.4 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. |
118 |
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5.4.1 GbE PCI ............................................................Express* Bus Interface |
120 |
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5.4.1.1 .................................................................. |
Transaction Layer |
120 |
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5.4.1.2 ..................................................................... |
Data Alignment |
120 |
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5.4.1.3 .......................................... |
Configuration Request Retry Status |
120 |
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5.4.2 Error Events ...........................................................and Error Reporting |
121 |
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5.4.2.1 ................................................................... |
Data Parity Error |
121 |
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5.4.3 |
5.4.2.2 ....................... |
Completion with Unsuccessful Completion Status |
121 |
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Ethernet ...............................................................................Interface |
121 |
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5.4.3.1 |
Intel ® Ethernet Network Connection I127LM/V Platform LAN |
121 |
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5.4.4 |
........................................................ |
Connect Device Interface |
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PCI Power ........................................................................Management |
122 |
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5.4.5 |
5.4.4.1 .............................................................................. |
Wake Up |
122 |
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Configurable ...............................................................................LEDs |
124 |
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5.4.6 Function ........................................................Level Reset Support (FLR) |
125 |
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5.4.6.1 ............................................................................. |
FLR Steps |
125 |
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5.5 Low Pin Count (LPC) Bridge (with System and |
126 |
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Management Functions) ......................................................................(D31:F0) |
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5.5.1 |
LPC Interface ...................................................................................... |
126 |
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5.5.1.1 .................................................................... |
LPC Cycle Types |
127 |
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5.5.1.2 .............................................................. |
Start Field Definition |
127 |
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5.5.1.3 ................................... |
Cycle Type / Direction (CYCTYPE + DIR) |
127 |
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5.5.1.4 ..................................................................................... |
Size |
128 |
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5.5.1.5 ................................................................................... |
SYNC |
128 |
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5.5.1.6 ..................................................................... |
SYNC Time - Out |
128 |
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5.5.1.7 ............................................................ |
SYNC Error Indication |
129 |
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5.5.1.8 .................................................................... |
LFRAME# Usage |
129 |
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5.5.1.9 ............................................................................ |
I/O Cycles |
129 |
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5.5.1.10 ................................................................. |
Bus Master Cycles |
129 |
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5.5.1.11 ......................................................... |
LPC Power Management |
129 |
5.6 |
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5.5.1.12 ......................................... |
Configuration and PCH Implications |
130 |
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DMA Operation (D31:F0) .................................................................................. |
130 |
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5.6.1 |
Channel ...................................................................................Priority |
131 |
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5.6.1.1 ........................................................................ |
Fixed Priority |
131 |
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5.6.2 |
5.6.1.2 .................................................................... |
Rotating Priority |
131 |
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Address ..................................................................Compatibility Mode |
131 |
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5.6.3 Summary ............................................................of DMA Transfer Sizes |
132 |
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5.6.3.1 |
Address Shifting When Programmed for 16 - Bit I/O Count |
132 |
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5.6.4 |
............................................................................. |
by Words |
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Autoinitialize....................................................................................... |
132 |
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5.6.5 |
Software ............................................................................Commands |
133 |
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5.7 Low Pin Count (LPC) DMA ................................................................................. |
133 |
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5.7.1 |
Asserting .......................................................................DMA Requests |
133 |
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5.7.2 |
Abandoning ...................................................................DMA Requests |
134 |
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5.7.3 General Flow ..............................................................of DMA Transfers |
134 |
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5.7.4 |
Terminal ...................................................................................Count |
135 |
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5.7.5 |
Verify Mode ........................................................................................ |
135 |
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5.7.6 |
DMA Request ....................................................................De-assertion |
135 |
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5.8 |
5.7.7 SYNC Field ..................................................................../ LDRQ# Rules |
136 |
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8254 Timers (D31:F0)...................................................................................... |
136 |
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5.8.1 |
Timer Programming ............................................................................. |
137 |
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5.8.2 Reading ............................................................from the Interval Timer |
138 |
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5.8.2.1 ......................................................................... |
Simple Read |
138 |
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5.8.2.2 ........................................................ |
Counter Latch Command |
138 |
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5.8.2.3 ............................................................. |
Read Back Command |
139 |
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5.9 8259 Programmable Interrupt Controllers (PIC) (D31:F0) ..................................... |
139 |
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5.9.1 |
Interrupt ...............................................................................Handling |
140 |
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5.9.1.1 ............................................................ |
Generating Interrupts |
140 |
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5.9.1.2 ....................................................... |
Acknowledging Interrupts |
140 |
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5.9.1.3 .................................... |
Hardware/Software Interrupt Sequence |
141 |
4 |
Datasheet |
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5.9.2 Initialization Command Words (ICWx).................................................... |
141 |
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5.9.2.1 |
ICW1 .................................................................................. |
141 |
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5.9.2.2 |
ICW2 .................................................................................. |
142 |
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5.9.2.3 |
ICW3 .................................................................................. |
142 |
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5.9.2.4 |
ICW4 .................................................................................. |
142 |
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5.9.3 Operation Command Words (OCW)........................................................ |
142 |
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5.9.4 |
Modes of Operation ............................................................................. |
143 |
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5.9.4.1 |
Fully Nested Mode................................................................. |
143 |
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5.9.4.2 |
Special Fully-Nested Mode...................................................... |
143 |
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5.9.4.3 |
Automatic Rotation Mode (Equal Priority Devices)...................... |
143 |
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5.9.4.4 |
Specific Rotation Mode (Specific Priority).................................. |
143 |
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5.9.4.5 |
Poll Mode ............................................................................. |
144 |
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5.9.4.6 |
Edge and Level Triggered Mode............................................... |
144 |
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5.9.4.7 |
End of Interrupt (EOI) Operations ........................................... |
144 |
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5.9.4.8 |
Normal End of Interrupt......................................................... |
144 |
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5.9.5 |
5.9.4.9 |
Automatic End of Interrupt Mode............................................. |
145 |
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Masking Interrupts .............................................................................. |
145 |
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5.9.5.1 |
Masking on an Individual Interrupt Request .............................. |
145 |
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5.9.6 |
5.9.5.2 |
Special Mask Mode ................................................................ |
145 |
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Steering PCI Interrupts ........................................................................ |
145 |
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5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. |
146 |
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5.10.1 |
Interrupt Handling............................................................................... |
146 |
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5.10.2 |
Interrupt Mapping ............................................................................... |
146 |
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5.10.3 |
PCI / PCI Express* Message-Based Interrupts......................................... |
147 |
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5.10.4 |
IOxAPIC Address Remapping ................................................................ |
147 |
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5.11 |
5.10.5 |
External Interrupt Controller Support..................................................... |
147 |
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Serial Interrupt (D31:F0) ................................................................................. |
148 |
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5.11.1 |
Start Frame........................................................................................ |
148 |
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5.11.2 |
Data Frames ...................................................................................... |
148 |
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5.11.3 |
Stop Frame ........................................................................................ |
149 |
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5.11.4 |
Specific Interrupts Not Supported Using SERIRQ ..................................... |
149 |
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5.11.5 |
Data Frame Format ............................................................................. |
149 |
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5.12 Real Time Clock (D31:F0)................................................................................. |
150 |
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5.12.1 |
Update Cycles..................................................................................... |
151 |
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5.12.2 |
Interrupts |
.......................................................................................... |
151 |
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5.12.3 |
Lockable RAM Ranges .......................................................................... |
151 |
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5.12.4 |
Century Rollover ................................................................................. |
151 |
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5.13 |
5.12.5 |
Clearing Battery-Backed RTC RAM ......................................................... |
151 |
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Processor Interface (D31:F0) ............................................................................ |
153 |
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5.13.1 |
Processor Interface Signals and VLW Messages ....................................... |
153 |
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5.13.1.1 |
INIT (Initialization)................................................................ |
153 |
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5.13.1.2 |
FERR# (Numeric Coprocessor Error) ........................................ |
153 |
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5.13.1.3 |
NMI (Non-Maskable Interrupt) ................................................ |
154 |
|
5.13.2 |
5.13.1.4 |
Processor Power Good (PROCPWRGD)...................................... |
154 |
|
Dual-Processor Issues.......................................................................... |
154 |
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|
5.13.3 |
5.13.2.1 |
Usage Differences ................................................................. |
154 |
5.14 |
Virtual Legacy Wire (VLW) Messages ..................................................... |
154 |
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Power Management ......................................................................................... |
155 |
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5.14.1 |
Features ............................................................................................ |
|
155 |
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5.14.2 |
PCH and System Power States .............................................................. |
155 |
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5.14.3 |
System Power Planes........................................................................... |
157 |
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5.14.4 |
SMI# / SCI Generation ........................................................................ |
157 |
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5.14.4.1 |
PCI Express* SCI .................................................................. |
160 |
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5.14.5 |
5.14.4.2 |
PCI Express* Hot-Plug ........................................................... |
160 |
|
C-States ............................................................................................ |
|
160 |
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5.14.6 |
Dynamic 33 MHz Clock Control (Mobile Only) .......................................... |
160 |
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5.14.6.1 |
Conditions for Checking the 33 MHz Clock ................................ |
161 |
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5.14.6.2 |
Conditions for Maintaining the 33MHz Clock.............................. |
161 |
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5.14.6.3 |
Conditions for Stopping the 33MHz Clock ................................. |
161 |
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5.14.6.4 |
Conditions for Re-Starting the 33MHz Clock .............................. |
161 |
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5.14.7 |
5.14.6.5 |
LPC Devices and CLKRUN#..................................................... |
161 |
|
Sleep States....................................................................................... |
162 |
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5.14.7.1 |
Sleep State Overview ............................................................ |
162 |
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5.14.7.2 |
Initiating Sleep State............................................................. |
162 |
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5.14.7.3 |
Exiting Sleep States .............................................................. |
162 |
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5.14.7.4 |
PCI Express* WAKE# Signal and PME Event Message................. |
164 |
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5.14.7.5 |
Sx-G3-Sx, Handling Power Failures.......................................... |
164 |
Datasheet |
5 |
|
|
5.14.7.6 |
...............................................................................Deep Sx |
165 |
|
5.14.8 Event Input Signals and Their Usage ...................................................... |
166 |
||
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5.14.8.1 |
PWRBTN# (Power Button) ...................................................... |
166 |
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5.14.8.2 |
RI# (Ring Indicator) .............................................................. |
167 |
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5.14.8.3 |
PME# (PCI Power Management Event) ..................................... |
168 |
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5.14.8.4 |
SYS_RESET# Signal............................................................... |
168 |
5.14.9 |
5.14.8.5 |
THRMTRIP# Signal ................................................................ |
168 |
|
ALT Access Mode ................................................................................. |
169 |
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5.14.9.1 |
Write Only Registers with Read Paths in ALT Access Mode ........... |
170 |
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5.14.9.2 |
PIC Reserved Bits .................................................................. |
171 |
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5.14.9.3 |
Read Only Registers with Write Paths in ALT Access Mode ........... |
171 |
|
5.14.10 System Power Supplies, Planes, and Signals ........................................... |
172 |
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|
5.14.10.1 |
Power Plane Control with SLP_S3#, |
172 |
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5.14.10.2 |
SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#............................. |
|
|
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SLP_S4# and Suspend-To-RAM Sequencing .............................. |
172 |
|
|
|
5.14.10.3 |
PWROK Signal....................................................................... |
173 |
|
|
5.14.10.4 |
BATLOW# (Battery Low) (Mobile Only)..................................... |
173 |
|
|
5.14.10.5 |
SLP_LAN# Pin Behavior.......................................................... |
173 |
|
|
5.14.10.6 |
SLP_WLAN# Pin Behavior ....................................................... |
175 |
|
|
5.14.10.7 SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior.. |
175 |
|
|
|
5.14.10.8 |
RTCRST# and SRTCRST# ....................................................... |
176 |
|
5.14.11 Legacy Power Management Theory of Operation ...................................... |
176 |
||
|
|
5.14.11.1 |
APM Power Management (Desktop Only) .................................. |
176 |
|
|
5.14.11.2 |
Mobile APM Power Management (Mobile Only) ........................... |
176 |
|
5.14.12 Reset Behavior.................................................................................... |
177 |
||
|
5.15 System Management (D31:F0) .......................................................................... |
178 |
||
5.15.1 |
Theory of Operation............................................................................. |
179 |
||
|
|
5.15.1.1 |
Detecting a System Lockup..................................................... |
179 |
|
|
5.15.1.2 |
Handling an Intruder.............................................................. |
179 |
|
|
5.15.1.3 |
Detecting Improper Flash Programming.................................... |
180 |
5.15.2 |
5.15.1.4 |
Heartbeat and Event Reporting using SMLink/SMBus .................. |
180 |
|
TCO Modes ......................................................................................... |
180 |
|||
|
|
5.15.2.1 |
TCO Legacy / Compatible Mode ............................................... |
180 |
|
|
5.15.2.2 |
Advanced TCO Mode .............................................................. |
181 |
|
5.16 General Purpose I/O (D31:F0)........................................................................... |
182 |
||
5.16.1 |
Power Wells ........................................................................................ |
182 |
||
|
5.16.2 SMI#, SCI, and NMI Routing................................................................. |
182 |
||
5.16.3 |
Triggering |
.......................................................................................... |
183 |
|
5.16.4 |
GPIO Registers Lockdown ..................................................................... |
183 |
||
|
5.16.5 Serial POST Codes over GPIO................................................................ |
183 |
||
|
|
5.16.5.1 |
Theory of Operation............................................................... |
184 |
|
|
5.16.5.2 |
Serial Message Format ........................................................... |
185 |
|
5.17 SATA Host Controller (D31:F2, F5)..................................................................... |
186 |
||
|
5.17.1 SATA 6 Gb/s Support ........................................................................... |
186 |
||
5.17.2 |
SATA Feature Support.......................................................................... |
186 |
||
5.17.3 |
Theory of Operation............................................................................. |
187 |
||
|
|
5.17.3.1 |
Standard ATA Emulation......................................................... |
187 |
|
|
5.17.3.2 |
48-Bit LBA Operation ............................................................. |
188 |
|
5.17.4 SATA Swap Bay Support....................................................................... |
188 |
||
5.17.5 |
Hot-Plug Operation .............................................................................. |
188 |
||
|
5.17.6 Intel® Rapid Storage Technology (Intel RST®) Configuration..................... |
188 |
||
|
|
5.17.6.1 |
Intel® Rapid Storage Technology (Intel® RST) RAID Option ROM.189 |
|
|
5.17.7 Intel® Smart Response Technology........................................................ |
189 |
||
5.17.8 |
Power Management Operation............................................................... |
189 |
||
|
|
5.17.8.1 |
Power State Mappings............................................................ |
190 |
|
|
5.17.8.2 |
Power State Transitions.......................................................... |
190 |
5.17.9 |
5.17.8.3 |
SMI Trapping (APM)............................................................... |
191 |
|
SATA Device Presence.......................................................................... |
191 |
|||
|
5.17.10 SATA LED........................................................................................... |
|
192 |
|
|
5.17.11 AHCI Operation ................................................................................... |
192 |
||
|
5.17.12 SGPIO Signals..................................................................................... |
193 |
||
|
|
5.17.12.1 |
Mechanism ........................................................................... |
193 |
|
|
5.17.12.2 |
Message Format.................................................................... |
194 |
|
|
5.17.12.3 |
LED Message Type................................................................. |
194 |
|
|
5.17.12.4 |
SGPIO Waveform .................................................................. |
196 |
|
5.17.13 External SATA..................................................................................... |
197 |
||
|
5.18 High Precision Event Timers (HPET).................................................................... |
197 |
||
6 |
Datasheet |
|
5.18.1 |
Timer Accuracy................................................................................... |
197 |
|
|
5.18.2 |
Interrupt Mapping ............................................................................... |
197 |
|
|
5.18.3 |
Periodic versus Non-Periodic Modes ....................................................... |
199 |
|
|
5.18.4 |
Enabling the Timers............................................................................. |
199 |
|
|
5.18.5 |
Interrupt Levels .................................................................................. |
200 |
|
|
5.18.6 |
Handling Interrupts ............................................................................. |
200 |
|
|
5.18.7 |
Issues Related to 64-Bit Timers with 32-Bit Processors............................. |
200 |
|
5.19 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. |
201 |
|||
|
5.19.1 |
EHC Initialization ................................................................................ |
201 |
|
|
|
5.19.1.1 |
BIOS Initialization ................................................................. |
201 |
|
|
5.19.1.2 |
Driver Initialization ................................................................ |
201 |
|
5.19.2 |
5.19.1.3 |
EHC Resets .......................................................................... |
201 |
|
Data Structures in Main Memory ........................................................... |
201 |
||
|
5.19.3 |
USB 2.0 Enhanced Host Controller DMA ................................................. |
202 |
|
|
5.19.4 |
Data Encoding and Bit Stuffing.............................................................. |
202 |
|
|
5.19.5 |
Packet Formats................................................................................... |
202 |
|
|
5.19.6 |
USB 2.0 Interrupts and Error Conditions................................................. |
202 |
|
|
5.19.7 |
5.19.6.1 |
Aborts on USB 2.0 - Initiated Memory Reads .............................. |
203 |
|
USB 2.0 Power Management................................................................. |
203 |
||
|
|
5.19.7.1 |
Pause Feature ...................................................................... |
203 |
|
|
5.19.7.2 |
Suspend Feature ................................................................... |
203 |
|
|
5.19.7.3 |
ACPI Device States ................................................................ |
203 |
|
5.19.8 |
5.19.7.4 |
ACPI System States .............................................................. |
204 |
|
USB 2.0 Legacy Keyboard Operation...................................................... |
204 |
||
|
5.19.9 |
USB 2.0 Based Debug Port ................................................................... |
204 |
|
|
|
5.19.9.1 |
Theory of Operation ............................................................. |
205 |
|
5.19.10 EHCI Caching ..................................................................................... |
209 |
||
|
5.19.11 Intel® USB Prefetch Based Pause .......................................................... |
209 |
||
|
5.19.12 Function Level Reset Support (FLR) ....................................................... |
209 |
||
|
|
5.19.12.1 |
FLR Steps ............................................................................ |
210 |
|
5.19.13 USB Overcurrent Protection .................................................................. |
210 |
||
5.20 Integrated USB 2.0 Rate Matching Hub .............................................................. |
211 |
|||
|
5.20.1 |
Overview |
........................................................................................... |
211 |
5.21 |
5.20.2 |
Architecture ....................................................................................... |
211 |
|
xHCI Controller (D20:F0) ................................................................................. |
212 |
|||
5.22 |
SMBus Controller (D31:F3)............................................................................... |
212 |
||
|
5.22.1 |
Host Controller ................................................................................... |
213 |
|
|
5.22.2 |
5.22.1.1 .............................................................. |
Command Protocols |
213 |
|
Bus Arbitration ................................................................................... |
217 |
||
|
5.22.3 |
Bus Timing......................................................................................... |
217 |
|
|
|
5.22.3.1 ................................................................... |
Clock Stretching |
217 |
|
5.22.4 |
5.22.3.2 ................................ |
Bus Time Out (The PCH as SMBus Master) |
217 |
|
Interrupts .............................................................................../ SMI# |
217 |
||
|
5.22.5 |
SMBALERT# ....................................................................................... |
218 |
|
|
5.22.6 SMBus CRC ....................................................Generation and Checking |
219 |
||
|
5.22.7 |
SMBus Slave .........................................................................Interface |
219 |
|
|
|
5.22.7.1 ................................................... |
Format of Slave Write Cycle |
220 |
|
|
5.22.7.2 ...................................................... |
Format of Read Command |
221 |
|
|
5.22.7.3 ................................................ |
Slave Read of RTC Time Bytes |
222 |
5.23 |
|
5.22.7.4 ............................................. |
Format of Host Notify Command |
223 |
Thermal Management ...................................................................................... |
224 |
|||
|
5.23.1 |
Thermal Sensor .................................................................................. |
224 |
|
|
5.23.2 |
5.23.1.1 .......................................... |
Internal Thermal Sensor Operation |
224 |
|
PCH Thermal ........................................................................Throttling |
225 |
||
|
5.23.3 Thermal Reporting ...Over System Management Link 1 Interface (SMLink1) |
226 |
||
|
|
5.23.3.1 ............................................................... |
Block Read Address |
227 |
|
|
5.23.3.2 ............................................................ |
Block Read Command |
227 |
|
|
5.23.3.3 ................................................................. |
Read Data Format |
227 |
|
|
5.23.3.4 ..................................................... |
Thermal Data Update Rate |
227 |
|
|
5.23.3.5 ......................................... |
Temperature Comparator and Alert |
228 |
|
|
5.23.3.6 ......................................................................... |
BIOS Set Up |
229 |
|
|
5.23.3.7 ........................................................................ |
SMBus Rules |
229 |
|
|
5.23.3.8 ......................................................... |
Case for Considerations |
230 |
5.24 Intel® High Definition ........................Audio (Intel® HD Audio) Overview (D27:F0) |
232 |
|||
|
5.24.1 Intel® High ........Definition Audio (Intel® HD Audio) Docking (Mobile Only) |
232 |
||
|
|
5.24.1.1 ..................................................................... |
Dock Sequence |
232 |
|
|
5.24.1.2 ............................................. |
Exiting D3/CRST# When Docked |
233 |
Datasheet |
7 |
|
.................................5.24.1.3 Cold Boot/Resume from S3 When Docked |
234 |
|
5.24.1.4 |
Undock Sequence .................................................................. |
234 |
|
5.24.1.5 |
Normal Undock ..................................................................... |
234 |
|
5.24.1.6 |
Surprise Undock.................................................................... |
235 |
|
|
5.24.1.7 Interaction between Dock/Undock and Power Management States235 |
||
|
5.24.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# ............ |
235 |
|
|
5.25 |
Intel® Management Engine (Intel® ME) and Intel® |
236 |
||
|
|
Management Engine Firmware (Intel® ME FW) 9.0 ............................................... |
|||
|
5.26 |
5.25.1 Intel® Management Engine (Intel® ME) Requirements.............................. |
237 |
||
|
Serial Peripheral Interface (SPI) ........................................................................ |
238 |
|||
|
|
5.26.1 SPI Supported Feature Overview ........................................................... |
238 |
||
|
|
|
5.26.1.1 |
Non-Descriptor Mode ............................................................. |
238 |
|
|
5.26.2 |
5.26.1.2 |
Descriptor Mode .................................................................... |
239 |
|
|
Flash Descriptor .................................................................................. |
240 |
||
|
|
5.26.3 |
5.26.2.1 |
Descriptor Master Region........................................................ |
241 |
|
|
Flash Access ....................................................................................... |
241 |
||
|
|
|
5.26.3.1 |
Direct Access Security............................................................ |
242 |
|
|
|
5.26.3.2 |
Register Access Security......................................................... |
242 |
|
|
5.26.4 Serial Flash Device Compatibility Requirements ....................................... |
242 |
||
|
|
|
5.26.4.1 PCH SPI Based BIOS Requirements.......................................... |
242 |
|
|
|
|
5.26.4.2 Integrated LAN Firmware SPI Flash Requirements...................... |
243 |
|
|
|
|
5.26.4.3 Intel® Management Engine Firmware (Intel® ME FW) SPI Flash |
243 |
|
|
|
|
5.26.4.4 |
Requirements ....................................................................... |
|
|
|
|
Hardware Sequencing Requirements ........................................ |
244 |
|
|
|
5.26.5 Multiple Page Write Usage Model ........................................................... |
245 |
||
|
|
|
5.26.5.1 |
Soft Flash Protection .............................................................. |
245 |
|
|
|
5.26.5.2 BIOS Range Write Protection................................................... |
246 |
|
|
|
5.26.6 |
5.26.5.3 SMI# Based Global Write Protection......................................... |
246 |
|
|
|
Flash Device Configurations .................................................................. |
246 |
||
|
|
5.26.7 SPI Flash Device Recommended Pinout................................................... |
246 |
||
|
|
5.26.8 Serial Flash Device Package .................................................................. |
247 |
||
|
|
|
5.26.8.1 Common Footprint Usage Model .............................................. |
247 |
|
|
|
|
5.26.8.2 Serial Flash Device Package Recommendations.......................... |
247 |
|
|
|
5.26.9 PWM Outputs (Server/Workstation Only) ................................................ |
247 |
||
|
5.27 |
5.26.10 TACH Inputs (Server/Workstation Only) ................................................. |
248 |
||
|
Feature Capability Mechanism ........................................................................... |
248 |
|||
|
5.28 |
PCH Display Interface and Intel® Flexible Display Interface (Intel® FDI) |
248 |
||
|
|
Interconnect ................................................................................................... |
|
||
|
|
5.28.1 Analog Display Interface Characteristics ................................................. |
249 |
||
|
|
|
5.28.1.1 |
Integrated RAMDAC ............................................................... |
250 |
|
|
|
5.28.1.2 DDC (Display Data Channel) ................................................... |
250 |
|
|
|
5.28.2 Digital Display Side Band Signals ........................................................... |
250 |
||
|
|
|
5.28.2.1 |
DisplayPort AUX CH ............................................................... |
251 |
|
|
|
5.28.2.2 DDC (Display Data Channel) ................................................... |
251 |
|
|
|
|
5.28.2.3 |
Hot-Plug Detect..................................................................... |
251 |
|
|
|
5.28.2.4 Map of Digital Display Side Band Signals Per Display |
251 |
|
|
|
|
|
Configuration ........................................................................ |
|
|
|
|
5.28.2.5 Panel Power Sequencing and Backlight Control .......................... |
251 |
|
|
5.29 |
5.28.3 Intel® Flexible Display Interface (Intel® FDI) .......................................... |
252 |
||
|
Intel® Virtualization Technology (Intel® VT) ........................................................ |
253 |
|||
|
|
5.29.1 Intel® Virtualization Technology (Intel® VT) for |
253 |
||
|
|
|
Directed I/O (Intel® VT-d) Objectives..................................................... |
||
|
|
5.29.2 Intel® VT-d Features Supported ............................................................ |
253 |
||
|
|
5.29.3 Support for Function Level Reset (FLR) in PCH......................................... |
253 |
||
|
|
5.29.4 Virtualization Support for PCH IOxAPIC................................................... |
254 |
||
|
|
5.29.5 Virtualization Support for High Precision Event Timer (HPET) ..................... |
254 |
||
6 |
Ballout Definition................................................................................................... |
|
255 |
||
|
6.1 |
Desktop/Server PCH Ballout .............................................................................. |
255 |
||
|
6.2 |
Mobile PCH Ballout |
........................................................................................... |
264 |
|
7 |
Package Information ............................................................................................. |
|
272 |
||
|
7.1 |
Desktop/Server PCH Package ............................................................................ |
272 |
||
|
7.2 |
7.1.1 Tape and Reel Pin 1 Placement.............................................................. |
272 |
||
|
Mobile PCH Package ......................................................................................... |
274 |
|||
|
|
7.2.1 Tape and Reel Pin 1 Placement.............................................................. |
274 |
||
8 |
Datasheet |
8 |
Electrical Characteristics ....................................................................................... |
276 |
||
|
8.1 |
Thermal Specifications ..................................................................................... |
276 |
|
|
8.2 |
8.1.1 |
Storage Specifications and Thermal Design Power (TDP) .......................... |
276 |
|
Absolute Maximum Ratings............................................................................... |
277 |
||
|
8.3 |
PCH Power Supply Range ................................................................................. |
277 |
|
|
8.4 |
General DC Characteristics ............................................................................... |
278 |
|
|
8.5 |
Display DC Characteristics ................................................................................ |
287 |
|
|
8.6 |
AC Characteristics ........................................................................................... |
288 |
|
|
8.7 |
Power Sequencing and Reset Signal Timings ....................................................... |
299 |
|
|
8.8 |
Power Management Timing Diagrams................................................................. |
303 |
|
|
8.9 |
AC Timing Diagrams ........................................................................................ |
308 |
|
|
8.10 |
Sequencing Rails Within The Same Well ............................................................. |
319 |
|
9 |
Register and Memory Mapping............................................................................... |
320 |
||
|
9.1 |
PCI Devices and Functions................................................................................ |
321 |
|
|
9.2 |
PCI Configuration Map ..................................................................................... |
322 |
|
|
9.3 |
I/O Map |
.........................................................................................................Fixed I/O Address Ranges |
322 |
|
|
9.3.1 |
322 |
|
|
9.4 |
9.3.2 |
Variable I/O Decode Ranges ................................................................. |
324 |
|
Memory ...................................................................................................Map |
325 |
||
|
|
9.4.1 .................................................................. |
Boot - Block Update Scheme |
327 |
10 |
Chipset Configuration .............................................................................Registers |
329 |
||
|
10.1 |
Chipset .................................................Configuration Registers (Memory Space) |
329 |
|
|
|
10.1.1 ................................................... |
RPC—Root Port Configuration Register |
331 |
|
|
10.1.2 |
RPFN—Root Port Function Number and Hide for PCI |
331 |
|
|
10.1.3 ................................................................ |
Express* Root Ports Register |
|
|
|
FLRSTAT—Function Level Reset Pending Status Register |
333 |
|
|
|
10.1.4 .................................................................. |
TRSR—Trap Status Register |
333 |
|
|
10.1.5 .............................................................. |
TRCR—Trapped Cycle Register |
334 |
|
|
10.1.6 ...................................................... |
TWDR—Trapped Write Data Register |
334 |
|
|
10.1.7 ............................................................ |
IOTRn—I/O Trap Register (0–3) |
335 |
|
|
10.1.8 ................................ |
V0CTL—Virtual Channel 0 Resource Control Register |
336 |
|
|
10.1.9 ................................. |
V0STS—Virtual Channel 0 Resource Status Register |
336 |
|
|
10.1.10 ................................ |
V1CTL—Virtual Channel 1 Resource Control Register |
336 |
|
|
10.1.11 ................................. |
V1STS—Virtual Channel 1 Resource Status Register |
337 |
|
|
10.1.12 ...................................................... |
REC—Root Error Command Register |
337 |
|
|
10.1.13 ............................................................ |
LCAP—Link Capabilities Register |
337 |
|
|
10.1.14 .................................................................. |
LCTL—Link Control Register |
338 |
|
|
10.1.15 ................................................................... |
LSTS—Link Status Register |
338 |
|
|
10.1.16 ........................................................ |
TCTL—TCO Configuration Register |
338 |
|
|
10.1.17 ................................................ |
D31IP—Device 31 Interrupt Pin Register |
339 |
|
|
10.1.18 ................................................ |
D30IP—Device 30 Interrupt Pin Register |
339 |
|
|
10.1.19 ................................................ |
D29IP—Device 29 Interrupt Pin Register |
340 |
|
|
10.1.20 ................................................ |
D28IP—Device 28 Interrupt Pin Register |
340 |
|
|
10.1.21 ................................................ |
D27IP—Device 27 Interrupt Pin Register |
341 |
|
|
10.1.22 ................................................ |
D26IP—Device 26 Interrupt Pin Register |
342 |
|
|
10.1.23 ................................................ |
D25IP—Device 25 Interrupt Pin Register |
342 |
|
|
10.1.24 ................................................ |
D22IP—Device 22 Interrupt Pin Register |
342 |
|
|
10.1.25 ................................................ |
D20IP—Device 20 Interrupt Pin Register |
343 |
|
|
10.1.26 ............................................ |
D31IR—Device 31 Interrupt Route Register |
343 |
|
|
10.1.27 ............................................ |
D30IR—Device 30 Interrupt Route Register |
344 |
|
|
10.1.28 ............................................ |
D29IR—Device 29 Interrupt Route Register |
344 |
|
|
10.1.29 ............................................ |
D28IR—Device 28 Interrupt Route Register |
345 |
|
|
10.1.30 ............................................ |
D27IR—Device 27 Interrupt Route Register |
346 |
|
|
10.1.31 ............................................ |
D26IR—Device 26 Interrupt Route Register |
347 |
|
|
10.1.32 ............................................ |
D25IR—Device 25 Interrupt Route Register |
348 |
|
|
10.1.33 ............................................ |
D22IR—Device 22 Interrupt Route Register |
349 |
|
|
10.1.34 ............................................ |
D20IR—Device 20 Interrupt Route Register |
350 |
|
|
10.1.35 .................................................... |
OIC—Other Interrupt Control Register |
351 |
|
|
10.1.36 ................................ |
WADT _ AC—Wake Alarm Device Timer – AC Register |
351 |
|
|
10.1.37 ............................... |
WADT _ DC—Wake Alarm Device Timer – DC Register |
351 |
|
|
10.1.38 WADT_EXP_AC—Wake Alarm Device Expired Timer – AC |
352 |
|
|
|
............................................................................................. |
Register |
|
|
|
10.1.39 WADT_EXP_DC—Wake Alarm Device Expired Timer – DC |
352 |
|
|
|
............................................................................................. |
Register |
|
|
|
10.1.40 ...............................................PRSTS—Power and Reset Status Register |
352 |
|
Datasheet |
9 |
10.1.41 |
PM_CFG—Power Management Configuration Register ............................... |
353 |
10.1.42 |
DEEP_S3_POL—Deep Sx From S3 Power Policies Register ......................... |
355 |
10.1.43 |
DEEP_S4_POL—Deep Sx From S4 Power Policies Register ......................... |
355 |
10.1.44 |
DEEP_S5_POL—Deep Sx From S5 Power Policies Register ......................... |
355 |
10.1.45 |
DSX_CFG—Deep Sx Configuration Register ............................................. |
356 |
10.1.46 |
PMSYNC_CFG—PMSYNC Configuration.................................................... |
356 |
10.1.47 |
RC—RTC Configuration Register............................................................. |
357 |
10.1.48 |
HPTC—High Precision Timer Configuration Register .................................. |
357 |
10.1.49 |
GCS—General Control and Status Register .............................................. |
358 |
10.1.50 |
BUC—Backed Up Control Register .......................................................... |
359 |
10.1.51 |
FD—Function Disable Register ............................................................... |
359 |
10.1.52 |
CG—Clock Gating Register .................................................................... |
361 |
10.1.53 |
FDSW—Function Disable SUS Well Register ............................................. |
362 |
10.1.54 DISPBDF—Display Bus, Device and Function |
|
|
|
Initialization Register ........................................................................... |
362 |
10.1.55 FD2—Function Disable 2 Register........................................................... |
362 |
|
11 Gigabit LAN Configuration Registers ...................................................................... |
363 |
|
11.1 Gigabit LAN Configuration Registers |
|
|
(Gigabit LAN—D25:F0) ..................................................................................... |
363 |
|
11.1.1 VID—Vendor Identification Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
364 |
11.1.2 DID—Device Identification Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
364 |
11.1.3 |
PCICMD—PCI Command Register |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
365 |
11.1.4 PCISTS—PCI Status Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
365 |
11.1.5 RID—Revision Identification Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
366 |
11.1.6 |
CC—Class Code Register |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
366 |
11.1.7 |
CLS—Cache Line Size Register |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
367 |
11.1.8 |
PLT—Primary Latency Timer Register |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
367 |
11.1.9 |
HEADTYP—Header Type Register |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
367 |
11.1.10 MBARA—Memory Base Address Register A |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
367 |
11.1.11 MBARB—Memory Base Address Register B |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
368 |
11.1.12 MBARC—Memory Base Address Register C |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
368 |
11.1.13 SVID—Subsystem Vendor ID Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
368 |
11.1.14 SID—Subsystem ID Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
369 |
11.1.15 ERBA—Expansion ROM Base Address Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
369 |
11.1.16 |
CAPP—Capabilities List Pointer Register |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
369 |
11.1.17 INTR—Interrupt Information Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
369 |
11.1.18 MLMG—Maximum Latency / Minimum Grant Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
369 |
11.1.19 STCL—System Time Control Low Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
370 |
11.1.20 STCH—System Time Control High Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
370 |
11.1.21 LTRCAP—System Time Control High Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
370 |
11.1.22 |
CLIST1—Capabilities List Register 1 |
|
|
(Gigabit LAN—D25:F0)......................................................................... |
371 |
11.1.23 PMC—PCI Power Management Capabilities Register |
|
|
|
(Gigabit LAN—D25:F0)......................................................................... |
371 |
10 |
Datasheet |
11.1.24 PMCS—PCI Power Management Control and Status |
|
|
|
Register (Gigabit LAN—D25:F0) ............................................................ |
371 |
11.1.25 DR—Data Register |
|
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
372 |
11.1.26 |
CLIST2—Capabilities List Register 2 |
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
372 |
11.1.27 MCTL—Message Control Register |
|
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
373 |
11.1.28 MADDL—Message Address Low Register |
|
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
373 |
11.1.29 MADDH—Message Address High Register |
|
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
373 |
11.1.30 MDAT—Message Data Register |
|
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
373 |
11.1.31 FLRCAP—Function Level Reset Capability |
|
|
|
(Gigabit LAN—D25:F0) ........................................................................ |
374 |
11.1.32 FLRCLV—Function Level Reset Capability Length and |
|
|
|
Version Register (Gigabit LAN—D25:F0) ................................................. |
374 |
11.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) ....................... |
375 |
|
11.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. |
375 |
|
11.2.1 |
GBECSR_00—Gigabit Ethernet Capabilities and Status Register 00............. |
376 |
11.2.2 |
GBECSR_18—Gigabit Ethernet Capabilities and Status Register 18............. |
376 |
11.2.3 |
GBECSR_20—Gigabit Ethernet Capabilities and Status Register 20............. |
376 |
11.2.4 |
GBECSR_F00—Gigabit Ethernet Capabilities and Status Register F00 ......... |
377 |
11.2.5 |
GBECSR_F10—Gigabit Ethernet Capabilities and Status Register F10 ......... |
377 |
11.2.6 |
GBECSR_5400—Gigabit Ethernet Capabilities and Status Register 5400...... |
377 |
11.2.7 |
GBECSR_5404—Gigabit Ethernet Capabilities and Status Register 5404...... |
377 |
11.2.8 |
GBECSR_5800—Gigabit Ethernet Capabilities and Status Register 5800...... |
378 |
11.2.9 |
GBECSR_5B54—Gigabit Ethernet Capabilities and Status Register 5B54 ..... |
378 |
12 LPC Interface Bridge Registers (D31:F0) ............................................................... |
379 |
|
12.1 PCI Configuration Registers (LPC I/F—D31:F0).................................................... |
379 |
|
12.1.1 |
VID—Vendor Identification Register (LPC I/F—D31:F0)............................. |
380 |
12.1.2 |
DID—Device Identification Register (LPC I/F—D31:F0) ............................. |
380 |
12.1.3 |
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ............................... |
380 |
12.1.4 |
PCISTS—PCI Status Register (LPC I/F—D31:F0)...................................... |
381 |
12.1.5 |
RID—Revision Identification Register (LPC I/F—D31:F0)........................... |
382 |
12.1.6 |
PI—Programming Interface Register (LPC I/F—D31:F0)............................ |
382 |
12.1.7 |
SCC—Sub Class Code Register (LPC I/F—D31:F0) ................................... |
382 |
12.1.8 |
BCC—Base Class Code Register (LPC I/F—D31:F0) .................................. |
382 |
12.1.9 |
PLT—Primary Latency Timer Register (LPC I/F—D31:F0) .......................... |
382 |
12.1.10 |
HEADTYP—Header Type Register (LPC I/F—D31:F0) ................................ |
382 |
12.1.11 |
SS—Sub System Identifiers Register (LPC I/F—D31:F0) ........................... |
383 |
12.1.12 |
CAPP—Capability List Pointer Register (LPC I/F—D31:F0) ......................... |
383 |
12.1.13 |
PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) ......................... |
383 |
12.1.14 |
ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) ............................. |
384 |
12.1.15 |
GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) ..................... |
384 |
12.1.16 |
GC—GPIO Control Register (LPC I/F—D31:F0) ........................................ |
385 |
12.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
385 |
12.1.18 SIRQ_CNTL—Serial IRQ Control Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
386 |
12.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
386 |
12.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
387 |
12.1.21 LPC_HnBDF—HPET n Bus:Device:Function |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
387 |
12.1.22 LPC_I/O_DEC—I/O Decode Ranges Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
388 |
12.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) .............................. |
388 |
|
12.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
389 |
12.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
390 |
12.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register |
|
|
|
(LPC I/F—D31:F0)............................................................................... |
390 |
Datasheet |
11 |
|
|
12.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register |
391 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.28 ULKMC—USB Legacy Keyboard / Mouse |
391 |
||
|
|
|
Control Register(LPC I/F—D31:F0)......................................................... |
||
|
|
12.1.29 LGMR—LPC I/F Generic Memory Range Register |
392 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.30 BIOS_SEL1—BIOS Select 1 Register |
393 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.31 BIOS_SEL2—BIOS Select 2 Register |
394 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.32 BIOS_DEC_EN1—BIOS Decode Enable |
394 |
||
|
|
|
Register (LPC I/F—D31:F0)................................................................... |
||
|
|
12.1.33 BIOS_CNTL—BIOS Control Register |
396 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.34 FDCAP—Feature Detection Capability ID Register |
396 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.35 FDLEN—Feature Detection Capability Length Register |
397 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.36 FDVER—Feature Detection Version Register |
397 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.37 FVECIDX—Feature Vector Index Register |
397 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.38 FVECD—Feature Vector Data Register |
397 |
||
|
|
|
(LPC I/F—D31:F0) ............................................................................... |
||
|
|
12.1.39 Feature Vector Space ........................................................................... |
398 |
||
|
|
|
12.1.39.1 |
FVEC0—Feature Vector Register 0............................................ |
398 |
|
|
|
12.1.39.2 |
FVEC1—Feature Vector Register 1............................................ |
399 |
|
|
|
12.1.39.3 |
FVEC2—Feature Vector Register 2............................................ |
399 |
|
|
|
12.1.39.4 |
FVEC3—Feature Vector Register 3............................................ |
399 |
|
|
12.1.40 RCBA—Root Complex Base Address Register |
400 |
||
12.2 |
|
(LPC I/F—D31:F0) ............................................................................... |
|||
DMA I/O Registers |
........................................................................................... |
400 |
|||
|
|
12.2.1 |
DMABASE_CA—DMA Base and Current Address Registers ......................... |
401 |
|
|
|
12.2.2 |
DMABASE_CC—DMA Base and Current Count Registers ............................ |
402 |
|
|
|
12.2.3 |
DMAMEM_LP—DMA Memory Low Page Registers ...................................... |
402 |
|
|
|
12.2.4 |
DMACMD—DMA Command Register........................................................ |
403 |
|
|
|
12.2.5 |
DMASTA—DMA Status Register.............................................................. |
403 |
|
|
|
12.2.6 |
DMA_WRSMSK—DMA Write Single Mask Register..................................... |
404 |
|
|
|
12.2.7 |
DMACH_MODE—DMA Channel Mode Register .......................................... |
404 |
|
|
|
12.2.8 |
DMA Clear Byte Pointer Register ............................................................ |
405 |
|
|
|
12.2.9 |
DMA Master Clear Register.................................................................... |
405 |
|
|
|
12.2.10 |
DMA_CLMSK—DMA Clear Mask Register ................................................. |
405 |
|
12.3 |
12.2.11 DMA_WRMSK—DMA Write All Mask Register............................................ |
406 |
|||
Timer I/O Registers.......................................................................................... |
406 |
||||
|
|
12.3.1 |
TCW—Timer Control Word Register ........................................................ |
407 |
|
|
|
12.3.2 |
SBYTE_FMT—Interval Timer Status Byte Format Register.......................... |
409 |
|
|
|
12.3.3 |
Counter Access Ports Register ............................................................... |
409 |
|
|
12.4 8259 Interrupt Controller (PIC) Registers............................................................ |
410 |
|||
|
|
12.4.1 |
Interrupt Controller I/O MAP ................................................................. |
410 |
|
|
|
12.4.2 |
ICW1—Initialization Command Word 1 Register ....................................... |
410 |
|
|
|
12.4.3 |
ICW2—Initialization Command Word 2 Register ....................................... |
411 |
|
|
|
12.4.4 |
ICW3—Master Controller Initialization Command |
412 |
|
|
|
12.4.5 |
Word 3 Register .................................................................................. |
||
|
|
ICW3—Slave Controller Initialization Command |
412 |
||
|
|
12.4.6 |
Word 3 Register .................................................................................. |
||
|
|
ICW4—Initialization Command Word 4 Register ....................................... |
412 |
||
|
|
12.4.7 |
OCW1—Operational Control Word 1 (Interrupt Mask) |
413 |
|
|
|
12.4.8 |
Register ............................................................................................. |
|
|
|
|
OCW2—Operational Control Word 2 Register ........................................... |
413 |
||
|
|
12.4.9 |
OCW3—Operational Control Word 3 Register ........................................... |
414 |
|
|
|
12.4.10 |
ELCR1—Master Controller Edge/Level Triggered Register .......................... |
415 |
|
|
|
12.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............................ |
416 |
||
|
12.5 Advanced Programmable Interrupt Controller (APIC) ............................................ |
417 |
|||
|
|
12.5.1 |
APIC Register Map ............................................................................... |
417 |
|
|
|
12.5.2 |
IND—Index Register ............................................................................ |
417 |
|
|
|
12.5.3 |
DAT—Data Register ............................................................................. |
418 |
|
|
|
12.5.4 |
EOIR—EOI Register ............................................................................. |
418 |
|
12 |
Datasheet |
|
12.5.5 |
ID—Identification Register.................................................................... |
419 |
|
|
12.5.6 |
VER—Version Register ......................................................................... |
419 |
|
12.6 |
12.5.7 |
REDIR_TBL—Redirection Table Register ................................................. |
420 |
|
Real Time Clock Registers................................................................................. |
421 |
|||
|
12.6.1 I/O Register Address Map..................................................................... |
421 |
||
|
12.6.2 |
Indexed Registers ............................................................................... |
422 |
|
|
|
12.6.2.1 |
RTC_REGA—Register A .......................................................... |
423 |
|
|
12.6.2.2 |
RTC_REGB—Register B (General Configuration) ........................ |
424 |
|
|
12.6.2.3 |
RTC_REGC—Register C (Flag Register)..................................... |
425 |
12.7 |
|
12.6.2.4 |
RTC_REGD—Register D (Flag Register) .................................... |
425 |
Processor Interface Registers............................................................................ |
425 |
|||
|
12.7.1 NMI_SC—NMI Status and Control Register.............................................. |
426 |
||
|
12.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) |
426 |
||
|
12.7.3 |
Register............................................................................................. |
|
|
|
PORT92—Init Register ......................................................................... |
427 |
||
|
12.7.4 |
COPROC_ERR—Coprocessor Error Register ............................................. |
427 |
|
12.8 |
12.7.5 |
RST_CNT—Reset Control Register ......................................................... |
427 |
|
Power Management Registers ........................................................................... |
428 |
|||
|
12.8.1 Power Management PCI Configuration Registers |
428 |
||
|
|
(PM—D31:F0)..................................................................................... |
||
|
|
12.8.1.1 |
GEN_PMCON_1—General PM Configuration 1 Register |
428 |
|
|
12.8.1.2 |
(PM—D31:F0)....................................................................... |
|
|
|
GEN_PMCON_2—General PM Configuration 2 Register |
430 |
|
|
|
12.8.1.3 |
(PM—D31:F0)....................................................................... |
|
|
|
GEN_PMCON_3—General PM Configuration 3 Register |
431 |
|
|
|
12.8.1.4 |
(PM—D31:F0)....................................................................... |
|
|
|
GEN_PMCON_LOCK—General Power Management Configuration |
434 |
|
|
|
12.8.1.5 |
Lock Register ....................................................................... |
|
|
|
BM_BREAK_EN_2 Register #2 (PM—D31:F0) ............................ |
434 |
|
|
|
12.8.1.6 |
BM_BREAK_EN Register (PM—D31:F0)..................................... |
435 |
|
|
12.8.1.7 |
GPI_ROUT—GPI Routing Control Register |
436 |
|
|
12.8.1.8 |
(PM—D31:F0)....................................................................... |
|
|
|
GPI_ROUT2—GPI Routing Control Register #2 (PM-D31:F0) ....... |
437 |
|
|
12.8.2 APM I/O Decode Register ..................................................................... |
437 |
||
|
|
12.8.2.1 |
APM_CNT—Advanced Power Management Control Port Register... |
437 |
|
|
12.8.2.2 |
APM_STS—Advanced Power Management Status Port Register .... |
438 |
|
12.8.3 Power Management I/O Registers.......................................................... |
438 |
||
|
|
12.8.3.1 |
PM1_STS—Power Management 1 Status Register ...................... |
439 |
|
|
12.8.3.2 |
PM1_EN—Power Management 1 Enable Register........................ |
440 |
|
|
12.8.3.3 |
PM1_CNT—Power Management 1 Control Register ..................... |
441 |
|
|
12.8.3.4 |
PM1_TMR—Power Management 1 Timer Register....................... |
442 |
|
|
12.8.3.5 |
GPE0_STS—General Purpose Event 0 Status Register ................ |
442 |
|
|
12.8.3.6 |
GPE0_EN—General Purpose Event 0 Enables Register ................ |
445 |
|
|
12.8.3.7 |
SMI_EN—SMI Control and Enable Register................................ |
446 |
|
|
12.8.3.8 |
SMI_STS—SMI Status Register ............................................... |
448 |
|
|
12.8.3.9 |
ALT_GPI_SMI_EN—Alternate GPI SMI Enable Register ............... |
450 |
|
|
12.8.3.10 |
ALT_GPI_SMI_STS—Alternate GPI SMI Status Register .............. |
450 |
|
|
12.8.3.11 |
GPE_CNTL—General Purpose Control Register........................... |
450 |
|
|
12.8.3.12 |
DEVACT_STS—Device Activity Status Register .......................... |
451 |
|
|
12.8.3.13 |
PM2_CNT—Power Management 2 Control Register ..................... |
452 |
|
|
12.8.3.14 |
ALT_GPI_SMI_EN2—Alternate GPI SMI Enable 2 Register ........... |
452 |
12.9 |
|
12.8.3.15 |
ALT_GPI_SMI_STS2—Alternate GPI SMI Status 2 Register.......... |
452 |
System Management TCO Registers................................................................... |
453 |
|||
|
12.9.1 TCO_RLD—TCO Timer Reload and Current Value Register......................... |
454 |
||
|
12.9.2 TCO_DAT_IN—TCO Data In Register...................................................... |
454 |
||
|
12.9.3 TCO_DAT_OUT—TCO Data Out Register ................................................. |
454 |
||
|
12.9.4 |
TCO1_STS—TCO1 Status Register ......................................................... |
454 |
|
|
12.9.5 |
TCO2_STS—TCO2 Status Register ......................................................... |
455 |
|
|
12.9.6 |
TCO1_CNT—TCO1 Control Register........................................................ |
456 |
|
|
12.9.7 |
TCO2_CNT—TCO2 Control Register........................................................ |
457 |
|
|
12.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers...................................... |
458 |
||
|
12.9.9 TCO_WDCNT—TCO Watchdog Control Register........................................ |
458 |
||
|
12.9.10 SW_IRQ_GEN—Software IRQ Generation Register ................................... |
458 |
||
12.10 |
12.9.11 TCO_TMR—TCO Timer Initial Value Register ........................................... |
458 |
||
General Purpose I/O Registers .......................................................................... |
459 |
|||
|
12.10.1 GPIO_USE_SEL—GPIO Use Select Register ............................................. |
460 |
||
|
12.10.2 GP_IO_SEL—GPIO Input/Output Select Register...................................... |
460 |
||
Datasheet |
13 |
12.10.3 |
GP_LVL—GPIO Level for Input or Output Register .................................... |
460 |
12.10.4 |
GPO_BLINK—GPO Blink Enable Register ................................................. |
461 |
12.10.5 |
GP_SER_BLINK—GP Serial Blink Register................................................ |
461 |
12.10.6 GP_SB_CMDSTS—GP Serial Blink Command |
|
|
|
Status Register ................................................................................... |
462 |
12.10.7 GP_SB_DATA—GP Serial Blink Data Register ........................................... |
462 |
|
12.10.8 GPI_NMI_EN—GPI NMI Enable Register .................................................. |
462 |
|
12.10.9 GPI_NMI_STS—GPI NMI Status Register................................................. |
463 |
|
12.10.10GPI_INV—GPIO Signal Invert Register.................................................... |
463 |
|
12.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register......................................... |
464 |
|
12.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register ................................. |
464 |
|
12.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................ |
465 |
|
12.10.14GPIO_USE_SEL3—GPIO Use Select 3 Register......................................... |
465 |
|
12.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register ................................. |
466 |
|
12.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................ |
466 |
|
12.10.17GP_RST_SEL1—GPIO Reset Select Register ............................................ |
466 |
|
12.10.18GP_RST_SEL2—GPIO Reset Select Register ............................................ |
467 |
|
12.10.19GP_RST_SEL3—GPIO Reset Select Register ............................................ |
467 |
|
13 SATA Controller Registers (D31:F2) ....................................................................... |
468 |
|
13.1 PCI Configuration Registers (SATA–D31:F2) ........................................................ |
468 |
|
13.1.1 |
VID—Vendor Identification Register (SATA—D31:F2)................................ |
469 |
13.1.2 |
DID—Device Identification Register (SATA—D31:F2) ................................ |
470 |
13.1.3 |
PCICMD—PCI Command Register (SATA–D31:F2) .................................... |
470 |
13.1.4 |
PCISTS—PCI Status Register (SATA–D31:F2) .......................................... |
471 |
13.1.5 |
RID—Revision Identification Register (SATA—D31:F2) .............................. |
471 |
13.1.6 |
PI—Programming Interface Register (SATA–D31:F2) ................................ |
472 |
|
13.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ......... |
472 |
|
13.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h ......... |
472 |
|
13.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h ......... |
472 |
13.1.7 |
SCC—Sub Class Code Register (SATA–D31:F2)........................................ |
473 |
13.1.8 |
BCC—Base Class Code Register |
|
|
(SATA–D31:F2SATA–D31:F2)................................................................ |
473 |
13.1.9 |
PMLT—Primary Master Latency Timer Register |
|
|
(SATA–D31:F2)................................................................................... |
473 |
13.1.10 HTYPE—Header Type Register |
|
|
|
(SATA–D31:F2)................................................................................... |
473 |
13.1.11 PCMD_BAR—Primary Command Block Base Address |
|
|
|
Register (SATA–D31:F2) ...................................................................... |
474 |
13.1.12 PCNL_BAR—Primary Control Block Base Address Register |
|
|
|
(SATA–D31:F2)................................................................................... |
474 |
13.1.13 SCMD_BAR—Secondary Command Block Base Address |
|
|
|
Register (SATA D31:F2) ....................................................................... |
474 |
13.1.14 SCNL_BAR—Secondary Control Block Base Address |
|
|
|
Register (SATA D31:F2) ....................................................................... |
475 |
13.1.15 BAR—Legacy Bus Master Base Address Register |
|
|
|
(SATA–D31:F2)................................................................................... |
475 |
13.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA |
|
|
|
Index Data Pair Base Address (SATA–D31:F2)......................................... |
475 |
|
13.1.16.1 When SCC is not 01h ............................................................. |
476 |
|
13.1.16.2 When SCC is 01h................................................................... |
476 |
13.1.17 SVID—Subsystem Vendor Identification Register |
|
|
|
(SATA–D31:F2)................................................................................... |
476 |
13.1.18 SID—Subsystem Identification Register (SATA–D31:F2) ........................... |
477 |
|
13.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)................................... |
477 |
|
13.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) ..................................... |
477 |
|
13.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2)....................................... |
477 |
|
13.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2)........................................ |
478 |
|
13.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)............................... |
478 |
|
13.1.24 SDMA_CNT—Synchronous DMA Control Register |
|
|
|
(SATA–D31:F2)................................................................................... |
478 |
13.1.25 SDMA_TIM—Synchronous DMA Timing Register |
|
|
|
(SATA–D31:F2)................................................................................... |
479 |
13.1.26 IDE_CONFIG—IDE I/O Configuration Register |
|
|
|
(SATA–D31:F2)................................................................................... |
479 |
13.1.27 PID—PCI Power Management Capability Identification |
|
|
|
Register (SATA–D31:F2) ...................................................................... |
479 |
14 |
Datasheet |
13.1.28 PC—PCI Power Management Capabilities Register |
|
|
(SATA–D31:F2) .................................................................................. |
480 |
|
13.1.29 PMCS—PCI Power Management Control and Status |
|
|
Register (SATA–D31:F2) ...................................................................... |
480 |
|
13.1.30 MSICI—Message Signaled Interrupt Capability |
|
|
Identification Register (SATA–D31:F2) ................................................... |
481 |
|
13.1.31 MSIMC—Message Signaled Interrupt Message |
|
|
Control Register (SATA–D31:F2) ........................................................... |
481 |
|
13.1.32 MSIMA—Message Signaled Interrupt Message |
|
|
Address Register (SATA–D31:F2) .......................................................... |
482 |
|
13.1.33 MSIMD—Message Signaled Interrupt Message |
|
|
Data Register (SATA–D31:F2)............................................................... |
483 |
|
13.1.34 MAP—Address Map Register (SATA–D31:F2)........................................... |
483 |
|
13.1.35 PCS—Port Control and Status Register (SATA–D31:F2) ............................ |
483 |
|
13.1.36 SCLKCG—SATA Clock Gating Control Register ......................................... |
486 |
|
13.1.37 SGC—SATA General Configuration Register............................................. |
486 |
|
13.1.38 SATACR0—SATA Capability Register 0 (SATA–D31:F2)............................. |
487 |
|
13.1.39 SATACR1—SATA Capability Register 1 (SATA–D31:F2)............................. |
487 |
|
13.1.40 FLRCID—FLR Capability Identification Register (SATA–D31:F2) ................. |
488 |
|
13.1.41 FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2)......... |
488 |
|
13.1.42 FLRC—FLR Control Register (SATA–D31:F2) ........................................... |
488 |
|
13.1.43 ATC—APM Trapping Control Register (SATA–D31:F2) ............................... |
489 |
|
13.1.44 ATS—APM Trapping Status Register (SATA–D31:F2) ................................ |
489 |
|
13.1.45 SP—Scratch Pad Register (SATA–D31:F2) .............................................. |
489 |
|
13.1.46 BFCS—BIST FIS Control/Status Register (SATA–D31:F2).......................... |
489 |
|
13.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)....................... |
491 |
|
13.1.48 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)....................... |
491 |
|
13.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. |
492 |
|
13.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)......................... |
493 |
|
13.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) .............................. |
493 |
|
13.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer |
|
|
Register (D31:F2) ............................................................................... |
494 |
|
13.2.4 AIR—AHCI Index Register (D31:F2)....................................................... |
494 |
|
13.2.5 AIDR—AHCI Index Data Register (D31:F2) ............................................. |
495 |
|
13.3 Serial ATA Index/Data Pair Superset Registers .................................................... |
495 |
|
13.3.1 SINDX—Serial ATA Index Register (D31:F2) ........................................... |
495 |
|
13.3.2 SDATA—Serial ATA Data Register (D31:F2) ............................................ |
496 |
|
13.3.2.1 |
PxSSTS—Serial ATA Status Register (D31:F2)........................... |
496 |
13.3.2.2 |
PxSCTL—Serial ATA Control Register (D31:F2).......................... |
497 |
13.3.2.3 |
PxSERR—Serial ATA Error Register (D31:F2) ............................ |
498 |
13.4 AHCI Registers (D31:F2) .................................................................................. |
499 |
|
13.4.1 AHCI Generic Host Control Registers (D31:F2) ........................................ |
500 |
|
13.4.1.1 CAP—Host Capabilities Register (D31:F2)................................. |
500 |
|
13.4.1.2 |
GHC—Global PCH Control Register (D31:F2) ............................. |
501 |
13.4.1.3 |
IS—Interrupt Status Register (D31:F2) .................................... |
502 |
13.4.1.4 |
PI—Ports Implemented Register (D31:F2) ................................ |
503 |
13.4.1.5 |
VS—AHCI Version Register (D31:F2) ....................................... |
504 |
13.4.1.6 |
EM_LOC—Enclosure Management Location Register (D31:F2) ..... |
504 |
13.4.1.7 |
EM_CTRL—Enclosure Management Control Register (D31:F2) ..... |
504 |
13.4.1.8 CAP2—HBA Capabilities Extended Register ............................... |
505 |
|
13.4.1.9 |
RSTF—Intel® RST Feature Capabilities Register......................... |
506 |
13.4.2 Port Registers (D31:F2) ....................................................................... |
507 |
|
13.4.2.1 |
PxCLB—Port [5:0] Command List Base Address Register |
|
|
(D31:F2) ............................................................................. |
509 |
13.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper |
|
|
|
32-Bits Register (D31:F2) ...................................................... |
510 |
13.4.2.3 |
PxFB—Port [5:0] FIS Base Address Register (D31:F2)................ |
510 |
13.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits |
|
|
|
Register (D31:F2) ................................................................. |
510 |
13.4.2.5 |
PxIS—Port [5:0] Interrupt Status Register (D31:F2) .................. |
511 |
13.4.2.6 |
PxIE—Port [5:0] Interrupt Enable Register (D31:F2).................. |
512 |
13.4.2.7 |
PxCMD—Port [5:0] Command Register (D31:F2) ....................... |
513 |
13.4.2.8 |
PxTFD—Port [5:0] Task File Data Register (D31:F2) .................. |
515 |
13.4.2.9 |
PxSIG—Port [5:0] Signature Register (D31:F2)......................... |
516 |
13.4.2.10 |
PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2)............ |
516 |
13.4.2.11 |
PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2) ........... |
517 |
13.4.2.12 |
PxSERR—Port [5:0] Serial ATA Error Register (D31:F2).............. |
518 |
Datasheet |
15 |
|
|
|
13.4.2.13 |
.............PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) |
519 |
|
|
|
13.4.2.14 |
PxCI—Port [5:0] Command Issue Register (D31:F2) .................. |
520 |
14 SATA Controller Registers (D31:F5) ....................................................................... |
521 |
||||
|
|
14.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ |
521 |
||
14.1.1 |
VID—Vendor Identification Register (SATA—D31:F5)................................ |
522 |
|||
14.1.2 |
DID—Device Identification Register (SATA—D31:F5) ................................ |
522 |
|||
14.1.3 |
PCICMD—PCI Command Register (SATA–D31:F5) .................................... |
522 |
|||
14.1.4 |
PCISTS—PCI Status Register (SATA–D31:F5) .......................................... |
523 |
|||
|
|
14.1.5 RID—Revision Identification Register (SATA—D31:F5) .............................. |
524 |
||
14.1.6 |
PI—Programming Interface Register (SATA–D31:F5) ................................ |
524 |
|||
14.1.7 |
SCC—Sub Class Code Register (SATA–D31:F5)........................................ |
524 |
|||
14.1.8 |
BCC—Base Class Code Register |
525 |
|||
14.1.9 |
(SATA–D31:F5SATA–D31:F5)................................................................ |
||||
PCMD_BAR—Primary Command Block Base Address |
525 |
||||
|
|
|
Register (SATA–D31:F5) ...................................................................... |
||
|
|
14.1.10 PCNL_BAR—Primary Control Block Base Address Register |
525 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.11 SCMD_BAR—Secondary Command Block Base Address |
526 |
||
|
|
|
Register (SATA D31:F5) ....................................................................... |
||
|
|
14.1.12 SCNL_BAR—Secondary Control Block Base Address |
526 |
||
|
|
|
Register (SATA D31:F5) ....................................................................... |
||
|
|
14.1.13 BAR—Legacy Bus Master Base Address Register |
526 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.14 SIDPBA—SATA Index/Data Pair Base Address Register |
527 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.15 SVID—Subsystem Vendor Identification Register |
527 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.16 SID—Subsystem Identification Register (SATA–D31:F5) ........................... |
527 |
||
|
|
14.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5)................................... |
527 |
||
|
|
14.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5) ..................................... |
528 |
||
|
|
14.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5)....................................... |
528 |
||
|
|
14.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5)........................................ |
528 |
||
|
|
14.1.21 SDMA_CNT—Synchronous DMA Control Register |
528 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.22 SDMA_TIM—Synchronous DMA Timing Register |
529 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.23 IDE_CONFIG—IDE I/O Configuration Register |
529 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.24 PID—PCI Power Management Capability Identification |
530 |
||
|
|
|
Register (SATA–D31:F5) ...................................................................... |
||
|
|
14.1.25 PC—PCI Power Management Capabilities Register |
530 |
||
|
|
|
(SATA–D31:F5)................................................................................... |
||
|
|
14.1.26 PMCS—PCI Power Management Control and Status |
530 |
||
|
|
|
Register (SATA–D31:F5) ...................................................................... |
||
|
|
14.1.27 MAP—Address Map Register (SATA–D31:F5) ........................................... |
531 |
||
|
|
14.1.28 PCS—Port Control and Status Register (SATA–D31:F5)............................. |
532 |
||
|
|
14.1.29 SATACR0—SATA Capability Register 0 (SATA–D31:F5) ............................. |
532 |
||
|
|
14.1.30 SATACR1—SATA Capability Register 1 (SATA–D31:F5) ............................. |
533 |
||
|
|
14.1.31 FLRCID—FLR Capability ID Register (SATA–D31:F5)................................. |
533 |
||
|
|
14.1.32 FLRCLV—FLR Capability Length and |
533 |
||
|
|
|
Value Register (SATA–D31:F5).............................................................. |
||
|
|
14.1.33 FLRCTRL—FLR Control Register (SATA–D31:F5)....................................... |
534 |
||
|
|
14.1.34 ATC—APM Trapping Control Register (SATA–D31:F5) ............................... |
534 |
||
|
|
14.1.35 ATC—APM Trapping Control Register (SATA–D31:F5) ............................... |
534 |
||
|
|
14.2 Bus Master IDE I/O Registers (D31:F5)............................................................... |
534 |
||
|
|
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ......................... |
535 |
||
|
|
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) .............................. |
536 |
||
|
|
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer |
536 |
||
|
|
|
Register (D31:F5)................................................................................ |
||
|
|
14.3 Serial ATA Index/Data Pair Superset Registers..................................................... |
537 |
||
|
|
14.3.1 SINDX—SATA Index Register (D31:F5)................................................... |
537 |
||
|
|
14.3.2 SDATA—SATA Index Data Register (D31:F5)........................................... |
537 |
||
|
|
|
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5) ........................... |
538 |
|
|
|
|
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F5) .......................... |
539 |
|
|
|
|
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) ............................. |
540 |
|
16 |
Datasheet |
15 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... |
541 |
|
15.1 USB EHCI Configuration Registers |
|
|
(USB EHCI—D29:F0, D26:F0) ........................................................................... |
541 |
|
15.1.1 |
VID—Vendor Identification Register |
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
542 |
15.1.2 |
DID—Device Identification Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
542 |
15.1.3 |
PCICMD—PCI Command Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
542 |
15.1.4 |
PCISTS—PCI Status Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
543 |
15.1.5 |
RID—Revision Identification Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
544 |
15.1.6 |
PI—Programming Interface Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
545 |
15.1.7 |
SCC—Sub Class Code Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
545 |
15.1.8 |
BCC—Base Class Code Register |
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
545 |
15.1.9 |
PMLT—Primary Master Latency Timer Register |
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
545 |
15.1.10 HEADTYP—Header Type Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
545 |
15.1.11 MEM_BASE—Memory Base Address Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
546 |
15.1.12 SVID—USB EHCI Subsystem Vendor ID Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
546 |
15.1.13 SID—USB EHCI Subsystem ID Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
546 |
15.1.14 |
CAP_PTR—Capabilities Pointer Register |
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
547 |
15.1.15 INT_LN—Interrupt Line Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
547 |
15.1.16 INT_PN—Interrupt Pin Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
547 |
15.1.17 PWR_CAPID—PCI Power Management Capability |
|
|
|
Identification Register (USB EHCI—D29:F0, D26:F0) ............................... |
547 |
15.1.18 NXT_PTR1—Next Item Pointer #1 Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
548 |
15.1.19 PWR_CAP—Power Management Capabilities Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
548 |
15.1.20 PWR_CNTL_STS—Power Management Control / |
|
|
|
Status Register (USB EHCI—D29:F0, D26:F0)......................................... |
549 |
15.1.21 DEBUG_CAPID—Debug Port Capability ID Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
549 |
15.1.22 NXT_PTR2—Next Item Pointer #2 Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
550 |
15.1.23 DEBUG_BASE—Debug Port Base Offset Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
550 |
15.1.24 USB_RELNUM—USB Release Number Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
550 |
15.1.25 FL_ADJ—Frame Length Adjustment Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
551 |
15.1.26 PWAKE_CAP—Port Wake Capability Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
552 |
15.1.27 PDO—Port Disable Override Register...................................................... |
552 |
|
15.1.28 RMHDEVR—RMH Device Removable Field Register ................................... |
553 |
|
15.1.29 LEG_EXT_CAP—USB EHCI Legacy Support Extended |
|
|
|
Capability Register (USB EHCI—D29:F0, D26:F0) .................................... |
553 |
15.1.30 LEG_EXT_CS—USB EHCI Legacy Support Extended |
|
|
|
Control / Status Register (USB EHCI—D29:F0, D26:F0)............................ |
554 |
15.1.31 SPECIAL_SMI—Intel® Specific USB 2.0 SMI Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
555 |
15.1.32 OCMAP—Over-Current Mapping Register ................................................ |
557 |
|
15.1.33 RMHWKCTL—RMH Wake Control Register ............................................... |
558 |
|
15.1.34 ACCESS_CNTL—Access Control Register |
|
|
|
(USB EHCI—D29:F0, D26:F0)............................................................... |
558 |
Datasheet |
17 |
|
|
15.1.35 EHCIIR1—EHCI Initialization Register 1 |
559 |
||
|
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
||
|
|
15.1.36 FLR_CID—Function Level Reset Capability ID Register |
559 |
||
|
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
||
|
|
15.1.37 FLR_NEXT—Function Level Reset Next Capability |
559 |
||
|
|
|
Pointer Register (USB EHCI—D29:F0, D26:F0) ........................................ |
||
|
|
15.1.38 FLR_CLV—Function Level Reset Capability Length and |
559 |
||
|
|
|
Version Register (USB EHCI—D29:F0, D26:F0)........................................ |
||
|
|
15.1.39 FLR_CTRL—Function Level Reset Control Register |
560 |
||
|
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
||
|
|
15.1.40 FLR_STS—Function Level Reset Status Register |
560 |
||
|
|
|
(USB EHCI—D29:F0, D26:F0) ............................................................... |
||
|
|
15.2 Memory-Mapped I/O Registers .......................................................................... |
561 |
||
|
|
15.2.1 Host Controller Capability Registers ....................................................... |
561 |
||
|
|
|
15.2.1.1 CAPLENGTH—Capability Registers Length Register ..................... |
562 |
|
|
|
|
15.2.1.2 HCIVERSION—Host Controller Interface Version Number |
562 |
|
|
|
|
|
Register ............................................................................... |
|
|
|
|
15.2.1.3 HCSPARAMS—Host Controller Structural Parameters .................. |
562 |
|
|
|
|
15.2.1.4 HCCPARAMS—Host Controller Capability Parameters |
563 |
|
15.2.2 |
|
Register ............................................................................... |
|||
Host Controller Operational Registers ..................................................... |
564 |
||||
|
|
|
15.2.2.1 USB2.0_CMD—USB 2.0 Command Register............................... |
565 |
|
|
|
|
15.2.2.2 USB2.0_STS—USB 2.0 Status Register ..................................... |
567 |
|
|
|
|
15.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register...................... |
569 |
|
|
|
|
15.2.2.4 |
FRINDEX—Frame Index Register ............................................. |
570 |
|
|
|
15.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment |
571 |
|
|
|
|
|
Register ............................................................................... |
|
|
|
|
15.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address |
571 |
|
|
|
|
|
Register ............................................................................... |
|
|
|
|
15.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address |
572 |
|
|
|
|
15.2.2.8 |
Register ............................................................................... |
|
|
|
|
CONFIGFLAG—Configure Flag Register ..................................... |
572 |
|
15.2.3 |
15.2.2.9 PORTSC—Port N Status and Control Register............................. |
572 |
|||
USB 2.0-Based Debug Port Registers...................................................... |
575 |
||||
|
|
|
15.2.3.1 CNTL_STS—Control / Status Register ....................................... |
576 |
|
|
|
|
15.2.3.2 |
USBPID—USB PIDs Register.................................................... |
577 |
|
|
|
15.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ....................... |
577 |
|
|
|
|
15.2.3.4 |
CONFIG—Configuration Register.............................................. |
578 |
16 xHCI Controller Registers (D20:F0)........................................................................ |
579 |
||||
|
|
16.1 USB xHCI Configuration Registers |
579 |
||
|
|
(USB xHCI—D20:F0)........................................................................................ |
|||
|
|
16.1.1 VID—Vendor Identification Register |
580 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.2 DID—Device Identification Register |
580 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.3 PCICMD—PCI Command Register |
581 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.4 PCISTS—PCI Status Register |
582 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.5 RID—Revision Identification Register |
583 |
||
16.1.6 |
(USB xHCI—D20:F0)............................................................................ |
||||
PI—Programming Interface Register |
583 |
||||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.7 SCC—Sub Class Code Register |
583 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.8 BCC—Base Class Code Register |
583 |
||
16.1.9 |
(USB xHCI—D20:F0)............................................................................ |
||||
PMLT—Primary Master Latency Timer Register |
583 |
||||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.10 HEADTYP—Header Type Register |
584 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.11 MEM_BASE_L—Memory Base Address Low Register |
584 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
|
|
16.1.12 MEM_BASE_H—Memory Base Address High Register |
584 |
||
|
|
|
(USB xHCI—D20:F0)............................................................................ |
||
18 |
Datasheet |
16.1.13 SVID—USB xHCI Subsystem Vendor ID Register |
|
(USB xHCI—D20:F0) ........................................................................... |
584 |
16.1.14 SID—USB xHCI Subsystem ID Register |
|
(USB xHCI—D20:F0) ........................................................................... |
585 |
16.1.15 CAP_PTR—Capabilities Pointer Register |
|
(USB xHCI—D20:F0) ........................................................................... |
585 |
16.1.16 INT_LN—Interrupt Line Register |
|
(USB xHCI—D20:F0) ........................................................................... |
585 |
16.1.17 INT_PN—Interrupt Pin Register |
|
(USB xHCI—D20:F0) ........................................................................... |
585 |
16.1.18 XHCC—xHC System Bus Configuration Register |
|
(USB xHCI—D20:F0) ........................................................................... |
585 |
16.1.19 XHCC2—xHC System Bus Configuration Register 2 |
|
(USB xHCI—D20:F0) ........................................................................... |
586 |
16.1.20 SBRN—Serial Bus Release Number |
|
Register (USB xHCI—D20:F0)............................................................... |
586 |
16.1.21 FL_ADJ—Frame Length Adjustment Register |
|
(USB xHCI—D20:F0) ........................................................................... |
587 |
16.1.22 PWR_CAPID—PCI Power Management Capability ID |
|
Register (USB xHCI—D20:F0)............................................................... |
587 |
16.1.23 NXT_PTR1—Next Item Pointer #1 Register |
|
(USB xHCI—D20:F0) ........................................................................... |
588 |
16.1.24 PWR_CAP—Power Management Capabilities Register |
|
(USB xHCI—D20:F0) ........................................................................... |
588 |
16.1.25 PWR_CNTL_STS—Power Management Control / |
|
Status Register (USB xHCI—D20:F0) ..................................................... |
589 |
16.1.26 MSI_CAPID—Message Signaled Interrupt Capability ID Register |
|
(USB xHCI—D20:F0) ........................................................................... |
589 |
16.1.27 NEXT_PTR2—Next Item Pointer Register #2 |
|
(USB xHCI—D20:F0) ........................................................................... |
589 |
16.1.28 MSI_MCTL—MSI Message Control Register |
|
(USB xHCI—D20:F0) ........................................................................... |
590 |
16.1.29 MSI_LMAD—MSI Lower Message Address Register |
|
(USB xHCI—D20:F0) ........................................................................... |
590 |
16.1.30 MSI_UMAD—MSI Upper Message Address Register |
|
(USB xHCI—D20:F0) ........................................................................... |
590 |
16.1.31 MSI_MD—MSI Message Data Register |
|
(USB xHCI—D20:F0) ........................................................................... |
591 |
16.1.32 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1 |
|
(USB xHCI—D20:F0) ........................................................................... |
591 |
16.1.33 U2OCM2 - XHCI USB2 Overcurrent Mapping Register 2 |
|
(USB xHCI—D20:F0) ........................................................................... |
591 |
16.1.34 U3OCM1 - XHCI USB3 Overcurrent Pin Mapping 1 |
|
(USB xHCI—D20:F0) ........................................................................... |
592 |
16.1.35 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2 |
|
(USB xHCI—D20:F0) ........................................................................... |
593 |
16.1.36 XUSB2PR—xHC USB 2.0 Port Routing Register |
|
(USB xHCI—D20:F0) ........................................................................... |
593 |
16.1.37 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register |
|
(USB xHCI—D20:F0) ........................................................................... |
594 |
16.1.38 USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register |
|
(USB xHCI—D20:F0) ........................................................................... |
594 |
16.1.39 USB3PRM—USB 3.0 Port Routing Mask Register |
|
(USB xHCI—D20:F0) ........................................................................... |
595 |
16.1.40 USB2PDO—xHCI USB Port Disable Override Register |
|
(USB xHCI—D20:F0) ........................................................................... |
595 |
16.1.41 USB3PDO—USB3 Port Disable Override |
|
(USB xHCI—D20:F0) ........................................................................... |
596 |
16.2 Memory-Mapped I/O Registers .......................................................................... |
596 |
16.2.1 Host Controller Capability Registers ....................................................... |
597 |
16.2.1.1CAPLENGTH—Capability Registers Length Register.....................
16.2.1.2HCIVERSION—Host Controller Interface Version Number Register...............................................................................
16.2.1.3HCSPARAMS1—Host Controller Structural Parameters #1 Register597
16.2.1.4HCSPARAMS2—Host Controller Structural Parameters #2 Register598
16.2.1.5HCSPARAMS3—Host Controller Structural Parameters #3 Register598
16.2.1.6HCCPARAMS—Host Controller Capability Parameters Register ..... 599597597
Datasheet |
19 |
16.2.1.7 |
dBOFF—Doorbell Offset Register.............................................. |
599 |
16.2.1.8 |
RTSOFF—Runtime Register Space Offset Register ...................... |
600 |
16.2.2 Host Controller Operational Registers ..................................................... |
600 |
|
16.2.2.1 |
USB_CMD—USB Command Register......................................... |
601 |
16.2.2.2 |
USB_STS—USB Status Register............................................... |
602 |
16.2.2.3 |
PAGESIZE—Page Size Register ................................................ |
603 |
16.2.2.4 |
DNCTRL—Device Notification Control Register ........................... |
603 |
16.2.2.5 |
CRCRL—Command Ring Control Low Register............................ |
604 |
16.2.2.6 |
CRCRH—Command Ring Control High Register .......................... |
605 |
16.2.2.7 |
DCBAAPL—Device Context Base Address Array Pointer Low |
|
|
Register ............................................................................... |
605 |
16.2.2.8 |
DCBAAPH—Device Context Base Address Array Pointer High |
|
|
Register ............................................................................... |
605 |
16.2.2.9 |
CONFIG—Configure Register ................................................... |
605 |
16.2.2.10 |
PORTSCNUSB2—Port N Status and Control USB2 Register........... |
606 |
16.2.2.11 PORTPMSCNUSB2—xHCI Port N Power Management Status and |
|
|
|
Control USB2 Register............................................................ |
610 |
16.2.2.12 |
PORTSCNUSB3—xHCI USB 3.0 Port N Status and Control Register611 |
|
16.2.2.13 PORTPMSCN—Port N Power Management Status and Control |
|
|
|
USB3 Register....................................................................... |
615 |
16.2.2.14 |
PORTLIX—USB 3.0 Port X Link Info Register.............................. |
616 |
16.2.3 Host Controller Runtime Registers.......................................................... |
616 |
|
16.2.3.1 |
MFINDEX—Microframe Index Register ...................................... |
616 |
16.2.3.2 |
IMAN—Interrupter X Management Register ............................... |
617 |
16.2.3.3 |
IMOD—Interrupter X Moderation Register ................................. |
618 |
16.2.3.4 |
ERSTSZ—Event Ring Segment Table Size X Register .................. |
618 |
16.2.3.5 |
ERSTBAL—Event Ring Segment Table Base Address Low X |
|
|
Register ............................................................................... |
619 |
16.2.3.6 |
ERSTBAH—Event Ring Segment Table Base Address High X |
|
|
Register ............................................................................... |
619 |
16.2.3.7 |
ERDPL—Event Ring Dequeue Pointer Low X Register .................. |
620 |
16.2.3.8 |
ERDPH—Event Ring Dequeue Pointer High X Register ................. |
620 |
16.2.4 Doorbell Registers ............................................................................... |
620 |
|
16.2.4.1 |
DOORBELL—Doorbell X Register .............................................. |
621 |
17 Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers .... |
622 |
|
17.1 Intel® High Definition Audio (Intel® HD Audio) Controller Registers (D27:F0) .......... |
622 |
|
17.1.1 Intel® High Definition Audio PCI Configuration Space |
|
|
(Intel® High Definition Audio—D27:F0) .................................................. |
622 |
|
17.1.1.1 |
VID—Vendor Identification Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
624 |
17.1.1.2 |
DID—Device Identification Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
624 |
17.1.1.3 |
PCICMD—PCI Command Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
624 |
17.1.1.4 |
PCISTS—PCI Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
625 |
17.1.1.5 |
RID—Revision Identification Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
625 |
17.1.1.6 |
PI—Programming Interface Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
626 |
17.1.1.7 |
SCC—Sub Class Code Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
626 |
17.1.1.8 |
BCC—Base Class Code Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
626 |
17.1.1.9 |
CLS—Cache Line Size Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
626 |
17.1.1.10 |
LT—Latency Timer Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
626 |
17.1.1.11 |
HEADTYP—Header Type Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
627 |
17.1.1.12 |
HdBARL—Intel® High Definition Audio Lower Base Address |
|
|
Register (Intel® High Definition Audio—D27:F0) ........................ |
627 |
17.1.1.13 |
HdBARU—Intel® High Definition Audio Upper Base Address |
|
|
Register (Intel® High Definition Audio Controller—D27:F0).......... |
627 |
17.1.1.14 |
SVID—Subsystem Vendor Identification Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
627 |
20 |
Datasheet |
17.1.1.15 |
SID—Subsystem Identification Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
628 |
17.1.1.16 |
CAPPTR—Capabilities Pointer Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
628 |
17.1.1.17 |
INTLN—Interrupt Line Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
628 |
17.1.1.18 |
INTPN—Interrupt Pin Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
628 |
17.1.1.19 |
HDCTL—Intel® High Definition Audio Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
629 |
17.1.1.20 |
DCKCTL—Docking Control Register (Mobile Only) |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
629 |
17.1.1.21 |
DCKSTS—Docking Status Register (Mobile Only) |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
629 |
17.1.1.22 |
PID—PCI Power Management Capability ID Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
630 |
17.1.1.23 |
PC—Power Management Capabilities Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
630 |
17.1.1.24 |
PCS—Power Management Control and Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
630 |
17.1.1.25 |
MID—MSI Capability ID Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
631 |
17.1.1.26 |
MMC—MSI Message Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
631 |
17.1.1.27 MMLA—MSI Message Lower Address Register |
|
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
632 |
17.1.1.28 MMUA—MSI Message Upper Address Register |
|
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
632 |
17.1.1.29 MMD—MSI Message Data Register |
|
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
632 |
17.1.1.30 |
PXID—PCI Express* Capability ID Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
632 |
17.1.1.31 |
PXC—PCI Express* Capabilities Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
632 |
17.1.1.32 |
DEVCAP—Device Capabilities Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
633 |
17.1.1.33 |
DEVC—Device Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
633 |
17.1.1.34 |
DEVS—Device Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
634 |
17.1.1.35 |
VCCAP—Virtual Channel Enhanced Capability Header |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
634 |
17.1.1.36 |
PVCCAP1—Port VC Capability Register 1 |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
635 |
17.1.1.37 |
PVCCAP2—Port VC Capability Register 2 |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
635 |
17.1.1.38 |
PVCCTL—Port VC Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
635 |
17.1.1.39 |
PVCSTS—Port VC Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
635 |
17.1.1.40 |
VC0CAP—VC0 Resource Capability Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
636 |
17.1.1.41 |
VC0CTL—VC0 Resource Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
636 |
17.1.1.42 |
VC0STS—VC0 Resource Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
636 |
17.1.1.43 |
VCiCAP—VCi Resource Capability Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
637 |
17.1.1.44 |
VCiCTL—VCi Resource Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
637 |
17.1.1.45 |
VCiSTS—VCi Resource Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
637 |
17.1.1.46 |
RCCAP—Root Complex Link Declaration Enhanced |
|
|
Capability Header Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
638 |
17.1.1.47 |
ESD—Element Self Description Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
638 |
Datasheet |
21 |
17.1.1.48 |
L1DESC—Link 1 Description Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
638 |
17.1.1.49 |
L1ADDL—Link 1 Lower Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
638 |
17.1.1.50 |
L1ADDU—Link 1 Upper Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
639 |
17.1.2 Intel® High Definition Audio Memory Mapped Configuration Registers |
|
|
(Intel® High Definition Audio D27:F0) .................................................... |
640 |
|
17.1.2.1 |
GCAP—Global Capabilities Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
643 |
17.1.2.2 |
VMIN—Minor Version Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
644 |
17.1.2.3 |
VMAJ—Major Version Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
644 |
17.1.2.4 |
OUTPAY—Output Payload Capability Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
644 |
17.1.2.5 |
INPAY—Input Payload Capability Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
644 |
17.1.2.6 |
GCTL—Global Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
645 |
17.1.2.7 |
WAKEEN—Wake Enable Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
646 |
17.1.2.8 |
STATESTS—State Change Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
646 |
17.1.2.9 |
GSTS—Global Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
646 |
17.1.2.10 |
GCAP2 Global Capabilities 2 Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
647 |
17.1.2.11 |
OUTSTRMPAY—Output Stream Payload Capability |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
647 |
17.1.2.12 |
INSTRMPAY—Input Stream Payload Capability |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
647 |
17.1.2.13 |
INTCTL—Interrupt Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
648 |
17.1.2.14 |
INTSTS—Interrupt Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
649 |
17.1.2.15 |
WALCLK—Wall Clock Counter Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
649 |
17.1.2.16 |
SSYNC—Stream Synchronization Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
650 |
17.1.2.17 |
CORBLBASE—CORB Lower Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
650 |
17.1.2.18 |
CORBUBASE—CORB Upper Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
650 |
17.1.2.19 |
CORBWP—CORB Write Pointer Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
651 |
17.1.2.20 |
CORBRP—CORB Read Pointer Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
651 |
17.1.2.21 |
CORBCTL—CORB Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
651 |
17.1.2.22 |
CORBST—CORB Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
652 |
17.1.2.23 |
CORBSIZE—CORB Size Register |
|
|
Intel® High Definition Audio Controller—D27:F0) ....................... |
652 |
17.1.2.24 |
RIRBLBASE—RIRB Lower Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
652 |
17.1.2.25 |
RIRBUBASE—RIRB Upper Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
652 |
17.1.2.26 |
RIRBWP—RIRB Write Pointer Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
653 |
17.1.2.27 |
RINTCNT—Response Interrupt Count Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
653 |
17.1.2.28 |
RIRBCTL—RIRB Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
653 |
17.1.2.29 |
RIRBSTS—RIRB Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0)...................... |
654 |
22 |
Datasheet |
17.1.2.30 |
RIRBSIZE—RIRB Size Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
654 |
17.1.2.31 IC—Immediate Command Register |
|
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
654 |
17.1.2.32 |
IR—Immediate Response Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
655 |
17.1.2.33 ICS—Immediate Command Status Register |
|
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
655 |
17.1.2.34 |
DPLBASE—DMA Position Lower Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
655 |
17.1.2.35 |
DPUBASE—DMA Position Upper Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
656 |
17.1.2.36 |
SDCTL—Stream Descriptor Control Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
656 |
17.1.2.37 |
SDSTS—Stream Descriptor Status Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
657 |
17.1.2.38 |
SDLPIB—Stream Descriptor Link Position in Buffer |
|
|
Register (Intel® High Definition Audio Controller—D27:F0) ......... |
658 |
17.1.2.39 |
SDCBL—Stream Descriptor Cyclic Buffer Length Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
658 |
17.1.2.40 |
SDLVI—Stream Descriptor Last Valid Index Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
659 |
17.1.2.41 |
SDFIFOW—Stream Descriptor FIFO Watermark Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
659 |
17.1.2.42 |
ISDFIFOS—Input Stream Descriptor FIFO Size Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
660 |
17.1.2.43 |
SDFMT—Stream Descriptor Format Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
660 |
17.1.2.44 |
SdBDPL—Stream Descriptor Buffer Descriptor List |
|
|
Pointer Lower Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
661 |
17.1.2.45 |
SdBDPU—Stream Descriptor Buffer Descriptor List |
|
|
Pointer Upper Base Address Register |
|
|
(Intel® High Definition Audio Controller—D27:F0) ..................... |
661 |
18 SMBus Controller Registers (D31:F3) .................................................................... |
662 |
|
18.1 PCI Configuration Registers (SMBus—D31:F3)..................................................... |
662 |
|
18.1.1 VID—Vendor Identification Register (SMBus—D31:F3) ............................. |
662 |
|
18.1.2 DID—Device Identification Register (SMBus—D31:F3).............................. |
663 |
|
18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3)................................. |
663 |
|
18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)....................................... |
664 |
|
18.1.5 RID—Revision Identification Register (SMBus—D31:F3)............................ |
664 |
|
18.1.6 PI—Programming Interface Register (SMBus—D31:F3)............................. |
664 |
|
18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3) .................................... |
665 |
|
18.1.8 BCC—Base Class Code Register (SMBus—D31:F3) ................................... |
665 |
|
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0 |
|
|
Register (SMBus—D31:F3) ................................................................... |
665 |
|
18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1 |
|
|
Register (SMBus—D31:F3) ................................................................... |
665 |
|
18.1.11 SMB_BASE—SMBus Base Address Register |
|
|
(SMBus—D31:F3) ............................................................................... |
666 |
|
18.1.12 SVID—Subsystem Vendor Identification Register |
|
|
(SMBus—D31:F2/F4)........................................................................... |
666 |
|
18.1.13 SID—Subsystem Identification Register |
|
|
(SMBus—D31:F2/F4)........................................................................... |
666 |
|
18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) .................................. |
666 |
|
18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3) ................................... |
667 |
|
18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) ............................ |
667 |
|
18.2 SMBus I/O and Memory Mapped I/O Registers .................................................... |
668 |
|
18.2.1 HST_STS—Host Status Register (SMBus—D31:F3) .................................. |
669 |
|
18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3) ................................. |
670 |
|
18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) ............................ |
671 |
|
18.2.4 XMIT_SLVA—Transmit Slave Address Register |
|
|
(SMBus—D31:F3) ............................................................................... |
671 |
|
18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3).................................... |
671 |
|
18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3).................................... |
672 |
|
Datasheet |
23 |
18.2.7 |
Host_BLOCK_dB—Host Block Data Byte Register |
|
|
(SMBus—D31:F3)................................................................................ |
672 |
18.2.8 |
PEC—Packet Error Check (PEC) Register |
|
|
(SMBus—D31:F3)................................................................................ |
672 |
18.2.9 |
RCV_SLVA—Receive Slave Address Register |
|
|
(SMBus—D31:F3)................................................................................ |
673 |
18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)....................... |
673 |
|
18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ............................. |
673 |
|
18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ............................ |
674 |
|
18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register |
|
|
|
(SMBus—D31:F3)................................................................................ |
674 |
18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register |
|
|
|
(SMBus—D31:F3)................................................................................ |
675 |
18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3) .................................. |
675 |
|
18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3) ............................ |
676 |
|
18.2.17 NOTIFY_DADDR—Notify Device Address Register |
|
|
|
(SMBus—D31:F3)................................................................................ |
676 |
18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register |
|
|
|
(SMBus—D31:F3)................................................................................ |
676 |
18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register |
|
|
|
(SMBus—D31:F3)................................................................................ |
677 |
19 PCI Express* Configuration Registers .................................................................... |
678 |
|
19.1 PCI Express* Configuration Registers |
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ................................................... |
678 |
|
19.1.1 VID—Vendor Identification Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
680 |
19.1.2 DID—Device Identification Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
680 |
19.1.3 |
PCICMD—PCI Command Register |
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
681 |
19.1.4 PCISTS—PCI Status Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
682 |
19.1.5 RID—Revision Identification Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
683 |
19.1.6 |
PI—Programming Interface Register |
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
683 |
19.1.7 |
SCC—Sub Class Code Register |
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
683 |
19.1.8 BCC—Base Class Code Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
683 |
19.1.9 |
CLS—Cache Line Size Register |
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
684 |
19.1.10 PLT—Primary Latency Timer Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
684 |
19.1.11 HEADTYP—Header Type Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
684 |
19.1.12 BNUM—Bus Number Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
685 |
19.1.13 SLT—Secondary Latency Timer Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
685 |
19.1.14 IOBL—I/O Base and Limit Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
685 |
19.1.15 SSTS—Secondary Status Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
686 |
19.1.16 MBL—Memory Base and Limit Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
687 |
19.1.17 PMBL—Prefetchable Memory Base and Limit Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
687 |
19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits |
|
|
|
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................... |
687 |
19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits |
|
|
|
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................... |
688 |
19.1.20 |
CAPP—Capabilities List Pointer Register |
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
688 |
19.1.21 INTR—Interrupt Information Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
688 |
24 |
Datasheet |
19.1.22 BCTRL—Bridge Control Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
689 |
19.1.23 CLIST—Capabilities List Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
689 |
19.1.24 XCAP—PCI Express* Capabilities Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
690 |
19.1.25 DCAP—Device Capabilities Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
690 |
19.1.26 DCTL—Device Control Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
691 |
19.1.27 DSTS—Device Status Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
692 |
19.1.28 LCAP—Link Capabilities Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
692 |
19.1.29 LCTL—Link Control Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
694 |
19.1.30 LSTS—Link Status Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
695 |
19.1.31 SLCAP—Slot Capabilities Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
696 |
19.1.32 SLCTL—Slot Control Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
697 |
19.1.33 SLSTS—Slot Status Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
697 |
19.1.34 RCTL—Root Control Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
698 |
19.1.35 RSTS—Root Status Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
698 |
19.1.36 DCAP2—Device Capabilities 2 Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
699 |
19.1.37 DCTL2—Device Control 2 Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
699 |
19.1.38 LCTL2—Link Control 2 Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
700 |
19.1.39 LSTS2—Link Status 2 Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
701 |
19.1.40 MID—Message Signaled Interrupt Identifiers Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
702 |
19.1.41 MC—Message Signaled Interrupt Message Control Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
702 |
19.1.42 MA—Message Signaled Interrupt Message Address |
|
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................... |
702 |
19.1.43 MD—Message Signaled Interrupt Message Data Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
703 |
19.1.44 SVCAP—Subsystem Vendor Capability Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
703 |
19.1.45 SVID—Subsystem Vendor Identification Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
703 |
19.1.46 PMCAP—Power Management Capability Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
703 |
19.1.47 PMC—PCI Power Management Capabilities Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
704 |
19.1.48 PMCS—PCI Power Management Control and Status |
|
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................... |
704 |
19.1.49 MPC2—Miscellaneous Port Configuration Register 2 |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
705 |
19.1.50 MPC—Miscellaneous Port Configuration Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
705 |
19.1.51 SMSCS—SMI/SCI Status Register |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
707 |
19.1.52 RPDCGEN—Root Port Dynamic Clock Gating Enable |
|
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7) ............................ |
707 |
19.1.53 PECR3—PCI Express* Configuration Register 3 |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... |
708 |
19.1.54 PECR4—PCI Express* Configuration Register 4 |
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5)................................................ |
708 |
Datasheet |
25 |
19.1.55 UES—Uncorrectable Error Status Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
710 |
19.1.56 UEM—Uncorrectable Error Mask Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
711 |
19.1.57 UEV—Uncorrectable Error Severity Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
712 |
19.1.58 CES—Correctable Error Status Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
713 |
19.1.59 CEM—Correctable Error Mask Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
713 |
19.1.60 AECC—Advanced Error Capabilities and Control Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
714 |
19.1.61 RES—Root Error Status Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
714 |
19.1.62 PECR2—PCI Express* Configuration Register 2 |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
715 |
19.1.63 PEETM—PCI Express* Extended Test Mode Register |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
715 |
19.1.64 PEC1—PCI Express* Configuration Register 1 |
|
|
|
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... |
715 |
20 High Precision Event Timer Registers..................................................................... |
716 |
|
20.1 Memory Mapped Registers ................................................................................ |
716 |
|
20.1.1 |
GCAP_ID—General Capabilities and Identification Register ........................ |
717 |
20.1.2 |
GEN_CONF—General Configuration Register............................................ |
718 |
20.1.3 |
GINTR_STA—General Interrupt Status Register ....................................... |
718 |
20.1.4 |
MAIN_CNT—Main Counter Value Register................................................ |
719 |
20.1.5 |
TIMn_CONF—Timer n Configuration and Capabilities Register .................... |
719 |
20.1.6 |
TIMn_COMP—Timer n Comparator Value Register .................................... |
721 |
20.1.7 |
TIMERn_PROCMSG_ROUT—Timer n Processor Message |
|
|
Interrupt Rout Register ........................................................................ |
722 |
21 Serial Peripheral Interface (SPI) ........................................................................... |
723 |
|
21.1 Serial Peripheral Interface Memory Mapped Configuration Registers........................ |
723 |
|
21.1.1 BFPR –BIOS Flash Primary Region Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
724 |
21.1.2 HSFS—Hardware Sequencing Flash Status Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
725 |
21.1.3 HSFC—Hardware Sequencing Flash Control Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
726 |
21.1.4 |
FADDR—Flash Address Register |
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
726 |
21.1.5 FDATA0—Flash Data 0 Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
727 |
21.1.6 FDATAN—Flash Data [N] Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
727 |
21.1.7 |
FRAP—Flash Regions Access Permissions Register |
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
728 |
21.1.8 |
FREG0—Flash Region 0 (Flash Descriptor) Register |
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
728 |
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
729 |
21.1.10 FREG2—Flash Region 2 (Intel® ME) Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
729 |
21.1.11 FREG3—Flash Region 3 (GbE) Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
729 |
21.1.12 FREG4—Flash Region 4 (Platform Data) Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
730 |
21.1.13 PR0—Protected Range 0 Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
730 |
21.1.14 PR1—Protected Range 1 Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
731 |
21.1.15 PR2—Protected Range 2 Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
731 |
21.1.16 PR3—Protected Range 3 Register |
|
|
|
(SPI Memory Mapped Configuration Registers) ........................................ |
732 |
26 |
Datasheet |
|
21.1.17 PR4—Protected Range 4 Register |
732 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.18 SSFS—Software Sequencing Flash Status Register |
733 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.19 SSFC—Software Sequencing Flash Control Register |
734 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.20 PREOP—Prefix Opcode Configuration Register |
735 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.21 OPTYPE—Opcode Type Configuration Register |
735 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.22 OPMENU—Opcode Menu Configuration Register |
736 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.23 BBAR—BIOS Base Address Configuration Register |
736 |
|
|
21.1.24 |
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
FDOC—Flash Descriptor Observability Control Register |
737 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.25 FDOD—Flash Descriptor Observability Data Register |
737 |
|
|
21.1.26 |
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
AFC—Additional Flash Control Register |
737 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.27 LVSCC—Host Lower Vendor Specific Component Capabilities Register |
738 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.28 UVSCC—Host Upper Vendor Specific Component Capabilities Register |
739 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.29 PTINX—Flash Parameter Table Index Register ......................................... |
740 |
|
|
21.1.30 PTDATA—Flash Parameter Table Data Register........................................ |
740 |
|
|
21.1.31 SRDL—Soft Reset Data Lock Register |
740 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.32 SRDC—Soft Reset Data Control Register |
741 |
|
|
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
|
21.1.33 SRD—Soft Reset Data Register |
741 |
|
21.2 |
|
(SPI Memory Mapped Configuration Registers)........................................ |
|
Flash Descriptor Records .................................................................................. |
741 |
||
21.3 |
OEM Section ................................................................................................... |
741 |
|
21.4 GbE SPI Flash Program Registers....................................................................... |
742 |
||
|
21.4.1 |
GLFPR –Gigabit LAN Flash Primary Region Register |
743 |
|
21.4.2 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
HSFS—Hardware Sequencing Flash Status Register |
743 |
|
|
21.4.3 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
HSFC—Hardware Sequencing Flash Control Register |
744 |
|
|
21.4.4 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
FADDR—Flash Address Register |
745 |
|
|
21.4.5 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
FDATA0—Flash Data 0 Register |
745 |
|
|
21.4.6 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
FRAP—Flash Regions Access Permissions Register |
745 |
|
|
21.4.7 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
FREG0—Flash Region 0 (Flash Descriptor) Register |
746 |
|
|
21.4.8 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
FREG1—Flash Region 1 (BIOS Descriptor) Register |
746 |
|
|
21.4.9 |
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
FREG2—Flash Region 2 (Intel® ME) Register |
746 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.10 FREG3—Flash Region 3 (GbE) Register |
747 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.11 PR0—Protected Range 0 Register |
747 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.12 PR1—Protected Range 1 Register |
748 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.13 SSFS—Software Sequencing Flash Status Register |
748 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.14 SSFC—Software Sequencing Flash Control Register |
749 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.15 PREOP—Prefix Opcode Configuration Register |
750 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
|
21.4.16 OPTYPE—Opcode Type Configuration Register |
750 |
|
|
|
(GbE LAN Memory Mapped Configuration Registers)................................. |
|
Datasheet |
27 |
21.4.17 OPMENU—Opcode Menu Configuration Register |
|
|
|
(GbE LAN Memory Mapped Configuration Registers) ................................. |
751 |
22 Thermal Sensor Registers (D31:F6) ....................................................................... |
752 |
|
22.1 PCI Bus Configuration Registers......................................................................... |
752 |
|
22.1.1 |
VID—Vendor Identification Register ....................................................... |
752 |
22.1.2 |
DID—Device Identification Register........................................................ |
753 |
22.1.3 |
CMD—Command Register ..................................................................... |
753 |
22.1.4 |
STS—Status Register ........................................................................... |
753 |
22.1.5 |
RID—Revision Identification Register...................................................... |
754 |
22.1.6 |
PI—Programming Interface Register....................................................... |
754 |
22.1.7 |
SCC—Sub Class Code Register .............................................................. |
754 |
22.1.8 |
BCC—Base Class Code Register ............................................................. |
754 |
22.1.9 |
CLS—Cache Line Size Register .............................................................. |
754 |
22.1.10 |
LT—Latency Timer Register................................................................... |
755 |
22.1.11 |
HTYPE—Header Type Register ............................................................... |
755 |
22.1.12 |
TBAR—Thermal Base Register ............................................................... |
755 |
22.1.13 TBARH—Thermal Base High DWord Register............................................ |
755 |
|
22.1.14 SVID—Subsystem Vendor ID Register .................................................... |
756 |
|
22.1.15 SID—Subsystem ID Register................................................................. |
756 |
|
22.1.16 CAP_PTR—Capabilities Pointer Register................................................... |
756 |
|
22.1.17 INTLN—Interrupt Line Register .............................................................. |
756 |
|
22.1.18 INTPN—Interrupt Pin Register ............................................................... |
757 |
|
22.1.19 TBARB—BIOS Assigned Thermal Base Address Register ............................ |
757 |
|
22.1.20 TBARBH—BIOS Assigned Thermal Base High |
|
|
|
DWord Register................................................................................... |
757 |
22.1.21 PID—PCI Power Management Capability ID Register................................. |
757 |
|
22.1.22 PC—Power Management Capabilities Register .......................................... |
758 |
|
22.1.23 PCS—Power Management Control And Status Register.............................. |
758 |
|
22.2 Thermal Memory Mapped Configuration Registers |
|
|
(Thermal Sensor – D31:F26)............................................................................. |
759 |
|
22.2.1 |
TEMP—Temperature Register ................................................................ |
759 |
22.2.2 |
TSC—Thermal Sensor Control Register ................................................... |
760 |
22.2.3 |
TSS—Thermal Sensor Status Register .................................................... |
760 |
22.2.4 |
TSEL—Thermal Sensor Enable and Lock Register ..................................... |
760 |
22.2.5 |
TSREL—Thermal Sensor Reporting Enable and Lock Register ..................... |
761 |
22.2.6 |
TSMIC—Thermal Sensor SMI Control Register ......................................... |
761 |
22.2.7 |
CTT—Catastrophic Trip Point Register..................................................... |
761 |
22.2.8 |
TAHV—Thermal Alert High Value Register ............................................... |
761 |
22.2.9 |
TALV—Thermal Alert Low Value Register................................................. |
762 |
22.2.10 |
TL—Throttle Levels Register.................................................................. |
762 |
22.2.11 |
PHL—PCH Hot Level Register................................................................. |
763 |
22.2.12 |
PHLC—PHL Control Register .................................................................. |
763 |
22.2.13 |
TAS—Thermal Alert Status Register ....................................................... |
763 |
22.2.14 |
TSPIEN—PCI Interrupt Event Enables Register......................................... |
763 |
22.2.15 TSGPEN—General Purpose Event Enables Register ................................... |
764 |
|
23 Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])........... |
765 |
|
23.1 First Intel® Management Engine Interface (Intel® MEI) Configuration Registers |
|
|
(Intel® MEI 1—D22:F0).................................................................................... |
765 |
|
23.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0)................................. |
765 |
|
|
23.1.1.1 VID—Vendor Identification Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
766 |
|
23.1.1.2 DID—Device Identification Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
766 |
|
23.1.1.3 PCICMD—PCI Command Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
766 |
|
23.1.1.4 PCISTS—PCI Status Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
767 |
|
23.1.1.5 RID—Revision Identification Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
767 |
|
23.1.1.6 CC—Class Code Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
767 |
|
23.1.1.7 HTYPE—Header Type Register |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
768 |
|
23.1.1.8 MEI0_MBAR—Intel® MEI 1 MMIO Base Address |
|
|
(Intel® MEI 1—D22:F0).......................................................... |
768 |
28 |
Datasheet |
23.1.1.9 |
SVID—Subsystem Vendor ID Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
768 |
23.1.1.10 |
SID—Subsystem ID Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
768 |
23.1.1.11 |
CAPP—Capabilities List Pointer Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
769 |
23.1.1.12 |
INTR—Interrupt Information Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
769 |
23.1.1.13 |
HFS—Host Firmware Status Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
769 |
23.1.1.14 |
ME_UMA—Intel® Management Engine UMA Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
769 |
23.1.1.15 |
GMES—General Intel® ME Status Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
770 |
23.1.1.16 |
H_GS—Host General Status Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
770 |
23.1.1.17 |
PID—PCI Power Management Capability ID Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
770 |
23.1.1.18 |
PC—PCI Power Management Capabilities Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
770 |
23.1.1.19 |
PMCS—PCI Power Management Control and Status |
|
|
Register (Intel® MEI 1—D22:F0)............................................. |
771 |
23.1.1.20 |
GMES2—General Intel® ME Status Register 2 |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
771 |
23.1.1.21 |
GMES3—General Intel® ME Status Register 3 |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
771 |
23.1.1.22 |
GMES4—General Intel® ME Status Register 4 |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
772 |
23.1.1.23 |
GMES5—General Intel® ME Status Register 5 |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
772 |
23.1.1.24 |
H_GS2—Host General Status Register 2 |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
772 |
23.1.1.25 |
H_GS3—Host General Status Register 3 |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
772 |
23.1.1.26 |
MID—Message Signaled Interrupt Identifiers Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
772 |
23.1.1.27 |
MC—Message Signaled Interrupt Message Control Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
773 |
23.1.1.28 |
MA—Message Signaled Interrupt Message Address Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
773 |
23.1.1.29 |
MUA—Message Signaled Interrupt Upper Address Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
773 |
23.1.1.30 |
MD—Message Signaled Interrupt Message Data Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
773 |
23.1.1.31 |
HIDM—MEI Interrupt Delivery Mode Register |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
774 |
23.1.1.32 |
HERES—Intel® MEI Extend Register Status |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
774 |
23.1.1.33 |
HERX—Intel® MEI Extend Register DWX |
|
|
(Intel® MEI 1—D22:F0) ......................................................... |
774 |
23.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers............................................. |
775 |
|
23.1.2.1 |
H_CB_WW—Host Circular Buffer Write Window Register |
|
|
(Intel® MEI 1 MMIO Register)................................................. |
775 |
23.1.2.2 |
H_CSR—Host Control Status Register |
|
|
(Intel® MEI 1 MMIO Register)................................................. |
775 |
23.1.2.3 |
ME_CB_RW—Intel® ME Circular Buffer Read Window Register |
|
|
(Intel® MEI 1 MMIO Register)................................................. |
776 |
23.1.2.4 |
ME_CSR_HA—Intel® ME Control Status Host Access Register |
|
|
(Intel® MEI 1 MMIO Register)................................................. |
776 |
23.2 Second Intel® Management Engine Interface |
|
|
(Intel® MEI 2) Configuration Registers |
|
|
(Intel® MEI 2—D22:F1) ................................................................................... |
777 |
|
23.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2) ................................ |
777 |
|
23.2.1.1 VID—Vendor Identification Register |
|
|
|
(Intel® MEI 2—D22:F1) ......................................................... |
778 |
23.2.1.2 DID—Device Identification Register |
|
|
|
(Intel® MEI 2—D22:F1) ......................................................... |
778 |
Datasheet |
29 |
23.2.1.3 |
PCICMD—PCI Command Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
778 |
23.2.1.4 |
PCISTS—PCI Status Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
779 |
23.2.1.5 |
RID—Revision Identification Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
779 |
23.2.1.6 |
CC—Class Code Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
779 |
23.2.1.7 |
HTYPE—Header Type Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
779 |
23.2.1.8 |
MEI1_MBAR—Intel MEI 2 MMIO Base Address |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
780 |
23.2.1.9 |
SVID—Subsystem Vendor ID Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
780 |
23.2.1.10 |
SID—Subsystem ID Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
780 |
23.2.1.11 |
CAPP—Capabilities List Pointer Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
780 |
23.2.1.12 |
INTR—Interrupt Information Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
781 |
23.2.1.13 |
HFS—Host Firmware Status Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
781 |
23.2.1.14 |
GMES—General Intel® ME Status Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
781 |
23.2.1.15 |
H_GS—Host General Status Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
781 |
23.2.1.16 |
PID—PCI Power Management Capability ID Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
781 |
23.2.1.17 |
PC—PCI Power Management Capabilities Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
782 |
23.2.1.18 |
PMCS—PCI Power Management Control and Status |
|
|
Register (Intel® MEI 2—D22:F1) ............................................. |
782 |
23.2.1.19 |
GMES2—General Intel® ME Status Register 2 |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
783 |
23.2.1.20 |
GMES3—General Intel® ME Status Register 3 |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
783 |
23.2.1.21 |
GMES4—General Intel® ME Status Register 4 |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
783 |
23.2.1.22 |
GMES5—General Intel® ME Status Register 5 |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
783 |
23.2.1.23 |
H_GS2—Host General Status Register 2 |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
783 |
23.2.1.24 |
H_GS3—Host General Status Register 3 |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
784 |
23.2.1.25 |
MID—Message Signaled Interrupt Identifiers Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
784 |
23.2.1.26 |
MC—Message Signaled Interrupt Message Control Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
784 |
23.2.1.27 |
MA—Message Signaled Interrupt Message Address Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
784 |
23.2.1.28 |
MUA—Message Signaled Interrupt Upper Address Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
785 |
23.2.1.29 |
MD—Message Signaled Interrupt Message Data Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
785 |
23.2.1.30 |
HIDM—Intel® MEI Interrupt Delivery Mode Register |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
785 |
23.2.1.31 |
HERES—Intel® MEI Extend Register Status |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
785 |
23.2.1.32 |
HERX—Intel® MEI Extend Register DWX |
|
|
(Intel® MEI 2—D22:F1).......................................................... |
786 |
23.2.2 MEI1_MBAR—Intel® MEI 2 MMIO Registers ............................................. |
786 |
|
23.2.2.1 |
H_CB_WW—Host Circular Buffer Write Window |
|
|
(Intel® MEI 2 MMIO Register) ................................................. |
786 |
23.2.2.2 |
H_CSR—Host Control Status Register |
|
|
(Intel® MEI 2 MMIO Register) ................................................. |
787 |
23.2.2.3 |
ME_CB_RW—Intel® ME Circular Buffer Read Window Register |
|
|
(Intel® MEI 2 MMIO Register) ................................................. |
787 |
30 |
Datasheet |
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