Apple iMac 21.5 A1418 Schematics
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
PROPRIETARY PROPERTY OF APPLE INC.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
DESCRIPTION OF REVISION
CK
APPD
2 1
1245678
B
D
6 5 4 3
C
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
THE INFORMATION CONTAINED HEREIN IS THE
C
A
D
DATE
R
SHEET
Apple Inc.
THE POSESSOR AGREES TO THE FOLLOWING:
DRAWING TITLE
D
SIZE
REVISION
DRAWING NUMBER
BRANCH
REV ECN
7
B
3
II NOT TO REPRODUCE OR COPY IT
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
IV ALL RIGHTS RESERVED
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
TABLE_TABLEOFCONTENTS_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_TABLEOFCONTENTS_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
DRAWING
DRAWING
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
D7 MLB
Schematic / PCB #’s
1 OF 100
2012-01-12
1 OF 113
4.2.0
051-9509
LAST_MODIFIED=Thu Jan 12 10:24:09 2012
LAST_MODIFIED=Thu Jan 12 10:24:09 2012
SCH,D7,MLB
49
11/30/2011
K70_MLB
54
I and V Sense(Development)
Contents
Page Sync
Date
(.csa)
CRITICAL
SCH
1
051-9509 SCH,MLB,D7
CRITICAL
PCB
1
820-3302
PCBF,MLB,D7
ABBREV=DRAWING
TITLE=D7
1
K70_MLB
11/30/2011
1
Table of Contents
(.csa)
Date
SyncPage
Contents
50
12/13/2011
D7_DOUG
55
Temperature Sensors
51
11/30/2011
K70_MLB
56
System Fan
52
01/03/2012
D7_BREECE
61
AUDIO: CODEC/REGULATORS
53
01/03/2012
D7_BREECE
62
AUDIO: HEADPHONE AMP
54
01/03/2012
D7_BREECE
63
AUDIO: LEFT SPKR AMP
55
01/03/2012
D7_BREECE
64
AUDIO: RIGHT SPKR AMP
56
01/03/2012
D7_BREECE
65
AUDIO: Jack, Mikey, CHS Switch
57
01/03/2012
D7_BREECE
66
Audio: Spkr/Mic Conn.
58
01/03/2012
D7_BREECE
67
AUDIO: Detects/Grounding
59
01/03/2012
D7_BREECE
68
AUDIO: Speaker ID
60
12/13/2011
D7_NICK
69
PM Regulator Enables
61
12/13/2011
D7_NICK
70
PM Power Good
62
01/04/2012
D7_NICK
71
VReg CPU Core/AXG Cntl
63
01/04/2012
D7_NICK
72
VReg CPU Core Phases
64
01/04/2012
D7_NICK
73
VReg CPU AXG Phases
65
01/04/2012
D7_NICK
74
VReg CPU/PCH 1.05V S0
66
01/04/2012
D7_NICK
75
VReg CPU VccSA S0
67
01/04/2012
D7_NICK
76
VReg 3.3V S5/5V S4
68
01/04/2012
D7_NICK
77
VReg VDDQ and 1.8V S0
69
01/04/2012
D7_NICK
78
VReg G3Hot
70
01/04/2012
D7_NICK
79
FET-Controlled S0 and S4
71
01/10/2012
D7_TONY
80
KEPLER PCI-E
72
01/10/2012
D7_TONY
81
KEPLER CORE/FB POWER
73
01/10/2012
D7_TONY
82
KEPLER FRAME BUFFER I/F
74
01/03/2012
D7_NICK
83
1V05 GPU POWER SUPPLY
75
12/13/2011
D7_TONY
84
GDDR5 Frame Buffer A
76
12/13/2011
D7_TONY
85
GDDR5 Frame Buffer B
77
12/13/2011
D7_TONY
86
KEPLER EDP/DP/GPIO
78
01/10/2012
D7_TONY
87
KEPLER GPIOS,CLK & STRAPS
79
01/10/2012
D7_TONY
88
KEPLER PEX PWR/GNDS
80
01/03/2012
D7_NICK
89
VReg GPU Core
81
11/30/2011
K70_MLB
91
Internal DP Support
82
12/14/2011
D7_NICK
92
Internal DP MUXing
83
12/15/2011
D7_DOUG
93
TBT DDC Crossbar
84
12/15/2011
D7_DOUG
94
Thunderbolt Connector A
85
12/15/2011
D7_DOUG
96
Thunderbolt Connector B
86
01/03/2012
D7_NICK
97
LCD Backlight Driver (LP8545)
87
12/12/2011
D7_DAVE
100
K70 Rule Definitions
88
12/12/2011
D7_DAVE
101
DDR3 Constraints
89
12/12/2011
D7_DAVE
102
CPU PCIe Constraints
90
12/12/2011
D7_DAVE
103
PCH PCIe/DMI Constaints
91
12/12/2011
D7_DAVE
104
SATA/FDI/XDP Constraints
92
12/12/2011
D7_DAVE
105
PCH and BR Constraints
93
12/12/2011
D7_DAVE
106
USB/Ethernet/SD Constraints
94
01/03/2012
D7_DOUG
107
SMBus/Sensor Constraints
95
12/12/2011
D7_DAVE
108
VReg Constraints
96
12/12/2011
D7_DAVE
109
CPU VReg Constraints
97
12/12/2011
D7_DAVE
110
Platform VReg Constraints
98
12/13/2011
D7_NICK
111
TBT/DP Constraints
99
12/12/2011
D7_DAVE
112
GDDR5/GPU Constraints
100
12/12/2011
D7_DAVE
113
BLC Constraints
2
K70_MLB
11/30/2011
2
System Block Diagram
3
D7_NICK
01/03/2012
3
Power Block Diagram
4
D7_NICK
12/13/2011
4
BOM Configuration
5
K70_MLB
11/30/2011
5
DEBUG LEDS
6
D7_NICK
01/11/2012
6
Power Connectors/Aliases
7
K70_MLB
11/30/2011
7
Holes/PD parts
8
K70_MLB
11/30/2011
8
Unused Signal Aliases
9
K70_MLB
11/30/2011
9
Signal Aliases
10
K70_MLB
11/30/2011
10
CPU DMI/PEG/FDI/RSVD
11
K70_MLB
11/30/2011
11
CPU CLOCK/MISC/JTAG
12
K70_MLB
11/30/2011
12
CPU DDR3 INTERFACES
13
K70_MLB
11/30/2011
13
CPU POWER
14
K70_MLB
11/30/2011
14
CPU GROUNDS
15
D7_TONY
01/11/2012
15
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
16
K70_MLB
11/30/2011
16
CPU NON-GFX DECOUPLING
17
K70_MLB
11/30/2011
17
GFX DECOUPLING & PCH PWR ALIAS
18
K70_MLB
11/30/2011
18
PCH SATA/PCIE/CLK/LPC/SPI
19
K70_MLB
11/30/2011
19
PCH DMI/FDI/GRAPHICS
20
K70_MLB
11/30/2011
20
PCH PCI/USB
21
D7_TONY
01/11/2012
21 PCH MISC
22
K70_MLB
11/30/2011
22
PCH POWER
23
K70_MLB
11/30/2011
23
PCH GROUNDS
24
K70_MLB
11/30/2011
24
PCH DECOUPLING
25
K70_MLB
11/30/2011
25
CPU and PCH XDP
26
K70_MLB
11/30/2011
26
CHIPSET SUPPORT
27
D7_NICK
12/13/2011
27 USB HUB
28
K70_MLB
11/30/2011
28
CPU Memory S3 Support
29
K70_MLB
11/30/2011
29
DDR3 SO-DIMM Connector A
31
K70_MLB
11/30/2011
30
DDR3 SO-DIMM CONNECTOR B
33
K70_MLB
11/30/2011
31
DDR3 ALIASES AND BITSWAPS
34
K70_MLB
11/30/2011
32
DDR3/FRAMEBUF VREF MARGINING
35
D7_NICK
12/13/2011
33
AIRPORT/BT
36
D7_DOUG
01/11/2012
34
Thunderbolt Host (1 of 2)
37
D7_DOUG
01/11/2012
35
Thunderbolt Host (2 of 2)
38
D7_DOUG
01/11/2012
36
Thunderbolt Power Support
39
D7_NICK
01/12/2012
37
ETHERNET PHY (CAESAR IV)
40
D7_NICK
01/12/2012
38
Ethernet Support & Connector
41
D7_NICK
01/12/2012
39
SD READER CONNECTOR
42
D7_TONY
01/11/2012
40
Camera Controller
45
D7_NICK
12/16/2011
41
SATA Connectors
46
D7_NICK
01/04/2012
42
EXTERNAL USB PORTS A & B
47
D7_NICK
01/04/2012
43
EXTERNAL USB PORTS C & D
49
D7_DOUG
01/11/2012
44 SMC
50
D7_DOUG
01/11/2012
45
SMC Support
51
D7_NICK
12/13/2011
46
SPI and Debug Connector
52
D7_DOUG
01/03/2012
47
SMBus Connections
53
D7_DOUG
01/06/2012
48
I and V Sense(Production)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram
System Block diagram can be found on Kismet
SYNC_DATE=11/30/2011
SYNC_MASTER=K70_MLB
System Block Diagram
051-9509
4.2.0
2 OF 113
2 OF 100
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AC/DC
Supply Module
12V
G3HReg
PP3V42_G3H
G3HRegG3H
Vin
en
Regulator
U7800
3.3V
S5
LDO5VS5
U7600
Regulator
Vin
en
PP5V_S5_LDO
S5
SMC, RTC, BT
Audio, LCD, PCH, Camera, GPU
Thunderbolt
SD Card
PP3V3_S0
Reg
PP3V3_S0_SSD
AirPort
PP3V3_TBTLC
PP3V3_S4_AP_FET
Ethernet
PP3V3_ENET
PP3V3_S5
USB ports
SO-DIMMs
PP5V_S4
5V
Reg S4
Reg S3
VDDQ
VTT
VTT
LDO S3
S0LDO
Regulator
en
S4
en
S3
Vin
U7700
en
S0
Loads
I
PPHDD_S0
PP5V_S0
I
SO-DIMMs
PPVDDQ_S3_DDR
PP1V5_S0
S0-DIMMs
PPDDRVTT_S0
PPDDRVTT_S3
PPVDDQ_S3
Thunderbolt
PP12V_S0_FET
CPU
CPU
CPU, PCH
PPVCCSA_S0_REG
S0Reg
Reg S0
AXG
Reg
Reg S0
VccIO
S0S0
S0
Regulator
S0
Regulator
Regulator
U7100
Vin
en
Vin
en
U7500
en
Vin
Internal display
Loads
Fan
PP12V_G3H
I
PP12V_ACDC
PP12V_S5
PPCPUCORE_S0
PPCPUAXG_S0
Core
U7400
PP1V05_S0_REG
VccSA
Speaker amps
GPU
S0
Regulator
U8900
Vin
CPU PLL, GPU PLL
PP1V8_S0_REG
S0Reg
1.8V
S0
Regulator
PP5V_S0_FET
U7750
Vin
en
Thunderbolt
CPU
PP1V05_TBTCIO
PP1V05_TBTLC
Thunderbolt
Audio, CPU
Audio, PCH, Camera
PP3V3_S0_SW_SD_PWR
Bootrom, PCH
SMC AVref
I
PPSSD_S0
SSD
I
I
PP12V_S0_GPUUNCORE
Core
RegS0
en
HDD
PP12V_S0_GPUCORE
PP12V_S0_GPUCORE
PP12V_S0_GPUUNCORE
PPVCORE_S0_GPU
en
Regulator
Reg S0
GPU
PP1V05_S0_GPU
S0Reg
Regulator
S0
en
Vin
Vin
S0
GPU FB
U8350
U8300
IOVDD
GPUVDDQ
PPVDDQ_S0_GPU
SYNC_DATE=01/03/2012
SYNC_MASTER=D7_NICK
Power Block Diagram
051-9509
4.2.0
3 OF 113
3 OF 100
BOM OPTIONS
BOM GROUP
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_BOMGROUP_ITEM
BOM OPTIONS
BOM NAME
BOM NUMBER
TABLE_BOMGROUP_HEAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BOM Groups
Programmable Parts
Alternate: 335S0854
GPU Module Parts
VRAM Alternates
Alternate: 335S0812
Alternates
CPUs
Programmable Parts (unused)
CPU Socket Alternates
VRAM Module Parts
VRAM BOM Variants
CPU Socket
Add ’K70_PRODUCTION’ at RevA release
Replace with 65W part
Main BOM Variants
Module Parts
Bar Code Labels / EEEE #’s
BOM Configuration
SYNC_DATE=12/13/2011
SYNC_MASTER=D7_NICK
PCBA,MLB,DEV,D7
085-4441
PCBA,MLB,D7,GSA,GOOD
639-3566
PCBA,MLB,D7,GTX,CTO
639-3665
639-3668
PCBA,MLB,D7,GSB,GOOD
639-3567
PCBA,MLB,D7,GTX,BETTER
MLB LABEL,48.0X4.8
825-7122
1
EEEE:DT42
CRITICAL
IVB,QC13,QS,E0,2.8G,65W,4+1,1.10,6M,LGA
337S4240
1
CRITICAL
CPU
CPU:GOOD
1
337S4246 CRITICAL
CPU
IVB,SR0PN,PRQ,E1,3.1G,65W,4+2,1.15,8M,LG
CPU:CTO
341S3390
U4900
CRITICAL
1
IC,SMC,PROGRMD,PVT,D7
SMC:PVT
CRITICAL
U1000
511S0073
1
SOCKET,MOLEX,LGA1155,CPU-LF
607-9432
FB:BOTH_SAMSUNG
K70,GDDR5,SAMSUNG
607-9435
FB:BOTH_HYNIX
K70,GDDR5,HYNIX
607-9433
FB:CH1_SAMSUNG
K70,GDDR5,SAMSUNG_CH1
607-9436
FB:CH1_HYNIX
K70,GDDR5,HYNIX_CH1
607-9437
FB:CH2_HYNIX
K70,GDDR5,HYNIX_CH2
FB:CH2_HYNIX
CRITICAL
IC,GDDR5,2GB,M-DIE,170B FBGA
2
U8500,U8550
333S0630
FB:CH2_SAMSUNG
U8500,U8550
IC,SGRAM,GDDR5,64MX32,4.2GBPS,D-DIE,HF
2
CRITICAL333S0631
IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE
FB:BOTH_HYNIX
CRITICAL
U8400,U8450,U8500,U8550
4
333S0620
607-9432607-9435
GDDR5_BOTH
VRAM
607-9433607-9436
GDDR5_CH1
VRAM
GPU:GSA
607-9437 607-9434
GDDR5_CH2
VRAM
GPU:GSB
607-9434
VRAM
CRITICAL
1
GPU:GSB
K70,GDDR5,SAMSUNG_CH2
511S0073511S0072
ALL
FOXCONN SOCKET
511S0071 511S0073
TYCO SOCKET
ALL
Enet magnetics
157S0058157S0055
ALL
607-9434
FB:CH2_SAMSUNG
K70,GDDR5,SAMSUNG_CH2
CRITICAL
U8701
GPUROM:BLANK
335S0724
1
IC,1 MBIT SERIAL FLASH
341S3388
U4900
CRITICAL
1
IC,SMC,PROGRMD,EVT,D7
SMC:EVT
341S3389
U4900
CRITICAL
1
IC,SMC,PROGRMD,DVT,D7
SMC:DVT
377S0126377S0107
USB diodes
ALL
1
EEEE_DF98
825-7122
EEEE:DF98
CRITICAL
XDP_CONN,LPCPLUS,VREFMRGN:EXT,BKLT_PWM,DEVEL_SENSORS,DEVEL_AUDIO
D7_DEVEL
1
U4202
CRITICAL
335S0852
IC,FLASH,SPI,1MBIT,3V3
CAMROM:BLANK
IC,PCH,PPT-DT,Z77,QS,C1
337S4234
U1800
1
CRITICAL
CRITICAL
CAMROM:PROG
U4202
1
IC,CAMERA FLASH,K70/K72
341S3453
1
CRITICAL
U4900
IC,SMC,PROGRMD,PROD,D7
SMC:PROD
341S3409
BOOTROM:BLANK
1
U5110
IC,64 MBIT SPI SERIAL FLASH
CRITICAL
335S0807
337S4220
GPU:GSB
U8000
CRITICAL
IC,GPU,NV,GK107-GS-2/1-QS-A
1
IC,SGRAM,GDDR5,64MX32,4.2GBPS,D-DIE,HF
FB:CH1_SAMSUNG
2
U8400,U8450
CRITICAL333S0631
IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF
FB:BOTH_SAMSUNG
U8400,U8450,U8500,U8550
CRITICAL
4
333S0619
IC,GDDR5,2GB,M-DIE,170B FBGA
FB:CH1_HYNIX
2
U8400,U8450
CRITICAL333S0630
K70,GDDR5,SAMSUNG_CH1
607-9433
VRAM
CRITICAL
GPU:GSA
1
U3990
CRITICAL
335S0862
IC,SERIAL FLASH,2MBIT,2.7V,REV F
1
CIVROM:BLANK
337S4239
IC,GPU,NV,GK107-GTX-QS-A2
1
GPU:107GTX
U8000
CRITICAL
IC,GPU,NV,GK107-GS-2/1-QS-A
337S4221 CRITICAL
GPU:GSA
U8000
1
338S1047
U3600
CRITICAL
1
IC,TBT,CR-4C,ES1,288 FCBGA,12X12MM
337S4258
IVB,QC48,QS,E1,2.9G,65W,4+2,1.10,6M,LGA
1
CPU:BETTER
CPU
CRITICAL
K70,GDDR5,SAMSUNG
GPU:107GTX
607-9432 CRITICAL
1
VRAM
1
BOOTROM:PROG
CRITICAL
U5110
IC,PROGRMD,EFI ROM,K70
341S3480
341S3487
U3990
1
IC,ENET 1MBITFLASH,CIV,PVT,J40
CRITICAL
CIVROM:PROG
IC,SMC12-A3,BLANK,D7
338S1098
U4900
1
SMC:BLANK
CRITICAL
IC,SMC,PROGRMD,PROTO1,D7
341S3484
U4900
CRITICAL
1
SMC:PROTO1
CRITICAL
335S0865
IC,EEPROM,SERIAL,256KB,MLP8
U3690
T29ROM:BLANK
1
341S3493
U3690
CRITICAL
IC,CR,V24.2,D7/D7I
1
T29ROM:PROG
IC,BCM57766,CIV+,A0,8X8
343S0592
U3900
CRITICAL
1
P/NCh dual FET
ALL
376S0975376S1081
341S3487341S3486
ALL
P/NCh dual FET
D7_COMMON1
XDP,RSMRST:SMC,SPEAKERID,TBTHV:P12V
SNS_CPUCORE:3PHASE,CPUCOREDRV:ISL6612,IG:N,GPU_ROM:YES,SNS_GPUS0:K70,SNS_VDDQS3_DDR:Y
D7_COMMON2
SMC:PROTO1,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG
D7_PROGPARTS
D7_PRODUCTION
SNS_VDDQS0_GPU:N,SNS_VDDQS3:N,VREFMRGN:N
825-7122
MLB LABEL,48.0X4.8
CRITICAL
1
EEEE:F117EEEE_F117
1
825-7122
MLB LABEL,48.0X4.8
CRITICAL
EEEE:F116
SNS_VDDQS0_GPU:Y,SNS_VDDQS3:Y,TEMPSNSDEV
DEVEL_SENSORS
COMMON,ALTERNATE,D7_COMMON1,D7_COMMON2,D7_PROGPARTS
D7_COMMON
MLB LABEL,48.0X4.8
EEEE_F116
EEEE_DT42
D7_COMMON,CPU:BETTER,GPU:107GTX,FBA,FBB,SSD:Y,EEEE:DT42
D7_COMMON,CPU:CTO,GPU:107GTX,FBA,FBB,SSD:Y,EEEE:F116
D7_COMMON,CPU:GOOD,GPU:GSB,GS,FBB,SSD:N,EEEE:F117
DEVELOPMENT,D7_DEVEL
D7_COMMON,CPU:GOOD,GPU:GSA,GS,FBA,SSD:N,EEEE:DF98
051-9509
4.2.0
4 OF 113
4 OF 100
IN
G
D
S
IN
G
D
S
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ALL_SYS_PWRGD Led
This LED is a GPIO driven from
that chipset has enumerated graphics
VIDEO ON Led
S5 Led
GPU GOOD Led
the southbridge that indicates
1/16W
5%
MF-LF
1K
402
81
SILK_PART=2
2.0X1.25MM-SM
GREEN-3.6MCD
SOT-363
2N7002DW-X-G
5%
MF-LF
1/16W
402
1K
44 61
SILK_PART=4
2.0X1.25MM-SM
GREEN-3.6MCD
1K
1/16W
402
MF-LF
5%
2.0X1.25MM-SM
SILK_PART=1
GREEN-3.6MCD
1K
5%
1/16W
MF-LF
402
SILK_PART=3
2.0X1.25MM-SM
GREEN-3.6MCD
SOT-363
2N7002DW-X-G
21
SYNC_MASTER=K70_MLB
DEBUG LEDS
SYNC_DATE=11/30/2011
ITS_PLUGGED_IN
=PP3V3_S5_LED
GPU_PRESENT_DRAIN
GPU_PRESENT_R
=PP3V3_S0_LED
VIDEO_ON_L
LCD_SHOULD_ON_R
=PP3V3_S0_LED
CORE_VOLTAGES_ON
CORE_VOLTAGES_ON_R
=PP3V3_S4_LED
ALL_SYS_PWRGD
GPU_GOOD
R502
1
2
LED502
A
K
Q502
3
5
4
R504
1
2
LED504
A
K
R501
1
2
LED501
A
K
R503
1
2
LED503
A
K
Q502
6
2
1
051-9509
4.2.0
5 OF 113
5 OF 100
6
5 6
5 6
6
OUT
OUT
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Enabled when system has AC and is in S5
Enabled when Thunderbolt cable is plugged in
Enabled when system is in run
S5 Rails
S3 Rails
Enabled when system is in run or sleep
Thunderbolt Rails (S0)
Enabled when system is in run
Ground/Common
S4 Rails
S0 Rails
Always on: Keeps the PCH RTC alive
G3 Rails
G3H Rails
Enabled when system has AC and is in run or sleep
GPU Rails (S0)
MLB to AC-DC Supplemental Signal Connector
MLB to AC-DC Connector
J600.7:3mm
EMC
5%
402
NP0-C0G
25V
1000PF
805
X5R
25V
10%
10UF
J600.6:3mm
EMC
1000PF
J600.8:3mm
25V
5%
402
NP0-C0G
50 94
50 94
45 67
6
45
10%
NOSTUFF
6.3V
1UF
CERM
402
402
6.8V-100PF
0
402
MF-LF
1/16W
5%
45
SILK_PART=PwrSig
CRITICAL
M-RT-SM
53780-8606
402
10K
5%
MF-LF
1/16W
CRITICAL
F-RT-TH
43650-0603
SYNC_DATE=01/11/2012
Power Connectors/Aliases
SYNC_MASTER=D7_NICK
GND
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP3V3_S4
MAKE_BASE=TRUE
PP5V_S4
PP3V3_S5
MAKE_BASE=TRUE
PP5V_S5
MAKE_BASE=TRUE
PP12V_S5
MAKE_BASE=TRUE
PPVDDQ_S0_GPU
MAKE_BASE=TRUE
PP1V05_S0_GPU
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP1V05_TBTCIO
MAKE_BASE=TRUE
PP1V05_TBTLC
PP3V3_TBTLC
MAKE_BASE=TRUE
PPVCCSA_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPVAXG_S0
PPDDRVREF_CA_MEM_B_S3
MAKE_BASE=TRUE
PPDDRVREF_DQ_MEM_B_S3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVREF_CA_MEM_A_S3
PPDDRVREF_DQ_MEM_A_S3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPDDRVTT_S0
PP12V_S0_GPUUNCORE
MAKE_BASE=TRUE
PP12V_S0_GPUCORE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP12V_S0
MAKE_BASE=TRUE
PP5V_S0
MAKE_BASE=TRUE
PPHDD_S0
MAKE_BASE=TRUE
PP3V42_G3H
PPDDRVTT_S3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPVDDQ_S3_DDR
PP3V3_S0_SSD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPSSD_S0
MAKE_BASE=TRUE
PPVDDQ_S3
MAKE_BASE=TRUE
PP12V_ACDC
VOLTAGE=3.3V
MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM
PP3V3_G3
MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3MM
MAKE_BASE=TRUE
PP12V_G3H
MAKE_BASE=TRUE
PPVCORE_S0_CPU
MAKE_BASE=TRUE
PPVCORE_S0_GPU
PP3V3_ENET
MAKE_BASE=TRUE
PP1V5_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP1V05_S0
=PP1V05_S0_DP
=PP1V05_S0_P1V05TBTFET
=PPVCCIO_S0_CPU
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_DMI
=PP1V05_S0_PCH_VCC_SSC
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCC_ASW
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCC_ADPLL
=PP1V05_S0_PCH
=PPVCCIO_S0_XDP
=PPVCCIO_S0_SMC
PPHDD_S0_SNS
SNS_ACDC_N
SNS_ACDC_P
SMC_ACDC_ID
PWR_BTN_R
BURSTMODE_EN_L
=PP1V8_S0_CAMERA
=PP1V5_S0_SENSE
=PPSPD_S0_MEM_A
=PP3V3_GPU_VDD33
=PP3V3_GPU_MISC
=PP3V3_GPU_IFPX_PLLVDD
=PP3V3_S0_BKLT_VDDIO
=PP3V3_S0_TBTPWRCTL
=PP3V3_S4_MEMRESET
=PP3V3_S4_PM
PP3V3_S4_FET
=PP5V_S4_FET_P5V_S0
=PP3V3_S4_ALS
PP12V_G3H_ACDC
=PPVDDQ_S3_LDO_DDRVTT
=PP3V3_ENET_PHY
PPDDRVTT_S3_LDO
=PPVDDQ_S3_MEMRESET
=PP3V3_S0_BT
=PP3V3_S0_AUDIO_DIG
=PP3V3_S0_VRD
=PP3V3_S0_AUDIO
=PP3V3_S0_CAMERA
PPCPUCORE_S0_REG
=PP5V_S4_REG_VDDQ_S3
=PP12V_S0_SNS_GPUUNCORE_R
=PP12V_S0_AUDIO_SPKRAMP
=PP12V_S0_BKLT
=PP12V_S0_SNS_GPUCORE_R
=PP3V3_G3H_BT
=PP12V_G3H_SNS_R
=PP12V_G3H_REG_3V42_G3H
PP5V_S5_LDO
=PP5V_S5_PWRCTL
PP3V3_S5_REG
=PP3V3_G3_PCH
=PP5V_S4_MEMRESET
=PP5V_S0_ISENSE
=PP1V8_S0_PCH_VCC_VRM
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_PCH
PP1V8_S0_REG
=PP3V3_S0_SSD
=PP3V3_S0_SMBUS_SMC_3
=PP3V3_S0_SMBUS_SMC_1
=PP3V3_S0_SMBUS_SMC_0
=PP3V3_S0_SENSE
=PP3V3_S0_SMBUS
=PP3V3_S0_SDCARD
=PP3V3_S0_RSTBUF
=PP3V3_S0_PCH_VCC_PCI
=PP3V3_S0_PCH_VCC_HVCMOS
=PP3V3_S0_PCH_VCC
=PP3V3_S0_PCH_PM
=PP3V3_S0_PCH_STRAPS
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_LED_SATA
=PP3V3_S0_LED
=PP3V3_S0_ENET
=PP3V3_S0_PWRCTL
PP3V3_S0_FET
=PPHDD_S0_SNS_R
=PP5V_S0_PCH
=PP5V_S0_BKLT
=PP5V_S0_LPCPLUS
=PP5V_S0_AUDIO
=PP5V_S0_CAMERA
=PP5V_S0_VRD
=PP5V_S0_REG_GPU_VDDQ_S0
=PP5V_S0_REG_GPUCORE_S0
=PP5V_S0_REG_GPU_P1V05_S0
=PP5V_S0_REG_P1V05_S0
=PP5V_S0_REG_VCCSA_S0
=PP12V_S0_REG_CPUCORE_S0
=PP12V_S0_REG_VCCSA_S0
PPVDDQ_S3_SNS_DDR
=PP12V_G3H_FET_P12V_S0
=PPVIN_G3H_SMCVREF
=PP12V_G3H_FET_P12V_S5
=PP12V_S0_REG_P1V05_S0
=PPVDDQ_S3_SNS_DDR_R
=PPVDDQ_S3_FET_VDDQ_S0
=PP3V3_ENET_SYSCLK
PPVDDQ_S3_REG
=PPVDDQ_S3_VSNS
PP3V3_ENET_FET
=PPVDDQ_S3_MEM_B
=PPVDDQ_S3_MEM_A
=PPVDDQ_S3_DDR_VREF
PWR_BTN
SMC_ACDC_ID
=PP3V3_S0_VRD
PP12V_S0_FET
=PP5V_S4_USB
=PP5V_S4_PWRCTL
=PP12V_S5_REG_VDDQ_S3
PP3V42_G3H_REG
=PP3V3_G3H_SMC
=PP3V3_RTC_D
=PP5V_S0_REG_P1V8_S0
PP5V_S0_FET
=PP5V_S0_REG_CPUCORE_S0
PP5V_S4_REG
=PP5V_S0_SATA
=PP12V_S0_FAN
=PP12V_S0_LCD
PP12V_S0_SNS_GPUCORE
PP12V_S0_SNS_GPUUNCORE
=PP12V_S0_REG_GPUCORE_S0
=PP12V_S0_REG_GPU_P1V05_S0
=PP12V_S0_REG_GPU_VDDQ_S0
=PP3V3_S0_PCH
PP1V5_S0_FET
=PP1V5_S0_CPU_MEM
=PP1V5_S0_AUD_DIG
PPDDRVTT_S0_LDO
=PPDDRVTT_S0_CLAMP
=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_B
PPDDRVREF_DQ_MEM_A
=PPDDRVREF_DQ_MEM_A
PPDDRVREF_CA_MEM_A
=PPDDRVREF_CA_MEM_A
PPDDRVREF_DQ_MEM_B
=PPDDRVREF_DQ_MEM_B
PPDDRVREF_CA_MEM_B
=PPDDRVREF_CA_MEM_B
PP1V05_S0_REG
=PPVCORE_S0_CPU
=PPVAXG_S0_CPU
PPCPUAXG_S0_REG
=PP3V3_TBTLC_FET
=PP3V3_TBT_PCH_GPIO
=PP3V3_TBTLC_RTR
=PP1V05_TBTLC_FET
=PP1V05_TBTCIO_FET
=PP1V05_GPU_IFPCD_IOVDD
=PP1V05_GPU_IFPEF_IOVDD
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD
PP1V5R1V35_S0_GPU_REG
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_S0_FB
=PP3V3_S0_P3V3TBTFET
=PP1V05_TBTLC_RTR
=PPVDDIO_ENET_CLK
=PP12V_S5_REG_P3V3P5V_S5
=PP12V_S5_PWRCTL
=PPHV_SW_TBTAPWRSW
=PPHV_SW_TBTBPWRSW
=PP12V_S5_SNS
=PP3V3_S5_FET_P3V3_S0
=PP3V3_S5_FET_P3V3_S4
=PP3V3_S5_PWRCTL
=PP3V3_S5_LPCPLUS
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_PCH_VCCSUS_HDA
=PP3V3_S5_PCH_VCCSUS_USB
=PP3V3_S5_ROM
=PP3V3_S0_PCH_VCC_GPIO
=PP3V3_S4_SDCARD
=PP3V3_S4_FET_ENET
=PP3V3_S4_PCH
=PP3V3_S4_LED
=PP3V3_S4_TBT
=PP3V3_S4_SMBUS_SMC_2
=PP3V3_S4_USB_HUB
=PP3V3_S4_TBTBPWRSW
=PP3V3_S4_TBTAPWRSW
=PP3V3_S4_VREFMRGN
PP12V_S5_FET
PP3V3_G3H_RTC
PP12V_G3H_SNS
=PP3V3_S0_DP
PPVCCSA_S0_REG
=PPVCCSA_S0_CPU
PP1V05_S0_GPU_REG
=PPVCORE_GPU
PPGPUCORE_S0_REG
=PP1V05_TBTCIO_RTR
=PPVDDIO_TBT_CLK
=PP3V3_S0_PCH_VCC_ADAC
=PPSPD_S0_MEM_B
PP12V_G3H_ACDC
=PP3V3_S4_PWRCTL
=PP3V3_S4_AP
=PP3V3_S4_SMC
=PP3V3_S5_XDP
=PP3V3_S5_SENSE
=PP3V3_S5_SMC
=PP3V3_S5_USBMUX
=PP3V3_S5_VRD
=PP5V_S5_PCH
=PP3V3_S5_LDO_P1V05_S5
=PP3V3_S5_LED
=PP3V3_S5_PCH
=PP3V3_S5_PCH_STRAPS
=PP3V3_S5_PCH_VCC_DSW
=PP3V3_G3H_SMC_USBMUX
PP3V3_S0
MAKE_BASE=TRUE
=PP3V3_S0_INTDPMUX
=PP3V3_S0_FAN
=PPDDRVTT_S3_VREFCA
=PPSSD_S0_SNS_R
PP3V3_S0_SSD_FET
=PP3V3_S0_SATAMUX
=PP1V8_S0_GPUVID
=PP1V8_S0_CPU_PLL
=PP3V3_S0_SMC
PPSSD_S0_SNS
=PPVDDIO_S0_SBCLK
=PP1V8_S0_ENET
MAKE_BASE=TRUE
PP1V8_S0
C602
1
2
C601
1
2
C603
1
2
C600
1
2
D600
1
2
R606
1 2
J601
7
8
1
2
3
4
5
6
R601
1
2
J600
1
2
3
4
5
6
051-9509
4.2.0
6 OF 113
6 OF 100
97
97
97
97
97
97
97
95
95
97
95
96
97
97
97
97
95
97
97
97
97
97
97
95
95
97
97
95
97
97
96
97
97
95
95
36
10 11 13 16 62
22 24
22
18 22 24
18 19 22
22
22
22
22 24
22 24
22 24
17
18 24
25
45
48
40
41
29
71 77 78 79
77 80
77
86
36
28
28
70
70
40
6
68
37 38
68
28
33
56
6
62 65 66 68 74
40 52 54 55 58
40
63
68
48
54 55
86
48
33
48
69
67
67 70
67
18 19
28
48
24
22 24
19
68
41
47
47
47
41 48 49 50
47
39
26
22 24
22 24
22 24
26
15
15 19 20 36
15 41
5
37
70 80
70
48
24
86
46
52 59
40
68
74
80
74
65
66
63
66
49
70
45
69
65
49
70
26
68
38
30
29
32
6
45
6
62 65 66 68 74
70
42 43
70
68
69
44 45
26
68
70
62
67
41
51
81
48
48
80
74
74
18 21 24
70
11 13 16
52
68
28
29
30
32
29
32
29
32
30
32
30
65
13 16 48 62
13 17 48 62
64
36
15
34 35 36
36
36
77
77
73 79
77 79
74
72 75 76
73
36
35 36
26
67
60 61 70
84
85
48
70
70
60 61 70 78
46
22 24
22 24
22 24
46
22 24
15 39
38
15
5
34 35 36 84 85
47
27
45 85
45 84
32
69
22 26
48
47 81 83
66
13 16
74
72 79
80
35
26
17
30
6
70
33
45
25
48
45
42 43
67 68
24
5
19 24 26
15
22 24
42
97
82
51
32
49
70
41
80
13 16
45
49
26
38
97
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)
APN: 870-1939
CPU Heatsink
WIRELESS CARD MTG HOLES
SSD STANDOFF
APN: 860-1461
4mm Plated Holes (998-0850)
POGO PINS
GPU HEATSINK MOUNTING FEATURES
(860-0988)
Rear Cover
998-4559 (Plated holes, 4mm inner diameter, 8mm pad)
USB Can holes
998-3975 (Plated slot holes, 1.10mm x 0.45mm)
8P5R5-NSP
OMIT
8P5R5-NSP
OMIT
8P5R5-NSP
OMIT OMIT
8P5R5-NSP
CRITICAL
STDOFF-4.5OD2.2ID-5.6H-SM
CRITICAL
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
CRITICAL
CRITICAL
STDOFF-4.5OD.98H-1.1-3.48-TH
CRITICAL
7P0R4P0-8P0B-NSP
CRITICAL
7P0R4P0-8P0B-NSP
7P0R4P0-8P0B-NSP
CRITICAL
CRITICAL
7P0R4P0-8P0B-NSP
5P5R2P3-4P3B-NSP
CRITICAL
5P5R2P3-4P3B-NSP
CRITICAL
TH-NSP
SL-1.1X0.45-1.4X0.75
TH-NSP
SL-1.1X0.45-1.4X0.75
SYNC_DATE=11/30/2011
SYNC_MASTER=K70_MLB
Holes/PD parts
ZH07001ZH07011ZH07021ZH0703
1
NUT0713
1
SH0777
1
SH0778
1
SH0779
1
ZH0713
1
ZH0714
1
ZH0715
1
ZH0716
1
ZH0721
1
ZH0722
1
ZH0730
1
ZH0731
1
051-9509
4.2.0
7 OF 113
7 OF 100
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CPU Memory
CPU Reserved
PCH PLL
UNUSED GRAPHICS ALIASES
PCH Reserved
PCH SATA
PCH Test Points
PCH Unused Display
PCH PCI
PCH Miscellaneous
PCH Clocks
PCH USB
PCH and CPU FDI
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
Unused Signal Aliases
TP_PCH_RESERVE_5
TP_PCI_PAR
TP_PCI_C_BE_L<3..0>
MEM_B_CLK_P<2..3>
MEM_B_CLK_N<2..3>
CPU_CFG<15..12>
TP_MEM_B_DQ_CB<7..0>
TP_MEM_A_DQS_N<8>
TP_MEM_A_DQ_CB<7..0>
TP_CPU_RSVD<46..19>
TP_SDVO_STALLN
TP_SDVO_STALLP
TP_SDVO_INTN
TP_PCH_RESERVE_23
TP_PCH_RESERVE_21
DP_IG_D_AUXP
DMI_MIDBUS_CLK100M_N
MEM_B_CS_L<2..3>
MEM_A_CKE<2..3>
MEM_A_CS_L<2..3>
TP_MEM_B_DQS_N<8>
TP_MEM_A_DQS_P<8>
TP_CPU_RSVD<16..1>
TP_CLKOUT_PEG_A_P
PP1V05_S0_PCH_VCCAPLL_SATA
PP1V05_S0_PCH_VCCAPLL_EXP
PP1V05_S0_PCH_VCCAPLLDMI2
CPU_FDI_TX_P<7..0>
TP_DVPCNTL_M<0..1>
TP_PCH_RESERVE_28
HDMI_EG_DATA_C_P<0..2>
TP_PCH_RESERVE_12
TP_PCH_RESERVE_20
USB_PCH_5_N
DP_IG_B_AUX_N
DP_IG_B_AUX_P
DP_IG_B_HPD
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO64_CLKOUTFLEX0
TP_CRT_IG_VSYNC
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
DP_IG_B_MLN<3..0>
DP_IG_C_MLP<3..0>
TP_PCH_GPIO67_CLKOUTFLEX3
HDMI_EG_DDC_DATA
PP1V05_S0_PCH_VCC_A_CLK
TP_PPVOUT_PCH_DCPSUSBYP
PP1V05_S0_PCH_FDIPLL
TP_PCH_GPIO8
TP_PCI_CLK33M_OUT3
TP_PCI_CLK33M_OUT2
TP_PCH_CL_RST1
TP_PCH_CL_CLK1
TP_PCH_CL_DATA1
TP_PCH_SST
TP_PCH_PWM3
TP_PCH_PWM2
TP_PCH_PWM1
TP_PCH_PWM0
TP_PCH_RESERVE_8
TP_PCH_RESERVE_7
TP_PCH_RESERVE_0
TP_DVPDATA<4..23>
TP_PCH_RESERVE_19
TP_PCH_RESERVE_22
TP_PCH_RESERVE_27
TP_PCH_RESERVE_26
TP_PCH_RESERVE_24
TP_PCH_RESERVE_17
TP_PCH_RESERVE_18
TP_PCH_RESERVE_15
TP_PCH_RESERVE_16
TP_PCH_RESERVE_14
TP_PCH_RESERVE_13
TP_PCH_RESERVE_10
TP_PCH_RESERVE_11
TP_PCH_RESERVE_9
TP_PCH_RESERVE_6
TP_PCH_RESERVE_3
TP_PCH_RESERVE_4
TP_PCH_RESERVE_2
TP_PCH_RESERVE_1
TP_PCH_L_BKLTEN
TP_SDVO_TVCLKINP
DP_IG_C_AUX_N
DP_IG_C_AUX_P
DP_IG_C_CTRL_CLK
TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN
TP_PCH_L_BKLTCTL
DP_IG_D_MLP<3..0>
DP_IG_B_DDC_CLK
DP_IG_D_CTRL_DATA
TP_SDVO_INTP
TP_SDVO_TVCLKINN
DP_IG_D_HPD
DP_IG_C_MLN<3..0>
DP_IG_B_DDC_DATA
TP_SATA_F_D2RP
TP_SATA_F_D2RN
DP_IG_B_MLP<3..0>
TP_CRT_IG_BLUE
TP_CRT_IG_RED
TP_CRT_IG_GREEN
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_PCH_TP20
TP_PCH_TP19
TP_PCH_TP18
TP_PCH_TP17
TP_PCH_TP16
TP_PCH_TP15
TP_PCH_TP13
TP_PCH_TP14
TP_PCH_TP12
TP_PCH_TP11
TP_PCH_TP10
TP_PCH_TP9
TP_PCH_TP8
TP_PCH_TP7
TP_PCH_TP6
TP_PCH_TP5
TP_PCH_TP4
TP_PCH_TP3
TP_PCH_TP1
TP_SATA_D_D2RP
TP_PCH_TP2
TP_SATA_C_R2D_CP
TP_SATA_E_D2RP
TP_SATA_E_D2RN
TP_SATA_D_D2RN
DP_IG_C_HPD
DP_IG_C_CTRL_DATA
TP_PCI_AD<31..0>
TP_PCI_RESET_L
TP_LPC_DREQ0_L
TP_PCH_INIT3V3_L
TP_HDA_SDIN1
TP_HDA_SDIN3
TP_HDA_SDIN2
HDMI_EG_DDC_CLK
HDMI_EG_DATA_C_N<0..2>
GPU_TDIODE_P
HDMI_EG_CLK_C_N
HDMI_EG_CLK_C_P
EG_LCD_PWR_EN
GPU_TDIODE_N
TP_DVPCLK
TP_DVPCNTL<0..2>
TP_PCH_L_VDD_EN
TP_PCH_RESERVE_25
TP_CRT_IG_HSYNC
USB_PCH_4_N
USB_PCH_4_P
USB_PCH_5_P
USB_PCH_6_N
USB_PCH_6_P
USB_PCH_11_P
USB_PCH_11_N
USB_PCH_12_P
USB_PCH_12_N
USB_PCH_13_P
USB_PCH_13_N
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7P
TP_PE_TX_P<3..0>
TP_PE_TX_N<3..0>
TP_PE_RX_N<3..0>
TP_PE_RX_P<3..0>
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
PCH_CLK25M_XTALOUT
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
CPU_FDI_TX_N<7..0>
PCH_FDI_RX_P<7..0>
PCH_FDI_RX_N<7..0>
CPU_FDI_INT
CPU_FDI_FSYNC<1..0>
CPU_FDI_LSYNC<1..0>
PCH_FDI_INT
PCH_FDI_LSYNC<1..0>
PCH_FDI_FSYNC<1..0>
DP_IG_D_MLN<3..0>
DP_IG_D_AUXN
DP_IG_D_CTRL_CLK
TP_CLKOUT_PEG_A_N
TP_MEM_B_DQS_P<8>
MEM_A_CLK_N<2..3>
DMI_MIDBUS_CLK100M_P
MEM_A_CLK_P<2..3>
MEM_B_CKE<2..3>
MEM_A_ODT<2..3>
MEM_B_ODT<2..3>
NC_MEM_A_DQSN<8>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE6N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE6P
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_A_CKE<2..3>
NC_MEM_A_CS_L<2..3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_CLKP<2..3>
MAKE_BASE=TRUE
NC_CLKOUT_PEG_AN
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_CPU_CFG<15..12>
MAKE_BASE=TRUE
NC_MEM_A_DQSP<8>
NO_TEST=TRUE
NC_MEM_B_DQ_CB<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CLKOUT_DPN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_RXN<3..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_TXP<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CPU_RSVD<46..19>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_ODT<2..3>
MAKE_BASE=TRUE
NC_MEM_B_CKE<2..3>
NO_TEST=TRUE
NC_MEM_B_CS_L<2..3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_A_ODT<2..3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLKP<2..3>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLKN<2..3>
MAKE_BASE=TRUE
NC_MEM_A_CLKN<2..3>
NO_TEST=TRUE
NC_MEM_B_DQSP<8>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_B_DQSN<8>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MEM_A_DQ_CB<7..0>
MAKE_BASE=TRUE
NC_PP1V05_S0_PCH_VCCAPLL_SATA
NO_TEST=TRUE
NC_PP1V05_S0_PCH_VCCAPLL_EXP
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PP1V05_S0_PCH_VCCAPLLDMI2
NC_PCH_RESERVE_20
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_21
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_2
NO_TEST=TRUE
NC_PCH_RESERVE_3
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DMI_MIDBUS_CLK100P
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_FDI_TXP<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_HPD
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_B_MLN<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_MLP<3..0>
NC_CLKOUT_PEG_AP
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_CLK25M_XTALOUT
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_TDIODE_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_EG_LCD_PWR_EN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_GPU_TDIODE_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PP1V05_S0_PCH_VCC_A_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PPVOUT_PCH_DCPSUSBYP
NC_PP1V05_S0_PCH_FDIPLL
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO8
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_CLK33M_OUT3
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_CLK33M_OUT2
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_CL_RST1
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_CL_CLK1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_CL_DATA1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_SST
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_PWM3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_PWM2
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_PWM1
NO_TEST=TRUE
NC_PCH_PWM0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_AUXN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DVPCLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DVPDATA<4..23>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DVPCNTL_M<0..1>
MAKE_BASE=TRUE
NC_DVPCNTL<0..2>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_28
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_26
NC_PCH_RESERVE_24
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_25
NO_TEST=TRUE
NC_PCH_RESERVE_23
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_22
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_19
NC_PCH_RESERVE_17
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_18
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_13
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_12
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_10
NO_TEST=TRUE
NC_PCH_RESERVE_11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_9
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_8
MAKE_BASE=TRUE
NC_PCH_RESERVE_7
NO_TEST=TRUE
NC_PCH_RESERVE_5
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_6
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_4
NC_SDVO_STALLN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_TVCLKINN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_HPD
NC_SATA_E_R2D_CN
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_CTRL_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_L_BKLTCTL
NC_PCH_L_BKLTEN
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_HPD
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_CTRL_CLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_CTRL_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_MLP<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_MLN<3..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_CTRL_DATA
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_F_D2RP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_F_D2RN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_F_R2D_CP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_CTRL_CLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_DDC_CLK
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_RED
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_GREEN
NC_SATA_E_R2D_CP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_C_D2RN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SATA_C_D2RP
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NC_SATA_C_R2D_CN
MAKE_BASE=TRUE
NC_SATA_C_R2D_CP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP20
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP19
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP18
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP17
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP16
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP15
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP13
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP14
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP12
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP11
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP10
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP9
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP8
MAKE_BASE=TRUE
NC_PCH_TP7
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP6
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP5
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_TP4
MAKE_BASE=TRUE
NC_PCH_TP1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP2
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_TP3
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_DDC_DATA
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_AUXP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_C_AUXP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_AUXP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCI_AD<31..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCI_PAR
MAKE_BASE=TRUE
NC_PCI_C_BE_L<3..0>
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCI_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LPC_DREQ0_L
NC_PCH_INIT3V3_L
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_HDA_SDIN1
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_HDA_SDIN3
MAKE_BASE=TRUE
NC_HDA_SDIN2
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_L_VDD_EN
NC_CPU_RSVD<16..1>
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_CTRL_DATA
NO_TEST=TRUE
NC_SDVO_STALLP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_SDVO_INTN
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_HDMI_EG_DDC_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_HDMI_EG_DDC_DATA
MAKE_BASE=TRUE
NC_HDMI_EG_DATA_C_P<0..2>
NO_TEST=TRUE
NC_HDMI_EG_DATA_C_N<0..2>
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_HDMI_EG_CLK_C_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_HDMI_EG_CLK_C_N
NC_SDVO_TVCLKINP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SDVO_INTP
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_RESERVE_27
NC_PCH_RESERVE_16
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_RESERVE_15
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_4_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_4_P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_5_P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_5_N
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_6_N
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_6_P
NC_USB_PCH_11_P
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_USB_PCH_11_N
NC_USB_PCH_12_P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_PCH_12_N
NO_TEST=TRUE
NO_TEST=TRUE
NC_USB_PCH_13_P
MAKE_BASE=TRUE
NC_USB_PCH_13_N
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE7P
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PE_TXN<3..0>
MAKE_BASE=TRUE
NC_PE_RXP<3..0>
NO_TEST=TRUE
NC_DMI_MIDBUS_CLK100N
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_CLKOUT_DPP
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO66_CLKOUTFLEX2
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO67_CLKOUTFLEX3
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4N
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PCIE_CLK100M_PE4P
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_B_AUXN
NC_CPU_FDI_TXN<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_RXP<7..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_RXN<7..0>
NO_TEST=TRUE
NC_CPU_FDI_INT
MAKE_BASE=TRUE
NC_CPU_FDI_FSYNC<1..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CPU_FDI_LSYNC<1..0>
NC_PCH_FDI_INT
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_LSYNC<1..0>
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCH_FDI_FSYNC<1..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_DP_IG_D_MLP<3..0>
MAKE_BASE=TRUE
NC_PCH_RESERVE_0
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_F_R2D_CN
NC_SATA_E_D2RP
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_SATA_E_D2RN
NO_TEST=TRUE
MAKE_BASE=TRUE
051-9509
4.2.0
8 OF 113
8 OF 100
19 20
20
12 88
12 88
10 91
12
12
12
10
19
19
19
19
19
19
18
12 88
12 88
12 88
12
12
10
18
22
22
22
10 91
19
19
19
20
19
19
19
18
18
19
19
19
19
19
18
22
22
22
21
20
20
18
18
18
21
21
21
21
21
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
18
19
19
19
19
18
18
18
19
19
19
19
19
19
19
19
18
18
19
19
19
19
18
18
18
18
18
18
18
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
18
21 18
18
18
18
19
19
20
20
18
19
18
18
18
77
78
77
18
19
19
20
20
20
20
20
20
20
20
20
20
20
21
21
21
21
10
10
10
10
18
18
18
18
18
18
10 91
19
19
10 91
10 91
10 91
19
19
19
19
19
19
18
12
12 88
18
12 88
12 88
12 88
12 88
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Whistler aliases
Signal Aliases
SYNC_DATE=11/30/2011
SYNC_MASTER=K70_MLB
=PEG_R2D_C_P<15..0>
=PEG_D2R_P<15..0>
=PEG_R2D_C_N<15..0>
=PEG_D2R_N<15..0>
MAKE_BASE=TRUE
PEG_D2R_N<0..15>
MAKE_BASE=TRUE
PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE
PEG_D2R_P<0..15>
051-9509
4.2.0
9 OF 113
9 OF 100
10
10
10
10 71 89
71 89
71 89
71 89
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DMI_TX_1*
PE_TX_3*
PE_TX_3
PE_TX_2*
PE_TX_2
PE_TX_1*
PE_TX_1
PE_TX_0*
PE_TX_0
PE_RX_3*
PE_RX_3
PE_RX_2*
PE_RX_2
PE_RX_1*
PE_RX_1
PE_RX_0*
PE_RX_0
PEG_TX_15*
PEG_TX_15
PEG_TX_14*
PEG_TX_14
PEG_TX_13*
PEG_TX_13
PEG_TX_12*
PEG_TX_12
PEG_TX_11*
PEG_TX_11
PEG_TX_10*
PEG_TX_10
PEG_TX_9*
PEG_TX_9
PEG_TX_8*
PEG_TX_8
PEG_TX_7*
PEG_TX_7
PEG_TX_6
PEG_TX_5*
PEG_TX_5
PEG_TX_4*
PEG_TX_4
PEG_TX_3*
PEG_TX_3
PEG_TX_2*
PEG_TX_2
PEG_TX_1*
PEG_TX_1
PEG_TX_0*
PEG_TX_0
PEG_RX_15*
PEG_RX_15
PEG_RX_13*
PEG_RX_12
PEG_RX_11*
PEG_RX_11
PEG_RX_10
PEG_RX_9
PEG_RX_8
PEG_RX_7
PEG_RX_6
PEG_RX_5
PEG_RX_4*
PEG_RX_4
PEG_RX_3*
PEG_RX_3
PEG_RX_2
PEG_RX_1*
PEG_RX_0
FDI_TX_7*
FDI_TX_7
FDI_TX_6*
FDI_TX_6
FDI_TX_5*
FDI_TX_5
FDI_TX_4*
FDI_TX_4
FDI_TX_3*
FDI_TX_3
FDI_TX_2*
FDI_TX_2
FDI_TX_1*
FDI_TX_1
FDI_TX_0*
FDI_TX_0
FDI_LSYNC_1
FDI_LSYNC_0
FDI_FSYNC_1
FDI_FSYNC_0
DMI_TX_3*
DMI_TX_3
DMI_TX_2*
DMI_TX_2
DMI_TX_1
DMI_TX_0*
DMI_TX_0
DMI_RX_3*
DMI_RX_3
DMI_RX_2*
DMI_RX_2
DMI_RX_1
DMI_RX_0*
FDI_COMPIO
FDI_ICOMPO
FDI_INT
PEG_COMPI
PEG_ICOMPO
PEG_RX_1
PEG_RX_14*
PEG_RX_12*
PEG_RX_6*
PEG_RX_13
PEG_RX_14
PEG_RCOMPO
PEG_RX_10*
PEG_RX_9*
PEG_RX_8*
PEG_RX_7*
PEG_RX_2*
PEG_RX_0*
PEG_RX_5*
PEG_TX_6*
DMI_RX_0
DMI_RX_1*
SYM 1 OF 10
FLEXIBLE DISPLAY INTERFACE
PCI EXPRESS -- GRAPHICS
DMI
PCI EXPRESS
RSVD_NCTF_AV1
RSVD_NCTF_AW2
RSVD_NCTF_AY3
RSVD_NCTF_B39
NCTF_AW38
NCTF_AU40
NCTF_D1
NCTF_C2
NCTF_A38
CFG_8
RSVD_J34
RSVD_J33
RSVD_J31
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
RSVD_K9
RSVD_K31
RSVD_K34
RSVD_L9
RSVD_L31
RSVD_L33
RSVD_L34
RSVD_M34
RSVD_N33
RSVD_N34
RSVD_P35
RSVD_P37
RSVD_P39
RSVD_R34
RSVD_R36
RSVD_R38
RSVD_R40
RSVD_AB6
RSVD_AB7
RSVD_AD34
RSVD_AD35
RSVD_AD37
RSVD_AE6
RSVD_AF4
RSVD_AG4
RSVD_AJ11
RSVD_AJ29
RSVD_AJ30
RSVD_AJ31
RSVD_AN20
RSVD_AP20
RSVD_AT11
RSVD_AT14
RSVD_AU10
RSVD_AV34
RSVD_AW34
RSVD_AY10
RSVD_J9
RSVD_H8
RSVD_H7
RSVD_C38
RSVD_D38
RSVD_C39
SYM 5 OF 10
RESERVED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ThermDA
ThermDC
CFG[17:7] Reserved config lanes
CFG[6:5] PCIe bifurcation; Refer to page 15 for more info
CFG[4] Reserved config lane
CFG[3] PCIe Static x4 lane reversal; Refer to page 15 for more info
CFG[2] PCIe Static x16 lane reversal; Refer to page 15 for more info
CFG[1:0] Reserved config lane
(Available for Workstation only)
INTEL SUGGESTS TO KEEP THESE TPS
(Unused)
SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1
ROUTE B5 TO R1010.1 AS A SEPERATE 10 MIL TRACE.
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
19 90
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
MF-LF
402
1/16W
1%
24.9
PLACE_NEAR=U1000.B4:12.7mm
25 91
25 91
8
91
8
91
8
91
8
91
25 91
25 91
25 91
25 91
25 91
15 25 91
15 25 91
25 91
15 25 91
15 25 91
25 91
25 91
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
24.9
1%
1/16W
MF-LF
402
CPU DMI/PEG/FDI/RSVD
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
NO_TEST=TRUE
NC_SNS_CPU_THERMDN
NO_TEST=TRUE
NC_SNS_CPU_THERMDP
CPU_FDI_TX_P<2>
CPU_FDI_TX_P<3>
CPU_FDI_TX_P<0>
CPU_FDI_TX_P<4>
CPU_FDI_TX_N<1>
CPU_FDI_TX_N<0>
DMI_N2S_P<1>
DMI_N2S_P<0>
DMI_N2S_N<3>
DMI_N2S_N<2>
CPU_FDI_TX_N<4>
CPU_FDI_TX_N<5>
=PEG_D2R_P<3>
=PEG_D2R_P<0>
=PEG_D2R_N<10>
=PEG_D2R_N<5>
=PEG_D2R_N<15>
=PEG_D2R_P<2>
=PEG_D2R_P<1>
=PEG_D2R_P<7>
TP_PE_RX_N<0>
TP_PE_RX_N<2>
TP_PE_TX_N<2>
TP_PE_TX_N<3>
TP_PE_TX_P<0>
CPU_FDI_TX_N<7>
DMI_N2S_P<3>
DMI_N2S_P<2>
CPU_FDI_TX_P<6>
=PEG_D2R_N<6>
=PEG_D2R_N<4>
=PEG_D2R_N<3>
=PEG_D2R_N<2>
=PEG_D2R_N<12>
=PEG_D2R_N<14>
=PEG_D2R_N<13>
=PEG_D2R_N<11>
DMI_S2N_N<3>
CPU_FDI_FSYNC<1>
=PEG_D2R_P<15>
=PEG_R2D_C_P<3>
CPU_CFG<16>
CPU_CFG<12>
CPU_CFG<9>
CPU_CFG<6>
CPU_CFG<3>
CPU_CFG<1>
CPU_CFG<0>
TP_CPU_RSVD<19>
TP_CPU_RSVD<8>
=PEG_D2R_P<10>
=PPVCCIO_S0_CPU
DMI_S2N_N<1>
=PEG_D2R_N<7>
=PEG_D2R_N<9>
=PEG_D2R_P<13>
CPU_FDI_INT
DMI_S2N_N<2>
CPU_FDI_FSYNC<0>
CPU_FDI_LSYNC<0>
CPU_FDI_LSYNC<1>
CPU_FDI_TX_P<1>
CPU_FDI_TX_N<2>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<11>
=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>
TP_PE_RX_P<0>
TP_PE_RX_P<1>
TP_PE_RX_N<1>
TP_PE_RX_P<2>
TP_PE_RX_P<3>
TP_PE_RX_N<3>
TP_PE_TX_N<0>
TP_PE_TX_P<1>
TP_PE_TX_N<1>
TP_PE_TX_P<2>
TP_PE_TX_P<3>
DMI_S2N_N<0>
DMI_S2N_P<3>
DMI_S2N_P<2>
TP_CPU_RSVD<2>
TP_CPU_RSVD<3>
TP_CPU_RSVD<1>
TP_CPU_RSVD<4>
TP_CPU_RSVD<5>
TP_CPU_RSVD<6>
TP_CPU_RSVD<46>
TP_CPU_RSVD<45>
TP_CPU_RSVD<44>
TP_CPU_RSVD<43>
TP_CPU_RSVD<42>
TP_CPU_RSVD<41>
TP_CPU_RSVD<40>
TP_CPU_RSVD<39>
TP_CPU_RSVD<38>
TP_CPU_RSVD<37>
TP_CPU_RSVD<36>
TP_CPU_RSVD<35>
TP_CPU_RSVD<34>
TP_CPU_RSVD<33>
TP_CPU_RSVD<32>
TP_CPU_RSVD<31>
TP_CPU_RSVD<30>
TP_CPU_RSVD<29>
TP_CPU_RSVD<28>
TP_CPU_RSVD<27>
TP_CPU_RSVD<26>
TP_CPU_RSVD<25>
TP_CPU_RSVD<24>
TP_CPU_RSVD<23>
TP_CPU_RSVD<22>
TP_CPU_RSVD<21>
TP_CPU_RSVD<20>
TP_CPU_RSVD<16>
TP_CPU_RSVD<11>
CPU_CFG<15>
CPU_CFG<11>
CPU_CFG<10>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>
TP_CPU_RSVD<7>
TP_CPU_RSVD<9>
TP_CPU_NCTF<1>
TP_CPU_NCTF<2>
TP_CPU_NCTF<3>
TP_CPU_NCTF<4>
TP_CPU_NCTF<5>
TP_CPU_RSVD_NCTF<4>
TP_CPU_RSVD_NCTF<3>
TP_CPU_RSVD_NCTF<2>
TP_CPU_RSVD_NCTF<1>
DMI_S2N_P<0>
DMI_S2N_P<1>
=PEG_D2R_N<8>
=PEG_D2R_P<14>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<12>
=PEG_D2R_P<12>
CPU_CFG<17>
CPU_CFG<14>
CPU_CFG<13>
CPU_CFG<7>
CPU_CFG<8>
=PEG_R2D_C_N<2>
=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_R2D_C_N<6>
CPU_PEG_COMP
DMI_N2S_N<1>
DMI_N2S_N<0>
CPU_FDI_TX_P<7>
CPU_FDI_TX_P<5>
TP_CPU_RSVD<15>
TP_CPU_RSVD<14>
TP_CPU_RSVD<13>
TP_CPU_RSVD<12>
TP_CPU_RSVD<10>
CPU_FDI_TX_N<6>
CPU_FDI_TX_N<3>
CPU_FDI_COMPIO
=PPVCCIO_S0_CPU
R1010
1 2
U1000
W5
W4
V3
V4
Y3
Y4
AA4
AA5
V7
V6
W7
W8
Y6
Y7
AA7
AA8
AE2
AC5
AE5
AE1
AG3
AC4
AE4
AC8
AC7
AC2
AC3
AD2
AD1
AD4
AD3
AD7
AD6
AE7
AE8
AF3
AF2
AG2
AG1
P3
P4
R2
R1
T4
T3
U2
U1
P8
P7
T7
T8
R6
R5
U5
U6
B4
B5
C4
B11
B12
D12
D11
H3
H4
J1
J2
K3
K4
L1
L2
M3
M4
N1
N2
C10
C9
E10
E9
B8
B7
C6
C5
A5
A6
E2
E1
F4
F3
G2
G1
C13
C14
E14
E13
G5
G6
K7
K8
J5
J6
M8
M7
L6
L5
N5
N6
G14
G13
F12
F11
J14
J13
D8
D7
D3
C3
E6
E5
F8
F7
G10
G9
U1000
H36
J36
M38
N36
N38
N39
N37
N40
G37
G36
J37
K36
L36
N35
L37
M36
J38
L35
A38
AU40
AW38
C2
D1
AB6
AB7
AD34
AD35
AD37
AE6
AF4
AG4
AJ11
AJ29
AJ30
AJ31
AN20
AP20
AT11
AT14
AU10
AV34
AW34
AY10
C38
C39
D38
H7
H8
J31
J33
J34
J9
K31
K34
K9
L31
L33
L34
L9
M34
N33
N34
AV1
AW2
AY3
B39
P35
P37
P39
R34
R36
R38
R40
R1011
1
2
051-9509
4.2.0
10 OF 113
10 OF 100
8
91
8
91
8
91
8
91
8
91
8
91
8
91
8
91
8
8
8
8
8
8
91
8
91
8
91
8
8
6
10 11 13 16 62
8
91
8
91
8
91
8
91
8
91
8
91
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
89
8
91
8
91
8
8
8
8
8
8
91
8
91
91
6
10 11
13 16 62
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
BI
BI
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SM_VREF
SM_DRAMRST*
SM_DRAMPWROK
PM_SYNC
PREQ*
TMS
TRST*
TDI
TDO
DBR*
BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
BPM[4]*
BPM[5]*
BPM[6]*
BPM[7]*
TCK
PRDY*
BCLK_ITP
BCLK_0
BCLK_ITP*
BCLK_0*
UNCOREPWRGOOD
SKTOCC*
RESET*
THERMTRIP*
CATERR*
PECI
PROCHOT*
PROC_SEL
SYM 2 OF 10
CLOCKS
THERMAL
DDR3 MISC
PWR MGMT
JTAG & BPM
OUT
IN
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
FROM PCH
BASED ON INTEL MOBILE SOLUTION
25 91
25 91
25 91
25 91
25 91
1K
MF-LF
402
5%
1/16W
19 28
21 25
32 97
32 97
28
15 91
15 91
19
45
44 45 62
21 44 45
MF-LF
PLACE_NEAR=U1000.F36:50mm
75
402
5%
1/16W
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
MF-LF
402
1K
1%
1/16W
1K
MF-LF
402
1%
1/16W
10%
X7R-CERM
16V
402
0.1UF
45
402
1/16W
0
5%
MF-LF
51
MF-LF
402
5%
1/16W
25
25
25 91
25 91
25 91
25 91
25
200
MF-LF
402
1%
1/16W
1/16W
1%
402
MF-LF
130
18 90
18 90
19
43
MF-LF
5%
1/16W
402
26
60
25
25 91
25 91
25 91
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
CPU CLOCK/MISC/JTAG
CPU_PROCHOT_L
=PPVCCIO_S0_CPU
CPU_PROCHOT_R_L
CPU_SKTOCC_L
CPU_PROC_SEL
CPU_CATERR_L
CPU_PECI
CPU_THRMTRIP_L
CPU_PWRGD
PM_SYNC
PLT_RESET_LS1V05_L
CPU_MEM_RESET_L
CPU_DIMM_VREF_DAC_B
CPU_DIMM_VREF_DAC_A
CPU_RESET_L
PM_MEM_PWRGD
CPU_DDR_VREF
PM_MEM_PWRGD_R
=PPVCCIO_S0_CPU
=PP1V5_S0_CPU_MEM
XDP_CPU_PREQ_L
XDP_CPU_TMS
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TDO
XDP_DBRESET_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>
XDP_CPU_TCK
XDP_CPU_PRDY_L
ITPCPU_CLK100M_P
DMI_CLK100M_CPU_P
ITPCPU_CLK100M_N
DMI_CLK100M_CPU_N
=PP1V5_S0_CPU_MEM
CPU_DDR_VREF
R1101
1
2
R1120
1
2
R1121
12
R1125
12
R1111
1
2
R1124
1
2
U1000
W2
W1
C40
D40
H40
H38
G38
G40
G39
F38
E40
F40
E37
E39
J35
E38
K38
K40
K32
H34
F36
AH4
AH1
AJ33
AJ19
AW18
AJ22
M40
L40
L39
G35
L38
J39
J40
R1141
1
2
R1140
1
2
C1140
1
2
R1102
12
051-9509
4.2.0
11 OF 113
11 OF 100
6
10 11 13 16 62
11 97
6
10 11 13 16 62
6
11 13 16
6
11 13 16
11 97
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
SA_DQ_32
SA_DQ_33
SA_DQS_8*
SA_BS_2
SA_CAS*
SA_BS_1
SA_BS_0
SA_DQ_63
SA_DQ_62
SA_DQ_61
SA_DQ_60
SA_DQ_9
SA_CK_1
SA_ODT_2
SA_ODT_1
SA_ODT_0
SA_RAS*
SA_WE*
SA_CK_0
SA_CK_0*
SA_CK_1*
SA_CK_2
SA_CK_2*
SA_CK_3
SA_CK_3*
SA_CKE_0
SA_CKE_1
SA_CKE_2
SA_CKE_3
SA_CS_0*
SA_CS_1*
SA_CS_2*
SA_CS_3*
SA_DQ_0
SA_DQ_1
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_2
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_3
SA_DQ_30
SA_DQ_31
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_4
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_5
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQS_0
SA_DQS_0*
SA_DQS_1
SA_DQS_1*
SA_DQS_2
SA_DQS_2*
SA_DQS_3
SA_DQS_3*
SA_DQS_4
SA_DQS_4*
SA_DQS_5
SA_DQS_5*
SA_DQS_6
SA_DQS_6*
SA_DQS_7
SA_DQS_7*
SA_DQS_8
SA_ECC_CB_0
SA_ECC_CB_1
SA_ECC_CB_2
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_5
SA_ECC_CB_6
SA_ECC_CB_7
SA_MA_0
SA_MA_1
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_ODT_3
SYM 3 OF 10
DDR SYSTEM MEMORY A
SB_CK_1*
SB_DQS_3*
SB_DQ_33
SB_DQS_4
SB_DQS_2
SB_DQS_8*
SB_CKE_3
SB_CS_0*
SB_CS_1*
SB_CS_2*
SB_CS_3*
SB_CAS*
SB_RAS*
SB_WE*
SB_BS_0
SB_BS_1
SB_BS_2
SB_CK_0
SB_CK_0*
SB_CK_1
SB_CK_2
SB_CK_2*
SB_CK_3
SB_CK_3*
SB_CKE_0
SB_CKE_1
SB_CKE_2
SB_DQ_0
SB_DQ_1
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_2
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_3
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_4
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_5
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_6
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQS_0
SB_DQS_0*
SB_DQS_1
SB_DQS_1*
SB_DQS_2*
SB_DQS_3
SB_DQS_4*
SB_DQS_5
SB_DQS_5*
SB_DQS_6
SB_DQS_6*
SB_DQS_7
SB_DQS_7*
SB_DQS_8
SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_4
SB_ECC_CB_5
SB_ECC_CB_6
SB_ECC_CB_7
SB_MA_0
SB_MA_1
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SYM 4 OF 10
DDR SYSTEM MEMORY B
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
29 88
29 88
29 88
29 88
29 88
29 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
29 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
31 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
30 88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
8
88
29 88 30 88
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
SYNC_MASTER=K70_MLB
CPU DDR3 INTERFACES
SYNC_DATE=11/30/2011
MEM_A_CLK_P<0>
MEM_A_DQ<8>
MEM_A_DQ<6>
MEM_A_DQS_P<3>
MEM_A_DQ<11> MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_A_DQ<9>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<10>
MEM_A_ODT<3>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<1>
MEM_A_A<0>
TP_MEM_A_DQ_CB<7>
TP_MEM_A_DQ_CB<6>
TP_MEM_A_DQ_CB<5>
TP_MEM_A_DQ_CB<4>
TP_MEM_A_DQ_CB<3>
TP_MEM_A_DQ_CB<2>
TP_MEM_A_DQ_CB<1>
TP_MEM_A_DQ_CB<0>
TP_MEM_A_DQS_P<8>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_N<5>
MEM_A_DQS_P<5>
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<2>
MEM_A_DQS_P<2>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
MEM_A_DQ<7>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_CS_L<3>
MEM_A_CS_L<2>
MEM_A_CS_L<0>
MEM_A_CKE<0>
MEM_A_CLK_P<3>
MEM_A_CLK_N<0>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_ODT<0>
MEM_A_ODT<1>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_CAS_L
MEM_A_BA<2>
TP_MEM_A_DQS_N<8>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_B_ODT<3>
MEM_B_ODT<2>
MEM_B_ODT<1>
MEM_B_ODT<0>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<15>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<1>
MEM_B_A<0>
TP_MEM_B_DQ_CB<7>
TP_MEM_B_DQ_CB<6>
TP_MEM_B_DQ_CB<5>
TP_MEM_B_DQ_CB<4>
TP_MEM_B_DQ_CB<3>
TP_MEM_B_DQ_CB<2>
TP_MEM_B_DQ_CB<1>
TP_MEM_B_DQ_CB<0>
TP_MEM_B_DQS_P<8>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
MEM_B_DQS_N<5>
MEM_B_DQS_P<5>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<6>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<5>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<4>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<3>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<2>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<10>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_CKE<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_CAS_L
TP_MEM_B_DQS_N<8>
MEM_B_DQS_P<2>
MEM_B_DQS_P<4>
MEM_B_DQ<33>
MEM_B_DQS_N<3>
MEM_B_CLK_N<1>
MEM_B_DQ<60>
MEM_B_DQS_N<1>
MEM_A_DQ<19>
MEM_A_DQ<26>
MEM_B_CLK_P<2>
MEM_A_CLK_N<2>
MEM_A_CLK_P<2>
MEM_A_CKE<3>
MEM_A_CLK_N<3>
MEM_A_CKE<2>
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<1>
MEM_A_ODT<2>
MEM_B_DQ<20>
MEM_B_CS_L<3>
MEM_B_CS_L<2>
MEM_B_CS_L<1>
MEM_B_CKE<2>
MEM_B_CLK_N<3>
MEM_B_CKE<3>
MEM_B_CS_L<0>
MEM_B_CLK_P<1>
MEM_B_CKE<1>
MEM_B_CLK_N<2>
MEM_B_CLK_P<3>
U1000
AY29
AW28
AV20
AV30
AY25
AW25
AU24
AU25
AW27
AY27
AV26
AW26
AV19
AT19
AU18
AV18
AU29
AV32
AW30
AU33
AJ3
AJ4
AR3
AR4
AN2
AN3
AR2
AR1
AV2
AW3
AV5
AW5
AL3
AU2
AU3
AU5
AY5
AY7
AU7
AV9
AU9
AV7
AW7
AL4
AW9
AY9
AU35
AW37
AU39
AU36
AW35
AY36
AU38
AU37
AJ2
AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40
AL40
AL37
AJ1
AJ38
AJ37
AL39
AL38
AJ39
AJ40
AG40
AG37
AE38
AE37
AL2
AG39
AG38
AE39
AE40
AL1
AN1
AN4
AK3
AK2
AP3
AP2
AW4
AV4
AV8
AW8
AV37
AV36
AP38
AP39
AK38
AK39
AF38
AF39
AV13
AV12
AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12
AV27
AY24
AV28
AU21
AT21
AW32
AU20
AT20
AW24
AW23
AV23
AT24
AT23
AU22
AV22
AT22
AV31
AU32
AU30
AW33
AU28
AW29
U1000
AP23
AM24
AW17
AK25
AL21
AL22
AL20
AK20
AL23
AM22
AP21
AN21
AU16
AY15
AW15
AV15
AN25
AN26
AL25
AT26
AG7
AG8
AM10
AL10
AL6
AM6
AL9
AM9
AP7
AR7
AP10
AR10
AJ9
AP6
AR6
AP9
AR9
AM12
AM13
AR13
AP13
AL12
AL13
AJ8
AR12
AP12
AR28
AR29
AL28
AL29
AP28
AP29
AM28
AM29
AG5
AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31
AG6
AL35
AL32
AM34
AL31
AM35
AL34
AH35
AH34
AE34
AE35
AJ6
AJ35
AJ34
AF33
AF35
AJ7
AL7
AM7
AH7
AH6
AM8
AL8
AR8
AP8
AN13
AN12
AN29
AN28
AP33
AR33
AL33
AM33
AG35
AG34
AN16
AN15
AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15
AK24
AM20
AN23
AU17
AT18
AR26
AY16
AV16
AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17
AL26
AP26
AM26
AK26
AP24
AR25
051-9509
4.2.0
12 OF 113
12 OF 100
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
VCCIO_31
VCCIO_44
VCCIO_SEL
VCCIO_45
VCCIO_30
VSSAXG_SENSE
VCCAXG_SENSE
VSSIO_SENSE
VCCIO_SENSE
VCC_024
VCC_038
VCCIO_42
VCCIO_29
VCCIO_28
VCCIO_09
VCC_001
VCC_002
VCC_003
VCC_004
VCCIO_27
VCC_012
VCC_015
VCC_005
VCC_006
VCC_007
VCC_008
VCC_009
VCC_010
VCC_011
VCC_013
VCC_014
VCC_016
VCC_017
VCC_018
VCC_020
VCC_021
VCC_022
VCC_023
VCC_025
VCC_026
VCC_027
VCC_028
VCC_029
VCC_030
VCC_031
VCC_032
VCC_033
VCC_034
VCC_035
VCC_036
VCC_037
VCC_039
VCC_040
VCC_041
VCC_042
VCC_043
VCC_044
VCC_045
VCC_046
VCC_047
VCC_048
VCC_049
VCC_050
VCC_051
VCC_052
VCC_057
VCC_058
VCC_059
VCC_060
VCC_061
VCC_062
VCC_063
VCC_064
VCC_065
VCC_066
VCC_067
VCC_068
VCC_069
VCC_070
VCCIO_02
VCCIO_01
VCCIO_20
VCCIO_26
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_40
VCCIO_43
VCCIO_04
VCCIO_05
VCCIO_06
VCCIO_07
VCCIO_08
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_16
VCCIO_19
VCCSA_SENSE
VIDALERT*
VIDSCLK
VIDSOUT
VSS_SENSE
VCCIO_41
VCC_SENSE
VCC_056
VCC_055
VCC_054
VCC_053
VCCIO_03
VCC_019
VCCIO_15
VCCIO_17
VCCIO_18
VCCIO_22
VCCIO_21
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_32
VCCIO_37
VCCIO_38
VCCIO_39
VCCSA_VID
SYM 6 OF 10
CPU VIDS
POWER
IO POWER
CPU CORE SUPPLY
SENSE LINES
VCCAXG_44
VCCAXG_43
VCCAXG_02
VCCAXG_03
VDDQ10
VCCPLL1
VCCPLL0
VDDQ22
VDDQ21
VDDQ20
VDDQ19
VDDQ16
VDDQ14
VDDQ13
VDDQ12
VDDQ11
VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ4
VDDQ3
VDDQ2
VDDQ1
VDDQ0
VCCAXG_16
VCCAXG_15
VCCAXG_14
VCCAXG_13
VCCAXG_12
VCCAXG_11
VCCAXG_10
VCCAXG_09
VCCAXG_07
VCCAXG_06
VCCAXG_05
VCCAXG_04
VCCAXG_42
VCCAXG_41
VCCAXG_40
VCCAXG_39
VCCAXG_38
VCCAXG_37
VCCAXG_36
VCCAXG_35
VCCAXG_34
VCCAXG_33
VCCAXG_32
VCCAXG_31
VCCAXG_30
VCCAXG_29
VCCAXG_28
VCCAXG_27
VCCAXG_26
VCCAXG_25
VCCAXG_24
VCCAXG_22
VCCAXG_21
VCCAXG_19
VCCAXG_18
VCCAXG_17
VCCAXG_23
VCCAXG_20
VDDQ15
VDDQ17
VDDQ18
VDDQ5
VCCAXG_01
VCCAXG_08
SYM 7 OF 10
1.8V
POWER
DDR3-1.5V RAILS
GRAPHICS
VCC_092
VSS_NCTF2
VSS_NCTF3
VCC_097
VCC_091
VCC_090
VCC_089
VCC_088
VCC_087
VCC_083
VCC_112
VCC_117
VCC_113
VCC_114
VCC_115
VCC_116
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCCSA0
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA8
VCCSA9
VSS_NCTF1
VCC_073
VCC_072
VCC_071
VCC_155
VCC_154
VCC_084
VCC_093
VSS_NCTF0
VCC_100
VCC_101
VCC_104
VCC_106
VCC_105
VCC_096
VCC_095
VCC_094
VCC_086
VCC_085
VCCSA7
VCCSA10
VCC_107
VCC_082
VCC_077
VCC_074
VCC_076
VCC_161
VCC_126
VCC_127
VCC_111
VCC_098
VCC_099
VCC_075
VCC_081
VCC_103
VCC_102
VCC_078
VCC_079
VCC_080
VCC_108
VCC_109
VCC_110
SYM 10 OF 10
CPU CORE SUPPLY
VCCSA
CPU CORE SUPPLY
POWER
NCTF
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
BGA-SKT-K70
OMIT_TABLE
IVY-BRIDGE
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
66 95
62 96
62 96
65 95
65 95
62 96
62 96
0
1/16W
MF-LF
5%
402
402
1/16W
1%
MF-LF
44.2
5%
0
MF-LF
1/16W
402
402
75
1%
1/16W
MF-LF
PLACE_NEAR=U1000.A37:10mm
MF-LF
1/16W
1%
110
402
PLACE_NEAR=U1000.B37:10mm
62 96
62 96
62 96
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
CPU POWER
NO_TEST=TRUE
NC_CPU_VCCSA_VID
NO_TEST=TRUE
NC_CPU_VCCIO_VID
SNS_CPU_VCCIO_P
SNS_CPU_VCCIO_N
SNS_CPU_VAXG_N
SNS_CPU_VCORE_P
=PPVCCIO_S0_CPU
=PPVCORE_S0_CPU
=PPVCCSA_S0_CPU
SNS_CPU_VAXG_P
SNS_CPU_VCCSA
=PPVCORE_S0_CPU
SNS_CPU_VCORE_N
CPU_VIDALERT_R_L
CPU_VIDALERT_L
CPU_VIDSOUT
CPU_VIDSCLK_R
=PPVCCIO_S0_CPU
CPU_VIDSOUT_R
CPU_VIDSCLK
=PP1V5_S0_CPU_MEM
=PP1V8_S0_CPU_PLL
=PPVAXG_S0_CPU
U1000
A12
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15
A36
L32
A11
A7
AA3
AB8
AF8
AG33
AJ16
AJ17
AJ26
AJ28
AJ32
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK30
B9
D10
D6
E3
E4
G3
G4
J3
J4
J7
J8
L3
L4
L7
M13
N3
N4
N7
R3
R4
R7
U3
U4
U7
V8
W3
P33
AB4
T2
P34
A37
C37
B37
B36
M32
AB3
U1000
AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40
T33
T34
T35
T36
T37
T38
T39
T40
U33
U34
U35
U36
U37
U38
U39
U40
W33
W34
W35
W36
W37
W38
Y33
Y34
Y35
Y36
Y37
Y38
AK11
AK12
AJ13
AJ14
AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31
AJ20
AY23
AY26
AY28
AJ23
AJ24
AR20
AR21
AR22
AR23
AR24
U1000
F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
F32
F33
F34
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G32
G33
H13
H14
H15
H16
H18
H19
H21
H22
H24
H25
H27
H28
H30
H31
H32
J12
J15
J16
J18
J19
J21
J22
J24
J25
J27
J28
J30
K15
K16
K18
K19
K21
K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M19
M21
M22
M24
M25
M27
M28
M30
H10
H11
M12
H12
J10
K10
K11
L11
L12
M10
M11
A4
B3
AV39
AY37
R1311
1 2
R1310
1 2
R1312
1 2
R1300
1
2
R1302
1
2
051-9509
4.2.0
13 OF 113
13 OF 100
6
10 11 13 16 62
6
13 16 48 62
6
16
6
13 16 48 62
96
96
6
10 11 13 16 62
96
6
11 16
6
16
6
17 48 62
VSS_180
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_144
VSS_143
VSS_142
VSS_141
VSS_140
VSS_139
VSS_138
VSS_137
VSS_136
VSS_135
VSS_134
VSS_133
VSS_132
VSS_131
VSS_130
VSS_129
VSS_128
VSS_127
VSS_126
VSS_125
VSS_124
VSS_123
VSS_122
VSS_121
VSS_120
VSS_119
VSS_118
VSS_117
VSS_116
VSS_115
VSS_114
VSS_113
VSS_112
VSS_111
VSS_110
VSS_109
VSS_108
VSS_107
VSS_106
VSS_105
VSS_104
VSS_103
VSS_102
VSS_101
VSS_100
VSS_099
VSS_098
VSS_097
VSS_096
VSS_095
VSS_094
VSS_093
VSS_092
VSS_091
VSS_090
VSS_089
VSS_088
VSS_087
VSS_086
VSS_085
VSS_084
VSS_083
VSS_082
VSS_081
VSS_080
VSS_079
VSS_078
VSS_077
VSS_076
VSS_075
VSS_074
VSS_073
VSS_072
VSS_071
VSS_070
VSS_069
VSS_068
VSS_067
VSS_066
VSS_065
VSS_064
VSS_063
VSS_062
VSS_061
VSS_060
VSS_059
VSS_058
VSS_057
VSS_056
VSS_055
VSS_054
VSS_053
VSS_052
VSS_051
VSS_050
VSS_049
VSS_048
VSS_047
VSS_046
VSS_045
VSS_044
VSS_043
VSS_042
VSS_041
VSS_040
VSS_039
VSS_038
VSS_037
VSS_036
VSS_035
VSS_034
VSS_033
VSS_032
VSS_031
VSS_030
VSS_029
VSS_028
VSS_027
VSS_026
VSS_025
VSS_024
VSS_023
VSS_020
VSS_019
VSS_001
VSS_002
VSS_003
VSS_004
VSS_005
VSS_012
VSS_006
VSS_007
VSS_008
VSS_009
VSS_010
VSS_011
VSS_013
VSS_014
VSS_015
VSS_021
VSS_022
VSS_016
VSS_017
VSS_018
SYM 8 OF 10
VSS
VSS_360
VSS_359
VSS_358
VSS_357
VSS_356
VSS_355
VSS_354
VSS_353
VSS_352
VSS_351
VSS_350
VSS_349
VSS_348
VSS_347
VSS_346
VSS_345
VSS_344
VSS_343
VSS_342
VSS_341
VSS_340
VSS_339
VSS_338
VSS_337
VSS_336
VSS_335
VSS_334
VSS_333
VSS_332
VSS_331
VSS_330
VSS_329
VSS_328
VSS_327
VSS_326
VSS_325
VSS_324
VSS_323
VSS_322
VSS_321
VSS_320
VSS_319
VSS_318
VSS_317
VSS_316
VSS_315
VSS_314
VSS_313
VSS_312
VSS_311
VSS_310
VSS_309
VSS_308
VSS_307
VSS_306
VSS_305
VSS_304
VSS_303
VSS_302
VSS_301
VSS_300
VSS_299
VSS_298
VSS_297
VSS_296
VSS_295
VSS_294
VSS_293
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
VSS_270
VSS_269
VSS_268
VSS_267
VSS_266
VSS_265
VSS_264
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_196
VSS_195
VSS_194
VSS_200
VSS_199
VSS_198
VSS_197
VSS_188
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_182
VSS_187
VSS_186
VSS_181
VSS_185
VSS_184
VSS_183
SYM 9 OF 10
VSS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
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NOTICE OF PROPRIETARY PROPERTY:
PAGE
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
IVY-BRIDGE
OMIT_TABLE
BGA-SKT-K70
CPU GROUNDS
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
U1000
A17
A23
A26
A29
A35
AA33
AA34
AA35
AA36
AA37
AA38
AA6
AB5
AC1
AC6
AD33
AD36
AD38
AD39
AD40
AD5
AD8
AE3
AE33
AE36
AF1
AF34
AF36
AF37
AF40
AF5
AF6
AF7
AG36
AH2
AH3
AH33
AH36
AH37
AH38
AH39
AH40
AH5
AH8
AJ12
AJ15
AJ18
AJ21
AJ25
AJ27
AJ36
AJ5
AK1
AK10
AK13
AK14
AK16
AK22
AK28
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK4
AK40
AK5
AK6
AK7
AK8
AK9
AL11
AL14
AL17
AL19
AL24
AL27
AL30
AL36
AL5
AM1
AM11
AM14
AM17
AM2
AM21
AM23
AM25
AM27
AM3
AM30
AM36
AM37
AM38
AM39
AM4
AM40
AM5
AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10
U1000
AV11
AV14
AV17
AV3
AV35
AV38
AV6
AW10
AW11
AW14
AW16
AW36
AW6
AY11
AY14
AY18
AY35
AY4
AY6
AY8
B10
B13
B14
B17
B23
B26
B29
B32
B35
B38
B6
C11
C12
C17
C20
C23
C26
C29
C32
C35
C7
C8
D17
D2
D20
D23
D26
D29
D32
D37
D39
D4
D5
D9
E11
E12
E17
E20
E23
E26
E29
E32
E36
E7
E8
F1
F10
F13
F14
F17
F2
F20
F23
F26
F29
F35
F37
F39
F5
F6
F9
G11
G12
G17
G20
G23
G26
G29
G34
G7
G8
H1
H17
H2
H20
H23
H26
H29
H33
H35
H37
H39
H5
H6
H9
J11
J17
J20
J23
J26
J29
J32
K1
K12
K13
K14
K17
K2
K20
K23
K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8
051-9509
4.2.0
14 OF 113
14 OF 100
IN
OUT
S
G
D
OUT
D
G S
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
10 = 2x8 0 = REV 0 = REV
00 = 1x8,2x4
11 = 1x16 (default) 1 = DIR 1 = DIR
IVB PCIe Straps configuration:
CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16
UNUSED clock terminations for FCIM MODE
DP_AUXIO_EN Inversion
Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP
402
5%
10K
1/16W MF-LF
5%
1/16W MF-LF
402
10K
MF-LF
5%
10K
1/16W
402
5%
10K
MF-LF
402
1/16W
5%
MF-LF
10K
1/16W
402
MF-LF
5%
10K
1/16W
402
1/16W MF-LF
5%
10K
402
MF-LF1/16W
402
5%
10K
5%
MF-LF1/16W
10K
402
10K
MF-LF1/16W
402
5%
1/16W5%MF-LF
10K
402
5%
402
NOSTUFF
1/16W MF-LF
1K
5%
1K
1/16W
NOSTUFF
MF-LF
402
MF-LF
1K
5%
1/16W
U1000.18:3mm
402
1/16W1KMF-LF5%402
10K
5%
1/16W
402
MF-LF
402
1/16W
100K
MF-LF
5%
10K
1/16W MF-LF5%402
MF-LF1/16W
5%
402
20K
1/16W MF-LF
5%
10K
402
1/16W MF-LF
5%
10K
402
PLACE_NEAR=U1800.AG56:5mm
5%
MF-LF1/16W
10K
402
PLACE_NEAR=U1800.R33:5mm
5%
MF-LF1/16W
10K
402
5%
MF-LF1/16W
10K
402
5%
MF-LF1/16W
10K
402
PLACE_NEAR=U1800.P33:5mm
5%
MF-LF1/16W
10K
402
PLACE_NEAR=U1800.AF55:5mm
MF-LF1/16W
5%
10K
402
5%
MF-LF1/16W
10K
402
PLACE_NEAR=U1800.BF38:5mm
5%
MF-LF1/16W
10K
402
PLACE_NEAR=U1800.BD38:5mm
5%
MF-LF1/16W
10K
402
1/16W
5%
10K
402
MF-LF
402
5%
MF-LF
10K
1/16W
1/16W
402
5%
10K
MF-LF
MF-LF1/16W
10K
402
5%
5%
1/16W
10K
MF-LF
402
5%
MF-LF1/16W
10K
402
MF-LF
402
10K
1/16W
5%
402
MF-LF1/16W
10K
5%
402
10K
1/16W MF-LF
5%
402
5%
MF-LF1/16W
10K
10K
402
MF-LF
5%
1/16W
402
10K
1/16W MF-LF
5%
MF-LF
5%
1/16W1K402
1/16W1K402
MF-LF
5%
402
1K
5%
MF-LF1/16W
NOSTUFF
402
MF-LF
5%
4.7K
1/16W
MF-LF1/16W
402
5%
10K
MF-LF
5%
1/16W
10K
402
10K
402
1/16W5%MF-LF
1/16W
10K
5%
MF-LF
402
10K
402
1/16W5%MF-LF
402
1/16W MF-LF
5%
1K
402
5%
MF-LF1/16W
10K
5%
402
1/16W
10K
MF-LF
MF-LF
5%
1/16W
10K
402
44
18 92
330
PLACE_NEAR=R1805.4:3mm
5%
1/16W MF-LF
402
NTR1P02L
SOT23-3-HF
MF-LF
100K
5%
1/16W
402
100K
5%
1/16W MF-LF
402
MF-LF
1/16W
5%
10K
402
402
10K
5%
1/16W
MF-LF
84 85
CRITICAL
VESM
SSM3K15AMFVAPE
402
5%
MF-LF
1/16W
10K
10K
5%
MF-LF1/16W
402
5%
MF-LF
402
10K
1/16W
402
MF-LF
1/16W
5%
0
NOSTUFF
0
1/16W
NOSTUFF
MF-LF
402
5%
SYNC_MASTER=D7_TONY
STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU
SYNC_DATE=01/11/2012
SSD_CLKREQ_L
ENET_CLKREQ_L
=PP3V3_S4_SDCARD
USB_EXTD_OC_L
USB_EXTB_OC_L
USB_EXTA_OC_L
USB_EXTB_OC_EHCI_L
USB_EXTD_OC_EHCI_L
=PP3V3_S5_PCH_STRAPS
ITPCPU_CLK100M_N
PCH_GPIO48
DP_AUXIO_EN
DP_AUXCH_ISOL
PCH_GPIO1
=PP3V3_S0_PCH_STRAPS
MLB_RAM_CFG0
SMC_RUNTIME_SCI_L
MLB_RAM_CFG1
PCH_SPKR
PEG_CLKREQ_L
AP_CLKREQ_L
TBT_CLKREQ_L
CPU_CFG<2>
HDA_SYNC
JTAG_TBT_TDI
=PP3V3_S4_PCH
=PP3V3_S0_LED_SATA
PCH_SATALED_L
ITPCPU_CLK100M_PITPXDP_CLK100M_P
ITPXDP_CLK100M_N
PCH_GPIO29
SPI_DESCRIPTOR_OVERRIDE_L
=PP3V3_S5_PCH_STRAPS
CPU_CFG<6>
CPU_CFG<3>
CPU_CFG<5>
TBT_PWR_REQ_L
=PP3V3_S0_PCH_GPIO
PCH_CLKIN_GND0
PCH_CLKIN_GND1
PCH_CLK100M_DMIN
PCH_CLK100M_SATAP
PCH_CLK96M_DOTN
PCH_GPIO72
PCH_CLK96M_DOTP
PCH_CLK100M_SATAN
PCH_CLK100M_DMIP
PCH_CLK14P3M_REFCLK
PCH_GPIO22
PCH_GPIO6
ENET_MEDIA_SENSE
WOL_EN
TBT_CIO_PLUG_EVENT
ENET_LOW_PWR_PCH
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
=PP3V3_S0_PCH_STRAPS
TBT_GO2SX_BIDIR
SMC_WAKE_SCI_L
PM_PWRBTN_L
PCH_SMBALERT_L
JTAG_TBT_TMS
BT_PWR_RST_L
HDA_SDOUT_R
SPI_DESCRIPTOR_OVERRIDE_R
JTAG_TBT_TDO
=PP3V3_TBT_PCH_GPIO
TBT_SW_RESET_R_L
JTAG_TBT_TCK
SDCONN_STATE_CHANGE
PCH_CAM_RESET
SATARDRVR_EN
PCH_SUSWARN_L
=PP3V3_S0_PCH_STRAPS
DP_AUXCH_ISOL
PCH_CAM_EXT_BOOT
USB_EXTC_OC_L
=PP3V3_S5_PCH_STRAPS
AP_PWR_EN
=PP3V3_S0_PCH_STRAPS
NOSTUFF
NOSTUFF
R1554
1 2
R1553
1 2
R1501
1 2
R1504
1 2
R1563
1 2
R1509
1 2
R1510
1 2
R1511
1 2
R1525
1 2
R1528
1 2
R1527
1 2
R1526
1 2
R1524
1 2
R1512
1 2
R1513
1 2
R1523
1 2
R1522
1 2
R1531
1 2
R1570
1 2
R1533
1 2
R1532
1 2
R1530
1 2
R1555
1 2
R1545
1 2
R1547
1 2
R1550
1 2
R1551
1 2
R1548
1 2
R1546
1 2
R1549
1 2
R1543
1 2
R1544
1 2
R1560
1 2
R1561
1 2
R1562
1 2
R1559
1 2
R1542
1 2
R1557
1 2
R1558
1 2
R1517
1 2
R1520
1 2
R1519
1 2
R1518
1 2
R1516
1 2
R1537
1 2
R1536
1 2
R1514
1 2
R1529
1 2
R1538
1 2
R1540
1 2
R1539
1 2
R1541
1 2
R1508
1 2
R1564
1 2
R1521
1 2
R1502
1 2
R1503
1 2
R1552
1 2
Q1500
3
1
2
R1571
1 2
R1572
1 2
R1505
1
2
R1556
1
2
Q1509
3
1
2
R1507
1
2
R1590
1 2
R1567
1 2
051-9509
4.2.0
15 OF 113
15 OF 100
18 41
18 37
6
39
20 43
20 42
20 42
20
20
6
15
11 91
21
15 18
21
6
15
21
21 44
21
18
18 71
21 33
21 36
10 25 91
18 52 92
21 34
6
6
41
18 41
11 91 18 25 91
18 25 91
19
6
15
10 25 91
10 25 91
10 25 91
20 34
6
19 20 36
18
18
18
18
18
19
18
18
18
18
21
21
18 37 93
21 38
21 34
21 26
19 33 44 60
19 44 60
19 28 38 44 45 60
6
15
21 34
21 44
19 25 44
18
18 34
20
20 33
21 34
6
21
21 34
20 39
21
18
19
6
15
15 18
6
15
21
20 43
6
15
33
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
10x 10UF and 10x 1UF CAPACITORS
BULK CAPS ON CPU VREG PAGE 72
PLACEMENT_NOTE (C1600-C1613):
14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)
BULK CAPS ON CPU VREG PAGE 74
PLL (CPU VCCSFR) DECOUPLING
2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 1x 10uF 0805
BULK CAPS ON VTT REG PAGE 77
PLACEMENT_NOTE (C1660-C1665):
CPU VCCIO DECOUPLING
8X 22UF 0805, 6X 10UF 0805
Memory (CPU VCCDDR) DECOUPLING
INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders
CPU VCORE DECOUPLING
Bulk decoupling is on VCCSA reg page 75
PLACEMENT_NOTE (C1650-C1657):
CPU VCCSA DECOUPLING
2x 10uF 0603. INTEL RECOMMENDATION 2X 10uF 0805
10V
10%
402
X5R
1UF
6.3V
10%
402
X5R
2.2UF
603
X5R-CERM
6.3V
10%
4.7UF
6.3V
20%
805
CERM-X5R
22uF
CERM-X5R
6.3V
20%
805
22uF
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
10V
20%
603
X5R
10UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
16V
10%
402
X5R
1UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
330UF-0.0045OHM
POLY
CASE-D2-SM
20%
2V
47UF
6.3V
20%
0805
X5R
6.3V
20%
603
X5R
10UF
20%
0805
6.3V
X5R
47UF
CERM-X5R
6.3V
20%
805
22uF
805
CERM-X5R
20%
22uF
6.3V6.3V
20%
805
CERM-X5R
22uF22uF
6.3V
CERM-X5R
20%
805
6.3V
20%
0201
X5R
1UF
6.3V
20%
0201
X5R
1UF
6.3V
20%
0201
X5R
1UF
6.3V
20%
0201
X5R
1UF 1UF
6.3V
20%
0201
X5R
NOSTUFF
POLY
CASE-D2-SM
2V
20%
330UF-0.0045OHM
603
10uF
X5R
20%
6.3V
603
6.3V
20%
X5R
10uF
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
Place under socket cavity on secondary side.
6.3V
20%
805
CERM-X5R
22UF
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805
CERM-X5R
22UF
Place under socket cavity on secondary side.
6.3V
20%
805
CERM-X5R
22UF
Place under socket cavity on secondary side.
6.3V
20%
805
CERM-X5R
22UF
Place under socket cavity on secondary side.
6.3V
20%
805
CERM-X5R
22UF
Place under socket cavity on secondary side.
6.3V
20%
805
CERM-X5R
22UF
Place under socket cavity on secondary side.
22UF
CERM-X5R
6.3V
20%
805
Place under socket cavity on secondary side.
6.3V
20%
805
CERM-X5R
22UF
Place under socket cavity on secondary side.
Place at edge of socket.
10uF
X5R
603
20%
6.3V
Place at edge of socket.
10uF
X5R
603
20%
6.3V6.3V
20%
603
X5R
10uF
Place at edge of socket.
603
X5R
6.3V
20%
10uF
Place at edge of socket.
6.3V
20%
603
X5R
10uF
Place at edge of socket.
10uF
6.3V
20%
603
X5R
Place at edge of socket.
6.3V
22uF
20%
805
CERM-X5R
10V
10%
402
X5R
1UF
SYNC_MASTER=K70_MLB
CPU NON-GFX DECOUPLING
SYNC_DATE=11/30/2011
=PPVCCSA_S0_CPU
=PPVCCIO_S0_CPU
=PP1V5_S0_CPU_MEM
=PPVCORE_S0_CPU
=PP1V8_S0_CPU_PLL
=PPVCORE_S0_CPU
C1650
1
2
C1600
1
2
C1601
1
2
C1602
1
2
C1603
1
2
C1604
1
2
C1605
1
2
C1606
1
2
C1651
1
2
C1652
1
2
C1653
1
2
C1654
1
2
C1655
1
2
C1656
1
2
C1657
1
2
C1665
1
2
C1664
1
2
C1663
1
2
C1662
1
2
C1661
1
2
C1660
1
2
C1680
1
2
C1694
1
2
C1693
1
2
C1692
1
2
C1691
1
2
C1690
1
2
C1681
1
2
C1609
1
2
C1608
1
2
C1607
1
2
C1613
1
2
C1612
1
2
C1611
1
2
C1610
1
2
C1629
1
2
C1628
1
2
C1627
1
2
C1626
1
2
C1624
1
2
C1623
1
2
C1622
1
2
C1621
1
2
C1620
1
2
C1630
1
2
C1625
1
2
C1631
1
2
C1632
1
2
C1633
1
2
C1634
1
2
C1635
1
2
C1636
1
2
C1637
1
2
C1638
1
2
C1639
1
2
C1670
1
2
C1696
1
2
C1695
1
2
C1697
1
2
C1679
1
2
C1678
1
2
C1677
1
2
C1676
1
2
C1682
1
2
C1683
1
2
C1684
1
2
C1685
1
2
C1686
1
2
C1687
1
2
C1667
1
2
C1666
1
2
051-9509
4.2.0
16 OF 113
16 OF 100
6
13
6
10 11 13
62
6
11 13
6
13 16
48 62
6
13
6
13 16 48 62
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF
VAXG DECOUPLING
PLACEMENT_NOTE (C1704-C1709):
BULK CAPS ON CPU VREG PAGE 73
1/16W
5%
402
MF-LF
0
0
MF-LF
402
5%
1/16W
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
20%
805-3
CERM-X5R
22UF
Place inside socket cavity
6.3V
10%
603
X5R-CERM
Place inside socket cavity
4.7UF
X5R-CERM
4.7UF
6.3V
10%
603
Place inside socket cavity
6.3V
10%
603
4.7UF
Place inside socket cavity
X5R-CERM
1/16W
5%
MF-LF
0
402
X5R
6.3V
20%
603
CRITICAL
10UF
IG:Y
X5R
0.1UF
16V
402
10%
IG:Y
CERM
0.01UF
10%
402
16V
IG:Y
TANT
2.5V
20%
220UF
B16
CRITICAL
IG:Y
TANT
2.5V
20%
220UF
B16
CRITICAL
IG:Y
1UF
6.3V
CERM
10%
402
NOSTUFF
1UF
10%
6.3V
CERM
402
NOSTUFF
10UH-0.12A-0.36OHM
0603
CRITICAL
OMIT_TABLE
0603
CRITICAL
10UH-0.12A-0.36OHM
OMIT_TABLE
RES,MF,1/10W,0OHM,5,0603,SMD,LF
113S0022 IG:N
2
L1730,L1740
CRITICAL
IND,WW,10UH,20%.120MA,0.36OHMS
152S1070
2
L1730,L1740
IG:Y
SYNC_DATE=11/30/2011
SYNC_MASTER=K70_MLB
GFX DECOUPLING & PCH PWR ALIAS
PP1V05_S0_PCH_VCCADPLLA_F
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4MM
PP1V05_S0_PCH_VCCADPLLA_R
MIN_NECK_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4MM
PP1V05_S0_PCH_VCCADPLLB_R
MAKE_BASE=TRUE
PP1V05_S0_PCH_VCCADPLLB_F
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP3V3_S0_PCH_VCCA_DAC_F
=PP1V05_S0_PCH_VCC_ADPLL
=PP3V3_S0_PCH_VCC_ADAC
=PPVAXG_S0_CPU
R1730
1 2
R1740
1 2
C1709
1
2
C1708
1
2
C1707
1
2
C1706
1
2
C1705
1
2
C1704
1
2
C1710
1
2
C1711
1
2
C1712
1
2
R1720
1 2
C1720
1
2
C1721
1
2
C1722
1
2
C1730
1
2
C1740
1
2
C1731
1
2
C1741
1
2
L1730
1 2
L1740
1 2
051-9509
4.2.0
17 OF 113
17 OF 100
22 24
22 24
22
6
6
6
13 48 62
IN
IN
OUT
OUT
OUT
IN
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
BI
BI
BI
BI
OUT
SATA3COMPI
SATA3RCOMP0
SATA3RBIAS
SATA3RXP
HDA_SYNC
INTRUDER*
LDRQ1*/GPIO23
SATA1TXN
SATA3RXN
SATA1RXN
SATA1TXP
SATA0RXN
SERIRQ
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME*
SATA1RXP
SATA2TXN
SATA2TXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATALED*
SATA0GP/GPIO21
SATA1GP/GPIO19
L_BKLTCTL
HDA_RST*
SPKR
HDA_SDIN1
HDA_SDIN3
HDA_SDIN2
HDA_SDO
GPIO33
GPIO13
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
SPI_CS0*
SPI_MOSI
SPI_MISO
RTCX1
RTCX2
SATA0TXP
SATA0TXN
SATA2RXN
SATA2RXP
SATA5RXP
SATA0RXP
LDRQ0*
L_BKLTEN
L_VDD_EN
FWH0/LAD0
INTVRMEN
SPI_CS1*
HDA_SDIN0
SRTCRST*
SPI_CLK
RTCRST*
HDA_BCLK
(1 OF 10)
LPC
RTC
IHDA
SATA
JTAG
SPI
CLKIN_DMI_P
PETN2
CLKOUT_PEG_A_N
CL_RST1*
CLKIN_DMI_N
PERP3
CLKOUT_PEG_B_N
CLKIN_DOT_96P
CL_DATA1
CL_CLK1
CLKIN_GND1_P
CLKIN_GND1_N
CLKIN_GND0_P
CLKOUT_ITPXDP_N
CLKOUTFLEX3/GPIO67
CLKOUTFLEX2/GPIO66
CLKOUTFLEX1/GPIO65
CLKOUTFLEX0/GPIO64
XCLK_RCOMP
XTAL25_OUT
XTAL25_IN
CLKIN_PCILOOPBACK
REFCLK14IN
CLKIN_SATA_P
CLKIN_DOT_96N
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_DMI_P
CLKOUT_DMI_N
CLKOUT_PEG_A_P
SMBCLK
SMBALERT*/GPIO11
SML1DATA/GPIO75
SML1CLK/GPIO58
SML1ALERT*/PCHHOT*/GPIO74
SML0DATA
SML0ALERT*/GPIO60
SML0CLK
SMBDATA
PERN3
PETP2
CLKOUT_PCIE5P
PCIECLKRQ5*/GPIO44
CLKOUT_PCIE4P
CLKOUT_PCIE5N
CLKOUT_PCIE3P
CLKOUT_PCIE4N
CLKOUT_PCIE3N
PCIECLKRQ2*/GPIO20/SMI*
CLKOUT_PCIE2P
CLKOUT_PCIE2N
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PETP8
PERP8
PETN8
PETP7
PERN8
PETN7
PERP7
PERN7
PETN6
PETP6
PERP5
PETP4
PERN5
PETN4
PERP4
PETP3
PERN4
PETN3
PERP2
CLKIN_SATA_N
CLKIN_GND0_N
CLKOUT_ITPXDP_P
CLKOUT_PEG_B_P
PETN5
PETP5
PERN6
PERP6
PERP1
PERN1
PETN1
PETP1
PERN2
FLEX
CLOCK
PCI-E*
PEG
FROM CLK BUFFER
SMBUS
(2 0F 10)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DOES THIS NEED LENGTH MATCH???
PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)
TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS
26 92
52 92
46 92
46 92
46 92
46 92
44 46
41 91
41 91
41 91
41 91
41 91
41 91
41 91
41 91
41 90
41 90
41 90
41 90
37 90
37 90
41 90
41 90
41 90
41 90
37 90
37 90
41 90
41 90
33 90
33 90
34 90
34 90
15 71
11 90
11 90
8
8
8
8
15
15
15
15
15
15
15
26 92
26 92
26 92
47 94
47 94
47 94
47 94
33 90
33 90
33 90
33 90
PLACE_NEAR=U1800.AJ53:2mm
37.4
MF-LF
1%
402
1/16W
MF-LF
402
5%
1/16W
10K
37 90
37 90
1/16W
PLACE_NEAR=U1800.AL2:2mm
MF-LF
402
1%
90.9
18
47
47
8
8
71 89
71 89
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
34 90
PLACE_NEAR=U1800.AC52:2mm
1/16W
750
MF-LF
1%
402
49.9
1%
1/16W
402
MF-LF
PLACE_NEAR=U1800.AE52:2mm
8
8
5%
402
MF-LF
33
1/16W
44 46 92
44 46 92
1/16W
33
5%
402
MF-LF
44 46 92
5%
MF-LF
402
33
1/16W
44 46 92
1/16W
33
5%
402
MF-LF
44 46
92
PANTHER-POINT
OMIT_TABLE
FCBGA
PANTHER-POINT
FCBGA
OMIT_TABLE
MF-LF
33
5%
402
1/16W
20K
1/16W
5%
402
MF-LF
402
5%
1/16W
20K
MF-LF
1UF
X5R
10V
402
10%
1UF
10V
10%
402
X5R
1M
1/16W
5%
MF-LF
402
MF-LF
5%
1/16W
402
390K
42
43
52 92
52 92
15 52 92
52 92
33
1/16W
SM-LF
5%
5%
402
1/16W
MF-LF
0
MF-LF
1/16W
402
5%
NOSTUFF
0
15
15
SIGNAL_MODEL=EMPTY
0
5% MF
201
1/20W
SIGNAL_MODEL=EMPTY
1/20W
0
5%
201
MF
SYNC_DATE=11/30/2011
SYNC_MASTER=K70_MLB
PCH SATA/PCIE/CLK/LPC/SPI
NO_TEST=TRUE
NC_SPI_CS1_L
PCIE_CLK100M_AP_N
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PCIE_TBT_R2D_C_N<2>
PCIE_TBT_R2D_C_N<1>
PCIE_TBT_D2R_N<1>
PCIE_AP_D2R_N
PEG_CLKREQ_L
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
PEG_CLK100M_N
PEG_CLK100M_P
PCIE_CLKREQ5_GPIO44_L
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
TP_SATA_E_D2RN
=PP1V05_S0_PCH_VCCIO_SATA
PCH_SATALED_L
TP_SATA_F_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_D_D2RP
TP_PCH_GPIO65_CLKOUTFLEX1
PCH_CLK25M_XTALIN
SATARDRVR_EN
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_N
PCIE_SSD_R2D_C_P<1>
PCIE_SSD_D2R_P<1>
PCIE_SSD_D2R_N<1>
PCH_SMBALERT_L
SMBUS_PCH_CLK
SMBUS_PCH_DATA
PCIE_CLKREQ5_GPIO44_L
PCIE_CLK100M_TBT_N
DMI_MIDBUS_CLK100M_N
DMI_MIDBUS_CLK100M_P
PCH_CLK100M_SATAP
TP_PCH_CL_CLK1
PCIE_TBT_D2R_N<3>
PCIE_TBT_D2R_P<3>
PCIE_TBT_R2D_C_N<3>
PCIE_TBT_R2D_C_P<3>
PCIE_CLK100M_AP_P
PCIE_TBT_R2D_C_P<0>
PCIE_TBT_R2D_C_N<0>
PCIE_TBT_D2R_P<1>
PCIE_AP_D2R_P
PCIE_TBT_R2D_C_P<2>
ITPXDP_CLK100M_P
TP_PCH_CLKOUT_DPN
PCIE_ENET_R2D_C_P
PCIE_ENET_D2R_P
PCIE_SSD_R2D_C_N<1>
PCIE_SSD_R2D_C_P<0>
DMI_CLK100M_CPU_N
TP_CLKOUT_PEG_A_P
TP_CLKOUT_PEG_A_N
PCIE_SSD_R2D_C_N<0>
SPI_CS0_R_L
=PP1V05_S0_PCH_VCCIO_PCIE
PCH_CLKIN_GND0
PCH_CLKIN_GND1
PCH_XCLK_RCOMP
ITPXDP_CLK100M_N
TP_PCH_GPIO67_CLKOUTFLEX3
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO64_CLKOUTFLEX0
PCH_CLK25M_XTALOUT
PCH_CLK33M_PCIIN
SML_PCH_1_CLK
USB_EXTD_SEL_XHCI
SML_PCH_0_DATA
USB_EXTB_SEL_XHCI
PCIE_CLK100M_TBT_P
PCIE_TBT_D2R_P<2>
PCIE_TBT_D2R_N<0>
PCIE_SSD_D2R_P<0>
PCIE_SSD_D2R_N<0>
PCH_SATAICOMP
PCH_SATA3RBIAS
TP_SATA_D_D2RN
TP_SATA_C_R2D_CN
TP_SATA_D_R2D_CN
TP_SATA_E_D2RP
JTAG_TBT_TMS
TP_SATA_C_D2RN
PCH_INTVRMEN
PCH_SRTCRST_L
RTC_RESET_L
HDA_BIT_CLK_R
SPI_CLK_R
SPI_MISO
LPC_R_AD<3>
LPC_AD<3>
LPC_R_AD<1>
LPC_R_AD<0>
LPC_AD<0>
LPC_R_AD<2>
LPC_AD<2>
LFRAME_L
LPC_FRAME_L
PCH_CLK32K_RTCX2
=PP3V3_S0_PCH
SATA_HDD_D2R_N
SATA_HDD_R2D_C_P
HDA_SDIN0
HDA_SDOUT
HDA_BIT_CLK
PCH_INTRUDER_L
PCH_INTVRMEN
RTC_RESET_L
PCH_SRTCRST_L
TP_PCH_CL_DATA1
HDA_RST_R_L
TP_SATA_C_R2D_CP
TP_HDA_SDIN1
ENET_CLKREQ_L
SSD_CLKREQ_L
PCH_CLK32K_RTCX1
SATA_SSD_D2R_N
LPC_SERIRQ
TBT_PWR_EN_PCH
TP_LPC_DREQ0_L
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCH_CLK100M_DMIP
HDA_RST_L
HDA_SYNC
HDA_SYNC_R
PCH_CLK100M_SATAN
PCIE_TBT_D2R_N<2>
PCH_CLK96M_DOTP
PCIE_TBT_R2D_C_P<1>
PCIE_TBT_D2R_P<0>
=PP3V3_G3_PCH
TP_PCH_L_BKLTCTL
TP_PCH_L_BKLTEN
TP_SATA_F_D2RN
SML_PCH_1_DATA
PCH_CLK96M_DOTN
TP_PCH_CL_RST1
PCH_INTRUDER_L
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_SSD_D2R_P
TP_SATA_C_D2RP
HDA_SDOUT_R
HDA_BIT_CLK_R
PCH_SATA3COMP
TP_SATA_D_R2D_CP
SPI_MOSI_R
SATA_SSD_R2D_C_P
SATA_SSD_R2D_C_N
LPC_AD<1>
TP_PCH_L_VDD_EN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
SATARDRVR_EN_R
DP_AUXCH_ISOL_R
DP_AUXCH_ISOL
PCH_CLK100M_DMIN
DMI_CLK100M_CPU_P
SML_PCH_0_CLK
=PP1V05_S0_PCH
PCH_CLK14P3M_REFCLK
XDP_PCH_TDO
HDA_SDOUT_R
XDP_PCH_TCK
TP_PCH_CLKOUT_DPP
ENET_MEDIA_SENSE
TP_HDA_SDIN3
TP_HDA_SDIN2
HDA_RST_R_L
PCH_SPKR
HDA_SYNC_R
XDP_PCH_TMS
XDP_PCH_TDI
R1830
1
2
R1820
1
2
R1890
1
2
R1832
1
2
R1831
1
2
R1860
1 2
R1861
1 2
R1862
1 2
R1863
1 2
U1800
BK15
BJ17
BJ20
BG20
BG17
BA25
BC25
BU22
BC22
BD22
BF22
BK22
BJ22
BT23
BP23
BM38
BN41
BA43
BC52
BF47
BC50
AG12
AG18
AG17
BK17
BA20
BT41
BR39
BN39
BC54
AC56
AB55
AE46
AE44
AY52
AA53
AA56
AG49
AG47
AL50
AL49
AL56
AL53
AE54
AC52
AE52
AN46
AN44
AN56
AM55
AN49
AN50
AT50
AT49
AT46
AT44
AV50
AV49
AJ55
AJ53
BF57
AV52
AR54
AT57
AR56
AT55
AU53
BE56
BN37
U1800
BA50
BF50
BF49
P33
R33
BD38
BF38
W53
V52
R27
P27
BD15
AF55
AG56
P31
R31
N56
M55
R52
N52
AE6
AC6
AA5
W5
AB12
AB14
AB9
AB8
Y9
Y8
AF3
AG2
AG8
AG9
AE12
AE11
AT9
BA5
AW5
BA2
AV43
BL54
J20
P20
H17
P17
N15
J15
J12
H10
L20
R20
J17
M17
M15
L15
H12
J10
F25
C22
E21
F18
B17
A16
F15
B13
F23
A22
B21
E17
C16
B15
F13
D13
AN8
BN49
BT47
BR49
BU49
BT51
BM50
BR46
BJ46
BK46
AL2
AJ3
AJ5
R1864
1 2
R1803
1
2
R1802
1
2
C1803
1
2
C1802
1
2
R1801
1
2
R1800
1
2
R1805
1
2
3
4
8
7
6
5
R1851
1 2
R1852
1 2
R1841
1 2
R1842
1 2
051-9509
4.2.0
18 OF 113
18 OF 100
8
6
22 24
15 41
8
8
8
8
8
15
18
8
15 25 91
6
19 22
15
15
92
15 25 91
8
8
8
8
91
91
8
8
8
8
15 34
8
18
18
18 45
18 92
92
92
92
92
6
21 24
18 45
18
8
18 92
8
8
15 37
15 41
26
8
18 92
6
19
8
8
8
8
18
8
15 18 92
18 92
91
8
8
8
8
25
25
6
24
25 91
15 18 92
25 91
15 37 93
8
8
18 92
15
18 92
25 91
25 91
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
INIT3_3V*
GPIO32
DMI2TXP
PWRBTN*
RSMRST*
SYS_RESET*
DMI3RXN
DMI2RXN
DMI2RXP
DMI3RXP
DMI_ZCOMP
SUSACK*
SLP_SUS*
DSWVRMEN
DF_TVS
SLP_LAN*/GPIO29
PMSYNCH
SLP_A*
SLP_S3*
SLP_S4*
SUSCLK/GPIO62
SUS_STAT*/GPIO61
FDI_LSYNC0
FDI_FSYNC1
FDI_INT
FDI_RXP7
FDI_RXP6
FDI_RXP5
FDI_RXP4
FDI_RXP3
FDI_RXP1
FDI_RXN7
FDI_RXN6
FDI_RXN5
FDI_RXN4
FDI_RXN3
FDI_RXN2
FDI_RXN1
FDI_RXN0
RI*
SUSWARN*/GPIO30
PWROK
SYS_PWROK
DMI_IRCOMP
DMI2RBIAS
DMI1TXN
DMI0TXN
DMI1RXP
DMI0RXP
FDI_RXP0
FDI_LSYNC1
DMI0RXN
FDI_RXP2
DMI1RXN
FDI_FSYNC0
APWROK
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
GPIO31
GPIO72
DMI3TXP
SLP_S5*/GPIO63
WAKE*
DPWROK
DRAMPWROK
DMI
FDI
(3 OF 10)
SYSTEM POWER
MANAGEMENT
DDPB_AUXN
DDPB_AUXP
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_3P
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_HPD
DDPB_0N
DDPB_2N
DDPB_2P
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_2P
DDPD_3N
RESERVED
(4 OF 10)
CRT
DIGITAL DISPLAY INTERFACE
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACE CLOSE TO U1800 PIN
SHORT THESE TWO PINS VERY NEAR THE PINS
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT
KEEPING TP, IF NEED TO USE IT LATER
10 90
8
8
8
8
8
PLACE_NEAR=U1800.E31:2mm
49.9
MF-LF
402
1%
1/16W
19 33 38
45 92
15 33 44 60
15 44 60
15 28 38 44 45 60
11 28
61
15 25 44
61
26 61
45 61
25 26 44
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
10 90
5%
1/16W
MF-LF
402
10K
11
26 44 46
402
1/16W
1%
1K
MF-LF
MF-LF
1/16W
5%
1K
402
PLACE_NEAR=U1800.AT3:3mm
5%
10K
1/16W
MF-LF
402
390K
5%
402
1/16W
MF-LF
PLACE_NEAR=U1800.A32:2mm
MF-LF
402
1/16W
1%
750
5%
2.2K
402
MF-LF
1/16W
4.7K
5%
1/16W
MF-LF
402
OMIT_TABLE
PANTHER-POINT
FCBGA
OMIT_TABLE
PANTHER-POINT
FCBGA
5%
10K
402
MF-LF
1/16W
1/16W
5%
402
MF-LF
10K
PCH DMI/FDI/GRAPHICS
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
MAKE_BASE=TRUE
PCIE_WAKE_L
PM_RSMRST_PCH_L
PCH_SUSWARN_L
PCH_GPIO31_ACPRESENT
PCH_DF_TVS
PM_SLP_S4_L
PCH_GPIO29
PCH_DSWVRMEN
PCH_FDI_FSYNC<0>
DMI_N2S_N<2>
PCH_GPIO32
LPC_PWRDWN_L
PCIE_WAKE_L
PCH_FDI_LSYNC<1>
DP_IG_D_CTRL_DATA
TP_PCH_RESERVE_6
TP_PCH_RESERVE_14
DP_IG_D_CTRL_CLK
TP_PCH_RESERVE_11
TP_PCH_RESERVE_10
TP_PCH_RESERVE_9
DP_IG_B_MLN<2>
PCH_RI_L
=PP3V3_G3_PCH
TP_PM_SLP_A_L
DP_IG_C_MLP<3>
DP_IG_B_MLP<3>
PCH_DSWVRMEN
PCH_DF_TVS
TP_PCH_SUSACK_L
=PP3V3_S5_PCH
DMI_S2N_P<0>
PM_PCH_APWROK
=PP1V05_S0_PCH_VCCIO_PCIE
PM_PCH_PWROK
PM_MEM_PWRGD
PM_SYSRST_L
DMI_S2N_P<3>
PM_SLP_S5_L
DMI_S2N_N<3>
DMI_S2N_N<2>
DMI_N2S_N<1>
DMI_N2S_N<0>
DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_S2N_N<1>
PCH_DMI2RBIAS
PCH_FDI_RX_N<0>
PM_SLP_S3_L
TP_PCH_SLP_SUS_L
DMI_N2S_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
CPU_PROC_SEL
=PP1V8_S0_PCH
DP_IG_D_MLN<3>
DP_IG_D_MLP<2>
DP_IG_D_AUXP
DP_IG_D_AUXN
DP_IG_C_MLN<3>
DP_IG_C_MLP<2>
DP_IG_C_MLN<2>
DP_IG_C_MLP<1>
DP_IG_C_MLN<1>
DP_IG_C_MLP<0>
DP_IG_B_MLP<2>
DP_IG_B_MLN<0>
DP_IG_B_DDC_DATA
DP_IG_B_DDC_CLK
TP_SDVO_INTP
TP_SDVO_INTN
TP_SDVO_STALLP
TP_SDVO_STALLN
TP_SDVO_TVCLKINP
TP_SDVO_TVCLKINN
DP_IG_D_MLP<3>
DP_IG_D_MLN<2>
DP_IG_D_MLP<1>
DP_IG_D_MLN<1>
DP_IG_D_MLP<0>
DP_IG_D_MLN<0>
DP_IG_D_HPD
DP_IG_C_MLN<0>
DP_IG_C_HPD
DP_IG_C_AUX_P
DP_IG_C_AUX_N
DP_IG_C_CTRL_DATA
DP_IG_C_CTRL_CLK
DP_IG_B_MLP<1>
DP_IG_B_AUX_P
DP_IG_B_MLP<0>
DP_IG_B_MLN<3>
DP_IG_B_MLN<1>
PM_PCH_SYS_PWROK
PCH_DMI_COMP
DMI_S2N_P<1>
DP_IG_B_HPD
DP_IG_B_AUX_N
DMI_N2S_P<2>
DMI_S2N_N<0>
TP_PCH_RESERVE_7
TP_PCH_RESERVE_5
TP_PCH_RESERVE_4
TP_PCH_RESERVE_3
TP_PCH_RESERVE_1
TP_PCH_RESERVE_2
TP_PCH_RESERVE_8
TP_PCH_RESERVE_12
TP_PCH_RESERVE_15
TP_PCH_RESERVE_16
TP_PCH_RESERVE_17
TP_PCH_RESERVE_0
TP_PCH_RESERVE_13
TP_PCH_RESERVE_20
TP_PCH_RESERVE_21
TP_PCH_RESERVE_19
TP_PCH_RESERVE_18
TP_PCH_RESERVE_26
TP_PCH_RESERVE_28
TP_PCH_RESERVE_27
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
TP_CRT_IG_DDC_CLK
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
=PP3V3_S0_PCH_GPIO
PCH_FDI_RX_N<1>
PM_SYNC
PCH_GPIO72
PM_PWRBTN_L
PM_CLK32K_SUSCLK_R
PCH_DAC_IREF
=PP3V3_S5_PCH
=TBT_WAKE_L
PCH_FDI_RX_N<5>
PCH_FDI_RX_N<4>
PCH_FDI_RX_N<3>
PCH_FDI_RX_N<2>
PCH_FDI_RX_N<6>
PCH_FDI_RX_N<7>
PCH_FDI_RX_P<6>
PCH_FDI_INT
PCH_FDI_FSYNC<1>
PCH_FDI_LSYNC<0>
PCH_FDI_RX_P<7>
PCH_FDI_RX_P<2>
PCH_FDI_RX_P<0>
PCH_FDI_RX_P<1>
PCH_FDI_RX_P<3>
TP_PCH_RESERVE_22
TP_PCH_RESERVE_23
TP_PCH_RESERVE_24
TP_PCH_RESERVE_25
PCH_FDI_RX_P<4>
PCH_FDI_RX_P<5>
TP_PCH_INIT3V3_L
TP_CRT_IG_DDC_DATA
R1900
1
2
R1905
1
2
R1925
1
2
R1951
1
2
R1909
1
2
R1915
1
2
R1920
1
2
R1981
1
2
R1980
12
U1800
BC46
R47
D33
B33
J36
H36
A36
B35
P38
R38
A32
B37
C36
H38
J38
E37
F38
M41
P41
B31
E31
BT37
BG46
BR42
B51
C52
H46
E49
D51
C42
F45
H41
C46
B45
B47
J43
M43
B43
F43
J41
D47
A46
C49
H43
P43
BG43
BC56
AV46
BN56
F55
BT43
BJ38
BJ48
BK38
BC41
BH49
BM53
BN52
BH50
BD43
BN54
BP45
BA47
BU46
BJ53
BE52 BC44
U1800
AM1
AW3
AW1
AN2
AR4
AM6
AN6
AR2
AT3
R12
R14
M12
M11
K8
H8
M3
L5
R9
R8
T1
J3
L2
G4
G2
F5
F3
E2
E4
U12
U14
AL12
AL14
N2
B5
D5
D7
C6
C9
B7
B11
E11
R6
N6
AL9
AL8
M1
J57
U43
R44
U49
AB44
AB49
E52
H52
F53
J55
L56
K46
M49
Y50
AB50
L53
Y44
G56
AB46
K49
K50
M48
M50
R50
Y41
H50
U44
U46
U50
AL15
AL17
T3
U2
U5
W3
U9
U8
R1999
1
2
R1998
1
2
051-9509
4.2.0
19 OF 113
19 OF 100
19 33 38
15
19
15
19
8
8
8
8
8
8
8
8
6
18
8
8
19
19
6
19 24 26
6
18 22
8
11
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
90
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
6
15 20 36
8
15
6
19 24 26
34
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
BI
BI
BI
BI
BI
BI
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
USB3TN1
USB3TP1
USB3RN1
USB3RN2
USB3RP2
CLKOUT_PCI0
CLKOUT_PCI1
USBP13P
AD0
AD1
AD2
AD3
AD18
USBP8P
USBP8N
USBP7P
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
PIRQD*
REQ0*
REQ2*/GPIO52
REQ3*/GPIO54
GNT0*
GNT3*/GPIO55
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PCIRST*
SERR*
PERR*
IRDY*
PAR
DEVSEL*
FRAME*
PLOCK*
STOP*
TRDY*
PME*
PLTRST*
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP9N
USBP9P
USBP10N
USBP11N
USBP11P
USBP12N
USBP13N
USBRBIAS*
REQ1*/GPIO50
AD29
AD30
AD31
USBP12P
USBP10P
C/BE3*
C/BE0*
C/BE1*
C/BE2*
PIRQA*
GNT2*/GPIO53
GNT1*/GPIO51
PIRQC*
PIRQB*
USBRBIAS
USB3RP1
CLKOUT_PCI4
CLKOUT_PCI3
CLKOUT_PCI2
USB3TN2
USB3TP2
USB3RP3
USB3RN3
USB3TP3
USB3TN3
USB3RN4
USB3RP4
USB3TP4
USB3TN4
OC0*/GPIO59
OC2*/GPIO41
OC1*/GPIO40
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC7*/GPIO14
OC6*/GPIO10
USB
(5 OF 10)
PCI
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PLACE THE RESISTOR CLOSE TO COMMON POINT
TIE TRACES TOGETHER CLOSE TO PINS
EXT A
EXT B
EXT C
EXT D
UNUSED
UNUSED
UNUSED
EHCI - EXT B
UNUSED
UNUSED
EHCI - EXT D
UNUSED
INTERNAL HUB (BT,SMC12)
CAMERA
42 93
42 93
8
8
42 93
42 93
42 93
42 93
42 93
42 93
42 93
42 93
42 93
42 93
43 93
43 93
43 93
43 93
43 93
43 93
43 93
OMIT_TABLE
PANTHER-POINT
FCBGA
43 93
10K
5%
1/16W
MF-LF
402
NOSTUFF
56
58
15 34
15 33
15 42
15 42
15 43
15 43
15 33
15
15
15 39
201
1/20W
5% MF
0
SIGNAL_MODEL=EMPTY
201
1/20W0MF
SIGNAL_MODEL=EMPTY
5%
201
1/20W
5% MF
0
SIGNAL_MODEL=EMPTY
1/20W
5%
0
MF
201
SIGNAL_MODEL=EMPTY
201
1/20W
5% MF
0
SIGNAL_MODEL=EMPTY
201
1/20W
5%
0
MF
SIGNAL_MODEL=EMPTY
201
1/20W
5%
0
MF
SIGNAL_MODEL=EMPTY
MF
201
1/20W
5%
0
SIGNAL_MODEL=EMPTY
42 93
42 93
43 93
43 93
43 93
8
43 93
8
8
8
8
8
40
40
43 93
43 93
8
8
1/16W
PLACE_NEAR=U1800.BM25:2mm
22.6
MF-LF
402
1%
10K
MF-LF
4025%
1/16W
1/16W MF-LF
4025%
10K
MF-LF
402
1/16W
10K
5%
402
MF-LF
5%
1/16W
10K
10K
MF-LF
5%
1/16W
402
10K
MF-LF1/16W
4025%
10K
MF-LF
4025%
1/16W
5%
10K
1/16W
402
MF-LF
5%
10K
1/16W MF-LF
402
10K
5%
1/16W
402
MF-LF
26
26 92
26 92
26 92
10K
5%
1/16W
402
MF-LF
402
10K
5%
1/16W MF-LF
1/16W MF-LF
4025%
10K
402
1/16W
10K
MF-LF
5%
402
1/16W
5%
10K
MF-LF
27 93
27 93
8
8
MF-LF
5%
1/16W
10K
402
SYNC_DATE=11/30/2011
SYNC_MASTER=K70_MLB
PCH PCI/USB
BLC_I2C_MUX_SEL
=PP3V3_S0_PCH_GPIO
USB3_EXTB_TX_N
USB3_EXTC_RX_F_P
USB3_EXTC_TX_N
USB_EXTA_OC_L
PCI_INTC_L
PCI_SERR_L
PCH_STRP_TOPBLK_SWP_L
USB3_EXTA_RX_F_N
USB3_EXTB_RX_F_N
USB3_EXTB_RX_F_P
TP_PCI_AD<1>
TP_PCI_AD<18>
USB_PCH_8_P
USB_PCH_8_N
USB_PCH_7_P
TP_PCI_AD<5>
TP_PCI_AD<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
USB_PCH_0_N
USB_PCH_0_P
USB_PCH_1_N
USB_PCH_1_P
USB_PCH_2_N
USB_PCH_2_P
USB_PCH_3_N
USB_PCH_3_P
USB_PCH_4_N
USB_PCH_4_P
USB_PCH_5_N
USB_PCH_5_P
USB_PCH_6_N
USB_PCH_6_P
USB_PCH_7_N
USB_PCH_9_P
USB_PCH_10_N
USB_PCH_11_P
USB_PCH_13_N
USB_PCH_12_P
USB_PCH_10_P
USB3_EXTA_RX_F_P
USB3_EXTC_RX_F_N
PLT_RESET_L
USB3_EXTC_TX_P
USB_PCH_11_N
TP_PCI_CLK33M_OUT3
TP_PCI_AD<28>
JTAG_GMUX_TMS
TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
BT_PWR_RST_L
TP_PCI_AD<6>
BLC_GPIO
PCI_STOP_L
PCI_TRDY_L
PCI_IRDY_L
TBT_PWR_REQ_L
LPC_CLK33M_LPCPLUS_R
LPC_CLK33M_SMC_R
AUD_I2C_INT_L
TP_PCH_PCI_GNT0_L
AUD_IP_PERIPHERAL_DET
TP_PCI_RESET_L
TP_PCI_AD<4>
TP_PCI_AD<3>
TP_PCI_AD<0>
TP_PCI_AD<2>
USB_PCH_12_N
USB_PCH_9_N
TP_PCI_AD<13>
TP_PCI_AD<12>
TP_PCI_AD<11>
PCI_PLOCK_L
PCI_INTB_L
TP_PCI_C_BE_L<1>
TP_PCI_AD<31>
TP_PCI_AD<30>
PCI_PERR_L
TP_PCI_PAR
PCI_FRAME_L
PCH_CLK33M_PCIOUT
USB3_EXTA_TX_P
TP_PCI_PME_L
USB_EXTB_OC_L
USB_EXTD_OC_L
USB_EXTC_OC_L
USB_EXTD_OC_EHCI_R_L
SDCONN_STATE_CHANGE_R
TP_PCI_AD<29>
PCH_USB_RBIAS
PCI_INTD_L
PCI_INTA_L
TP_PCI_C_BE_L<3>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<0>
PCI_REQ0_L
USB3_EXTB_TX_P
PCI_DEVSEL_L
TP_PCI_CLK33M_OUT2
USB3_EXTD_RX_F_N
USB3_EXTD_RX_F_P
USB_EXTB_OC_EHCI_L
USB_EXTD_OC_EHCI_L
AP_PWR_EN
SDCONN_STATE_CHANGE
AP_PWR_EN_R
USB_EXTB_OC_EHCI_R_L
USB_EXTD_OC_R_L
USB_EXTC_OC_R_L
USB_EXTB_OC_R_L
USB_EXTA_OC_R_L
USB3_EXTD_TX_N
USB3_EXTD_TX_P
USB3_EXTA_TX_N
USB_PCH_13_P
R2070
1
2
R2010
1 2
R2011
1 2
R2012
1 2
R2013
1 2
R2015
1 2
R2016
1 2
R2017
1 2
R2020
1 2
R2021
1 2
R2022
1 2
R2023
1 2
R2024
1 2
R2026
1 2
R2025
1 2
R2027
1 2
R2030
1 2
U1800
BF15
BF17
BR9
BJ10
BM8
BF3
BN2
BE4
BE6
BG15
BC6
BT11
BT7
BA14
BL2
BC4
BL4
BC2
BM13
BA9
BF9
BA8
BF8
BT13
AV17
BK12
BG12
BN11
BJ12
BU9
BR12
BJ3
BN4
BP7
BG2
BP13
AT11
AN14
AT12
AT17
AT14
BH9
BC11
BA15
AV8
BU12
BE2
BF11
BM43
BD41
BG41
BK43
BP43
BJ41
BT45
BM45
BH8
AV14
BM3
BK10
BJ5
BM15
BP5
BN9
AV9
BT15
BR4
BA17
BK48
AV15
BG5
BT5
BK8
AV11
BR6
BC12
BC8
H31
J27
J25
L22
J31
L27
L25
J22
C29
F28
C26
B25
E29
E27
B27
D25
BF36
BD36
BK25
BJ25
BJ31
BK31
BF27
BD27
BJ27
BK27
BC33
BA33
BM33
BM35
BT33
BU32
BR32
BT31
BN29
BM30
BK33
BJ33
BF31
BD31
BN27
BR29
BR26
BT27
BM25
BP25
R2019
1
2
R2001
1 2
R2002
1 2
R2003
1 2
R2007
1 2
R2004
1 2
R2005
1 2
R2006
1 2
R2008
1 2
051-9509
4.2.0
20 OF 113
20 OF 100
6
15 19 36
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
25
25
8
93
8
8
8
8
25
25
25
25
25
25
OUT
IN
OUT
IN
NCTF
RSVD
GPIO
MISC
CPU
NCTF
(6 OF 10)
VSS_NCTF
SDATAOUT0/GPIO39
SLOAD/GPIO38
SATA4GP/GPIO16
PCIECLKRQ6*/GPIO45
TACH4/GPIO68
A20GATE
BMBUSY*/GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P
CLKOUT_PCIE7N
CLKOUT_PCIE7P
GPIO27
GPIO28
GPIO35/NMI*
GPIO57
GPIO8
NC_5
PCIECLKRQ7*/GPIO46
PECI
PROCPWRGD
PWM0
PWM1
PWM2
PWM3
RCIN*
SATA3GP/GPIO37
SATA5GP_GPIO49
SCLOCK/GPIO22
SDATAOUT1/GPIO48
SST
STP_PCI*/GPIO34
TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71
THRMTRIP*
TP1
TP10
TP11
TP12
TP13
TP14
TP16
TP17
TP18
TP19
TP2
TP20
TP3
TP4
TP5
TP6
TP7
TP8
TP9
NC_1
NC_2
NC_3
NC_4
VSSADAC
GPIO15
LAN_PHY_PWR_CTRL/GPIO12
GPIO24/PROC_MISSING
SATA2GP/GPIO36
TP15
BI
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
NC
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Place this near the T point
X
11 25
45
5%
1/16W
MF-LF
10K
402
402
MF-LF
1/16W
10K
5%
28 32
5%
100K
MF-LF
1/16W
402
46
NOSTUFF
0
5%
402
1/16W MF-LF
0
1/16W
5%
402
MF-LF
FCBGA
PANTHER-POINT
OMIT_TABLE
11 44 45
5
15 44
36
26
58 82
15 34
15 34
15 33
15 36
15 26
46 92
SIGNAL_MODEL=EMPTY
MF
1/20W
5%
0
201
SIGNAL_MODEL=EMPTY
201
5%
1/20W
MF
0
SIGNAL_MODEL=EMPTY
201
5% MF
1/20W
0
SIGNAL_MODEL=EMPTY
0
5%
201
MF
1/20W
0
5%
201
MF
1/20W
SIGNAL_MODEL=EMPTY
0
5%
1/20W
201
MF
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
0
MF
1/20W
5%
201
201
0
5%
1/20W
MF
SIGNAL_MODEL=EMPTY
MF
1/20W
201
5%
33
201
33
5% MF
1/20W
40
40
SYNC_MASTER=D7_TONY
SYNC_DATE=01/11/2012
PCH MISC
PCH_CAM_RESET_R
JTAG_TBT_TDO
TP_PCH_TP6
TP_PCH_TP5
=PP3V3_S0_PCH
TP_PCH_TP10
TP_PCH_TP11
PCH_CAM_RESET
PCH_CAM_EXT_BOOT
MLB_RAM_CFG1
PCH_CAM_EXT_BOOT_R
SPIROM_USE_MLB
MLB_RAM_CFG0
ENET_LOW_PWR_PCH
PCH_GPIO48
TP_PCH_TP14
TP_PCH_TP13
TBT_CLKREQ_L
TP_PCH_SST
TP_PCH_PWM3
JTAG_TBT_TCK
LPCPLUS_GPIO
JTAG_TBT_TCK_R
TBT_CIO_PLUG_EVENT
DP_GPU_TBT_SEL
GPU_GOOD
PCH_GPIO22
XDP_PIN03
WOL_EN
TBT_GO2SX_BIDIR
ENET_LOW_PWR_PCH_R
AUD_IPHS_SWITCH_EN_PCH_R
DP_GPU_TBT_SEL_R
TBT_CIO_PLUG_EVENT_R
TP_PCH_TP15
TP_PCH_TP17
TP_PCH_PWM0
TP_PCH_PWM1
SMC_RUNTIME_SCI_L
PCH_GPIO6
TP_PCH_GPIO8
PCH_A20GATE
PM_THRMTRIP_L
TP_PCH_TP1
TP_PCH_TP2
TP_PCH_TP9
AP_CLKREQ_L
JTAG_TBT_TDI
=PP3V3_S0_PCH
PCH_GPIO1
TP_PCH_TP16
TP_PCH_TP12
TP_PCH_TP4
TP_PCH_TP7
TP_PCH_TP8
CPU_PECI
CPU_PWRGD
TP_PCH_TP20
TP_PCH_TP19
PCH_PROCPWRGD
PCH_PECI
TP_PCIE_CLK100M_PE7P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N
TP_PCH_TP3
PCH_RCIN_L
TP_PCH_PWM2
TP_PCH_TP18
SMC_WAKE_SCI_L
TBT_SW_RESET_R_L
GPU_GOOD_R
TBT_SW_RESET_L
ISOLATE_CPU_MEM_L
ISOLATE_CPU_MEM_R_L
AUD_IPHS_SWITCH_EN_PCH
R2155
1
2
R2150
1
2
R2190
1
2
R2170
1 2
R2140
1 2
U1800
BB57
AW55
AB3
AA2
AE2
AF1
BM55
BP53
BJ43
BJ55
BJ57
BT53
BP51
BK50
A54
A52
F57
D57
AY20
AV44
BP55
H48
D53
BN21
BT21
BM20
BN19
BG56
BB55
BG53
AU56
BA56
BA53
BF55
AW53
BE54
BC43
BL56
BT17
BR19
BA22
BR16
BU16
BM18
BN17
BP15
E56
P22
BM46
BA27
BC49
AE49
AE41
AE43
AE50
BA36
AY36
Y14
L31
Y12
L33
M38
L36
Y18
Y17
AB18
AB17
A4
A6
BU54
BU6
D1
F1
B2
BM1
BM57
BP1
BP57
BT2
BU4
BU52
AU2
R2106
1 2
R2101
1 2
R2104
1 2
R2107
1 2
R2108
1 2
R2103
1 2
R2109
1 2
R2105
1 2
R2110
1 2
R2111
1 2
051-9509
4.2.0
21 OF 113
21 OF 100
8
8
6
18 21 24
8
8
15
15
15
15
15
8
8
8
8
25
15 34
15
25
15 38
15 34
25
25
25
25
8
8
8
8
15
8
8
8
8
15 34
6
18 21 24
15
8
8
8
8
8
8
8
8
8
8
8
8
8
8
15 44
25
15
25
VCCAPLLEXP
VCCCLKDMI
VCCAPLLDMI2
VCCIO
VCCADAC
VCCVRM1
VCCIO
VCC3_3_0
VCCVRM0
VCCASW
VCCCORE
VCC3_3
VCCAFDIPLL
VCCDMI
(7 OF 10)
VCCIO_DMI/CLK
VCC CORE
CRTDMI
FDI
VCCASW
VCCIO_PCIE
HVCMOS
V_PROC_IO_NCTF
VCCRTC
V5REF_SUS
VCCADPLLB
VCCSPI
VCCIO
V5REF
VCCAPLLSATA
VCC3_3
DCPSUSBYP
VCCACLK
DCPRTC
VCCADPLLA
DCPSST
V_PROC_IO
VCCDFTERM0
VCCDFTERM1
VCCDIFFCLKN
VCCDSW3_3
VCCIO
VCCVRM3
VCCSUSHDA
VCCVRM2
DCPRTC_NCTF
VCCSUS3_3
VCCSSC
VCC3_3
DCPSUS
SATA
PCI/GPIO/LPC
PCI/GPIO/LPC
(10 OF 10)
USB
CPURTC
HDA
CLOCK AND MISCELLANEOUS
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Max and Idle = 1mA
1.61A Max, 433mA Idle
(VCC3_3[1-9] total)
10 mA Max, 1mA Idle
105mA Max, 90mA Idle
Max and Idle = 1mA
159mA Max, 114mA Idle
(VCCVRM 4 total)
97mA Max, 15mA Idle
Max and Idle = 1mA
40mA Max, 5mA Idle
40mA Max, 10mA Idle
Max and Idle = 1 MA
409 mA Max, 42mA Idle
Need to check layout decoupling
(VCCSUS3_3 - 11 TOTAL)
200 mA Max, 2mA Idle
3mA Max, 1mA Idle
20mA Max, 1mA Idle
55mA Max, 5mA Idle
1.44 A Max, 474mA Idle
57 mA Max, 30mA Idle
PCH output, for decoupling only
PCH output, for decoupling only
3.456A Max, 426mA Idle
(VCCIO[1-31] total)
20mA Max, 10mA Idle
This should stay as RTC, correct?
10V
CERM
20%
402
0.1UF
PLACE_NEAR=U1800.BR54:2mm
10%
201
X5R
6.3V
0.1UF
PLACE_NEAR=U1800.BA46:2mm
402
PLACE_NEAR=U1800.BU42:2mm
0.1UF
CERM
20%
10V
10%
CERM
402
PLACE_NEAR=U1800.BU42:2mm
6.3V
1UF
PANTHER-POINT
FCBGA
OMIT_TABLE
PANTHER-POINT
FCBGA
OMIT_TABLE
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
PCH POWER
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V
PPVOUT_S0_PCH_DCPSST
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
PPVOUT_G3_PCH_DCPRTC
TP_DCPSUS_1
=PP3V3_S5_PCH_VCCSUS_HDA
=PP1V05_S0_PCH_VCCIO_PCIE
PP1V05_S0_PCH_VCCAPLLDMI2
=PP1V05_S0_PCH_VCCCLKDMI
PP1V05_S0_PCH_FDIPLL
PP1V8_S0_PCH_VCCVRM_F
=PP1V05_S0_PCH_VCCIO_DMI
=PP5V_S5_PCH_V5REFSUS
=PP3V3_S0_PCH_VCC_GPIO
PP1V05_S0_PCH_VCCAPLL_SATA
TP_DCPSUS_2
=PP3V3_S5_PCH_VCCSUS_USB
=PP3V3_S0_PCH_VCC
=PP1V05_S0_PCH_VCC_DMI
PP1V05_S0_PCH_VCC_A_CLK
TP_PPVOUT_PCH_DCPSUSBYP
=PP5V_S0_PCH_V5REF
=PP1V05_S0_PCH_VCCIO_USB
PP3V3_S0_PCH_VCCA_DAC_F
PP1V8_S0_PCH_VCCVRM_F
=PP3V3_S5_PCH_VCC_SPI
PP1V05_S0_PCH_VCCADPLLA_F
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V05_S0_PCH_VCC_DIFFCLK
=PP3V3_S5_PCH_VCC_DSW
PP1V8_S0_PCH_VCCVRM_F
=PP1V05_S0_PCH_VCC_SSC
TP_DCPSUS_0
PP1V05_S0_PCH_VCCAPLL_EXP
PP1V8_S0_PCH_VCCVRM_F
=PP1V05_S0_PCH_V_PROC_IO
PP1V05_S0_PCH_VCCADPLLB_F
=PP1V05_S0_PCH_VCC_CORE
=PP3V3_S0_PCH_VCC_HVCMOS
PP3V3_G3H_RTC
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCC_ASW
=PP3V3_S0_PCH_VCC_PCI
C2210
1
2
C2222
1
2
C2232
1
2
C2231
1
2
U1800
AF57
BC17
BD17
BD20
AT1
C54
A19
B53
AU32
AV36
AL28
AN22
AN24
AN26
AN28
AR24
AR26
AR28
AR30
AR36
AU34
AR38
AU30
AU36
AG24
AG26
AG28
AJ24
AJ26
AJ28
AL24
AJ20
AC24
AC26
AE36
AG32
AG34
AJ32
AJ34
AJ36
AL32
AL34
AN32
AN34
AC28
AR32
AR34
AC30
AC32
AE24
AE28
AE30
AE32
AE34
E41
B41
V36
Y28
AA34
AA36
F20
F30
V25
V27
V31
V33
Y24
Y26
Y30
Y32
Y34
V22
Y20
Y22
Y36
AJ1
R56
U1800
BR54
BT56
BA46
AA32
AT41
A39
AV41
BF1
BT25
D55
B56
AL38
AN38
AU22
A12
AU20
AV20
AL5
AB1
AC2
U56
T55
T57
AE15
AE17
AG15
AV40
AV24
AV26
AE40
BA38
AG38
AG40
AY25
AY27
AG41
AL40
AN40
AN41
AJ38
BU42
AN52
AC20
AE20
U31
AV30
BT35
AV32
AY31
AY33
BJ36
BK36
BM36
AT40
AU38
AV28
R54
R2
051-9509
4.2.0
22 OF 113
22 OF 100
6
24
6
18 19
8
24
8
22 24
6
24
6
24
8
6
24
6
24
6
24
8
8
24
6
17
22 24
6
24
17 24
6
24
6
6
24
22 24
6
8
22 24
6
24
17 24
6
24
6
24
6
26
6
18 24
6
24
6
24
VSS
VSS
(8 OF 10)
VSS
VSS
(9 OF 10)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
OMIT_TABLE
PANTHER-POINT
FCBGA
OMIT_TABLE
PANTHER-POINT
FCBGA
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
PCH GROUNDS
U1800
AE56
BR36
AA22
AU28
AU5
AV12
AV18
AV22
AV34
AV38
AV47
AV6
AW57
AA24
AY38
AY6
B23
BA11
BA12
BA31
BA41
BA44
BA49
BB1
AA26
BB3
BB52
BB6
BC14
BC15
BC20
BC27
BC31
BC36
BC38
AA28
BC47
BC9
BD25
BD33
BF12
BF20
BF25
BF33
BF41
BF43
AA30
BF46
BF52
BF6
BG22
BG25
BG27
BG31
BG33
BG36
AA38
AB11
AB15
AB40
AB41
C12
AB43
AB47
AB52
AB57
AB6
AC22
AC34
AC36
AC38
AC4
AY22
AC54
AE14
AE18
AE22
AE26
AE38
AE4
AE47
AE8
AE9
A26
AF52
AF6
AG11
AG14
AG20
AG22
AG30
AG36
AG43
AG44
A29
AG46
AG5
AG50
AG53
AH52
AH6
AJ22
AJ30
AJ57
AK52
A42
AK6
AL11
AL18
AL20
AL22
AL26
AL30
AL36
AL41
AL46
A49
AL47
AM3
AM52
AM57
AN11
AN12
AN15
AN17
AN18
AN20
A9
AN30
AN36
AN4
AN43
AN47
AN54
AN9
AR20
AR22
AR52
AA20
AR6
AT15
AT18
AT43
AT47
AT52
AT6
AT8
AU24
AU26
U1800
BG38
BH52
BH6
BJ1
BJ15
BK20
BK41
BK52
BK6
BM10
BM12
BM16
BM22
BM23
BM26
BM28
BM32
BM40
BM42
BM48
BM5
BN31
BN47
BN6
BP3
BP33
BP35
BR22
BR52
BU19
BU26
BU29
BU36
BU39
C19
C32
C39
C4
D15
D23
D3
D35
D43
D45
E19
E39
E54
E6
E9
F10
F12
F16
F22
F26
F32
F33
F35
F36
F40
F42
F46
F48
F50
F8
G54
H15
H20
H22
H25
H27
H33
H6
J1
J33
J46
J48
J5
J53
K52
K6
K9
L12
L17
L38
L41
L43
M20
M22
M25
M27
M31
M33
M36
M46
M52
M57
M6
M8
M9
N4
N54
R11
R15
R17
R22
R4
R41
R43
R46
R49
T52
T6
U11
U15
U17
U20
U22
U25
U27
U33
U36
U38
U41
U47
U53
V20
V38
V6
W1
W55
W57
Y11
Y15
Y38
Y40
Y43
Y46
Y47
Y49
Y52
Y6
AL43
AL44
R36
P36
R25
P25
051-9509
4.2.0
23 OF 113
23 OF 100
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
3V3 S0 Rails
3V3 S5 Rails
1V05 S0 Rails
1 mA S0-S5
1 mA
<1 MA
<1 MA S0-S5
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
Power Sequencing
1V8 S0 Rails
(PCH Reference for 5V Tolerance on PCI)
PCH V5REF Filter & Follower
X5R
10V
402
10%
PLACE_NEAR=U1800.BF1:2mm
1UF
100
5%
1/16W
402
MF-LF
20%
10V
0.1UF
CERM
402
PLACE_NEAR=U1800.BT25:2mm
10
1/16W
MF-LF
5%
402
5%
1/16W
402
MF-LF
0
PLACE_NEAR=U1800.AF57:2mm
0.1UF
402
X5R
16V
10%
0.1UF
402
10V
CERM
20%
PLACE_NEAR=U1800.T55:2mm
0.1UF
20%
CERM
402
10V
PLACE_NEAR=U1800.AV28:2mm
0.1UF
16V
10%
X5R
402
PLACE_NEAR=U1800.A12:2mm
PLACE_NEAR=U1800.AU20:2mm
CERM
1UF
6.3V
402
10%
PLACE_NEAR=U1800.BT35:2mm
10%
402
X5R
16V
0.1UF
PLACE_NEAR=U1800.AV30:2mm
2.2UF
603
X5R
10%
16V
PLACE_NEAR=U1800.D55:2mm
0.1UF
X5R
16V
10%
402
PLACE_NEAR=U1800.D55:2mm
4.7UF
6.3V
20%
X5R
402
PLACE_NEAR=U1800.U31:2mm
16V
0.1UF
10%
X5R
402
201
6.3V
0.1UF
10%
X5R
PLACE_NEAR=U1800.AL38:2mm
PLACE_NEAR=U1800.E41:2mm
6.3V
1UF
CERM
402
10%
10%
PLACE_NEAR=U1800.AG38:2mm
6.3V
402
CERM
1UF
PLACE_NEAR=U1800.AJ38:2mm
10%
6.3V
402
CERM
1UF
402
20%
CERM
10V
0.1UF
PLACE_NEAR=U1800.AV40:2mm
CERM
10%
1UF
402
6.3V
PLACE_NEAR=U1800.AN52:2mm
PLACE_NEAR=U1800.AJ1:2mm
CERM
6.3V
402
10%
1UF
PLACE_NEAR=U1800.R54:2mm
402
CERM
6.3V
10%
1UF
PLACE_NEAR=U1800.R56:2mm
0.1UF
10%
402
X5R
16V
0.1UF
16V
402
X5R
10%
PLACE_NEAR=U1800.BC17:2mm
0.1UF
X5R
16V
PLACE_NEAR=U1800.BC17:2mm
10%
402
6.3V
CERM
PLACE_NEAR=U1800.AC24:2mm
10%
1UF
402
PLACE_NEAR=U1800.F20:2mm
6.3V
1UF
10%
CERM
402
1UF
PLACE_NEAR=U1800.AC20:2mm
6.3V
10%
CERM
402
PLACE_NEAR=U1800.AN22:2mm
6.3V
10%
1UF
402
CERM
PLACE_NEAR=U1800.AJ24:2mm
1UF
402
10%
6.3V
CERM
10%
X5R
16V
402
1UF
PLACE_NEAR=U1800.AJ20:2mm
PLACE_NEAR=U1800.D55:2mm
0.1UF
402
10%
16V
X5R
20%
10UF
603
X5R
6.3V
PLACE_NEAR=U1800.AA34:2mm
20%
10UF
603
X5R
6.3V
PLACE_NEAR=U1800.Y20:2mm
10UF
20%
6.3V
X5R
603
PLACE_NEAR=U1800.AN24:2mm
X5R
6.3V
603
20%
10UF
PLACE_NEAR=U1800.AC2:2mm
1UF
402
10%
6.3V
CERM
PLACE_NEAR=U1800.AB1:2mm
CERM
6.3V
10%
402
1UF
PLACE_NEAR=U1800.AE15:2mm
1UF
CERM
6.3V
10%
402
22UF
20%
6.3V
CERM
805
20%
22UF
805
6.3V
CERM
0201-MUR
PLACE_NEAR=U1800.AN22:2mm
X5R
6.3V
20%
1.0UF
BAT54XV2T1
SOD-523
BAT54XV2T1
SOD-523
PCH DECOUPLING
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP1V8_S0_PCH_VCCVRM_F
MAKE_BASE=TRUE
PP5V_S0_PCH_V5REF
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
PP5V_S5_PCH_V5REFSUS
=PP3V3_S5_PCH
=PP3V3_S0_PCH
=PP5V_S0_PCH
=PP1V05_S0_PCH_VCC_ASW
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_V_PROC_IO
=PP5V_S0_PCH_V5REF
PP1V05_S0_PCH_VCCADPLLA_F
=PP3V3_S0_PCH_VCC
=PP3V3_S0_PCH_VCC_PCI
=PP1V8_S0_PCH_VCC_VRM
=PP1V8_S0_PCH_VCC_DFTERM
=PP3V3_S5_PCH_VCCSUS_USB
=PP5V_S5_PCH
=PP5V_S5_PCH_V5REFSUS
=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_PCH_VCCSUS_HDA
=PP3V3_S5_PCH_VCC_DSW
=PP3V3_S0_PCH_VCC_HVCMOS
=PP1V05_S0_PCH_VCCCLKDMI
=PP1V05_S0_PCH
PP1V05_S0_PCH_VCCADPLLB_F
=PP1V05_S0_PCH_VCC_CORE
=PP3V3_S0_PCH_VCC_GPIO
C2439
1
2
R2405
2
1
C2438
1
2
R2404
2
1
R2400
1 2
C2423
1
2
C2440
1
2
C2441
1
2
C2421
1
2
C2422
1
2
C2413
1
2
C2455
1
2
C2417
1
2
C2416
1
2
C2484
1
2
C2485
1
2
C2487
1
2
C2452
1
2
C2453
1
2
C2499
1
2
C2442
1
2
C2443
1
2
C2436
1
2
C2447
1
2
C2424
1
2
C2427
1
2
C2482
1
2
C2481
1
2
C2483
1
2
C2456
1
2
C2426
1
2
C2411
1
2
C2430
1
2
C2445
1
2
C2460
1
2
C2461
1
2
C2428
1
2
C2491
1
2
C2490
1
2
C2400
1
2
C2471
1
2
C2470
1
2
C2496
1
2
D2400
A
K
D2401
A
K
051-9509
4.2.0
24 OF 113
24 OF 100
6
19 26
6
18 21
6
6
22
6
18 22
6
22
6
22
22
17 22
6
22
6
22
6
6
22
6
22
6
22
6
22
6
22
6
22
6
22
22
6
18
17 22
6
22
6
22
BI
IN
IN
IN
IN
IN
IN
IN
NC
IN
BI
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
NC
BI
IN
OUT
IN
IN
IN
IN
OUT
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PCH Micro2-XDP
1K series resistor on csa 26 (PCH Support)
obsdata_b0
xdp_present#
obsdata_c1
obsdata_c2
obsdata_c3
obsen_d1
vcc_obs_cd
obsen_c0
obsdata_c2
obsen_d0
obsdata_c1
obsdata_a2
trstn
itpclk/hook4
obsen_a1
998-2516
998-2516
obsdata_d3
itpclk#/hook5
reset#/hook6
obsdata_c3
obsen_d1
tms
tdi
tdo
dbr#/hook7
vcc_obs_cd
obsen_c0
obsen_d0
obsdata_c0
obsen_c1
itpclk/hook4
obsdata_d3
tdo
tdi
tms
obsdata_a2
obsdata_a3
obsen_b0
vcc_obs_ab
pwrgd/hook0
scl
sda
hook3
hook1
obsdata_b2
obsen_b1
hook2
obsdata_b0
tck1
tck0
and path to non-XDP signal destination.
tck0
tck1
scl
sda
vcc_obs_ab
hook2
hook3
hook1
pwrgd/hook0
obsdata_b3
obsdata_b2
obsdata_b1
obsdata_a1
obsdata_a0
obsdata_a0
obsen_a1
obsen_a0
obsdata_b1
obsdata_b3
CPU Micro2-XDP
- USB OC#’s not isolated, avoid USB port overcurrent
obsdata_a1
PCH/XDP Signal Isolation Notes:
events while using PCH XDP.
- MXM_GOOD not isolated as only LED is affected.
- For isolated GPIOs:
be replaced with aliases. Otherwise these R’s must
- ’Output’ PCH/XDP signals require pulls.
- Unused GPIOs 0 & 15 not isolated.
reset#/hook6
obsdata_d0
obsdata_d1
obsdata_d2
obsdata_c0
obsen_c1
obsen_a0
XDP Signals
- ’Output’ non-XDP signals require pulls.
If PCH XDP not implemented, all of R2524-R2537 can
R2524-R2537 should be placed where signal path
be stuffed even in production so that PCH pins
connect to appropriate non-XDP signals on PCB.
needs to split between route from PCH to J2550
obsen_b1
obsen_b0
oc3#/gpio42
oc2#/gpio41
oc0#/gpio59
oc6#/gpio10
oc5#/gpio9
sata1gp/gpio19
sata0gp/gpio21
gpio0
sata3gp/gpio37
gpio15
gpio35
sata2gp/gpio36
sata5gp/gpio49
sata4gp/gpio16
1K series resistor on csa 26 (PCH Support)
mgpio7/gpio28
Connects to PCH XDP Conn
Pull-up to 3.3V on csa 26 (PCH Support)
xdp_present#
trstn
dbr#/hook7
itpclk#/hook5
obsdata_d2
obsdata_d1
obsdata_d0
oc7#/gpio14
oc4#/gpio43
PCH Signals
oc1#/gpio40
obsdata_a3
X5R
16V
10%
0.1UF
XDP
402
16V
X5R
XDP
10%
0.1UF
402
11
11
11 91
11 91
11 91
11 91
10 91
10 91
25 47
25 47
11 25 91
10 91
10 91
10 91
10 25 91
10 15 91
10 15 91
10 91
10 91
10 15 91
10 91
10 15 91
10 91
26
11 25 91
11 25
11 25 91
11 25 91
1/16W
SW2800.2:10MM
0
5%
MF-LF
XDP
402
19 26 44
5%
XDP
402
MF-LF
1/16W
0
R1553.1:5MM
1/16W
XDP
0
MF-LF
402
5%
R1554.1:5MM
15 18 91
15 18 91
11 91
11 91
11 91
11 91
XDP
U1000.J40:10MM
1/16W
MF-LF
402
1K
5%
402
U4900.D10:10MM
MF-LF
1/16W
XDP
0
5%
U1000.H36:10MM
XDP
1/16W
MF-LF
402
5%
1K
5%
XDP
1/16W
402
J2500.47:10MM
MF-LF
0
61 62
10 25 91
15 19 25 44
11 21
J2500.52:10MM
402
1/16W
51
MF-LF
5%
XDP
MF-LF
U1000.L40:10MM
402
1/16W
5%
51
XDP
U1000.L38:10MM
402
MF-LF
1/16W
5%
51
XDP
U1000.J39:10MM
402
MF-LF
1/16W
5%
51
XDP
U1000.M40:10MM
402
MF-LF
1/16W
5%
51
XDP
25
25
25
25
25
25
25
25
25
25
26
18 25 91
18 25 91
18 25 91
0.1UF
402
10%
16V
X5R
XDP
25
25
25
25
X5R
16V
10%
402
0.1UF
XDP
25 47
25 47
18 25 91
25
25
25
25
15 19 25 44
XDP
402
MF-LF
1/16W
5%
1K
J2550.30:10MM
6
25
402
5%
U1800.BC50:10MM
200
1/16W
MF-LF
XDP
MF-LF
5%
1/16W
402
200
U1800.BC52:10MM
XDP
51
5%
402
1/16W
MF-LF
U1800.BA43:10MM
XDP
5%
200
XDP
MF-LF
1/16W
402
J2500.52:10MM
20
20
20
20
20
20
20
20
21
21
21
18
18
21
21
21
21
M-ST-SM
XDP_CONN
DF40RC-60DP-0.4V
CRITICAL
CRITICAL
DF40RC-60DP-0.4V
XDP_CONN
M-ST-SM
402
0
5%
MF-LF
1/16W
XDP_CONN
1/16W
MF-LF
402
5%
100
U1800.BA43:10MM
XDP
5%
402
MF-LF
1/16W
100
U1800.BA43:10MM
XDP
1/16W
MF-LF
402
100
XDP
5%
J2500.52:10MM
5%
402
MF-LF
1/16W
33
5%
402
MF-LF
33
1/16W
5%
MF-LF
33
402
1/16W
MF-LF
402
1/16W
5%
33
1/16W
5%
402
MF-LF
33
5%
1/16W
402
MF-LF
33
5%
1/16W
402
MF-LF
33
5%
1/16W
MF-LF
33
402
1/16W
MF-LF
33
402
5%
5%
1/16W
33
402
MF-LF
33
402
MF-LF
1/16W
5%
33
MF-LF
4025%1/16W
1/16W
5%
33
MF-LF
402
402
MF-LF335%
1/16W
402
MF-LF
5%
33
1/16W
MF-LF
1/16W
5%
33
402
21
MF-LF
33
402
1/16W
5%
402
MF-LF
1/16W
5%
33
11 25
11 25
5%
0
XDP
1/16W
MF-LF
U4900.D10:10MM
402
CPU and PCH XDP
MAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.3V
PP3V3_S5_XDP_R
ISOLATE_CPU_MEM_R_L
XDP_PIN03
ENET_LOW_PWR_PCH_R
XDP_DA3_USB_EXTD_OC_L
JTAG_TBT_TCK_R
SATARDRVR_EN_R
USB_EXTD_OC_R_L
USB_EXTB_OC_EHCI_R_L
USB_EXTD_OC_EHCI_R_L
AP_PWR_EN_R
USB_EXTA_OC_R_L
USB_EXTB_OC_R_L
USB_EXTC_OC_R_L
XDP_PCH_PWRBTN_L
PM_PWRBTN_L
=PP3V3_S5_XDP
XDP_PCH_PWRGD
CPU_CFG<2>
CPU_CFG<7>
XDP_FC0_PCH_GPIO15
XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_PCH_TDO
XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DD3_ENET_LOW_PWR_PCH
AUD_IPHS_SWITCH_EN_PCH_R
DP_AUXCH_ISOL_R
XDP_DB2_AP_PWR_EN
CPU_CFG<5>
XDP_DBRESET_L
CPU_CFG<3>
CPU_CFG<8>
CPU_CFG<9>
XDP_CPU_CLK100M_P
ITPXDP_CLK100M_N
=PPVCCIO_S0_XDP
CPU_CFG<6>
XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TRST_L
XDP_DBRESET_L
=PP3V3_S5_XDP
XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TCK
XDP_DA1_USB_EXTB_OC_L
XDP_FC0_PCH_GPIO15
GPU_GOOD_R
DP_GPU_TBT_SEL_R
XDP_DB3_SDCONN_STATE_CHANGE
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DA0_USB_EXTA_OC_L
CPU_CFG<0>
PM_PGOOD_REG_CPUCORE_S0
XDP_DA2_USB_EXTC_OC_L
XDP_DA1_USB_EXTB_OC_L
XDP_BPM_L<5>
XDP_BPM_L<4>
SDCONN_STATE_CHANGE_R
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_CPU_PLTRST_L
XDP_CPU_CLK100M_N
XDP_DA0_USB_EXTA_OC_L
CPU_PWRGD
XDP_BPM_L<6>
XDP_BPM_L<7>
XDP_VR_READY
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
XDP_PCH_TDO
XDP_DD3_ENET_LOW_PWR_PCH
XDP_DC1_GPU_GOOD
XDP_PCH_PLTRST_L
XDP_PCH_TMS
XDP_DB1_USB_EXTD_OC_EHCI_L
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
XDP_PCH_TCK
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
CPU_CFG<1>
CPU_CFG<17>
CPU_CFG<0>
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
CPU_CFG<4>
XDP_CPU_PRDY_L
CPU_CFG<10>
CPU_CFG<11>
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
XDP_CPU_TCK
XDP_BPM_L<3>
XDP_CPU_PREQ_L
=PPVCCIO_S0_XDP
PM_PWRBTN_L
ITPXDP_CLK100M_P
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_CFG<0>
PM_SYSRST_L
CPU_CFG<16>
XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DD1_JTAG_TBT_TCK
XDP_DD0_DP_GPU_TBT_SEL
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_GPU_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_TBT_TCK
TBT_CIO_PLUG_EVENT_R
XDP_FC1_TBT_CIO_PLUG_EVENT
XDP_PCH_TDI
XDP_CPU_TMS
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
=PP3V3_S5_XDP
XDP_DC3_SATARDRVR_EN
XDP_DC2_DP_AUXCH_ISOL
XDP_DC0_ISOLATE_CPU_MEM_L
C2501
1
2
C2500
1
2
R2506
1 2
R2505
1 2
R2504
1 2
R2500
1 2
R2501
1 2
R2502
1 2
R2503
1 2
R2510
1
2
R2511
1
2
R2512
1
2
R2513
1
2
R2514
1
2
C2551
1
2
C2550
1
2
R2550
1 2
R2562
1
2
R2561
1
2
R2566
1
2
R2560
1
2
J2500
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
61
62
6364
78
9
J2550
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
61
62
6364
78
9
R2567
1 2
R2565
1
2
R2564
1
2
R2563
1
2
R2520
1 2
R2521
1 2
R2522
1 2
R2523
1 2
R2524
1 2
R2525
1 2
R2526
1 2
R2527
1 2
R2537
1 2
R2528
1 2
R2529
1 2
R2530
1 2
R2533
1 2
R2534
1 2
R2535
1 2
R2536
1 2
R2531
1 2
R2532
1 2
R2551
1 2
051-9509
4.2.0
25 OF 113
25 OF 100
18 25 91
25
25
25
91
6
25
6
25
18 25 91
18 25 91
18 25 91
25
25
25
25
25
25
91
6
25
11 25 91
11 25
11 25 91
11 25 91
11 25 91
25
25
25
25
25
25
25
25
25
6
25
OUT
NCNC
OUT
OUT
IN
OUT
IN
IN
NCNC
OUT
OUT
IN
OUT
IN
OUT
OUT
NC
OUT
OUT
OUT
OUT
NC
NC
OUT
GND
VDD
25MHZ_A
VDDIO_B
VDDIO_A
VDDIO_C
25MHZ_B
25MHZ_C
THRM
XIN
XOUT
PAD
NC
OUT
OUT
OUT
OUT
OUT
2A
VCC
GND
4Y
3Y
2Y
1Y
2B
3A
3B
4A
4B
08
1B
1A
OUT
OUT
OUT
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Platform Reset Connections
Unbuffered
MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED
PCH RTC Crystal
OPEN-DRAIN BUFFER
From GreenClk @ 1.8V
PCH 25MHZ CLOCK
VTT VOLTAGE DIVIDER AND PU ON CPU PAGE
GreenClk 25MHz Power
Coin-Cell Holder
Buffered
To PCH @ 1.1V
511-0054
VDD must be powered if any VDDIO is.
ENET > S0 > TBT, so ENET is used here.
System 25MHz Clock Generator
Reset Button
Ethernet XTAL Power
NOTE: R2800 and D2800 form the double fault protection for RTC battery.
Clock series termination
SB XTAL Power
TBT XTAL Power
RTC Power Sources
NOTE: 30 PPM crystal required
GPIO Isolation to prevent glitches on critical core well GPIOs
19 25 44
1K
5%
1/16W
MF-LF
402
402
CERM
50V
5%
12pF
PLACE_NEAR=Y2810.3:2mm
5%
50V
CERM
402
12pF
PLACE_NEAR=Y2810.1:2mm
BAT54DW-X-G
SOT-363
33
MF-LF
402
5%
1/16W
33
402
5%
MF-LF
1/16W
46
71 78
18 92
18 92
20
PLACE_NEAR=U1800.AN14:10mm
MF-LF
33
5%
1/16W
402
201
1/20W
MF
5%
33
PLACE_NEAR=U1800.AT11:10mm
20 92
46 92
44 92
20 92
18 92
PLACE_NEAR=U1800.AT14:10mm
33
402
1/16W
5%
MF-LF
20 92
20%
0.1UF
10V
CERM
402
MF-LF
5%
100K
1/16W
402
BB10201-C1403-7H
SM
4.7K
5%
402
MF-LF
1/16W
402
10M
1/16W
5%
MF-LF
MC74VHC1G08
SOT23-5-HF
0.1UF
20%
10V
CERM
402
402
5%
MF-LF
1/16W
0
25
1/16W
402
5%
1K
XDP
MF-LF
33
402
1/16W
MF-LF
5%
33
33
1/16W
5%
MF-LF
402
74LVC1G07
SC70
1/16W
MF-LF
5%
1K
402
XDP
25
39
MF-LF
402
5%
1/16W
33
402
604
1/16W
MF-LF
1%
1K
1%
MF-LF
402
1/16W
18 92
34 92
10V
20%
CERM
402
0.1UF
20%
0.1UF
402
10V
CERM
0.1UF
CERM
402
20%
10V
MF-LF
402
1/16W
5%
0
1/16W
NO STUFF
5%
MF-LF
402
1M
CERM
402
12PF
50V
5%
CERM
50V
5%
12PF
402
37 92
PLACE_NEAR=U2800.4:10mm
MF-LF
1/16W
402
5%
33
CERM
6.3V
10%
1UF
402
CRITICAL
TDFN
SLG3NB146V
SILK_PART=SYS RESET
0
5%
MF-LF
402
NOSTUFF
1/16W
44
5%
33
402
1/16W
MF-LF
33
5%
MF-LF
1/16W
402
32
11
41
MF-LF
402
5%
1/16W
33
36
CRITICAL
TSSOP-HF
74LVC08
34
56
37 39
402
0.1UF
10V
20%
CERM
402
100K
5%
MF-LF
1/16W
SM-HF
CRITICAL
32.768K-12.5PF
PLACE_NEAR=U1800.BR39:10mm
25.000MHZ-12PF-20PPM
SM-3.2X2.5MM
CRITICAL
CHIPSET SUPPORT
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
PLT_RESET_L
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PPVBATT_G3_RTC_R
VOLTAGE=3.3V
PPVBATT_G3_RTC
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mm
MAKE_BASE=TRUE
SMC_LRESET_L
MAKE_BASE=TRUE
TBT_PLT_RST_L
PM_PCH_PWROK
ENET_LOW_PWR_PCH
AUD_IPHS_SWITCH_EN_PCH
TBT_PWR_EN_PCH
PM_PCH_PWROK
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_X1
LPC_CLK33M_SMC_R
SYSCLK_CLK25M_SB
PCH_CLK32K_RTCX1
LPC_CLK33M_SMC
PCH_CLK32K_RTCX2
=PP3V3_RTC_D
PP3V3_G3H_RTC
AUD_IPHS_SWITCH_EN_PCH
TBT_PWR_EN
=PP3V3_S0_RSTBUF
LPC_CLK33M_LPCPLUS_R
=PP3V3_S5_PCH
LPC_PWRDWN_L
AUD_IPHS_SWITCH_EN
ENET_LOW_PWR
=PPVDDIO_ENET_CLK
=PP3V3_ENET_SYSCLK
PCA9557D_RESET_L
GPU_RESET_L
SYSCLK_CLK25M_TBT
CPU_RESET_L
=PPVDDIO_TBT_CLK
PM_SYSRST_L
=PP3V3_S0_PCH_PM
DEBUG_RESET_L
XDP_CPU_PLTRST_L
LPC_CLK33M_LPCPLUS
PCH_CLK33M_PCIIN
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_ENET
PCH_CLK33M_PCIOUT
=PPVDDIO_S0_SBCLK
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_X2_R
PCH_CLK25M_XTALIN
SYSCLK_CLK25M_SB
ENET_SD_RESET_L
SSD_RESET_L
=PP3V3_S0_RSTBUF
PCH_CLK32K_RTCX2_R
AP_RESET_L
=TBT_RESET_L
PLT_RST_BUF_L
XDP_PCH_PLTRST_L
R2602
2 1
C2610
1 2
C2611
1 2
D2600
1
4
6
3
R2681
1 2
R2690
1 2
R2626
1 2
R2625
1 2
R2627
1 2
C2680
1
2
R2680
1
2
J2600
2
1
R2697
1
2
R2611
1
2
U2680
3
2
1
4
5
C2690
1
2
R2610
1 2
R2699
1 2
R2688
1 2
R2655
1 2
U2690
2
3
5
4
R2698
1 2
R2692
1 2
R2671
1 2
R2672
1
2
C2620
1
2
C2622
1
2
C2624
1
2
R2605
1 2
R2606
1
2
C2605
12
C2606
1 2
R2628
1 2
C2602
1
2
U2600
5
4
8
9
11
263
7
1
10
R2696
1
2
R2691
1 2
R2694
1 2
R2693
1 2
U2650
7
13
10
4
1
12
9
5
2
11
8
6
3
14
C2650
1
2
R2650
1
2
Y2610
1 4
Y2605
2 4
1 3
051-9509
4.2.0
26 OF 113
26 OF 100
2
5
1
19 26 61
15 21
21 26
18
19 26 61
92
92
26 92
6
6
22
21 26
6
26
6
19 24
19 44 46
6
6
6
6
26 92
6
26 92
92
26 92
6
26
92
BI
BI
BI
BI
NC
BI
BI
NC
NC
NC
NC
TEST1
USBDM_DN1
USBDP_DN1
VBUS_DET
USBDP_DN2
USBDM_DN2
SUSP_IND/NON_REM0
VDD33
NC
XTALOUT
XTALIN/CLKIN
TEST
RESET*
HS_IND
NON_REM1
PLLFILT
CRFILT
VDD33
VDD33
VDD33
USBDM_UP
USBDP_UP
PRTPWR1
PRTPWR2
OCS1*
OCS2*
RBIAS
VDD33
EPAD
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
downstream ports have removable devices or not
NON_REM 0 and 1 are used to indicate whether the
NON_REM[1:0] = 00 ---> all ports removable
NON_REM[1:0] = 01 ---> port 1 is non-removable
NON_REM[1:0] = 1x ---> ports 1 and 2 are non-removable
1%
MF
402
1/16W
12K
50V
18PF
402
5%
CERM
20 93
20 93
33 93
33 93
50V
CERM
402
18PF
5%
5X3.2X1.4-SM
24.000M-60PPM-16PF
1/16W
402
MF-LF
5%
100K
MF-LF
402
1/16W
5%
10K
402
25V
X5R
10%
0.1UF
603
4.7UF
10%
6.3V
X5R-CERM
402
10%
0.1UF
X5R
25V
402
10%
0.1UF
X5R
25V
X5R
402
0.1UF
10%
25V
10%
25V
X5R
402
0.1UF
402
MF-LF
1/16W
1M
5%
NOSTUFF
5%
0
402
1/16W
MF-LF
NOSTUFF
5%
0
402
1/16W
MF-LF
MF-LF
10K
402
1/16W
5%
402
X5R
10%
16V
0.1UF
44 93
44 93
QFN
USB2412-DZK
MF-LF
1/16W
5%
0
402
0.1UF
10%
X5R
402
16V
10%
16V
X5R
402
0.1UF
100K
5%
MF-LF
402
1/16W
1/16W
402
MF-LF
5%
100K
402
X5R
25V
0.1UF
10%
USB HUB
SYNC_DATE=12/13/2011
SYNC_MASTER=D7_NICK
MAX_NECK_LENGTH=3MM
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PPUSB_HUB_VDD1V2
MIN_LINE_WIDTH=0.4MM
MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PPUSB_HUB_VDD1V2PLL
USB_HUB_VBUS_DET
USB_HUB_2_N
USB_PCH_7_P
USB_PCH_7_N
=PP3V3_S4_USB_HUB
USB_SMC_P
USB_BT_N
USB_BT_P
USB_HUB_RBIAS
USB_SMC_N
USB_HUB_2_P
USB_HUB_XTAL_R
=PP3V3_S4_USB_HUB
USB_HUB_HS_IND
USB_HUB_XTAL2
USB_HUB_XTAL1
USB_HUB_RESET_L
USB_HUB_NON_REM1
=PP3V3_S4_USB_HUB
USB_HUB_NON_REM0
Y2700
1 2
C2707
1
2
R2707
1
2
C2701
1
2
C2702
1
2
R2708
1
2
R2703
1
2
C2706
1
2
C2705
1
2
C2711
1
2
C2710
1
2
C2709
1
2
C2708
1
2
R2706
1 2
R2711
1
2
R2710
1
2
R2712
1
2
C2712
1
2
U2700
9
29
16
13
8
12
25
7
11
26
17
19
6
15
28
2
21
1
3
22
18
410142027
24
23
R2709
1 2
C2703
1
2
C2704
1
2
R2705
1
2
R2704
1
2
051-9509
4.2.0
27 OF 113
27 OF 100
5
93
6
27
93
93
6
27
93
93
6
27
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
D
SG
D
S G
D
SG
D
SG
D
SG
D
SG
NC
NC
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
Ensures CKE signals are held low in S3
2 0 0 1 1 1 0
MEMVTT_EN = PM_PGOOD_FET_VDDQ_S0 * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN
0 1 1 1 1 CPU_MEM_RESET_L 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
75mA max load @ 0.75V
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
S0
S3
to
S0
60mW max power
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
6 0 1 1 1 1 1
7 1 1 1 1 CPU_MEM_RESET_L 1
to
1 0 1 1 1 1 1
3 0 0 0 X 1 0
4 0 0 1 X 1 0
5 0 1 1 0 (*) 1 1
must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
MEMVTT Clamp
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
1V5 S0 "PGOOD" for CPU
21 32
MF-LF
5%
1/16W
402
10K
28 60
402
MF-LF
100K
5%
1/16W
29 30 88
5%
402
MF-LF
20K
1/16W
28 60
1/16W
5%
402
MF-LF
100K
50V
20%
402
CERM
0.001UF
NO STUFF
5%
603
10
1/10W
MF-LF
11
11 19
402
X5R
16V
10%
0.1UF
6
28
MF-LF
402
5%
10K
1/16W
15 19 28 38 44 45 60
28 60 70
SOT563
SSM6N15AFE
CRITICAL
SOT563
SSM6N15AFE
CRITICAL
SOT563
CRITICAL
SSM6N15AFE
SOT563
SSM6N15AFE
CRITICAL
SOT563
SSM6N15AFE
CRITICAL
CRITICAL
SSM6N15AFE
SOT563
SC70
74LVC1G07
402
0.01UF
16V
CERM
20%
28 60 70
CPU Memory S3 Support
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
VTTCLAMP_L
MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.25mm
MAKE_BASE=TRUE
CPU_MEM_RESET_L
PM_MEM_PWRGD
PM_PGOOD_FET_VDDQ_S0
=PP3V3_S4_PM
=PP3V3_S4_MEMRESET
PM_SLP_S3_L
=PP3V3_S4_MEMRESET
=PPVDDQ_S3_MEMRESET
=PP5V_S4_MEMRESET
ISOLATE_CPU_MEM_L
MEMRESET_ISOL_LS5V_L
MEMVTT_EN
VTTCLAMP_EN
MEMVTT_EN
=PPDDRVTT_S0_CLAMP
PM_PGOOD_FET_VDDQ_S0
PM_SLP_S3_L
MEMVTT_EN_L
MEM_RESET_L
R2802
1
2
R2815
1
2
R2816
1
2
R2851
1
2
C2851
1
2
R2850
1
2
C2816
1
2
R2810
1
2
Q2810
3
5
4
Q2815
6
2
1
Q2815
3
5
4
Q2850
6
2
1
Q2850
3
5
4
Q2810
6
2
1
U2820
2
3
5
4
C2821
1
2
051-9509
4.2.0
28 OF 113
28 OF 100
1
6
6
28
6
6
15 19 28 38 44 45 60
BI
BIBI
BI
IN
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
A13
VDD_14
VDD_12
BA0
A10_AP
A3
DQ54
DQ55
VSS_44
VSS_0
VSS_2
VSS_5
DQS0
DQ5
DQ4
DQ6
DQ7
VREFDQ
VSS_1
VSS_3
DQ0
DQ1
DM0
VSS_4
VSS_7
DQ12
DQ20
VSS_13
DQ15
DQ14
VSS_11
VSS_9
DQ13
DM1
DQ21
VSS_15
DQ22
VSS_16
VSS_18
DQ23
DQ28
VSS_20
DQ29
DM2
VSS_23
DQS3
DQ30
VSS_25
VDD_1
CKE1
A15
A14
VDD_3
VDD_9
VDD_5
VDD_7
A7
A11
A4
A6
A2
A0
CK1
NC_1
ODT1
VDD_15
ODT0
VDD_13
VDD_11
BA1
DQ39
DQ38
VSS_30
VSS_29
DQ37
DQ36
VSS_27
VREFCA
VDD_17
DM4
VSS_32
DQ47
DQ44
DQ46
VSS_37
DQS5
VSS_39
VSS_34
DQ45
DQ52
VSS_46
DQ61
DQ60
VSS_42
VSS_41
DQ53
DM6
DQS7
VSS_51
DQ63
DQ62
VSS_49
SDA
SCL
DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1
VSS_10
DQ16
VSS_12
DQ11
DQ10
DQ17
DQ18
DQS2
VSS_17
VSS_14
VSS_21
DQ24
DQ25
DQ19
VSS_19
VSS_24
DQ27
DQ26
DM3
VSS_22
CKE0
A5
VDD_4
CK0
VDD_8
A1
VDD_6
VDD_10
DQ33
VSS_26
VDD_16
TEST
DQ32
DQ34
VSS_31
DQS4
VSS_28
DQ35
DQ41
VSS_33
VSS_35
DQ40
DM5
VSS_38
DQ43
DQ42
VSS_36
DQ48
VSS_43
DQS6
VSS_40
DQ49
DQ51
DQ50
VSS_45
DQ56
DQ57
VSS_47
DM7
DQ58
VSS_48
DQ59
SA0
SA1
VDDSPD
VSS_50
A8
A9
A12/BC*
VDD_2
BA2
NC_0
VDD_0
DQ31
DQS0*
DQS1*
RESET*
DQS2*
DQS3*
CK0* CK1*
RAS*
WE* S0*
CAS*
S1*
DQS4*
DQS5*
DQS6*
DQS7*
EVENT*
VTT_0 VTT_1
MTG_PINMTG_PIN
KEY
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
31
31
10V
20%
402
CERM
0.1UF
6.3V
20%
402-LF
CERM
2.2UF
31
31
12 88
31
31
31
31
31
31
31
28 30 88
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
31
31
31
31
31
31
12 88
31
31
31
31
31
31
31
31
31
10V
20%
402
CERM
0.1UF
6.3V
20%
402-LF
CERM
2.2UF
31
31
31
31
31
31
31
31
31
31
31
30 44 45
47
47
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
10K
MF-LF
402
5%
1/16W
10K
MF-LF
402
5%
1/16W
2.2UF
CERM
402-LF
20%
6.3V
10UF
X5R
603
20%
6.3V
603
X5R
6.3V
10UF
20%
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
CERM
402
20%
10V
0.1UF 0.1UF
CERM
402
20%
10V
0.1UF
20%
10V
402
CERM
20%
0.1UF
CERM
402
10V
CERM
10V
0.1UF
402
20%
CERM
402
10V
20%
0.1UF
402
CERM
0.1UF
20%
10V
0.1UF
CERM
402
20%
10V
10V
20%
402
CERM
0.1UF
1UF
X5R
402
10%
10V
1UF
X5R
402
10%
10V
1UF
X5R
402
10%
10V
1UF
X5R
402
10%
10V
F-RT-SM
2013311
402
CERM
10V
20%
0.1UF
0.1UF
CERM
402
20%
10V
SYNC_MASTER=K70_MLB
SYNC_DATE=11/30/2011
DDR3 SO-DIMM Connector A
=PPVDDQ_S3_MEM_A
=MEM_A_DQS_P<0>
MEM_A_A<13>
MEM_A_BA<0>
MEM_A_A<10>
MEM_A_A<3>
=MEM_A_DQ<54>
=MEM_A_DQ<55>
=MEM_A_DQ<5>
=MEM_A_DQ<4>
=MEM_A_DQ<6>
=MEM_A_DQ<7>
=PPDDRVREF_DQ_MEM_A
=MEM_A_DQ<0>
=MEM_A_DQ<1>
=MEM_A_DQ<12>
=MEM_A_DQ<20>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<21>
=MEM_A_DQ<22>
=MEM_A_DQ<23>
=MEM_A_DQ<28>
=MEM_A_DQ<29>
=MEM_A_DQS_P<3>
=MEM_A_DQ<30>
MEM_A_CKE<1>
MEM_A_A<15>
MEM_A_A<14>
MEM_A_A<7>
MEM_A_A<11>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<2>
MEM_A_A<0>
MEM_A_CLK_P<1>
MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_BA<1>
=MEM_A_DQ<39>
=MEM_A_DQ<38>
=MEM_A_DQ<37>
=MEM_A_DQ<36>
=PPDDRVREF_CA_MEM_A
=MEM_A_DQ<47>
=MEM_A_DQ<44>
=MEM_A_DQ<46>
=MEM_A_DQS_P<5>
=MEM_A_DQ<45>
=MEM_A_DQ<52>
=MEM_A_DQ<61>
=MEM_A_DQ<60>
=MEM_A_DQ<53>
=MEM_A_DQS_P<7>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
=MEM_A_DQ<2>
=MEM_A_DQ<3>
=MEM_A_DQ<8>
=MEM_A_DQ<9>
=MEM_A_DQS_P<1>
=MEM_A_DQ<16>
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<17>
=MEM_A_DQ<18>
=MEM_A_DQS_P<2>
=MEM_A_DQ<24>
=MEM_A_DQ<25>
=MEM_A_DQ<19>
=MEM_A_DQ<27>
=MEM_A_DQ<26>
MEM_A_CKE<0>
MEM_A_A<5>
MEM_A_CLK_P<0>
MEM_A_A<1>
=MEM_A_DQ<33>
=MEM_A_DQ<32>
=MEM_A_DQ<34>
=MEM_A_DQS_P<4>
=MEM_A_DQ<35>
=MEM_A_DQ<41>
=MEM_A_DQ<40>
=MEM_A_DQ<43>
=MEM_A_DQ<42>
=MEM_A_DQ<48>
=MEM_A_DQS_P<6>
=MEM_A_DQ<49>
=MEM_A_DQ<51>
=MEM_A_DQ<50>
=MEM_A_DQ<56>
=MEM_A_DQ<57>
=MEM_A_DQ<58>
=MEM_A_DQ<59>
MEM_A_SA<0>
MEM_A_SA<1>
=PPSPD_S0_MEM_A
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BA<2>
=MEM_A_DQ<31>
=MEM_A_DQS_N<0>
=MEM_A_DQS_N<1>
MEM_RESET_L
=MEM_A_DQS_N<2>
=MEM_A_DQS_N<3>
MEM_A_CLK_N<0> MEM_A_CLK_N<1>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_CS_L<0>
MEM_A_CAS_L
MEM_A_CS_L<1>
=MEM_A_DQS_N<4>
=MEM_A_DQS_N<5>
=MEM_A_DQS_N<6>
=MEM_A_DQS_N<7>
MEM_EVENT_L
=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_A
=PPSPD_S0_MEM_A
MEM_A_SA<0>
MEM_A_SA<1>
=PPVDDQ_S3_MEM_A
C2931
1
2
C2930
1
2
C2936
1
2
C2935
1
2
R2941
1
2
R2940
1
2
C2940
1
2
C2900
1
2
C2901
1
2
C2910
1
2
C2911
1
2
C2912
1
2
C2913
1
2
C2914
1
2
C2915
1
2
C2916
1
2
C2917
1
2
C2918
1
2
C2919
1
2
C2920
1
2
C2921
1
2
C2922
1
2
C2923
1
2
C2953
1
2
C2952
1
2
C2951
1
2
C2950
1
2
J2900
9897
107
8483
119
80
78
9695
9291
90
86
89
85
109
108
79
115
101
103
102
104
73 74
11
28
46
63
136
153
170
187
5
7
33
35
22
24
34
36
39
41
51
53
15
40
42
50
52
57
59
67
69
56
58
17
68
70
129
131
141
143
130
132
140
142
4
147
149
157
159
146
148
158
160
163
165
6
175
177
164
166
174
176
181
183
191
193
16
180
182
192
194
18
21
23
12
10
29
27
47
45
64
62
137
135
154
152
171
169
188
186
198
205 206
77
122
116
120
110
30
114
121
197
201 202
200
125
75 76
105 106
111 112
117 118
123 124
81 82
87 88
93 94
99 100
199
126
1 2
3
31 32
37 38
43 44
48
49
54
55
8
60
61
65 66
71 72
127 128
133 134
9
138
139
144
145
150
151
155 156
161 162
13
167 168
172
173
178
179
184
185
189 190
14
195 196
19 20
25 26
203 204
113
C2902
1
2
C2924
1
2
051-9509
4.2.0
29 OF 113
29 OF 100
6
29
6
6
29
29
6
29
6
29
6
29
6
29
29
29
6
29
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NC
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
A13
VDD_14
VDD_12
BA0
A10_AP
A3
DQ54
DQ55
VSS_44
VSS_0
VSS_2
VSS_5
DQS0
DQ5
DQ4
DQ6
DQ7
VREFDQ
VSS_1
VSS_3
DQ0
DQ1
DM0
VSS_4
VSS_7
DQ12
DQ20
VSS_13
DQ15
DQ14
VSS_11
VSS_9
DQ13
DM1
DQ21
VSS_15
DQ22
VSS_16
VSS_18
DQ23
DQ28
VSS_20
DQ29
DM2
VSS_23
DQS3
DQ30
VSS_25
VDD_1
CKE1
A15
A14
VDD_3
VDD_9
VDD_5
VDD_7
A7
A11
A4
A6
A2
A0
CK1
NC_1
ODT1
VDD_15
ODT0
VDD_13
VDD_11
BA1
DQ39
DQ38
VSS_30
VSS_29
DQ37
DQ36
VSS_27
VREFCA
VDD_17
DM4
VSS_32
DQ47
DQ44
DQ46
VSS_37
DQS5
VSS_39
VSS_34
DQ45
DQ52
VSS_46
DQ61
DQ60
VSS_42
VSS_41
DQ53
DM6
DQS7
VSS_51
DQ63
DQ62
VSS_49
SDA
SCL
DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8
DQS1
VSS_10
DQ16
VSS_12
DQ11
DQ10
DQ17
DQ18
DQS2
VSS_17
VSS_14
VSS_21
DQ24
DQ25
DQ19
VSS_19
VSS_24
DQ27
DQ26
DM3
VSS_22
CKE0
A5
VDD_4
CK0
VDD_8
A1
VDD_6
VDD_10
DQ33
VSS_26
VDD_16
TEST
DQ32
DQ34
VSS_31
DQS4
VSS_28
DQ35
DQ41
VSS_33
VSS_35
DQ40
DM5
VSS_38
DQ43
DQ42
VSS_36
DQ48
VSS_43
DQS6
VSS_40
DQ49
DQ51
DQ50
VSS_45
DQ56
DQ57
VSS_47
DM7
DQ58
VSS_48
DQ59
SA0
SA1
VDDSPD
VSS_50
A8
A9
A12/BC*
VDD_2
BA2
NC_0
VDD_0
DQ31
DQS0*
DQS1*
RESET*
DQS2*
DQS3*
CK0* CK1*
RAS*
WE* S0*
CAS*
S1*
DQS4*
DQS5*
DQS6*
DQS7*
EVENT*
VTT_0 VTT_1
MTG_PINMTG_PIN
KEY
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
1UF
X5R
402
10%
10V
47
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
12 88
31
31
31
31
31
31
31
CERM
402
20%
10V
0.1UF
12 88
31
31
31
31
31
31
31
6.3V
20%
402-LF
2.2UF
CERM
31
12 88
31
31
31
31
31
12 88
12 88
12 88
12 88
12 88
0.1UF
CERM
402
20%
10V
12 88
12 88
12 88
12 88
12 88
12 88
10V
20%
402
CERM
0.1UF
0.1UF
10V
20%
402
CERM
12 88
0.1UF
10V
20%
402
CERM
10V
20%
402
CERM
0.1UF
10V
20%
402
CERM
0.1UF
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
0.1UF
CERM
402
20%
10V
20%
CERM
10V
0.1UF
402
0.1UF
10V
20%
402
CERMCERM
10V
20%
402
0.1UF
31
0.1UF
CERM
402
20%
10V
10UF
X5R
603
20%
6.3V
10UF
X5R
603
20%
6.3V
F-RT-SM
2013290
10V
20%
402
CERM
0.1UF
402
10V
20%
CERM
0.1UF
31
31
31
31
31
31
31
31
31
31
10V
20%
402
CERM
0.1UF
31
31
31
31
31
31
31
31
31
6.3V
20%
402-LF
CERM
2.2UF
29 44 45
12 88
12 88
12 88
12 88
12 88
12 88
31
31
31
31
31
31
31
31
31
31
1UF
X5R
402
10%
10V
31
31
31
31
31
31
31
31
31
1UF
X5R
402
10%
10V
31
1/16W
5%
402
MF-LF
10K
1/16W
5%
402
MF-LF
10K
6.3V
20%
402-LF
CERM
2.2UF
31
31
31
31
1UF
X5R
402
10%
10V
31
31
31
31
31
28 29 88
31
31
47
31
31
31
31
31
31
31
31
31
12 88
DDR3 SO-DIMM CONNECTOR B
SYNC_DATE=11/30/2011SYNC_MASTER=K70_MLB
MEM_B_SA<0>
MEM_B_SA<1>
=PPSPD_S0_MEM_B
=PPSPD_S0_MEM_B
=PPDDRVTT_S0_MEM_B=PPDDRVTT_S0_MEM_B
MEM_EVENT_L
=MEM_B_DQS_N<7>
=MEM_B_DQS_N<6>
=MEM_B_DQS_N<5>
=MEM_B_DQS_N<4>
MEM_B_CS_L<1>
MEM_B_CAS_L
MEM_B_CS_L<0>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_CLK_N<1>MEM_B_CLK_N<0>
=MEM_B_DQS_N<3>
=MEM_B_DQS_N<2>
MEM_RESET_L
=MEM_B_DQS_N<1>
=MEM_B_DQS_N<0>
=MEM_B_DQ<31>
MEM_B_BA<2>
MEM_B_A<12>
MEM_B_A<9>
MEM_B_A<8>
=PPSPD_S0_MEM_B
MEM_B_SA<1>
MEM_B_SA<0>
=MEM_B_DQ<59>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<56>
=MEM_B_DQ<50>
=MEM_B_DQ<51>
=MEM_B_DQ<49>
=MEM_B_DQS_P<6>
=MEM_B_DQ<48>
=MEM_B_DQ<42>
=MEM_B_DQ<43>
=MEM_B_DQ<40>
=MEM_B_DQ<41>
=MEM_B_DQ<35>
=MEM_B_DQS_P<4>
=MEM_B_DQ<34>
=MEM_B_DQ<32>
=MEM_B_DQ<33>
MEM_B_A<1>
MEM_B_CLK_P<0>
MEM_B_A<5>
MEM_B_CKE<0>
=MEM_B_DQ<26>
=MEM_B_DQ<27>
=MEM_B_DQ<19>
=MEM_B_DQ<25>
=MEM_B_DQ<24>
=MEM_B_DQS_P<2>
=MEM_B_DQ<18>
=MEM_B_DQ<17>
=MEM_B_DQ<10>
=MEM_B_DQ<11>
=MEM_B_DQ<16>
=MEM_B_DQS_P<1>
=MEM_B_DQ<9>
=MEM_B_DQ<8>
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
=MEM_B_DQ<62>
=MEM_B_DQ<63>
=MEM_B_DQS_P<7>
=MEM_B_DQ<53>
=MEM_B_DQ<60>
=MEM_B_DQ<61>
=MEM_B_DQ<52>
=MEM_B_DQ<45>
=MEM_B_DQS_P<5>
=MEM_B_DQ<46>
=MEM_B_DQ<44>
=MEM_B_DQ<47>
=PPDDRVREF_CA_MEM_B
=MEM_B_DQ<36>
=MEM_B_DQ<37>
=MEM_B_DQ<38>
=MEM_B_DQ<39>
MEM_B_BA<1>
MEM_B_ODT<0>
MEM_B_ODT<1>
MEM_B_CLK_P<1>
MEM_B_A<0>
MEM_B_A<2>
MEM_B_A<6>
MEM_B_A<4>
MEM_B_A<11>
MEM_B_A<7>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_CKE<1>
=MEM_B_DQ<30>
=MEM_B_DQS_P<3>
=MEM_B_DQ<29>
=MEM_B_DQ<28>
=MEM_B_DQ<23>
=MEM_B_DQ<22>
=MEM_B_DQ<21>
=MEM_B_DQ<13>
=MEM_B_DQ<14>
=MEM_B_DQ<15>
=MEM_B_DQ<20>
=MEM_B_DQ<12>
=MEM_B_DQ<1>
=MEM_B_DQ<0>
=PPDDRVREF_DQ_MEM_B
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<4>
=MEM_B_DQ<5>
=MEM_B_DQS_P<0>
=MEM_B_DQ<55>
=MEM_B_DQ<54>
MEM_B_A<3>
MEM_B_A<10>
MEM_B_BA<0>
MEM_B_A<13>
=PPVDDQ_S3_MEM_B=PPVDDQ_S3_MEM_B
C3153
1
2
C3136
1
2
C3135
1
2
C3152
1
2
C3151
1
2
C3150
1
2
R3141
1
2
R3140
1
2
C3140
1
2
C3131
1
2
C3130
1
2
C3117
1
2
C3123
1
2
C3116
1
2
C3115
1
2
C3114
1
2
C3113
1
2
C3122
1
2
C3121
1
2
C3120
1
2
C3119
1
2
C3112
1
2
C3111
1
2
C3110
1
2
C3118
1
2
C3101
1
2
C3100
1
2
J3100
9897
107
8483
119
80
78
9695
9291
90
86
89
85
109
108
79
115
101
103
102
104
73 74
11
28
46
63
136
153
170
187
5
7
33
35
22
24
34
36
39
41
51
53
15
40
42
50
52
57
59
67
69
56
58
17
68
70
129
131
141
143
130
132
140
142
4
147
149
157
159
146
148
158
160
163
165
6
175
177
164
166
174
176
181
183
191
193
16
180
182
192
194
18
21
23
12
10
29
27
47
45
64
62
137
135
154
152
171
169
188
186
198
205 206
77
122
116
120
110
30
114
121
197
201 202
200
125
75 76
105 106
111 112
117 118
123 124
81 82
87 88
93 94
99
100
199
126
1 2
3
31 32
37 38
43 44
48
49
54
55
8
60
61
65 66
71 72
127 128
133 134
9
138
139
144
145
150
151
155 156
161 162
13
167 168
172
173
178
179
184
185
189 190
14
195 196
19 20
25 26
203 204
113
C3124
1
2
C3102
1
2
051-9509
4.2.0
31 OF 113
30 OF 100
30
30
6
30
6
30
6
30
6
30
6
30
30
30
6
6
6
30
6
30
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