Apple iMac 21.5 A1418 Schematics

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK
APPD

2 1

1245678

B

D

6 5 4 3

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

D

SIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVED

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

TABLE_TABLEOFCONTENTS_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_TABLEOFCONTENTS_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

DRAWING

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

D7 MLB

Schematic / PCB #’s

1 OF 100

2012-01-12

1 OF 113

4.2.0

051-9509

LAST_MODIFIED=Thu Jan 12 10:24:09 2012

LAST_MODIFIED=Thu Jan 12 10:24:09 2012

SCH,D7,MLB

49

11/30/2011

K70_MLB

54

I and V Sense(Development)

Contents

Page Sync

Date

(.csa)

CRITICAL

SCH

1

051-9509 SCH,MLB,D7

CRITICAL

PCB

1

820-3302

PCBF,MLB,D7

ABBREV=DRAWING

TITLE=D7

1

K70_MLB

11/30/2011

1

Table of Contents

(.csa)

Date

SyncPage

Contents

50

12/13/2011

D7_DOUG

55

Temperature Sensors

51

11/30/2011

K70_MLB

56

System Fan

52

01/03/2012

D7_BREECE

61

AUDIO: CODEC/REGULATORS

53

01/03/2012

D7_BREECE

62

AUDIO: HEADPHONE AMP

54

01/03/2012

D7_BREECE

63

AUDIO: LEFT SPKR AMP

55

01/03/2012

D7_BREECE

64

AUDIO: RIGHT SPKR AMP

56

01/03/2012

D7_BREECE

65

AUDIO: Jack, Mikey, CHS Switch

57

01/03/2012

D7_BREECE

66

Audio: Spkr/Mic Conn.

58

01/03/2012

D7_BREECE

67

AUDIO: Detects/Grounding

59

01/03/2012

D7_BREECE

68

AUDIO: Speaker ID

60

12/13/2011

D7_NICK

69

PM Regulator Enables

61

12/13/2011

D7_NICK

70

PM Power Good

62

01/04/2012

D7_NICK

71

VReg CPU Core/AXG Cntl

63

01/04/2012

D7_NICK

72

VReg CPU Core Phases

64

01/04/2012

D7_NICK

73

VReg CPU AXG Phases

65

01/04/2012

D7_NICK

74

VReg CPU/PCH 1.05V S0

66

01/04/2012

D7_NICK

75

VReg CPU VccSA S0

67

01/04/2012

D7_NICK

76

VReg 3.3V S5/5V S4

68

01/04/2012

D7_NICK

77

VReg VDDQ and 1.8V S0

69

01/04/2012

D7_NICK

78

VReg G3Hot

70

01/04/2012

D7_NICK

79

FET-Controlled S0 and S4

71

01/10/2012

D7_TONY

80

KEPLER PCI-E

72

01/10/2012

D7_TONY

81

KEPLER CORE/FB POWER

73

01/10/2012

D7_TONY

82

KEPLER FRAME BUFFER I/F

74

01/03/2012

D7_NICK

83

1V05 GPU POWER SUPPLY

75

12/13/2011

D7_TONY

84

GDDR5 Frame Buffer A

76

12/13/2011

D7_TONY

85

GDDR5 Frame Buffer B

77

12/13/2011

D7_TONY

86

KEPLER EDP/DP/GPIO

78

01/10/2012

D7_TONY

87

KEPLER GPIOS,CLK & STRAPS

79

01/10/2012

D7_TONY

88

KEPLER PEX PWR/GNDS

80

01/03/2012

D7_NICK

89

VReg GPU Core

81

11/30/2011

K70_MLB

91

Internal DP Support

82

12/14/2011

D7_NICK

92

Internal DP MUXing

83

12/15/2011

D7_DOUG

93

TBT DDC Crossbar

84

12/15/2011

D7_DOUG

94

Thunderbolt Connector A

85

12/15/2011

D7_DOUG

96

Thunderbolt Connector B

86

01/03/2012

D7_NICK

97

LCD Backlight Driver (LP8545)

87

12/12/2011

D7_DAVE

100

K70 Rule Definitions

88

12/12/2011

D7_DAVE

101

DDR3 Constraints

89

12/12/2011

D7_DAVE

102

CPU PCIe Constraints

90

12/12/2011

D7_DAVE

103

PCH PCIe/DMI Constaints

91

12/12/2011

D7_DAVE

104

SATA/FDI/XDP Constraints

92

12/12/2011

D7_DAVE

105

PCH and BR Constraints

93

12/12/2011

D7_DAVE

106

USB/Ethernet/SD Constraints

94

01/03/2012

D7_DOUG

107

SMBus/Sensor Constraints

95

12/12/2011

D7_DAVE

108

VReg Constraints

96

12/12/2011

D7_DAVE

109

CPU VReg Constraints

97

12/12/2011

D7_DAVE

110

Platform VReg Constraints

98

12/13/2011

D7_NICK

111

TBT/DP Constraints

99

12/12/2011

D7_DAVE

112

GDDR5/GPU Constraints

100

12/12/2011

D7_DAVE

113

BLC Constraints

2

K70_MLB

11/30/2011

2

System Block Diagram

3

D7_NICK

01/03/2012

3

Power Block Diagram

4

D7_NICK

12/13/2011

4

BOM Configuration

5

K70_MLB

11/30/2011

5

DEBUG LEDS

6

D7_NICK

01/11/2012

6

Power Connectors/Aliases

7

K70_MLB

11/30/2011

7

Holes/PD parts

8

K70_MLB

11/30/2011

8

Unused Signal Aliases

9

K70_MLB

11/30/2011

9

Signal Aliases

10

K70_MLB

11/30/2011

10

CPU DMI/PEG/FDI/RSVD

11

K70_MLB

11/30/2011

11

CPU CLOCK/MISC/JTAG

12

K70_MLB

11/30/2011

12

CPU DDR3 INTERFACES

13

K70_MLB

11/30/2011

13

CPU POWER

14

K70_MLB

11/30/2011

14

CPU GROUNDS

15

D7_TONY

01/11/2012

15

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

16

K70_MLB

11/30/2011

16

CPU NON-GFX DECOUPLING

17

K70_MLB

11/30/2011

17

GFX DECOUPLING & PCH PWR ALIAS

18

K70_MLB

11/30/2011

18

PCH SATA/PCIE/CLK/LPC/SPI

19

K70_MLB

11/30/2011

19

PCH DMI/FDI/GRAPHICS

20

K70_MLB

11/30/2011

20

PCH PCI/USB

21

D7_TONY

01/11/2012

21 PCH MISC

22

K70_MLB

11/30/2011

22

PCH POWER

23

K70_MLB

11/30/2011

23

PCH GROUNDS

24

K70_MLB

11/30/2011

24

PCH DECOUPLING

25

K70_MLB

11/30/2011

25

CPU and PCH XDP

26

K70_MLB

11/30/2011

26

CHIPSET SUPPORT

27

D7_NICK

12/13/2011

27 USB HUB

28

K70_MLB

11/30/2011

28

CPU Memory S3 Support

29

K70_MLB

11/30/2011

29

DDR3 SO-DIMM Connector A

31

K70_MLB

11/30/2011

30

DDR3 SO-DIMM CONNECTOR B

33

K70_MLB

11/30/2011

31

DDR3 ALIASES AND BITSWAPS

34

K70_MLB

11/30/2011

32

DDR3/FRAMEBUF VREF MARGINING

35

D7_NICK

12/13/2011

33

AIRPORT/BT

36

D7_DOUG

01/11/2012

34

Thunderbolt Host (1 of 2)

37

D7_DOUG

01/11/2012

35

Thunderbolt Host (2 of 2)

38

D7_DOUG

01/11/2012

36

Thunderbolt Power Support

39

D7_NICK

01/12/2012

37

ETHERNET PHY (CAESAR IV)

40

D7_NICK

01/12/2012

38

Ethernet Support & Connector

41

D7_NICK

01/12/2012

39

SD READER CONNECTOR

42

D7_TONY

01/11/2012

40

Camera Controller

45

D7_NICK

12/16/2011

41

SATA Connectors

46

D7_NICK

01/04/2012

42

EXTERNAL USB PORTS A & B

47

D7_NICK

01/04/2012

43

EXTERNAL USB PORTS C & D

49

D7_DOUG

01/11/2012

44 SMC

50

D7_DOUG

01/11/2012

45

SMC Support

51

D7_NICK

12/13/2011

46

SPI and Debug Connector

52

D7_DOUG

01/03/2012

47

SMBus Connections

53

D7_DOUG

01/06/2012

48

I and V Sense(Production)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram

System Block diagram can be found on Kismet

SYNC_DATE=11/30/2011

SYNC_MASTER=K70_MLB

System Block Diagram

051-9509

4.2.0

2 OF 113
2 OF 100

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AC/DC

Supply Module

12V

G3HReg

PP3V42_G3H

G3HRegG3H

Vin
en

Regulator

U7800

3.3V

S5

LDO5VS5

U7600

Regulator

Vin
en

PP5V_S5_LDO

S5

SMC, RTC, BT

Audio, LCD, PCH, Camera, GPU

Thunderbolt

SD Card

PP3V3_S0

Reg

PP3V3_S0_SSD

AirPort

PP3V3_TBTLC

PP3V3_S4_AP_FET

Ethernet

PP3V3_ENET

PP3V3_S5

USB ports

SO-DIMMs

PP5V_S4

5V

Reg S4

Reg S3

VDDQ

VTT

VTT

LDO S3

S0LDO

Regulator

en

S4

en

S3

Vin

U7700

en

S0

Loads

I

PPHDD_S0

PP5V_S0

I

SO-DIMMs

PPVDDQ_S3_DDR

PP1V5_S0

S0-DIMMs

PPDDRVTT_S0

PPDDRVTT_S3

PPVDDQ_S3

Thunderbolt

PP12V_S0_FET

CPU

CPU

CPU, PCH

PPVCCSA_S0_REG

S0Reg

Reg S0

AXG

Reg

Reg S0

VccIO

S0S0

S0

Regulator

S0

Regulator

Regulator

U7100

Vin
en

Vin
en

U7500

en

Vin

Internal display

Loads

Fan

PP12V_G3H

I

PP12V_ACDC

PP12V_S5

PPCPUCORE_S0

PPCPUAXG_S0

Core

U7400

PP1V05_S0_REG

VccSA

Speaker amps

GPU

S0

Regulator

U8900

Vin

CPU PLL, GPU PLL

PP1V8_S0_REG

S0Reg

1.8V

S0

Regulator

PP5V_S0_FET

U7750

Vin
en

Thunderbolt

CPU

PP1V05_TBTCIO

PP1V05_TBTLC

Thunderbolt

Audio, CPU

Audio, PCH, Camera

PP3V3_S0_SW_SD_PWR

Bootrom, PCH

SMC AVref

I

PPSSD_S0

SSD

I

I

PP12V_S0_GPUUNCORE

Core

RegS0

en

HDD

PP12V_S0_GPUCORE

PP12V_S0_GPUCORE

PP12V_S0_GPUUNCORE

PPVCORE_S0_GPU

en

Regulator

Reg S0

GPU

PP1V05_S0_GPU

S0Reg

Regulator

S0

en

Vin

Vin

S0

GPU FB

U8350

U8300

IOVDD

GPUVDDQ

PPVDDQ_S0_GPU

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_NICK

Power Block Diagram

051-9509

4.2.0

3 OF 113
3 OF 100

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM Groups

Programmable Parts

Alternate: 335S0854

GPU Module Parts

VRAM Alternates

Alternate: 335S0812

Alternates

CPUs

Programmable Parts (unused)

CPU Socket Alternates

VRAM Module Parts

VRAM BOM Variants

CPU Socket

Add ’K70_PRODUCTION’ at RevA release

Replace with 65W part

Main BOM Variants

Module Parts

Bar Code Labels / EEEE #’s

BOM Configuration

SYNC_DATE=12/13/2011

SYNC_MASTER=D7_NICK

PCBA,MLB,DEV,D7

085-4441

PCBA,MLB,D7,GSA,GOOD

639-3566

PCBA,MLB,D7,GTX,CTO

639-3665

639-3668

PCBA,MLB,D7,GSB,GOOD

639-3567

PCBA,MLB,D7,GTX,BETTER

MLB LABEL,48.0X4.8

825-7122

1

EEEE:DT42

CRITICAL

IVB,QC13,QS,E0,2.8G,65W,4+1,1.10,6M,LGA

337S4240

1

CRITICAL

CPU

CPU:GOOD

1

337S4246 CRITICAL

CPU

IVB,SR0PN,PRQ,E1,3.1G,65W,4+2,1.15,8M,LG

CPU:CTO

341S3390

U4900

CRITICAL

1

IC,SMC,PROGRMD,PVT,D7

SMC:PVT

CRITICAL

U1000

511S0073

1

SOCKET,MOLEX,LGA1155,CPU-LF

607-9432

FB:BOTH_SAMSUNG

K70,GDDR5,SAMSUNG

607-9435

FB:BOTH_HYNIX

K70,GDDR5,HYNIX

607-9433

FB:CH1_SAMSUNG

K70,GDDR5,SAMSUNG_CH1

607-9436

FB:CH1_HYNIX

K70,GDDR5,HYNIX_CH1

607-9437

FB:CH2_HYNIX

K70,GDDR5,HYNIX_CH2

FB:CH2_HYNIX

CRITICAL

IC,GDDR5,2GB,M-DIE,170B FBGA

2

U8500,U8550

333S0630

FB:CH2_SAMSUNG

U8500,U8550

IC,SGRAM,GDDR5,64MX32,4.2GBPS,D-DIE,HF

2

CRITICAL333S0631

IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE

FB:BOTH_HYNIX

CRITICAL

U8400,U8450,U8500,U8550

4

333S0620

607-9432607-9435

GDDR5_BOTH

VRAM

607-9433607-9436

GDDR5_CH1

VRAM

GPU:GSA

607-9437 607-9434

GDDR5_CH2

VRAM

GPU:GSB

607-9434

VRAM

CRITICAL

1

GPU:GSB

K70,GDDR5,SAMSUNG_CH2

511S0073511S0072

ALL

FOXCONN SOCKET

511S0071 511S0073

TYCO SOCKET

ALL

Enet magnetics

157S0058157S0055

ALL

607-9434

FB:CH2_SAMSUNG

K70,GDDR5,SAMSUNG_CH2

CRITICAL

U8701

GPUROM:BLANK

335S0724

1

IC,1 MBIT SERIAL FLASH

341S3388

U4900

CRITICAL

1

IC,SMC,PROGRMD,EVT,D7

SMC:EVT

341S3389

U4900

CRITICAL

1

IC,SMC,PROGRMD,DVT,D7

SMC:DVT

377S0126377S0107

USB diodes

ALL

1

EEEE_DF98

825-7122

EEEE:DF98

CRITICAL

XDP_CONN,LPCPLUS,VREFMRGN:EXT,BKLT_PWM,DEVEL_SENSORS,DEVEL_AUDIO

D7_DEVEL

1

U4202

CRITICAL

335S0852

IC,FLASH,SPI,1MBIT,3V3

CAMROM:BLANK

IC,PCH,PPT-DT,Z77,QS,C1

337S4234

U1800

1

CRITICAL

CRITICAL

CAMROM:PROG

U4202

1

IC,CAMERA FLASH,K70/K72

341S3453

1

CRITICAL

U4900

IC,SMC,PROGRMD,PROD,D7

SMC:PROD

341S3409

BOOTROM:BLANK

1

U5110

IC,64 MBIT SPI SERIAL FLASH

CRITICAL

335S0807

337S4220

GPU:GSB

U8000

CRITICAL

IC,GPU,NV,GK107-GS-2/1-QS-A

1

IC,SGRAM,GDDR5,64MX32,4.2GBPS,D-DIE,HF

FB:CH1_SAMSUNG

2

U8400,U8450

CRITICAL333S0631

IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF

FB:BOTH_SAMSUNG

U8400,U8450,U8500,U8550

CRITICAL

4

333S0619

IC,GDDR5,2GB,M-DIE,170B FBGA

FB:CH1_HYNIX

2

U8400,U8450

CRITICAL333S0630

K70,GDDR5,SAMSUNG_CH1

607-9433

VRAM

CRITICAL

GPU:GSA

1

U3990

CRITICAL

335S0862

IC,SERIAL FLASH,2MBIT,2.7V,REV F

1

CIVROM:BLANK

337S4239

IC,GPU,NV,GK107-GTX-QS-A2

1

GPU:107GTX

U8000

CRITICAL

IC,GPU,NV,GK107-GS-2/1-QS-A

337S4221 CRITICAL

GPU:GSA

U8000

1

338S1047

U3600

CRITICAL

1

IC,TBT,CR-4C,ES1,288 FCBGA,12X12MM

337S4258

IVB,QC48,QS,E1,2.9G,65W,4+2,1.10,6M,LGA

1

CPU:BETTER

CPU

CRITICAL

K70,GDDR5,SAMSUNG

GPU:107GTX

607-9432 CRITICAL

1

VRAM

1

BOOTROM:PROG

CRITICAL

U5110

IC,PROGRMD,EFI ROM,K70

341S3480

341S3487

U3990

1

IC,ENET 1MBITFLASH,CIV,PVT,J40

CRITICAL

CIVROM:PROG

IC,SMC12-A3,BLANK,D7

338S1098

U4900

1

SMC:BLANK

CRITICAL

IC,SMC,PROGRMD,PROTO1,D7

341S3484

U4900

CRITICAL

1

SMC:PROTO1

CRITICAL

335S0865

IC,EEPROM,SERIAL,256KB,MLP8

U3690

T29ROM:BLANK

1

341S3493

U3690

CRITICAL

IC,CR,V24.2,D7/D7I

1

T29ROM:PROG

IC,BCM57766,CIV+,A0,8X8

343S0592

U3900

CRITICAL

1

P/NCh dual FET

ALL

376S0975376S1081
341S3487341S3486

ALL

P/NCh dual FET

D7_COMMON1

XDP,RSMRST:SMC,SPEAKERID,TBTHV:P12V

SNS_CPUCORE:3PHASE,CPUCOREDRV:ISL6612,IG:N,GPU_ROM:YES,SNS_GPUS0:K70,SNS_VDDQS3_DDR:Y

D7_COMMON2

SMC:PROTO1,BOOTROM:PROG,T29ROM:PROG,CIVROM:PROG,CAMROM:PROG

D7_PROGPARTS

D7_PRODUCTION

SNS_VDDQS0_GPU:N,SNS_VDDQS3:N,VREFMRGN:N

825-7122

MLB LABEL,48.0X4.8

CRITICAL

1

EEEE:F117EEEE_F117

1

825-7122

MLB LABEL,48.0X4.8

CRITICAL

EEEE:F116

SNS_VDDQS0_GPU:Y,SNS_VDDQS3:Y,TEMPSNSDEV

DEVEL_SENSORS

COMMON,ALTERNATE,D7_COMMON1,D7_COMMON2,D7_PROGPARTS

D7_COMMON

MLB LABEL,48.0X4.8

EEEE_F116

EEEE_DT42

D7_COMMON,CPU:BETTER,GPU:107GTX,FBA,FBB,SSD:Y,EEEE:DT42

D7_COMMON,CPU:CTO,GPU:107GTX,FBA,FBB,SSD:Y,EEEE:F116

D7_COMMON,CPU:GOOD,GPU:GSB,GS,FBB,SSD:N,EEEE:F117

DEVELOPMENT,D7_DEVEL

D7_COMMON,CPU:GOOD,GPU:GSA,GS,FBA,SSD:N,EEEE:DF98

051-9509

4.2.0

4 OF 113
4 OF 100

IN

G

D

S

IN

G

D

S

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ALL_SYS_PWRGD Led

This LED is a GPIO driven from
that chipset has enumerated graphics

VIDEO ON Led

S5 Led

GPU GOOD Led

the southbridge that indicates

1/16W

5%
MF-LF

1K

402

81

SILK_PART=2

2.0X1.25MM-SM

GREEN-3.6MCD

SOT-363

2N7002DW-X-G

5%
MF-LF

1/16W
402

1K

44 61

SILK_PART=4

2.0X1.25MM-SM

GREEN-3.6MCD

1K

1/16W
402

MF-LF

5%

2.0X1.25MM-SM

SILK_PART=1

GREEN-3.6MCD

1K

5%
1/16W
MF-LF
402

SILK_PART=3

2.0X1.25MM-SM

GREEN-3.6MCD

SOT-363

2N7002DW-X-G

21

SYNC_MASTER=K70_MLB

DEBUG LEDS

SYNC_DATE=11/30/2011

ITS_PLUGGED_IN

=PP3V3_S5_LED

GPU_PRESENT_DRAIN

GPU_PRESENT_R

=PP3V3_S0_LED

VIDEO_ON_L

LCD_SHOULD_ON_R

=PP3V3_S0_LED

CORE_VOLTAGES_ON

CORE_VOLTAGES_ON_R

=PP3V3_S4_LED

ALL_SYS_PWRGD

GPU_GOOD

R502

1

2

LED502

A

K

Q502

3

5

4

R504

1

2

LED504

A

K

R501

1

2

LED501

A

K

R503

1

2

LED503

A

K

Q502

6

2

1

051-9509

4.2.0

5 OF 113
5 OF 100

6

5 6

5 6

6

OUT
OUT
IN
OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Enabled when system has AC and is in S5

Enabled when Thunderbolt cable is plugged in

Enabled when system is in run

S5 Rails

S3 Rails

Enabled when system is in run or sleep

Thunderbolt Rails (S0)

Enabled when system is in run

Ground/Common

S4 Rails

S0 Rails

Always on: Keeps the PCH RTC alive

G3 Rails

G3H Rails

Enabled when system has AC and is in run or sleep

GPU Rails (S0)

MLB to AC-DC Supplemental Signal Connector

MLB to AC-DC Connector

J600.7:3mm

EMC

5%

402

NP0-C0G

25V

1000PF

805

X5R

25V

10%

10UF

J600.6:3mm

EMC

1000PF

J600.8:3mm

25V

5%

402

NP0-C0G

50 94

50 94

45 67

6

45

10%

NOSTUFF

6.3V

1UF

CERM

402

402

6.8V-100PF

0

402

MF-LF

1/16W

5%

45

SILK_PART=PwrSig

CRITICAL

M-RT-SM

53780-8606

402

10K

5%
MF-LF

1/16W

CRITICAL

F-RT-TH

43650-0603

SYNC_DATE=01/11/2012

Power Connectors/Aliases

SYNC_MASTER=D7_NICK

GND

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP3V3_S4

MAKE_BASE=TRUE

PP5V_S4

PP3V3_S5

MAKE_BASE=TRUE

PP5V_S5

MAKE_BASE=TRUE

PP12V_S5

MAKE_BASE=TRUE

PPVDDQ_S0_GPU

MAKE_BASE=TRUE

PP1V05_S0_GPU

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP1V05_TBTCIO

MAKE_BASE=TRUE

PP1V05_TBTLC

PP3V3_TBTLC

MAKE_BASE=TRUE

PPVCCSA_S0

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPVAXG_S0

PPDDRVREF_CA_MEM_B_S3

MAKE_BASE=TRUE

PPDDRVREF_DQ_MEM_B_S3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPDDRVREF_CA_MEM_A_S3

PPDDRVREF_DQ_MEM_A_S3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPDDRVTT_S0

PP12V_S0_GPUUNCORE

MAKE_BASE=TRUE

PP12V_S0_GPUCORE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP12V_S0

MAKE_BASE=TRUE

PP5V_S0

MAKE_BASE=TRUE

PPHDD_S0

MAKE_BASE=TRUE

PP3V42_G3H

PPDDRVTT_S3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPVDDQ_S3_DDR

PP3V3_S0_SSD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PPSSD_S0

MAKE_BASE=TRUE

PPVDDQ_S3

MAKE_BASE=TRUE

PP12V_ACDC

VOLTAGE=3.3V

MAKE_BASE=TRUE
NET_SPACING_TYPE=POWER
MIN_LINE_WIDTH=0.6MM

PP3V3_G3

MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3MM

MAKE_BASE=TRUE

PP12V_G3H

MAKE_BASE=TRUE

PPVCORE_S0_CPU

MAKE_BASE=TRUE

PPVCORE_S0_GPU

PP3V3_ENET

MAKE_BASE=TRUE

PP1V5_S0

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP1V05_S0

=PP1V05_S0_DP
=PP1V05_S0_P1V05TBTFET

=PPVCCIO_S0_CPU

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO_DMI

=PP1V05_S0_PCH_VCC_SSC

=PP1V05_S0_PCH_VCC_DIFFCLK

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCC_ASW
=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCC_ADPLL

=PP1V05_S0_PCH

=PPVCCIO_S0_XDP

=PPVCCIO_S0_SMC

PPHDD_S0_SNS

SNS_ACDC_N
SNS_ACDC_P

SMC_ACDC_ID

PWR_BTN_R

BURSTMODE_EN_L

=PP1V8_S0_CAMERA

=PP1V5_S0_SENSE

=PPSPD_S0_MEM_A

=PP3V3_GPU_VDD33

=PP3V3_GPU_MISC

=PP3V3_GPU_IFPX_PLLVDD

=PP3V3_S0_BKLT_VDDIO

=PP3V3_S0_TBTPWRCTL

=PP3V3_S4_MEMRESET

=PP3V3_S4_PM

PP3V3_S4_FET

=PP5V_S4_FET_P5V_S0

=PP3V3_S4_ALS

PP12V_G3H_ACDC

=PPVDDQ_S3_LDO_DDRVTT

=PP3V3_ENET_PHY

PPDDRVTT_S3_LDO

=PPVDDQ_S3_MEMRESET

=PP3V3_S0_BT

=PP3V3_S0_AUDIO_DIG

=PP3V3_S0_VRD
=PP3V3_S0_AUDIO

=PP3V3_S0_CAMERA

PPCPUCORE_S0_REG

=PP5V_S4_REG_VDDQ_S3

=PP12V_S0_SNS_GPUUNCORE_R
=PP12V_S0_AUDIO_SPKRAMP
=PP12V_S0_BKLT

=PP12V_S0_SNS_GPUCORE_R

=PP3V3_G3H_BT

=PP12V_G3H_SNS_R

=PP12V_G3H_REG_3V42_G3H

PP5V_S5_LDO
=PP5V_S5_PWRCTL

PP3V3_S5_REG

=PP3V3_G3_PCH

=PP5V_S4_MEMRESET

=PP5V_S0_ISENSE

=PP1V8_S0_PCH_VCC_VRM

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8_S0_PCH

PP1V8_S0_REG

=PP3V3_S0_SSD

=PP3V3_S0_SMBUS_SMC_3

=PP3V3_S0_SMBUS_SMC_1

=PP3V3_S0_SMBUS_SMC_0

=PP3V3_S0_SENSE
=PP3V3_S0_SMBUS

=PP3V3_S0_SDCARD

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCC_PCI

=PP3V3_S0_PCH_VCC_HVCMOS

=PP3V3_S0_PCH_VCC

=PP3V3_S0_PCH_PM
=PP3V3_S0_PCH_STRAPS

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_LED_SATA

=PP3V3_S0_LED

=PP3V3_S0_ENET

=PP3V3_S0_PWRCTL

PP3V3_S0_FET

=PPHDD_S0_SNS_R

=PP5V_S0_PCH
=PP5V_S0_BKLT

=PP5V_S0_LPCPLUS

=PP5V_S0_AUDIO
=PP5V_S0_CAMERA

=PP5V_S0_VRD

=PP5V_S0_REG_GPU_VDDQ_S0

=PP5V_S0_REG_GPUCORE_S0

=PP5V_S0_REG_GPU_P1V05_S0

=PP5V_S0_REG_P1V05_S0

=PP5V_S0_REG_VCCSA_S0

=PP12V_S0_REG_CPUCORE_S0
=PP12V_S0_REG_VCCSA_S0

PPVDDQ_S3_SNS_DDR

=PP12V_G3H_FET_P12V_S0

=PPVIN_G3H_SMCVREF

=PP12V_G3H_FET_P12V_S5

=PP12V_S0_REG_P1V05_S0

=PPVDDQ_S3_SNS_DDR_R

=PPVDDQ_S3_FET_VDDQ_S0

=PP3V3_ENET_SYSCLK

PPVDDQ_S3_REG

=PPVDDQ_S3_VSNS

PP3V3_ENET_FET

=PPVDDQ_S3_MEM_B

=PPVDDQ_S3_MEM_A

=PPVDDQ_S3_DDR_VREF

PWR_BTN

SMC_ACDC_ID

=PP3V3_S0_VRD

PP12V_S0_FET

=PP5V_S4_USB

=PP5V_S4_PWRCTL

=PP12V_S5_REG_VDDQ_S3

PP3V42_G3H_REG

=PP3V3_G3H_SMC
=PP3V3_RTC_D

=PP5V_S0_REG_P1V8_S0

PP5V_S0_FET
=PP5V_S0_REG_CPUCORE_S0

PP5V_S4_REG

=PP5V_S0_SATA

=PP12V_S0_FAN
=PP12V_S0_LCD

PP12V_S0_SNS_GPUCORE

PP12V_S0_SNS_GPUUNCORE

=PP12V_S0_REG_GPUCORE_S0

=PP12V_S0_REG_GPU_P1V05_S0
=PP12V_S0_REG_GPU_VDDQ_S0

=PP3V3_S0_PCH

PP1V5_S0_FET
=PP1V5_S0_CPU_MEM
=PP1V5_S0_AUD_DIG

PPDDRVTT_S0_LDO
=PPDDRVTT_S0_CLAMP
=PPDDRVTT_S0_MEM_A
=PPDDRVTT_S0_MEM_B

PPDDRVREF_DQ_MEM_A
=PPDDRVREF_DQ_MEM_A

PPDDRVREF_CA_MEM_A
=PPDDRVREF_CA_MEM_A

PPDDRVREF_DQ_MEM_B
=PPDDRVREF_DQ_MEM_B

PPDDRVREF_CA_MEM_B
=PPDDRVREF_CA_MEM_B

PP1V05_S0_REG

=PPVCORE_S0_CPU

=PPVAXG_S0_CPU

PPCPUAXG_S0_REG

=PP3V3_TBTLC_FET
=PP3V3_TBT_PCH_GPIO
=PP3V3_TBTLC_RTR

=PP1V05_TBTLC_FET

=PP1V05_TBTCIO_FET

=PP1V05_GPU_IFPCD_IOVDD
=PP1V05_GPU_IFPEF_IOVDD
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD

PP1V5R1V35_S0_GPU_REG
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_S0_FB

=PP3V3_S0_P3V3TBTFET

=PP1V05_TBTLC_RTR

=PPVDDIO_ENET_CLK

=PP12V_S5_REG_P3V3P5V_S5

=PP12V_S5_PWRCTL
=PPHV_SW_TBTAPWRSW
=PPHV_SW_TBTBPWRSW
=PP12V_S5_SNS

=PP3V3_S5_FET_P3V3_S0

=PP3V3_S5_FET_P3V3_S4

=PP3V3_S5_PWRCTL

=PP3V3_S5_LPCPLUS

=PP3V3_S5_PCH_VCC_SPI
=PP3V3_S5_PCH_VCCSUS_HDA
=PP3V3_S5_PCH_VCCSUS_USB
=PP3V3_S5_ROM

=PP3V3_S0_PCH_VCC_GPIO

=PP3V3_S4_SDCARD

=PP3V3_S4_FET_ENET

=PP3V3_S4_PCH

=PP3V3_S4_LED

=PP3V3_S4_TBT

=PP3V3_S4_SMBUS_SMC_2

=PP3V3_S4_USB_HUB

=PP3V3_S4_TBTBPWRSW

=PP3V3_S4_TBTAPWRSW

=PP3V3_S4_VREFMRGN

PP12V_S5_FET

PP3V3_G3H_RTC

PP12V_G3H_SNS

=PP3V3_S0_DP

PPVCCSA_S0_REG
=PPVCCSA_S0_CPU

PP1V05_S0_GPU_REG

=PPVCORE_GPU

PPGPUCORE_S0_REG

=PP1V05_TBTCIO_RTR

=PPVDDIO_TBT_CLK

=PP3V3_S0_PCH_VCC_ADAC

=PPSPD_S0_MEM_B

PP12V_G3H_ACDC

=PP3V3_S4_PWRCTL

=PP3V3_S4_AP

=PP3V3_S4_SMC

=PP3V3_S5_XDP

=PP3V3_S5_SENSE
=PP3V3_S5_SMC
=PP3V3_S5_USBMUX

=PP3V3_S5_VRD

=PP5V_S5_PCH

=PP3V3_S5_LDO_P1V05_S5

=PP3V3_S5_LED

=PP3V3_S5_PCH
=PP3V3_S5_PCH_STRAPS
=PP3V3_S5_PCH_VCC_DSW

=PP3V3_G3H_SMC_USBMUX

PP3V3_S0

MAKE_BASE=TRUE

=PP3V3_S0_INTDPMUX

=PP3V3_S0_FAN

=PPDDRVTT_S3_VREFCA

=PPSSD_S0_SNS_R

PP3V3_S0_SSD_FET

=PP3V3_S0_SATAMUX

=PP1V8_S0_GPUVID

=PP1V8_S0_CPU_PLL

=PP3V3_S0_SMC

PPSSD_S0_SNS

=PPVDDIO_S0_SBCLK

=PP1V8_S0_ENET

MAKE_BASE=TRUE

PP1V8_S0

C602

1

2

C601

1

2

C603

1

2

C600

1

2

D600

1

2

R606

1 2

J601

7

8

1
2
3
4
5
6

R601

1

2

J600

1
2
3
4
5
6

051-9509

4.2.0

6 OF 113
6 OF 100

97

97

97

97

97

97

97

95

95

97

95

96

97

97

97

97

95

97

97

97

97

97

97

95

95

97

97

95

97

97

96

97

97

95

95

36

10 11 13 16 62

22 24

22

18 22 24

18 19 22

22

22

22

22 24

22 24

22 24

17

18 24

25

45

48

40

41

29

71 77 78 79

77 80

77

86

36

28

28

70

70

40

6

68

37 38

68

28

33

56

6

62 65 66 68 74

40 52 54 55 58

40

63

68

48

54 55

86

48

33

48

69

67

67 70

67

18 19

28

48

24

22 24

19

68

41

47

47

47

41 48 49 50

47

39

26

22 24

22 24

22 24

26

15

15 19 20 36

15 41

5

37

70 80

70

48

24

86

46

52 59

40

68

74

80

74

65

66

63

66

49

70

45

69

65

49

70

26

68

38

30

29

32

6

45

6

62 65 66 68 74

70

42 43

70

68

69

44 45

26

68

70

62

67

41

51

81

48

48

80

74

74

18 21 24

70

11 13 16

52

68

28

29

30

32

29

32

29

32

30

32

30

65

13 16 48 62

13 17 48 62

64

36

15

34 35 36

36

36

77

77

73 79

77 79

74

72 75 76

73

36

35 36

26

67

60 61 70

84

85

48

70

70

60 61 70 78

46

22 24

22 24

22 24

46

22 24

15 39

38

15

5

34 35 36 84 85

47

27

45 85

45 84

32

69

22 26

48

47 81 83

66

13 16

74

72 79

80

35

26

17

30

6

70

33

45

25

48

45

42 43

67 68

24

5

19 24 26

15

22 24

42

97

82

51

32

49

70

41

80

13 16

45

49

26

38

97

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

998-4560 (Plated holes, 2.3mm inner diameter, 4.3mm pad)

APN: 870-1939

CPU Heatsink

WIRELESS CARD MTG HOLES

SSD STANDOFF

APN: 860-1461

4mm Plated Holes (998-0850)

POGO PINS

GPU HEATSINK MOUNTING FEATURES

(860-0988)

Rear Cover

998-4559 (Plated holes, 4mm inner diameter, 8mm pad)

USB Can holes

998-3975 (Plated slot holes, 1.10mm x 0.45mm)

8P5R5-NSP

OMIT

8P5R5-NSP

OMIT

8P5R5-NSP

OMIT OMIT

8P5R5-NSP

CRITICAL

STDOFF-4.5OD2.2ID-5.6H-SM

CRITICAL

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

CRITICAL

CRITICAL

STDOFF-4.5OD.98H-1.1-3.48-TH

CRITICAL

7P0R4P0-8P0B-NSP

CRITICAL

7P0R4P0-8P0B-NSP

7P0R4P0-8P0B-NSP

CRITICAL

CRITICAL

7P0R4P0-8P0B-NSP

5P5R2P3-4P3B-NSP

CRITICAL

5P5R2P3-4P3B-NSP

CRITICAL

TH-NSP

SL-1.1X0.45-1.4X0.75

TH-NSP

SL-1.1X0.45-1.4X0.75

SYNC_DATE=11/30/2011

SYNC_MASTER=K70_MLB

Holes/PD parts

ZH07001ZH07011ZH07021ZH0703

1

NUT0713

1

SH0777

1

SH0778

1

SH0779

1

ZH0713

1

ZH0714

1

ZH0715

1

ZH0716

1

ZH0721

1

ZH0722

1

ZH0730

1

ZH0731

1

051-9509

4.2.0

7 OF 113
7 OF 100

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Memory

CPU Reserved

PCH PLL

UNUSED GRAPHICS ALIASES

PCH Reserved

PCH SATA

PCH Test Points

PCH Unused Display

PCH PCI

PCH Miscellaneous

PCH Clocks

PCH USB

PCH and CPU FDI

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

Unused Signal Aliases

TP_PCH_RESERVE_5

TP_PCI_PAR

TP_PCI_C_BE_L<3..0>

MEM_B_CLK_P<2..3>

MEM_B_CLK_N<2..3>

CPU_CFG<15..12>

TP_MEM_B_DQ_CB<7..0>

TP_MEM_A_DQS_N<8>

TP_MEM_A_DQ_CB<7..0>

TP_CPU_RSVD<46..19>

TP_SDVO_STALLN

TP_SDVO_STALLP

TP_SDVO_INTN

TP_PCH_RESERVE_23

TP_PCH_RESERVE_21

DP_IG_D_AUXP

DMI_MIDBUS_CLK100M_N

MEM_B_CS_L<2..3>

MEM_A_CKE<2..3>

MEM_A_CS_L<2..3>

TP_MEM_B_DQS_N<8>

TP_MEM_A_DQS_P<8>

TP_CPU_RSVD<16..1>

TP_CLKOUT_PEG_A_P

PP1V05_S0_PCH_VCCAPLL_SATA

PP1V05_S0_PCH_VCCAPLL_EXP

PP1V05_S0_PCH_VCCAPLLDMI2

CPU_FDI_TX_P<7..0>

TP_DVPCNTL_M<0..1>

TP_PCH_RESERVE_28

HDMI_EG_DATA_C_P<0..2>

TP_PCH_RESERVE_12

TP_PCH_RESERVE_20

USB_PCH_5_N

DP_IG_B_AUX_N

DP_IG_B_AUX_P

DP_IG_B_HPD

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO64_CLKOUTFLEX0

TP_CRT_IG_VSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_DDC_DATA

DP_IG_B_MLN<3..0>

DP_IG_C_MLP<3..0>

TP_PCH_GPIO67_CLKOUTFLEX3

HDMI_EG_DDC_DATA

PP1V05_S0_PCH_VCC_A_CLK

TP_PPVOUT_PCH_DCPSUSBYP

PP1V05_S0_PCH_FDIPLL

TP_PCH_GPIO8

TP_PCI_CLK33M_OUT3

TP_PCI_CLK33M_OUT2

TP_PCH_CL_RST1

TP_PCH_CL_CLK1

TP_PCH_CL_DATA1

TP_PCH_SST

TP_PCH_PWM3

TP_PCH_PWM2

TP_PCH_PWM1

TP_PCH_PWM0

TP_PCH_RESERVE_8

TP_PCH_RESERVE_7

TP_PCH_RESERVE_0

TP_DVPDATA<4..23>

TP_PCH_RESERVE_19

TP_PCH_RESERVE_22

TP_PCH_RESERVE_27

TP_PCH_RESERVE_26

TP_PCH_RESERVE_24

TP_PCH_RESERVE_17

TP_PCH_RESERVE_18

TP_PCH_RESERVE_15

TP_PCH_RESERVE_16

TP_PCH_RESERVE_14

TP_PCH_RESERVE_13

TP_PCH_RESERVE_10

TP_PCH_RESERVE_11

TP_PCH_RESERVE_9

TP_PCH_RESERVE_6

TP_PCH_RESERVE_3

TP_PCH_RESERVE_4

TP_PCH_RESERVE_2

TP_PCH_RESERVE_1

TP_PCH_L_BKLTEN

TP_SDVO_TVCLKINP

DP_IG_C_AUX_N

DP_IG_C_AUX_P

DP_IG_C_CTRL_CLK

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_PCH_L_BKLTCTL

DP_IG_D_MLP<3..0>

DP_IG_B_DDC_CLK

DP_IG_D_CTRL_DATA

TP_SDVO_INTP

TP_SDVO_TVCLKINN

DP_IG_D_HPD

DP_IG_C_MLN<3..0>

DP_IG_B_DDC_DATA

TP_SATA_F_D2RP

TP_SATA_F_D2RN

DP_IG_B_MLP<3..0>

TP_CRT_IG_BLUE

TP_CRT_IG_RED

TP_CRT_IG_GREEN

TP_SATA_E_R2D_CP

TP_SATA_E_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_C_D2RN

TP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_PCH_TP20

TP_PCH_TP19

TP_PCH_TP18

TP_PCH_TP17

TP_PCH_TP16

TP_PCH_TP15

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP12

TP_PCH_TP11

TP_PCH_TP10

TP_PCH_TP9

TP_PCH_TP8

TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5

TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP1

TP_SATA_D_D2RP

TP_PCH_TP2

TP_SATA_C_R2D_CP

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_D_D2RN

DP_IG_C_HPD

DP_IG_C_CTRL_DATA

TP_PCI_AD<31..0>

TP_PCI_RESET_L

TP_LPC_DREQ0_L

TP_PCH_INIT3V3_L

TP_HDA_SDIN1

TP_HDA_SDIN3

TP_HDA_SDIN2

HDMI_EG_DDC_CLK

HDMI_EG_DATA_C_N<0..2>

GPU_TDIODE_P

HDMI_EG_CLK_C_N

HDMI_EG_CLK_C_P

EG_LCD_PWR_EN

GPU_TDIODE_N

TP_DVPCLK

TP_DVPCNTL<0..2>

TP_PCH_L_VDD_EN

TP_PCH_RESERVE_25

TP_CRT_IG_HSYNC

USB_PCH_4_N

USB_PCH_4_P

USB_PCH_5_P

USB_PCH_6_N

USB_PCH_6_P

USB_PCH_11_P

USB_PCH_11_N

USB_PCH_12_P

USB_PCH_12_N

USB_PCH_13_P

USB_PCH_13_N

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE7P

TP_PE_TX_P<3..0>

TP_PE_TX_N<3..0>

TP_PE_RX_N<3..0>

TP_PE_RX_P<3..0>

TP_PCH_CLKOUT_DPN

TP_PCH_CLKOUT_DPP

PCH_CLK25M_XTALOUT

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

CPU_FDI_TX_N<7..0>

PCH_FDI_RX_P<7..0>

PCH_FDI_RX_N<7..0>

CPU_FDI_INT

CPU_FDI_FSYNC<1..0>

CPU_FDI_LSYNC<1..0>

PCH_FDI_INT

PCH_FDI_LSYNC<1..0>

PCH_FDI_FSYNC<1..0>

DP_IG_D_MLN<3..0>

DP_IG_D_AUXN

DP_IG_D_CTRL_CLK

TP_CLKOUT_PEG_A_N

TP_MEM_B_DQS_P<8>

MEM_A_CLK_N<2..3>

DMI_MIDBUS_CLK100M_P

MEM_A_CLK_P<2..3>

MEM_B_CKE<2..3>

MEM_A_ODT<2..3>

MEM_B_ODT<2..3>

NC_MEM_A_DQSN<8>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_CKE<2..3>

NC_MEM_A_CS_L<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CLKP<2..3>

MAKE_BASE=TRUE

NC_CLKOUT_PEG_AN

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_CPU_CFG<15..12>

MAKE_BASE=TRUE

NC_MEM_A_DQSP<8>

NO_TEST=TRUE

NC_MEM_B_DQ_CB<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_CLKOUT_DPN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PE_RXN<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PE_TXP<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_RSVD<46..19>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_ODT<2..3>

MAKE_BASE=TRUE

NC_MEM_B_CKE<2..3>

NO_TEST=TRUE

NC_MEM_B_CS_L<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_ODT<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLKP<2..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLKN<2..3>

MAKE_BASE=TRUE

NC_MEM_A_CLKN<2..3>

NO_TEST=TRUE

NC_MEM_B_DQSP<8>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_DQSN<8>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_DQ_CB<7..0>

MAKE_BASE=TRUE

NC_PP1V05_S0_PCH_VCCAPLL_SATA

NO_TEST=TRUE

NC_PP1V05_S0_PCH_VCCAPLL_EXP

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PP1V05_S0_PCH_VCCAPLLDMI2

NC_PCH_RESERVE_20

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_21

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_2

NO_TEST=TRUE

NC_PCH_RESERVE_3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DMI_MIDBUS_CLK100P

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_TXP<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_MLN<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_MLP<3..0>

NC_CLKOUT_PEG_AP

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCH_CLK25M_XTALOUT

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_TDIODE_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_EG_LCD_PWR_EN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_TDIODE_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PP1V05_S0_PCH_VCC_A_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PPVOUT_PCH_DCPSUSBYP

NC_PP1V05_S0_PCH_FDIPLL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_GPIO8

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_CLK33M_OUT3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_CLK33M_OUT2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_CL_RST1

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_CL_CLK1

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCH_CL_DATA1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_SST

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCH_PWM3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PCH_PWM2

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_PWM1

NO_TEST=TRUE

NC_PCH_PWM0

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_AUXN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DVPCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DVPDATA<4..23>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DVPCNTL_M<0..1>

MAKE_BASE=TRUE

NC_DVPCNTL<0..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_26

NC_PCH_RESERVE_24

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_25

NO_TEST=TRUE

NC_PCH_RESERVE_23

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_22

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_19

NC_PCH_RESERVE_17

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_18

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_14

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_13

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_12

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_10

NO_TEST=TRUE

NC_PCH_RESERVE_11

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_9

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_8

MAKE_BASE=TRUE

NC_PCH_RESERVE_7

NO_TEST=TRUE

NC_PCH_RESERVE_5

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_6

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_4

NC_SDVO_STALLN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_HPD

NC_SATA_E_R2D_CN

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_CTRL_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_L_BKLTCTL

NC_PCH_L_BKLTEN

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_CTRL_DATA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_CTRL_DATA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_F_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_CTRL_CLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_DDC_CLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_RED

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_GREEN

NC_SATA_E_R2D_CP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_D_R2D_CN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_C_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_C_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP20

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP19

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP18

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP17

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP16

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP15

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP13

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP14

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP12

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP11

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP10

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP9

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP8

MAKE_BASE=TRUE

NC_PCH_TP7

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP6

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP5

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP4

MAKE_BASE=TRUE

NC_PCH_TP1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_TP3

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_AUXP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_AUXP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_AUXP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_AD<31..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_PAR

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3..0>

NO_TEST=TRUE

NO_TEST=TRUE

NC_PCI_RESET_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LPC_DREQ0_L

NC_PCH_INIT3V3_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDA_SDIN1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDA_SDIN3

MAKE_BASE=TRUE

NC_HDA_SDIN2

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_L_VDD_EN

NC_CPU_RSVD<16..1>

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_CTRL_DATA

NO_TEST=TRUE

NC_SDVO_STALLP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_INTN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDMI_EG_DDC_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDMI_EG_DDC_DATA

MAKE_BASE=TRUE

NC_HDMI_EG_DATA_C_P<0..2>

NO_TEST=TRUE

NC_HDMI_EG_DATA_C_N<0..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_HDMI_EG_CLK_C_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_HDMI_EG_CLK_C_N

NC_SDVO_TVCLKINP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SDVO_INTP

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_27

NC_PCH_RESERVE_16

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_15

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_4_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_4_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_5_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_5_N

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_6_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_6_P

NC_USB_PCH_11_P

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_11_N

NC_USB_PCH_12_P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_12_N

NO_TEST=TRUE

NO_TEST=TRUE

NC_USB_PCH_13_P

MAKE_BASE=TRUE

NC_USB_PCH_13_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE7P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PE_TXN<3..0>

MAKE_BASE=TRUE

NC_PE_RXP<3..0>

NO_TEST=TRUE

NC_DMI_MIDBUS_CLK100N

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

NC_PCH_GPIO67_CLKOUTFLEX3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_AUXN

NC_CPU_FDI_TXN<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_RXP<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_RXN<7..0>

NO_TEST=TRUE

NC_CPU_FDI_INT

MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_LSYNC<1..0>

NC_PCH_FDI_INT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_LSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_FSYNC<1..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_MLP<3..0>

MAKE_BASE=TRUE

NC_PCH_RESERVE_0

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CN

NC_SATA_E_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

NO_TEST=TRUE

MAKE_BASE=TRUE

051-9509

4.2.0

8 OF 113
8 OF 100

19 20

20

12 88

12 88

10 91

12

12

12

10

19

19

19

19

19

19

18

12 88

12 88

12 88

12

12

10

18

22

22

22

10 91

19

19

19

20

19

19

19

18

18

19

19

19

19

19

18

22

22

22

21

20

20

18

18

18

21

21

21

21

21

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

18

19

19

19

19

18

18

18

19

19

19

19

19

19

19

19

18

18

19

19

19

19

18

18

18

18

18

18

18

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

21

18

21 18

18

18

18

19

19

20

20

18

19

18

18

18

77

78

77

18

19

19

20

20

20

20

20

20

20

20

20

20

20

21

21

21

21

10

10

10

10

18

18

18

18

18

18

10 91

19

19

10 91

10 91

10 91

19

19

19

19

19

19

18

12

12 88

18

12 88

12 88

12 88

12 88

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Whistler aliases

Signal Aliases

SYNC_DATE=11/30/2011

SYNC_MASTER=K70_MLB

=PEG_R2D_C_P<15..0>

=PEG_D2R_P<15..0>

=PEG_R2D_C_N<15..0>

=PEG_D2R_N<15..0>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

051-9509

4.2.0

9 OF 113
9 OF 100

10

10

10

10 71 89

71 89

71 89

71 89

IN
IN
IN
IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

DMI_TX_1*

PE_TX_3*

PE_TX_3

PE_TX_2*

PE_TX_2

PE_TX_1*

PE_TX_1

PE_TX_0*

PE_TX_0

PE_RX_3*

PE_RX_3

PE_RX_2*

PE_RX_2

PE_RX_1*

PE_RX_1

PE_RX_0*

PE_RX_0

PEG_TX_15*

PEG_TX_15

PEG_TX_14*

PEG_TX_14

PEG_TX_13*

PEG_TX_13

PEG_TX_12*

PEG_TX_12

PEG_TX_11*

PEG_TX_11

PEG_TX_10*

PEG_TX_10

PEG_TX_9*

PEG_TX_9

PEG_TX_8*

PEG_TX_8

PEG_TX_7*

PEG_TX_7

PEG_TX_6

PEG_TX_5*

PEG_TX_5

PEG_TX_4*

PEG_TX_4

PEG_TX_3*

PEG_TX_3

PEG_TX_2*

PEG_TX_2

PEG_TX_1*

PEG_TX_1

PEG_TX_0*

PEG_TX_0

PEG_RX_15*

PEG_RX_15

PEG_RX_13*

PEG_RX_12

PEG_RX_11*

PEG_RX_11

PEG_RX_10

PEG_RX_9

PEG_RX_8

PEG_RX_7

PEG_RX_6

PEG_RX_5

PEG_RX_4*

PEG_RX_4

PEG_RX_3*

PEG_RX_3

PEG_RX_2

PEG_RX_1*

PEG_RX_0

FDI_TX_7*

FDI_TX_7

FDI_TX_6*

FDI_TX_6

FDI_TX_5*

FDI_TX_5

FDI_TX_4*

FDI_TX_4

FDI_TX_3*

FDI_TX_3

FDI_TX_2*

FDI_TX_2

FDI_TX_1*

FDI_TX_1

FDI_TX_0*

FDI_TX_0

FDI_LSYNC_1

FDI_LSYNC_0

FDI_FSYNC_1

FDI_FSYNC_0

DMI_TX_3*

DMI_TX_3

DMI_TX_2*

DMI_TX_2

DMI_TX_1

DMI_TX_0*

DMI_TX_0

DMI_RX_3*

DMI_RX_3

DMI_RX_2*

DMI_RX_2

DMI_RX_1

DMI_RX_0*

FDI_COMPIO
FDI_ICOMPO

FDI_INT

PEG_COMPI

PEG_ICOMPO

PEG_RX_1

PEG_RX_14*

PEG_RX_12*

PEG_RX_6*

PEG_RX_13
PEG_RX_14

PEG_RCOMPO

PEG_RX_10*

PEG_RX_9*

PEG_RX_8*

PEG_RX_7*

PEG_RX_2*

PEG_RX_0*

PEG_RX_5*

PEG_TX_6*

DMI_RX_0

DMI_RX_1*

SYM 1 OF 10

FLEXIBLE DISPLAY INTERFACE

PCI EXPRESS -- GRAPHICS

DMI

PCI EXPRESS

RSVD_NCTF_AV1
RSVD_NCTF_AW2
RSVD_NCTF_AY3

RSVD_NCTF_B39

NCTF_AW38

NCTF_AU40

NCTF_D1

NCTF_C2

NCTF_A38

CFG_8

RSVD_J34

RSVD_J33

RSVD_J31

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17

RSVD_K9
RSVD_K31
RSVD_K34
RSVD_L9
RSVD_L31
RSVD_L33
RSVD_L34
RSVD_M34
RSVD_N33
RSVD_N34

RSVD_P35
RSVD_P37
RSVD_P39
RSVD_R34
RSVD_R36
RSVD_R38
RSVD_R40
RSVD_AB6

RSVD_AB7
RSVD_AD34
RSVD_AD35
RSVD_AD37

RSVD_AE6

RSVD_AF4

RSVD_AG4
RSVD_AJ11
RSVD_AJ29
RSVD_AJ30
RSVD_AJ31
RSVD_AN20
RSVD_AP20
RSVD_AT11
RSVD_AT14
RSVD_AU10
RSVD_AV34
RSVD_AW34
RSVD_AY10

RSVD_J9

RSVD_H8

RSVD_H7

RSVD_C38

RSVD_D38

RSVD_C39

SYM 5 OF 10

RESERVED

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ThermDA

ThermDC

CFG[17:7] Reserved config lanes

CFG[6:5] PCIe bifurcation; Refer to page 15 for more info

CFG[4] Reserved config lane

CFG[3] PCIe Static x4 lane reversal; Refer to page 15 for more info

CFG[2] PCIe Static x16 lane reversal; Refer to page 15 for more info

CFG[1:0] Reserved config lane

(Available for Workstation only)

INTEL SUGGESTS TO KEEP THESE TPS

(Unused)

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1
ROUTE B5 TO R1010.1 AS A SEPERATE 10 MIL TRACE.

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

19 90

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

MF-LF

402

1/16W

1%

24.9

PLACE_NEAR=U1000.B4:12.7mm

25 91

25 91

8

91

8

91

8

91

8

91

25 91

25 91

25 91

25 91

25 91

15 25 91

15 25 91

25 91

15 25 91

15 25 91

25 91

25 91

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

24.9

1%
1/16W
MF-LF

402

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

NO_TEST=TRUE

NC_SNS_CPU_THERMDN

NO_TEST=TRUE

NC_SNS_CPU_THERMDP

CPU_FDI_TX_P<2>
CPU_FDI_TX_P<3>

CPU_FDI_TX_P<0>

CPU_FDI_TX_P<4>

CPU_FDI_TX_N<1>

CPU_FDI_TX_N<0>

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_N2S_N<3>

DMI_N2S_N<2>

CPU_FDI_TX_N<4>
CPU_FDI_TX_N<5>

=PEG_D2R_P<3>

=PEG_D2R_P<0>

=PEG_D2R_N<10>

=PEG_D2R_N<5>

=PEG_D2R_N<15>

=PEG_D2R_P<2>

=PEG_D2R_P<1>

=PEG_D2R_P<7>

TP_PE_RX_N<0>

TP_PE_RX_N<2>

TP_PE_TX_N<2>
TP_PE_TX_N<3>

TP_PE_TX_P<0>

CPU_FDI_TX_N<7>

DMI_N2S_P<3>

DMI_N2S_P<2>

CPU_FDI_TX_P<6>

=PEG_D2R_N<6>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<2>

=PEG_D2R_N<12>

=PEG_D2R_N<14>

=PEG_D2R_N<13>

=PEG_D2R_N<11>

DMI_S2N_N<3>

CPU_FDI_FSYNC<1>

=PEG_D2R_P<15>

=PEG_R2D_C_P<3>

CPU_CFG<16>

CPU_CFG<12>

CPU_CFG<9>

CPU_CFG<6>

CPU_CFG<3>

CPU_CFG<1>

CPU_CFG<0>

TP_CPU_RSVD<19>

TP_CPU_RSVD<8>

=PEG_D2R_P<10>

=PPVCCIO_S0_CPU

DMI_S2N_N<1>

=PEG_D2R_N<7>

=PEG_D2R_N<9>

=PEG_D2R_P<13>

CPU_FDI_INT

DMI_S2N_N<2>

CPU_FDI_FSYNC<0>

CPU_FDI_LSYNC<0>
CPU_FDI_LSYNC<1>

CPU_FDI_TX_P<1>

CPU_FDI_TX_N<2>

=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>

=PEG_D2R_P<8>
=PEG_D2R_P<9>

=PEG_D2R_P<11>

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<5>

=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<10>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>

TP_PE_RX_P<0>
TP_PE_RX_P<1>

TP_PE_RX_N<1>

TP_PE_RX_P<2>
TP_PE_RX_P<3>

TP_PE_RX_N<3>

TP_PE_TX_N<0>

TP_PE_TX_P<1>

TP_PE_TX_N<1>

TP_PE_TX_P<2>
TP_PE_TX_P<3>

DMI_S2N_N<0>

DMI_S2N_P<3>

DMI_S2N_P<2>

TP_CPU_RSVD<2>
TP_CPU_RSVD<3>

TP_CPU_RSVD<1>

TP_CPU_RSVD<4>
TP_CPU_RSVD<5>
TP_CPU_RSVD<6>

TP_CPU_RSVD<46>

TP_CPU_RSVD<45>

TP_CPU_RSVD<44>

TP_CPU_RSVD<43>

TP_CPU_RSVD<42>

TP_CPU_RSVD<41>

TP_CPU_RSVD<40>

TP_CPU_RSVD<39>

TP_CPU_RSVD<38>

TP_CPU_RSVD<37>

TP_CPU_RSVD<36>

TP_CPU_RSVD<35>

TP_CPU_RSVD<34>

TP_CPU_RSVD<33>

TP_CPU_RSVD<32>

TP_CPU_RSVD<31>

TP_CPU_RSVD<30>

TP_CPU_RSVD<29>

TP_CPU_RSVD<28>

TP_CPU_RSVD<27>

TP_CPU_RSVD<26>

TP_CPU_RSVD<25>

TP_CPU_RSVD<24>

TP_CPU_RSVD<23>

TP_CPU_RSVD<22>

TP_CPU_RSVD<21>

TP_CPU_RSVD<20>

TP_CPU_RSVD<16>

TP_CPU_RSVD<11>

CPU_CFG<15>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<5>

CPU_CFG<4>

CPU_CFG<2>

TP_CPU_RSVD<7>

TP_CPU_RSVD<9>

TP_CPU_NCTF<1>
TP_CPU_NCTF<2>
TP_CPU_NCTF<3>
TP_CPU_NCTF<4>
TP_CPU_NCTF<5>

TP_CPU_RSVD_NCTF<4>

TP_CPU_RSVD_NCTF<3>

TP_CPU_RSVD_NCTF<2>

TP_CPU_RSVD_NCTF<1>

DMI_S2N_P<0>
DMI_S2N_P<1>

=PEG_D2R_N<8>

=PEG_D2R_P<14>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<12>

=PEG_D2R_P<12>

CPU_CFG<17>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<7>
CPU_CFG<8>

=PEG_R2D_C_N<2>

=PEG_D2R_N<0>
=PEG_D2R_N<1>

=PEG_R2D_C_N<6>

CPU_PEG_COMP

DMI_N2S_N<1>

DMI_N2S_N<0>

CPU_FDI_TX_P<7>

CPU_FDI_TX_P<5>

TP_CPU_RSVD<15>

TP_CPU_RSVD<14>

TP_CPU_RSVD<13>

TP_CPU_RSVD<12>

TP_CPU_RSVD<10>

CPU_FDI_TX_N<6>

CPU_FDI_TX_N<3>

CPU_FDI_COMPIO

=PPVCCIO_S0_CPU

R1010

1 2

U1000

W5

W4

V3

V4

Y3

Y4

AA4

AA5

V7

V6

W7

W8

Y6

Y7

AA7

AA8

AE2

AC5
AE5

AE1

AG3

AC4
AE4

AC8

AC7

AC2

AC3

AD2

AD1

AD4

AD3

AD7

AD6

AE7

AE8

AF3

AF2

AG2

AG1

P3

P4

R2

R1

T4

T3

U2

U1

P8

P7

T7

T8

R6

R5

U5

U6

B4
B5
C4

B11

B12

D12

D11

H3

H4

J1

J2

K3

K4

L1

L2

M3

M4

N1

N2

C10

C9

E10

E9

B8

B7

C6

C5

A5

A6

E2

E1

F4

F3

G2

G1

C13

C14

E14

E13

G5

G6

K7

K8

J5

J6

M8

M7

L6

L5

N5

N6

G14

G13

F12

F11

J14

J13

D8

D7

D3

C3

E6

E5

F8

F7

G10

G9

U1000

H36
J36

M38
N36
N38
N39
N37
N40
G37
G36

J37
K36
L36
N35
L37
M36
J38
L35

A38

AU40
AW38

C2
D1

AB6
AB7
AD34
AD35
AD37
AE6
AF4
AG4
AJ11
AJ29
AJ30
AJ31
AN20
AP20
AT11
AT14
AU10
AV34
AW34
AY10

C38
C39
D38

H7
H8

J31
J33
J34

J9

K31
K34

K9

L31
L33
L34

L9

M34
N33
N34

AV1
AW2
AY3
B39

P35
P37
P39
R34
R36
R38
R40

R1011

1

2

051-9509

4.2.0

10 OF 113
10 OF 100

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

91

8

8

8

8

8

8

91

8

91

8

91

8

8

6

10 11 13 16 62

8

91

8

91

8

91

8

91

8

91

8

91

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

89

8

91

8

91

8

8

8

8

8

8

91

8

91

91

6

10 11

13 16 62

BI
BI
BI
BI
BI

IN

IN

OUT
OUT

OUT

IN
IN

OUT

OUT

BI

BI

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMS

TRST*

TDI
TDO

DBR*

BPM[0]*
BPM[1]*
BPM[2]*
BPM[3]*
BPM[4]*
BPM[5]*
BPM[6]*
BPM[7]*

TCK

PRDY*

BCLK_ITP

BCLK_0

BCLK_ITP*

BCLK_0*

UNCOREPWRGOOD

SKTOCC*

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

PROC_SEL

SYM 2 OF 10

CLOCKS

THERMAL

DDR3 MISC

PWR MGMT

JTAG & BPM

OUT

IN

OUT

IN
IN

IN

OUT

IN

IN
IN

IN

IN

OUT

OUT

BI
BI
BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FROM PCH

BASED ON INTEL MOBILE SOLUTION

25 91

25 91

25 91

25 91

25 91

1K

MF-LF
402

5%
1/16W

19 28

21 25

32 97

32 97

28

15 91

15 91

19

45

44 45 62

21 44 45

MF-LF

PLACE_NEAR=U1000.F36:50mm

75

402

5%

1/16W

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

MF-LF
402

1K

1%
1/16W

1K

MF-LF
402

1%
1/16W

10%
X7R-CERM

16V
402

0.1UF

45

402

1/16W

0

5%

MF-LF

51

MF-LF

402

5%

1/16W

25

25

25 91

25 91

25 91

25 91

25

200

MF-LF

402

1%

1/16W

1/16W

1%

402

MF-LF

130

18 90

18 90

19

43

MF-LF

5%

1/16W

402

26

60

25

25 91

25 91

25 91

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

CPU CLOCK/MISC/JTAG

CPU_PROCHOT_L

=PPVCCIO_S0_CPU

CPU_PROCHOT_R_L

CPU_SKTOCC_L
CPU_PROC_SEL

CPU_CATERR_L

CPU_PECI

CPU_THRMTRIP_L

CPU_PWRGD

PM_SYNC

PLT_RESET_LS1V05_L

CPU_MEM_RESET_L

CPU_DIMM_VREF_DAC_B
CPU_DIMM_VREF_DAC_A

CPU_RESET_L

PM_MEM_PWRGD

CPU_DDR_VREF

PM_MEM_PWRGD_R

=PPVCCIO_S0_CPU

=PP1V5_S0_CPU_MEM

XDP_CPU_PREQ_L

XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

XDP_CPU_TCK

XDP_CPU_PRDY_L

ITPCPU_CLK100M_P

DMI_CLK100M_CPU_P

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_N

=PP1V5_S0_CPU_MEM

CPU_DDR_VREF

R1101

1

2

R1120

1

2

R1121

12

R1125

12

R1111

1

2

R1124

1

2

U1000

W2
W1

C40
D40

H40
H38
G38
G40
G39
F38
E40
F40

E37

E39

J35

E38

K38
K40

K32

H34

F36

AH4

AH1

AJ33

AJ19

AW18

AJ22

M40

L40
L39

G35

L38
J39

J40

R1141

1

2

R1140

1

2

C1140

1

2

R1102

12

051-9509

4.2.0

11 OF 113
11 OF 100

6

10 11 13 16 62

11 97

6

10 11 13 16 62

6

11 13 16

6

11 13 16

11 97

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT

OUT OUT

SA_DQ_32
SA_DQ_33

SA_DQS_8*

SA_BS_2

SA_CAS*

SA_BS_1

SA_BS_0

SA_DQ_63

SA_DQ_62

SA_DQ_61

SA_DQ_60

SA_DQ_9

SA_CK_1

SA_ODT_2

SA_ODT_1

SA_ODT_0

SA_RAS*
SA_WE*

SA_CK_0

SA_CK_0*

SA_CK_1*

SA_CK_2

SA_CK_2*

SA_CK_3

SA_CK_3*

SA_CKE_0

SA_CKE_1

SA_CKE_2

SA_CKE_3

SA_CS_0*
SA_CS_1*
SA_CS_2*
SA_CS_3*

SA_DQ_0
SA_DQ_1

SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19

SA_DQ_2

SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29

SA_DQ_3

SA_DQ_30
SA_DQ_31

SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39

SA_DQ_4

SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49

SA_DQ_5

SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59

SA_DQ_6
SA_DQ_7
SA_DQ_8

SA_DQS_0

SA_DQS_0*

SA_DQS_1

SA_DQS_1*

SA_DQS_2

SA_DQS_2*

SA_DQS_3

SA_DQS_3*

SA_DQS_4

SA_DQS_4*

SA_DQS_5

SA_DQS_5*

SA_DQS_6

SA_DQS_6*

SA_DQS_7

SA_DQS_7*

SA_DQS_8

SA_ECC_CB_0
SA_ECC_CB_1
SA_ECC_CB_2
SA_ECC_CB_3
SA_ECC_CB_4
SA_ECC_CB_5
SA_ECC_CB_6
SA_ECC_CB_7

SA_MA_0
SA_MA_1

SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9

SA_ODT_3

SYM 3 OF 10

DDR SYSTEM MEMORY A

SB_CK_1*

SB_DQS_3*

SB_DQ_33

SB_DQS_4

SB_DQS_2

SB_DQS_8*

SB_CKE_3

SB_CS_0*
SB_CS_1*
SB_CS_2*
SB_CS_3*

SB_CAS*
SB_RAS*
SB_WE*

SB_BS_0
SB_BS_1
SB_BS_2

SB_CK_0

SB_CK_0*

SB_CK_1

SB_CK_2

SB_CK_2*

SB_CK_3

SB_CK_3*

SB_CKE_0

SB_CKE_1

SB_CKE_2

SB_DQ_0
SB_DQ_1

SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19

SB_DQ_2

SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29

SB_DQ_3

SB_DQ_30
SB_DQ_31
SB_DQ_32

SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39

SB_DQ_4

SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49

SB_DQ_5

SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59

SB_DQ_6

SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_DQ_7
SB_DQ_8
SB_DQ_9

SB_DQS_0

SB_DQS_0*

SB_DQS_1

SB_DQS_1*
SB_DQS_2*

SB_DQS_3

SB_DQS_4*

SB_DQS_5

SB_DQS_5*

SB_DQS_6

SB_DQS_6*

SB_DQS_7

SB_DQS_7*

SB_DQS_8

SB_ECC_CB_0
SB_ECC_CB_1
SB_ECC_CB_2
SB_ECC_CB_3
SB_ECC_CB_4
SB_ECC_CB_5
SB_ECC_CB_6
SB_ECC_CB_7

SB_MA_0
SB_MA_1

SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9

SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3

SYM 4 OF 10

DDR SYSTEM MEMORY B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

29 88

29 88

29 88

29 88

29 88

29 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

29 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

31 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

30 88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

8

88

29 88 30 88

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

SYNC_MASTER=K70_MLB

CPU DDR3 INTERFACES

SYNC_DATE=11/30/2011

MEM_A_CLK_P<0>

MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQS_P<3>

MEM_A_DQ<11> MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_A_DQ<9>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<10>

MEM_A_ODT<3>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<1>

MEM_A_A<0>

TP_MEM_A_DQ_CB<7>

TP_MEM_A_DQ_CB<6>

TP_MEM_A_DQ_CB<5>

TP_MEM_A_DQ_CB<4>

TP_MEM_A_DQ_CB<3>

TP_MEM_A_DQ_CB<2>

TP_MEM_A_DQ_CB<1>

TP_MEM_A_DQ_CB<0>

TP_MEM_A_DQS_P<8>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQ<7>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_CS_L<3>

MEM_A_CS_L<2>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_CLK_P<3>

MEM_A_CLK_N<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_A_BA<0>
MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_BA<2>

TP_MEM_A_DQS_N<8>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<0>

TP_MEM_B_DQ_CB<7>

TP_MEM_B_DQ_CB<6>

TP_MEM_B_DQ_CB<5>

TP_MEM_B_DQ_CB<4>

TP_MEM_B_DQ_CB<3>

TP_MEM_B_DQ_CB<2>

TP_MEM_B_DQ_CB<1>

TP_MEM_B_DQ_CB<0>

TP_MEM_B_DQS_P<8>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<2>

MEM_B_DQS_P<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<6>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<5>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<4>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<3>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<2>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CAS_L

TP_MEM_B_DQS_N<8>

MEM_B_DQS_P<2>

MEM_B_DQS_P<4>

MEM_B_DQ<33>

MEM_B_DQS_N<3>

MEM_B_CLK_N<1>

MEM_B_DQ<60>

MEM_B_DQS_N<1>

MEM_A_DQ<19>

MEM_A_DQ<26>

MEM_B_CLK_P<2>

MEM_A_CLK_N<2>

MEM_A_CLK_P<2>

MEM_A_CKE<3>

MEM_A_CLK_N<3>

MEM_A_CKE<2>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_ODT<2>

MEM_B_DQ<20>

MEM_B_CS_L<3>

MEM_B_CS_L<2>

MEM_B_CS_L<1>

MEM_B_CKE<2>

MEM_B_CLK_N<3>

MEM_B_CKE<3>

MEM_B_CS_L<0>

MEM_B_CLK_P<1>

MEM_B_CKE<1>

MEM_B_CLK_N<2>

MEM_B_CLK_P<3>

U1000

AY29
AW28
AV20

AV30

AY25
AW25

AU24
AU25

AW27
AY27

AV26
AW26

AV19

AT19

AU18

AV18

AU29
AV32
AW30
AU33

AJ3
AJ4

AR3
AR4
AN2
AN3
AR2
AR1
AV2
AW3
AV5
AW5

AL3

AU2
AU3
AU5
AY5
AY7
AU7
AV9
AU9
AV7
AW7

AL4

AW9

AY9
AU35
AW37
AU39
AU36
AW35
AY36
AU38
AU37

AJ2

AR40
AR37
AN38
AN37
AR39
AR38
AN39
AN40
AL40
AL37

AJ1

AJ38
AJ37
AL39
AL38
AJ39
AJ40
AG40
AG37
AE38
AE37

AL2

AG39
AG38
AE39
AE40

AL1

AN1

AN4

AK3

AK2

AP3

AP2

AW4

AV4

AV8

AW8

AV37

AV36

AP38

AP39

AK38

AK39

AF38

AF39

AV13

AV12

AU12
AU14
AW13
AY13
AU13
AU11
AY12
AW12

AV27
AY24

AV28
AU21
AT21
AW32
AU20
AT20

AW24
AW23
AV23
AT24
AT23
AU22
AV22
AT22

AV31
AU32
AU30
AW33

AU28
AW29

U1000

AP23
AM24
AW17

AK25

AL21
AL22

AL20
AK20

AL23
AM22

AP21
AN21

AU16

AY15

AW15

AV15

AN25
AN26
AL25
AT26

AG7
AG8

AM10
AL10

AL6
AM6
AL9
AM9
AP7

AR7
AP10
AR10

AJ9

AP6

AR6

AP9

AR9
AM12
AM13
AR13
AP13
AL12
AL13

AJ8

AR12
AP12
AR28
AR29
AL28
AL29
AP28
AP29
AM28
AM29

AG5

AP32
AP31
AP35
AP34
AR32
AR31
AR35
AR34
AM32
AM31

AG6

AL35
AL32
AM34
AL31
AM35
AL34
AH35
AH34
AE34
AE35

AJ6

AJ35
AJ34
AF33
AF35

AJ7

AL7

AM7

AH7

AH6

AM8

AL8

AR8

AP8

AN13

AN12

AN29

AN28

AP33

AR33

AL33

AM33

AG35

AG34

AN16

AN15

AL16
AM16
AP16
AR16
AL15
AM15
AR15
AP15

AK24
AM20

AN23
AU17
AT18
AR26
AY16
AV16

AM19
AK18
AP19
AP18
AM18
AL18
AN18
AY17

AL26
AP26
AM26
AK26

AP24
AR25

051-9509

4.2.0

12 OF 113
12 OF 100

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

VCCIO_31

VCCIO_44

VCCIO_SEL

VCCIO_45

VCCIO_30

VSSAXG_SENSE

VCCAXG_SENSE

VSSIO_SENSE

VCCIO_SENSE

VCC_024

VCC_038

VCCIO_42

VCCIO_29

VCCIO_28

VCCIO_09

VCC_001
VCC_002
VCC_003
VCC_004

VCCIO_27

VCC_012

VCC_015

VCC_005
VCC_006
VCC_007
VCC_008
VCC_009
VCC_010
VCC_011

VCC_013
VCC_014

VCC_016
VCC_017
VCC_018

VCC_020
VCC_021
VCC_022
VCC_023

VCC_025
VCC_026
VCC_027
VCC_028
VCC_029
VCC_030
VCC_031
VCC_032
VCC_033
VCC_034
VCC_035
VCC_036
VCC_037

VCC_039
VCC_040
VCC_041
VCC_042
VCC_043
VCC_044
VCC_045
VCC_046
VCC_047
VCC_048
VCC_049
VCC_050
VCC_051
VCC_052

VCC_057
VCC_058
VCC_059
VCC_060
VCC_061
VCC_062
VCC_063
VCC_064
VCC_065
VCC_066
VCC_067
VCC_068
VCC_069
VCC_070

VCCIO_02

VCCIO_01

VCCIO_20

VCCIO_26

VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36

VCCIO_40

VCCIO_43

VCCIO_04
VCCIO_05
VCCIO_06
VCCIO_07
VCCIO_08

VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14

VCCIO_16

VCCIO_19

VCCSA_SENSE

VIDALERT*

VIDSCLK

VIDSOUT

VSS_SENSE

VCCIO_41

VCC_SENSE

VCC_056

VCC_055

VCC_054

VCC_053

VCCIO_03

VCC_019

VCCIO_15

VCCIO_17
VCCIO_18

VCCIO_22
VCCIO_21
VCCIO_23
VCCIO_24
VCCIO_25

VCCIO_32

VCCIO_37
VCCIO_38
VCCIO_39

VCCSA_VID

SYM 6 OF 10

CPU VIDS

POWER

IO POWER

CPU CORE SUPPLY

SENSE LINES

VCCAXG_44

VCCAXG_43

VCCAXG_02
VCCAXG_03

VDDQ10

VCCPLL1

VCCPLL0

VDDQ22

VDDQ21

VDDQ20

VDDQ19

VDDQ16

VDDQ14

VDDQ13

VDDQ12

VDDQ11

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ4

VDDQ3

VDDQ2

VDDQ1

VDDQ0

VCCAXG_16

VCCAXG_15

VCCAXG_14

VCCAXG_13

VCCAXG_12

VCCAXG_11

VCCAXG_10

VCCAXG_09

VCCAXG_07

VCCAXG_06

VCCAXG_05

VCCAXG_04

VCCAXG_42

VCCAXG_41

VCCAXG_40

VCCAXG_39

VCCAXG_38

VCCAXG_37

VCCAXG_36

VCCAXG_35

VCCAXG_34

VCCAXG_33

VCCAXG_32

VCCAXG_31

VCCAXG_30

VCCAXG_29

VCCAXG_28

VCCAXG_27

VCCAXG_26

VCCAXG_25

VCCAXG_24

VCCAXG_22

VCCAXG_21

VCCAXG_19

VCCAXG_18

VCCAXG_17

VCCAXG_23

VCCAXG_20

VDDQ15

VDDQ17
VDDQ18

VDDQ5

VCCAXG_01

VCCAXG_08

SYM 7 OF 10

1.8V

POWER

DDR3-1.5V RAILS

GRAPHICS

VCC_092

VSS_NCTF2
VSS_NCTF3

VCC_097

VCC_091

VCC_090

VCC_089

VCC_088

VCC_087

VCC_083

VCC_112

VCC_117

VCC_113
VCC_114
VCC_115
VCC_116

VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125

VCC_128
VCC_129
VCC_130

VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153

VCC_156
VCC_157
VCC_158
VCC_159
VCC_160

VCCSA0
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6

VCCSA8
VCCSA9

VSS_NCTF1

VCC_073

VCC_072

VCC_071

VCC_155

VCC_154

VCC_084

VCC_093

VSS_NCTF0

VCC_100
VCC_101

VCC_104

VCC_106

VCC_105

VCC_096

VCC_095

VCC_094

VCC_086

VCC_085

VCCSA7

VCCSA10

VCC_107

VCC_082

VCC_077

VCC_074

VCC_076

VCC_161

VCC_126
VCC_127

VCC_111

VCC_098
VCC_099

VCC_075

VCC_081

VCC_103

VCC_102

VCC_078
VCC_079
VCC_080

VCC_108
VCC_109
VCC_110

SYM 10 OF 10

CPU CORE SUPPLY

VCCSA

CPU CORE SUPPLY

POWER

NCTF

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

66 95

62 96

62 96

65 95

65 95

62 96

62 96

0

1/16W

MF-LF

5%

402

402

1/16W

1%

MF-LF

44.2

5%

0

MF-LF

1/16W

402

402

75

1%
1/16W
MF-LF

PLACE_NEAR=U1000.A37:10mm

MF-LF

1/16W

1%

110

402

PLACE_NEAR=U1000.B37:10mm

62 96

62 96

62 96

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

CPU POWER

NO_TEST=TRUE

NC_CPU_VCCSA_VID

NO_TEST=TRUE

NC_CPU_VCCIO_VID

SNS_CPU_VCCIO_P
SNS_CPU_VCCIO_N

SNS_CPU_VAXG_N

SNS_CPU_VCORE_P

=PPVCCIO_S0_CPU

=PPVCORE_S0_CPU

=PPVCCSA_S0_CPU

SNS_CPU_VAXG_P

SNS_CPU_VCCSA

=PPVCORE_S0_CPU

SNS_CPU_VCORE_N

CPU_VIDALERT_R_L

CPU_VIDALERT_L

CPU_VIDSOUT

CPU_VIDSCLK_R

=PPVCCIO_S0_CPU

CPU_VIDSOUT_R

CPU_VIDSCLK

=PP1V5_S0_CPU_MEM

=PP1V8_S0_CPU_PLL

=PPVAXG_S0_CPU

U1000

A12
A13
A14
A15
A16
A18
A24
A25
A27
A28
B15
B16
B18
B24
B25
B27
B28
B30
B31
B33
B34
C15
C16
C18
C19
C21
C22
C24
C25
C27
C28
C30
C31
C33
C34
C36
D13
D14
D15
D16
D18
D19
D21
D22
D24
D25
D27
D28
D30
D31
D33
D34
D35
D36
E15
E16
E18
E19
E21
E22
E24
E25
E27
E28
E30
E31
E33
E34
E35
F15

A36

L32

A11
A7
AA3
AB8
AF8
AG33
AJ16
AJ17
AJ26
AJ28
AJ32
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK30
B9

D10

D6

E3
E4
G3
G4
J3
J4
J7
J8
L3
L4
L7
M13
N3
N4
N7
R3
R4
R7
U3
U4
U7
V8
W3

P33

AB4

T2

P34

A37

C37

B37

B36

M32

AB3

U1000

AB33
AB34
AB35
AB36
AB37
AB38
AB39
AB40
AC33
AC34
AC35
AC36
AC37
AC38
AC39
AC40

T33
T34
T35
T36
T37
T38
T39
T40
U33
U34
U35
U36
U37
U38
U39
U40
W33
W34
W35
W36
W37
W38
Y33
Y34
Y35
Y36
Y37
Y38

AK11
AK12

AJ13
AJ14

AU19
AU23
AU27
AU31
AV21
AV24
AV25
AV29
AV33
AW31

AJ20

AY23
AY26
AY28

AJ23
AJ24
AR20
AR21
AR22
AR23
AR24

U1000

F16
F18
F19
F21
F22
F24
F25
F27
F28
F30
F31
F32
F33
F34
G15
G16
G18
G19
G21
G22
G24
G25
G27
G28
G30
G31
G32
G33
H13
H14
H15
H16
H18
H19
H21
H22
H24
H25
H27
H28
H30
H31
H32
J12
J15
J16
J18
J19
J21
J22
J24
J25
J27
J28
J30
K15
K16
K18
K19
K21

K22
K24
K25
K27
K28
K30
L13
L14
L15
L16
L18
L19
L21
L22
L24
L25
L27
L28
L30
M14
M15
M16
M18
M19
M21
M22
M24
M25
M27
M28
M30

H10
H11

M12

H12
J10
K10
K11
L11
L12
M10
M11

A4
B3
AV39
AY37

R1311

1 2

R1310

1 2

R1312

1 2

R1300

1

2

R1302

1

2

051-9509

4.2.0

13 OF 113
13 OF 100

6

10 11 13 16 62

6

13 16 48 62

6

16

6

13 16 48 62

96

96

6

10 11 13 16 62

96

6

11 16

6

16

6

17 48 62

VSS_180

VSS_179

VSS_178

VSS_177

VSS_176

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_154

VSS_153

VSS_152

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_146

VSS_145

VSS_144

VSS_143

VSS_142

VSS_141

VSS_140

VSS_139

VSS_138

VSS_137

VSS_136

VSS_135

VSS_134

VSS_133

VSS_132

VSS_131

VSS_130

VSS_129

VSS_128

VSS_127

VSS_126

VSS_125

VSS_124

VSS_123

VSS_122

VSS_121

VSS_120

VSS_119

VSS_118

VSS_117

VSS_116

VSS_115

VSS_114

VSS_113

VSS_112

VSS_111

VSS_110

VSS_109

VSS_108

VSS_107

VSS_106

VSS_105

VSS_104

VSS_103

VSS_102

VSS_101

VSS_100

VSS_099

VSS_098

VSS_097

VSS_096

VSS_095

VSS_094

VSS_093

VSS_092

VSS_091

VSS_090

VSS_089

VSS_088

VSS_087

VSS_086

VSS_085

VSS_084

VSS_083

VSS_082

VSS_081

VSS_080

VSS_079

VSS_078

VSS_077

VSS_076

VSS_075

VSS_074

VSS_073

VSS_072

VSS_071

VSS_070

VSS_069

VSS_068

VSS_067

VSS_066

VSS_065

VSS_064

VSS_063

VSS_062

VSS_061

VSS_060

VSS_059

VSS_058

VSS_057

VSS_056

VSS_055

VSS_054

VSS_053

VSS_052

VSS_051

VSS_050

VSS_049

VSS_048

VSS_047

VSS_046

VSS_045

VSS_044

VSS_043

VSS_042

VSS_041

VSS_040

VSS_039

VSS_038

VSS_037

VSS_036

VSS_035

VSS_034

VSS_033

VSS_032

VSS_031

VSS_030

VSS_029

VSS_028

VSS_027

VSS_026

VSS_025

VSS_024

VSS_023

VSS_020

VSS_019

VSS_001
VSS_002
VSS_003
VSS_004
VSS_005

VSS_012

VSS_006
VSS_007
VSS_008
VSS_009
VSS_010
VSS_011

VSS_013
VSS_014
VSS_015

VSS_021
VSS_022

VSS_016
VSS_017
VSS_018

SYM 8 OF 10

VSS

VSS_360

VSS_359

VSS_358

VSS_357

VSS_356

VSS_355

VSS_354

VSS_353

VSS_352

VSS_351

VSS_350

VSS_349

VSS_348

VSS_347

VSS_346

VSS_345

VSS_344

VSS_343

VSS_342

VSS_341

VSS_340

VSS_339

VSS_338

VSS_337

VSS_336

VSS_335

VSS_334

VSS_333

VSS_332

VSS_331

VSS_330

VSS_329

VSS_328

VSS_327

VSS_326

VSS_325

VSS_324

VSS_323

VSS_322

VSS_321

VSS_320

VSS_319

VSS_318

VSS_317

VSS_316

VSS_315

VSS_314

VSS_313

VSS_312

VSS_311

VSS_310

VSS_309

VSS_308

VSS_307

VSS_306

VSS_305

VSS_304

VSS_303

VSS_302

VSS_301

VSS_300

VSS_299

VSS_298

VSS_297

VSS_296

VSS_295

VSS_294

VSS_293

VSS_292

VSS_291

VSS_290

VSS_289

VSS_288

VSS_287

VSS_286

VSS_285

VSS_284

VSS_283

VSS_282

VSS_281

VSS_280

VSS_279

VSS_278

VSS_277

VSS_276

VSS_275

VSS_274

VSS_273

VSS_272

VSS_271

VSS_270

VSS_269

VSS_268

VSS_267

VSS_266

VSS_265

VSS_264

VSS_263

VSS_262

VSS_261

VSS_260

VSS_259

VSS_258

VSS_257

VSS_256

VSS_255

VSS_254

VSS_253

VSS_252

VSS_251

VSS_250

VSS_249

VSS_248

VSS_247

VSS_246

VSS_245

VSS_244

VSS_243

VSS_242

VSS_241

VSS_240

VSS_239

VSS_238

VSS_237

VSS_236

VSS_235

VSS_234

VSS_233

VSS_232

VSS_231

VSS_230

VSS_229

VSS_228

VSS_227

VSS_226

VSS_225

VSS_224

VSS_223

VSS_222

VSS_221

VSS_220

VSS_219

VSS_218

VSS_217

VSS_216

VSS_215

VSS_214

VSS_213

VSS_212

VSS_211

VSS_210

VSS_209

VSS_208

VSS_207

VSS_206

VSS_205

VSS_204

VSS_203

VSS_202

VSS_201

VSS_196

VSS_195

VSS_194

VSS_200

VSS_199

VSS_198

VSS_197

VSS_188

VSS_193

VSS_192

VSS_191

VSS_190

VSS_189

VSS_182

VSS_187

VSS_186

VSS_181

VSS_185

VSS_184

VSS_183

SYM 9 OF 10

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

CPU GROUNDS

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

U1000

A17
A23
A26
A29

A35
AA33
AA34
AA35
AA36
AA37
AA38

AA6

AB5

AC1

AC6
AD33
AD36
AD38
AD39
AD40

AD5

AD8

AE3
AE33
AE36

AF1
AF34
AF36
AF37
AF40

AF5

AF6

AF7
AG36

AH2

AH3
AH33
AH36
AH37
AH38
AH39
AH40

AH5

AH8
AJ12
AJ15
AJ18
AJ21
AJ25
AJ27
AJ36

AJ5

AK1
AK10
AK13
AK14
AK16
AK22
AK28
AK31
AK32
AK33
AK34
AK35
AK36
AK37

AK4
AK40

AK5

AK6

AK7

AK8

AK9
AL11
AL14
AL17
AL19
AL24
AL27
AL30
AL36

AL5

AM1
AM11
AM14
AM17

AM2
AM21
AM23
AM25

AM27
AM3
AM30
AM36
AM37
AM38
AM39
AM4
AM40
AM5
AN10
AN11
AN14
AN17
AN19
AN22
AN24
AN27
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN5
AN6
AN7
AN8
AN9
AP1
AP11
AP14
AP17
AP22
AP25
AP27
AP30
AP36
AP37
AP4
AP40
AP5
AR11
AR14
AR17
AR18
AR19
AR27
AR30
AR36
AR5
AT1
AT10
AT12
AT13
AT15
AT16
AT17
AT2
AT25
AT27
AT28
AT29
AT3
AT30
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AT39
AT4
AT40
AT5
AT6
AT7
AT8
AT9
AU1
AU15
AU26
AU34
AU4
AU6
AU8
AV10

U1000

AV11
AV14
AV17

AV3
AV35
AV38

AV6
AW10
AW11
AW14
AW16
AW36

AW6
AY11
AY14
AY18
AY35

AY4

AY6

AY8

B10

B13

B14

B17

B23

B26

B29

B32

B35

B38

B6
C11
C12
C17
C20
C23
C26
C29
C32
C35

C7

C8
D17

D2
D20
D23
D26
D29
D32
D37
D39

D4

D5

D9
E11
E12
E17
E20
E23
E26
E29
E32
E36

E7

E8

F1
F10
F13
F14
F17

F2
F20
F23
F26
F29
F35
F37
F39

F5

F6

F9
G11
G12
G17
G20
G23
G26
G29
G34

G7

G8
H1
H17
H2
H20
H23
H26
H29
H33
H35
H37
H39
H5
H6
H9
J11
J17
J20
J23
J26
J29
J32
K1
K12
K13
K14
K17
K2
K20
K23
K26
K29
K33
K35
K37
K39
K5
K6
L10
L17
L20
L23
L26
L29
L8
M1
M17
M2
M20
M23
M26
M29
M33
M35
M37
M39
M5
M6
M9
N8
P1
P2
P36
P38
P40
P5
P6
R33
R35
R37
R39
R8
T1
T5
T6
U8
V1
V2
V33
V34
V35
V36
V37
V38
V39
V40
V5
W6
Y5
Y8

051-9509

4.2.0

14 OF 113
14 OF 100

IN

OUT

S

G

D

OUT

D

G S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10 = 2x8 0 = REV 0 = REV
00 = 1x8,2x4

11 = 1x16 (default) 1 = DIR 1 = DIR

IVB PCIe Straps configuration:

CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16

UNUSED clock terminations for FCIM MODE

DP_AUXIO_EN Inversion

Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP

402

5%

10K

1/16W MF-LF

5%

1/16W MF-LF

402

10K

MF-LF

5%

10K

1/16W

402

5%

10K

MF-LF

402

1/16W

5%

MF-LF

10K

1/16W

402

MF-LF

5%

10K

1/16W

402

1/16W MF-LF

5%

10K

402

MF-LF1/16W

402

5%

10K

5%

MF-LF1/16W

10K

402

10K

MF-LF1/16W

402

5%

1/16W5%MF-LF

10K

402

5%

402

NOSTUFF

1/16W MF-LF

1K

5%

1K

1/16W

NOSTUFF

MF-LF

402

MF-LF

1K

5%

1/16W

U1000.18:3mm

402

1/16W1KMF-LF5%402

10K

5%

1/16W

402

MF-LF

402

1/16W

100K

MF-LF

5%

10K

1/16W MF-LF5%402

MF-LF1/16W

5%

402

20K

1/16W MF-LF

5%

10K

402

1/16W MF-LF

5%

10K

402

PLACE_NEAR=U1800.AG56:5mm

5%

MF-LF1/16W

10K

402

PLACE_NEAR=U1800.R33:5mm

5%

MF-LF1/16W

10K

402

5%

MF-LF1/16W

10K

402

5%

MF-LF1/16W

10K

402

PLACE_NEAR=U1800.P33:5mm

5%

MF-LF1/16W

10K

402

PLACE_NEAR=U1800.AF55:5mm

MF-LF1/16W

5%

10K

402

5%

MF-LF1/16W

10K

402

PLACE_NEAR=U1800.BF38:5mm

5%

MF-LF1/16W

10K

402

PLACE_NEAR=U1800.BD38:5mm

5%

MF-LF1/16W

10K

402

1/16W

5%

10K

402

MF-LF

402

5%

MF-LF

10K

1/16W

1/16W

402

5%

10K

MF-LF

MF-LF1/16W

10K

402

5%

5%

1/16W

10K

MF-LF

402

5%

MF-LF1/16W

10K

402

MF-LF

402

10K

1/16W

5%

402

MF-LF1/16W

10K

5%

402

10K

1/16W MF-LF

5%

402

5%

MF-LF1/16W

10K

10K

402

MF-LF

5%

1/16W

402

10K

1/16W MF-LF

5%

MF-LF

5%

1/16W1K402

1/16W1K402

MF-LF

5%

402

1K

5%

MF-LF1/16W

NOSTUFF

402

MF-LF

5%

4.7K

1/16W

MF-LF1/16W

402

5%

10K

MF-LF

5%

1/16W

10K

402

10K

402

1/16W5%MF-LF

1/16W

10K

5%

MF-LF

402

10K

402

1/16W5%MF-LF

402

1/16W MF-LF

5%

1K

402

5%

MF-LF1/16W

10K

5%

402

1/16W

10K

MF-LF

MF-LF

5%

1/16W

10K

402

44

18 92

330

PLACE_NEAR=R1805.4:3mm

5%

1/16W MF-LF

402

NTR1P02L

SOT23-3-HF

MF-LF

100K

5%

1/16W

402

100K

5%

1/16W MF-LF

402

MF-LF

1/16W

5%

10K

402

402

10K

5%
1/16W
MF-LF

84 85

CRITICAL

VESM

SSM3K15AMFVAPE

402

5%
MF-LF

1/16W

10K

10K

5%

MF-LF1/16W

402

5%

MF-LF

402

10K

1/16W

402

MF-LF

1/16W

5%

0

NOSTUFF

0

1/16W

NOSTUFF

MF-LF

402

5%

SYNC_MASTER=D7_TONY

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

SYNC_DATE=01/11/2012

SSD_CLKREQ_L

ENET_CLKREQ_L

=PP3V3_S4_SDCARD

USB_EXTD_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB_EXTB_OC_EHCI_L

USB_EXTD_OC_EHCI_L

=PP3V3_S5_PCH_STRAPS

ITPCPU_CLK100M_N

PCH_GPIO48

DP_AUXIO_EN

DP_AUXCH_ISOL

PCH_GPIO1

=PP3V3_S0_PCH_STRAPS

MLB_RAM_CFG0

SMC_RUNTIME_SCI_L

MLB_RAM_CFG1

PCH_SPKR

PEG_CLKREQ_L

AP_CLKREQ_L

TBT_CLKREQ_L

CPU_CFG<2>

HDA_SYNC

JTAG_TBT_TDI

=PP3V3_S4_PCH

=PP3V3_S0_LED_SATA

PCH_SATALED_L

ITPCPU_CLK100M_PITPXDP_CLK100M_P

ITPXDP_CLK100M_N

PCH_GPIO29

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S5_PCH_STRAPS

CPU_CFG<6>

CPU_CFG<3>

CPU_CFG<5>

TBT_PWR_REQ_L

=PP3V3_S0_PCH_GPIO

PCH_CLKIN_GND0

PCH_CLKIN_GND1

PCH_CLK100M_DMIN

PCH_CLK100M_SATAP

PCH_CLK96M_DOTN

PCH_GPIO72

PCH_CLK96M_DOTP

PCH_CLK100M_SATAN

PCH_CLK100M_DMIP

PCH_CLK14P3M_REFCLK

PCH_GPIO22

PCH_GPIO6

ENET_MEDIA_SENSE

WOL_EN

TBT_CIO_PLUG_EVENT

ENET_LOW_PWR_PCH

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

=PP3V3_S0_PCH_STRAPS

TBT_GO2SX_BIDIR

SMC_WAKE_SCI_L

PM_PWRBTN_L

PCH_SMBALERT_L

JTAG_TBT_TMS

BT_PWR_RST_L

HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE_R

JTAG_TBT_TDO

=PP3V3_TBT_PCH_GPIO

TBT_SW_RESET_R_L

JTAG_TBT_TCK

SDCONN_STATE_CHANGE

PCH_CAM_RESET

SATARDRVR_EN

PCH_SUSWARN_L

=PP3V3_S0_PCH_STRAPS

DP_AUXCH_ISOL

PCH_CAM_EXT_BOOT

USB_EXTC_OC_L

=PP3V3_S5_PCH_STRAPS

AP_PWR_EN

=PP3V3_S0_PCH_STRAPS

NOSTUFF

NOSTUFF

R1554

1 2

R1553

1 2

R1501

1 2

R1504

1 2

R1563

1 2

R1509

1 2

R1510

1 2

R1511

1 2

R1525

1 2

R1528

1 2

R1527

1 2

R1526

1 2

R1524

1 2

R1512

1 2

R1513

1 2

R1523

1 2

R1522

1 2

R1531

1 2

R1570

1 2

R1533

1 2

R1532

1 2

R1530

1 2

R1555

1 2

R1545

1 2

R1547

1 2

R1550

1 2

R1551

1 2

R1548

1 2

R1546

1 2

R1549

1 2

R1543

1 2

R1544

1 2

R1560

1 2

R1561

1 2

R1562

1 2

R1559

1 2

R1542

1 2

R1557

1 2

R1558

1 2

R1517

1 2

R1520

1 2

R1519

1 2

R1518

1 2

R1516

1 2

R1537

1 2

R1536

1 2

R1514

1 2

R1529

1 2

R1538

1 2

R1540

1 2

R1539

1 2

R1541

1 2

R1508

1 2

R1564

1 2

R1521

1 2

R1502

1 2

R1503

1 2

R1552

1 2

Q1500

3

1

2

R1571

1 2

R1572

1 2

R1505

1

2

R1556

1

2

Q1509

3

1

2

R1507

1

2

R1590

1 2

R1567

1 2

051-9509

4.2.0

15 OF 113
15 OF 100

18 41

18 37

6

39

20 43

20 42

20 42

20

20

6

15

11 91

21

15 18

21

6

15

21

21 44

21

18

18 71

21 33

21 36

10 25 91

18 52 92

21 34

6

6

41

18 41

11 91 18 25 91

18 25 91

19

6

15

10 25 91

10 25 91

10 25 91

20 34

6

19 20 36

18

18

18

18

18

19

18

18

18

18

21

21

18 37 93

21 38

21 34

21 26

19 33 44 60

19 44 60

19 28 38 44 45 60

6

15

21 34

21 44

19 25 44

18

18 34

20

20 33

21 34

6

21

21 34

20 39

21

18

19

6

15

15 18

6

15

21

20 43

6

15

33

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10x 10UF and 10x 1UF CAPACITORS

BULK CAPS ON CPU VREG PAGE 72

PLACEMENT_NOTE (C1600-C1613):

14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)

BULK CAPS ON CPU VREG PAGE 74

PLL (CPU VCCSFR) DECOUPLING

2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 1x 10uF 0805

BULK CAPS ON VTT REG PAGE 77

PLACEMENT_NOTE (C1660-C1665):

CPU VCCIO DECOUPLING

8X 22UF 0805, 6X 10UF 0805

Memory (CPU VCCDDR) DECOUPLING

INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders

CPU VCORE DECOUPLING

Bulk decoupling is on VCCSA reg page 75

PLACEMENT_NOTE (C1650-C1657):

CPU VCCSA DECOUPLING

2x 10uF 0603. INTEL RECOMMENDATION 2X 10uF 0805

10V

10%

402

X5R

1UF

6.3V

10%

402

X5R

2.2UF

603

X5R-CERM

6.3V

10%

4.7UF

6.3V

20%

805

CERM-X5R

22uF

CERM-X5R

6.3V

20%

805

22uF

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

10V

20%

603

X5R

10UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

16V

10%
402

X5R

1UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

330UF-0.0045OHM

POLY
CASE-D2-SM

20%
2V

47UF

6.3V

20%

0805

X5R

6.3V

20%

603

X5R

10UF

20%

0805

6.3V
X5R

47UF

CERM-X5R

6.3V

20%

805

22uF

805

CERM-X5R

20%

22uF

6.3V6.3V

20%

805

CERM-X5R

22uF22uF

6.3V
CERM-X5R

20%

805

6.3V

20%

0201

X5R

1UF

6.3V

20%

0201

X5R

1UF

6.3V

20%

0201

X5R

1UF

6.3V

20%

0201

X5R

1UF 1UF

6.3V

20%

0201

X5R

NOSTUFF

POLY
CASE-D2-SM

2V

20%

330UF-0.0045OHM

603

10uF

X5R

20%

6.3V

603

6.3V

20%
X5R

10uF

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

Place under socket cavity on secondary side.

6.3V

20%

805

CERM-X5R

22UF

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%
805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805

CERM-X5R

22UF

Place under socket cavity on secondary side.

6.3V

20%

805

CERM-X5R

22UF

Place under socket cavity on secondary side.

6.3V

20%

805

CERM-X5R

22UF

Place under socket cavity on secondary side.

6.3V

20%

805

CERM-X5R

22UF

Place under socket cavity on secondary side.

6.3V

20%

805

CERM-X5R

22UF

Place under socket cavity on secondary side.

22UF

CERM-X5R

6.3V

20%

805

Place under socket cavity on secondary side.

6.3V

20%

805

CERM-X5R

22UF

Place under socket cavity on secondary side.

Place at edge of socket.

10uF

X5R
603

20%

6.3V

Place at edge of socket.

10uF

X5R
603

20%

6.3V6.3V

20%
603

X5R

10uF

Place at edge of socket.

603

X5R

6.3V

20%

10uF

Place at edge of socket.

6.3V

20%
603

X5R

10uF

Place at edge of socket.

10uF

6.3V

20%
603

X5R

Place at edge of socket.

6.3V

22uF

20%

805

CERM-X5R

10V

10%

402

X5R

1UF

SYNC_MASTER=K70_MLB

CPU NON-GFX DECOUPLING

SYNC_DATE=11/30/2011

=PPVCCSA_S0_CPU

=PPVCCIO_S0_CPU

=PP1V5_S0_CPU_MEM

=PPVCORE_S0_CPU

=PP1V8_S0_CPU_PLL

=PPVCORE_S0_CPU

C1650

1

2

C1600

1

2

C1601

1

2

C1602

1

2

C1603

1

2

C1604

1

2

C1605

1

2

C1606

1

2

C1651

1

2

C1652

1

2

C1653

1

2

C1654

1

2

C1655

1

2

C1656

1

2

C1657

1

2

C1665

1

2

C1664

1

2

C1663

1

2

C1662

1

2

C1661

1

2

C1660

1

2

C1680

1

2

C1694

1

2

C1693

1

2

C1692

1

2

C1691

1

2

C1690

1

2

C1681

1

2

C1609

1

2

C1608

1

2

C1607

1

2

C1613

1

2

C1612

1

2

C1611

1

2

C1610

1

2

C1629

1

2

C1628

1

2

C1627

1

2

C1626

1

2

C1624

1

2

C1623

1

2

C1622

1

2

C1621

1

2

C1620

1

2

C1630

1

2

C1625

1

2

C1631

1

2

C1632

1

2

C1633

1

2

C1634

1

2

C1635

1

2

C1636

1

2

C1637

1

2

C1638

1

2

C1639

1

2

C1670

1

2

C1696

1

2

C1695

1

2

C1697

1

2

C1679

1

2

C1678

1

2

C1677

1

2

C1676

1

2

C1682

1

2

C1683

1

2

C1684

1

2

C1685

1

2

C1686

1

2

C1687

1

2

C1667

1

2

C1666

1

2

051-9509

4.2.0

16 OF 113
16 OF 100

6

13

6

10 11 13

62

6

11 13

6

13 16

48 62

6

13

6

13 16 48 62

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF

VAXG DECOUPLING

PLACEMENT_NOTE (C1704-C1709):

BULK CAPS ON CPU VREG PAGE 73

1/16W

5%

402

MF-LF

0

0

MF-LF

402

5%

1/16W

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

20%

805-3

CERM-X5R

22UF

Place inside socket cavity

6.3V

10%

603

X5R-CERM

Place inside socket cavity

4.7UF

X5R-CERM

4.7UF

6.3V

10%

603

Place inside socket cavity

6.3V

10%

603

4.7UF

Place inside socket cavity

X5R-CERM

1/16W

5%

MF-LF

0

402

X5R

6.3V

20%

603

CRITICAL

10UF

IG:Y

X5R

0.1UF

16V
402

10%

IG:Y

CERM

0.01UF

10%

402

16V

IG:Y

TANT

2.5V

20%

220UF

B16

CRITICAL

IG:Y

TANT

2.5V

20%

220UF

B16

CRITICAL

IG:Y

1UF

6.3V
CERM

10%

402

NOSTUFF

1UF

10%

6.3V
CERM
402

NOSTUFF

10UH-0.12A-0.36OHM

0603

CRITICAL

OMIT_TABLE

0603

CRITICAL

10UH-0.12A-0.36OHM

OMIT_TABLE

RES,MF,1/10W,0OHM,5,0603,SMD,LF

113S0022 IG:N

2

L1730,L1740

CRITICAL

IND,WW,10UH,20%.120MA,0.36OHMS

152S1070

2

L1730,L1740

IG:Y

SYNC_DATE=11/30/2011

SYNC_MASTER=K70_MLB

GFX DECOUPLING & PCH PWR ALIAS

PP1V05_S0_PCH_VCCADPLLA_F

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4MM

PP1V05_S0_PCH_VCCADPLLA_R

MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4MM

PP1V05_S0_PCH_VCCADPLLB_R

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCC_ADPLL

=PP3V3_S0_PCH_VCC_ADAC

=PPVAXG_S0_CPU

R1730

1 2

R1740

1 2

C1709

1

2

C1708

1

2

C1707

1

2

C1706

1

2

C1705

1

2

C1704

1

2

C1710

1

2

C1711

1

2

C1712

1

2

R1720

1 2

C1720

1

2

C1721

1

2

C1722

1

2

C1730

1

2

C1740

1

2

C1731

1

2

C1741

1

2

L1730

1 2

L1740

1 2

051-9509

4.2.0

17 OF 113
17 OF 100

22 24

22 24

22

6

6

6

13 48 62

IN

IN

OUT

OUT

OUT

IN

BI

IN

IN
OUT
OUT

IN

IN
OUT
OUT

IN
IN

IN
IN

IN
IN

OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

OUT
OUT

OUT

OUT

OUT

OUT

IN

IN

IN
IN

IN
IN

IN

IN

IN

OUT

OUT

BI

OUT

BI

IN

IN
OUT
OUT

OUT
OUT

IN

OUT

BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT

BI

BI

BI

BI

OUT

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

SATA3RXP

HDA_SYNC

INTRUDER*

LDRQ1*/GPIO23

SATA1TXN

SATA3RXN

SATA1RXN

SATA1TXP

SATA0RXN

SERIRQ

FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME*

SATA1RXP

SATA2TXN
SATA2TXP

SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN

SATA5TXN
SATA5TXP

SATAICOMPO
SATAICOMPI

SATALED*

SATA0GP/GPIO21
SATA1GP/GPIO19

L_BKLTCTL

HDA_RST*

SPKR

HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

GPIO33
GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_MOSI

SPI_MISO

RTCX1
RTCX2

SATA0TXP

SATA0TXN

SATA2RXN
SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

L_BKLTEN
L_VDD_EN

FWH0/LAD0

INTVRMEN

SPI_CS1*

HDA_SDIN0

SRTCRST*

SPI_CLK

RTCRST*

HDA_BCLK

(1 OF 10)

LPC

RTC

IHDA

SATA

JTAG

SPI

CLKIN_DMI_P

PETN2

CLKOUT_PEG_A_N

CL_RST1*

CLKIN_DMI_N

PERP3

CLKOUT_PEG_B_N

CLKIN_DOT_96P

CL_DATA1

CL_CLK1

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_GND0_P

CLKOUT_ITPXDP_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

XTAL25_OUT

XTAL25_IN

CLKIN_PCILOOPBACK

REFCLK14IN

CLKIN_SATA_P

CLKIN_DOT_96N

CLKOUT_DP_N
CLKOUT_DP_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_PEG_A_P

SMBCLK

SMBALERT*/GPIO11

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0ALERT*/GPIO60

SML0CLK

SMBDATA

PERN3

PETP2

CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE4P

CLKOUT_PCIE5N

CLKOUT_PCIE3P

CLKOUT_PCIE4N

CLKOUT_PCIE3N

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1N
CLKOUT_PCIE1P

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PETP8

PERP8
PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6
PETP6

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP2

CLKIN_SATA_N

CLKIN_GND0_N

CLKOUT_ITPXDP_P

CLKOUT_PEG_B_P

PETN5
PETP5

PERN6
PERP6

PERP1

PERN1

PETN1
PETP1

PERN2

FLEX

CLOCK

PCI-E*

PEG

FROM CLK BUFFER

SMBUS

(2 0F 10)

OUT

OUT

OUT
OUT
OUT
OUT

OUT
OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DOES THIS NEED LENGTH MATCH???

PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

26 92

52 92

46 92

46 92

46 92

46 92

44 46

41 91

41 91

41 91

41 91

41 91

41 91

41 91

41 91

41 90

41 90

41 90

41 90

37 90

37 90

41 90

41 90

41 90

41 90

37 90

37 90

41 90

41 90

33 90

33 90

34 90

34 90

15 71

11 90

11 90

8

8

8

8

15

15

15

15

15

15

15

26 92

26 92

26 92

47 94

47 94

47 94

47 94

33 90

33 90

33 90

33 90

PLACE_NEAR=U1800.AJ53:2mm

37.4

MF-LF

1%

402

1/16W

MF-LF
402

5%
1/16W

10K

37 90

37 90

1/16W

PLACE_NEAR=U1800.AL2:2mm

MF-LF

402

1%

90.9

18

47

47

8

8

71 89

71 89

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

34 90

PLACE_NEAR=U1800.AC52:2mm

1/16W

750

MF-LF

1%

402

49.9

1%
1/16W

402

MF-LF

PLACE_NEAR=U1800.AE52:2mm

8

8

5%

402

MF-LF

33

1/16W

44 46 92

44 46 92

1/16W

33

5%

402

MF-LF

44 46 92

5%

MF-LF

402

33

1/16W

44 46 92

1/16W

33

5%

402

MF-LF

44 46
92

PANTHER-POINT

OMIT_TABLE

FCBGA

PANTHER-POINT

FCBGA

OMIT_TABLE

MF-LF

33

5%

402

1/16W

20K

1/16W

5%

402

MF-LF

402

5%

1/16W

20K

MF-LF

1UF

X5R

10V

402

10%

1UF

10V

10%

402

X5R

1M

1/16W

5%

MF-LF
402

MF-LF

5%

1/16W

402

390K

42

43

52 92

52 92

15 52 92

52 92

33

1/16W
SM-LF

5%

5%

402

1/16W
MF-LF

0

MF-LF

1/16W

402

5%

NOSTUFF

0

15

15

SIGNAL_MODEL=EMPTY

0

5% MF

201

1/20W

SIGNAL_MODEL=EMPTY

1/20W

0

5%

201

MF

SYNC_DATE=11/30/2011

SYNC_MASTER=K70_MLB

PCH SATA/PCIE/CLK/LPC/SPI

NO_TEST=TRUE

NC_SPI_CS1_L

PCIE_CLK100M_AP_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_D2R_N<1>

PCIE_AP_D2R_N

PEG_CLKREQ_L

TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P

PEG_CLK100M_N
PEG_CLK100M_P

PCIE_CLKREQ5_GPIO44_L

PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P

TP_SATA_E_D2RN

=PP1V05_S0_PCH_VCCIO_SATA

PCH_SATALED_L

TP_SATA_F_R2D_CP

TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP

TP_SATA_D_D2RP

TP_PCH_GPIO65_CLKOUTFLEX1

PCH_CLK25M_XTALIN

SATARDRVR_EN

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCH_SMBALERT_L

SMBUS_PCH_CLK
SMBUS_PCH_DATA

PCIE_CLKREQ5_GPIO44_L

PCIE_CLK100M_TBT_N

DMI_MIDBUS_CLK100M_N
DMI_MIDBUS_CLK100M_P

PCH_CLK100M_SATAP

TP_PCH_CL_CLK1

PCIE_TBT_D2R_N<3>
PCIE_TBT_D2R_P<3>
PCIE_TBT_R2D_C_N<3>
PCIE_TBT_R2D_C_P<3>

PCIE_CLK100M_AP_P

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_D2R_P<1>

PCIE_AP_D2R_P

PCIE_TBT_R2D_C_P<2>

ITPXDP_CLK100M_P

TP_PCH_CLKOUT_DPN

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D_C_P<0>

DMI_CLK100M_CPU_N

TP_CLKOUT_PEG_A_P

TP_CLKOUT_PEG_A_N

PCIE_SSD_R2D_C_N<0>

SPI_CS0_R_L

=PP1V05_S0_PCH_VCCIO_PCIE

PCH_CLKIN_GND0

PCH_CLKIN_GND1

PCH_XCLK_RCOMP

ITPXDP_CLK100M_N

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO64_CLKOUTFLEX0

PCH_CLK25M_XTALOUT

PCH_CLK33M_PCIIN

SML_PCH_1_CLK

USB_EXTD_SEL_XHCI

SML_PCH_0_DATA

USB_EXTB_SEL_XHCI

PCIE_CLK100M_TBT_P

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_D2R_N<0>

PCH_SATAICOMP

PCH_SATA3RBIAS

TP_SATA_D_D2RN

TP_SATA_C_R2D_CN

TP_SATA_D_R2D_CN

TP_SATA_E_D2RP

JTAG_TBT_TMS

TP_SATA_C_D2RN

PCH_INTVRMEN

PCH_SRTCRST_L

RTC_RESET_L

HDA_BIT_CLK_R

SPI_CLK_R

SPI_MISO

LPC_R_AD<3>

LPC_AD<3>

LPC_R_AD<1>

LPC_R_AD<0>

LPC_AD<0>

LPC_R_AD<2>

LPC_AD<2>

LFRAME_L

LPC_FRAME_L

PCH_CLK32K_RTCX2

=PP3V3_S0_PCH

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

HDA_SDIN0

HDA_SDOUT
HDA_BIT_CLK

PCH_INTRUDER_L
PCH_INTVRMEN

RTC_RESET_L
PCH_SRTCRST_L

TP_PCH_CL_DATA1

HDA_RST_R_L

TP_SATA_C_R2D_CP

TP_HDA_SDIN1

ENET_CLKREQ_L

SSD_CLKREQ_L

PCH_CLK32K_RTCX1

SATA_SSD_D2R_N

LPC_SERIRQ

TBT_PWR_EN_PCH

TP_LPC_DREQ0_L

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCH_CLK100M_DMIP

HDA_RST_L

HDA_SYNC

HDA_SYNC_R

PCH_CLK100M_SATAN

PCIE_TBT_D2R_N<2>

PCH_CLK96M_DOTP

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_P<0>

=PP3V3_G3_PCH

TP_PCH_L_BKLTCTL

TP_PCH_L_BKLTEN

TP_SATA_F_D2RN

SML_PCH_1_DATA

PCH_CLK96M_DOTN

TP_PCH_CL_RST1

PCH_INTRUDER_L

SATA_HDD_D2R_P
SATA_HDD_R2D_C_N

SATA_SSD_D2R_P

TP_SATA_C_D2RP

HDA_SDOUT_R
HDA_BIT_CLK_R

PCH_SATA3COMP

TP_SATA_D_R2D_CP

SPI_MOSI_R

SATA_SSD_R2D_C_P

SATA_SSD_R2D_C_N

LPC_AD<1>

TP_PCH_L_VDD_EN

TP_SATA_F_D2RP
TP_SATA_F_R2D_CN

SATARDRVR_EN_R

DP_AUXCH_ISOL_R

DP_AUXCH_ISOL

PCH_CLK100M_DMIN

DMI_CLK100M_CPU_P

SML_PCH_0_CLK

=PP1V05_S0_PCH

PCH_CLK14P3M_REFCLK

XDP_PCH_TDO

HDA_SDOUT_R

XDP_PCH_TCK

TP_PCH_CLKOUT_DPP

ENET_MEDIA_SENSE

TP_HDA_SDIN3

TP_HDA_SDIN2

HDA_RST_R_L

PCH_SPKR

HDA_SYNC_R

XDP_PCH_TMS

XDP_PCH_TDI

R1830

1

2

R1820

1

2

R1890

1

2

R1832

1

2

R1831

1

2

R1860

1 2

R1861

1 2

R1862

1 2

R1863

1 2

U1800

BK15
BJ17
BJ20
BG20

BG17

BA25

BC25

BU22

BC22

BD22
BF22
BK22
BJ22

BT23

BP23

BM38

BN41

BA43

BC52

BF47

BC50

AG12
AG18
AG17

BK17
BA20

BT41

BR39
BN39

BC54

AC56
AB55
AE46
AE44

AY52

AA53
AA56
AG49
AG47

AL50
AL49
AL56
AL53

AE54

AC52

AE52

AN46
AN44
AN56
AM55

AN49
AN50
AT50
AT49

AT46
AT44
AV50
AV49

AJ55

AJ53

BF57

AV52

AR54

AT57

AR56

AT55

AU53

BE56

BN37

U1800

BA50

BF50

BF49

P33
R33

BD38
BF38

W53
V52

R27
P27

BD15

AF55
AG56

P31
R31

N56
M55

R52
N52

AE6
AC6

AA5

W5

AB12
AB14

AB9
AB8

Y9
Y8

AF3
AG2

AG8
AG9

AE12
AE11

AT9

BA5

AW5

BA2

AV43

BL54

J20

P20

H17

P17

N15

J15

J12

H10

L20

R20

J17

M17

M15

L15

H12

J10

F25

C22

E21

F18

B17

A16

F15

B13

F23

A22

B21

E17

C16

B15

F13

D13

AN8

BN49

BT47
BR49

BU49

BT51
BM50

BR46

BJ46
BK46

AL2

AJ3
AJ5

R1864

1 2

R1803

1

2

R1802

1

2

C1803

1

2

C1802

1

2

R1801

1

2

R1800

1

2

R1805

1
2
3
4

8
7
6
5

R1851

1 2

R1852

1 2

R1841

1 2

R1842

1 2

051-9509

4.2.0

18 OF 113
18 OF 100

8

6

22 24

15 41

8

8

8

8

8

15

18

8

15 25 91

6

19 22

15

15

92

15 25 91

8

8

8

8

91

91

8

8

8

8

15 34

8

18

18

18 45

18 92

92

92

92

92

6

21 24

18 45

18

8

18 92

8

8

15 37

15 41

26

8

18 92

6

19

8

8

8

8

18

8

15 18 92

18 92

91

8

8

8

8

25

25

6

24

25 91

15 18 92

25 91

15 37 93

8

8

18 92

15

18 92

25 91

25 91

IN

OUT

OUT
OUT

OUT
OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

INIT3_3V*

GPIO32

DMI2TXP

PWRBTN*

RSMRST*

SYS_RESET*

DMI3RXN

DMI2RXN

DMI2RXP
DMI3RXP

DMI_ZCOMP

SUSACK*

SLP_SUS*

DSWVRMEN

DF_TVS

SLP_LAN*/GPIO29

PMSYNCH

SLP_A*

SLP_S3*

SLP_S4*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

FDI_LSYNC0

FDI_FSYNC1

FDI_INT

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP1

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

FDI_RXN0

RI*

SUSWARN*/GPIO30

PWROK

SYS_PWROK

DMI_IRCOMP

DMI2RBIAS

DMI1TXN

DMI0TXN

DMI1RXP

DMI0RXP

FDI_RXP0

FDI_LSYNC1

DMI0RXN

FDI_RXP2

DMI1RXN

FDI_FSYNC0

APWROK

DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP

GPIO31
GPIO72

DMI3TXP

SLP_S5*/GPIO63

WAKE*

DPWROK

DRAMPWROK

DMI

FDI

(3 OF 10)

SYSTEM POWER

MANAGEMENT

DDPB_AUXN
DDPB_AUXP

DDPB_0P
DDPB_1N
DDPB_1P

DDPB_3N
DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N

DDPD_3P

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_HPD

DDPB_0N

DDPB_2N
DDPB_2P

DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_2P
DDPD_3N

RESERVED

(4 OF 10)

CRT

DIGITAL DISPLAY INTERFACE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE CLOSE TO U1800 PIN

SHORT THESE TWO PINS VERY NEAR THE PINS
PLACE THE RESISTOR VERY CLOSE TO COMMON POINT

KEEPING TP, IF NEED TO USE IT LATER

10 90

8

8

8

8

8

PLACE_NEAR=U1800.E31:2mm

49.9

MF-LF

402

1%

1/16W

19 33 38

45 92

15 33 44 60

15 44 60

15 28 38 44 45 60

11 28

61

15 25 44

61

26 61

45 61

25 26 44

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

10 90

5%
1/16W
MF-LF

402

10K

11

26 44 46

402

1/16W

1%

1K

MF-LF

MF-LF

1/16W

5%

1K

402

PLACE_NEAR=U1800.AT3:3mm

5%

10K

1/16W
MF-LF

402

390K

5%

402

1/16W

MF-LF

PLACE_NEAR=U1800.A32:2mm

MF-LF
402

1/16W

1%

750

5%

2.2K

402

MF-LF

1/16W

4.7K

5%
1/16W
MF-LF

402

OMIT_TABLE

PANTHER-POINT

FCBGA

OMIT_TABLE

PANTHER-POINT

FCBGA

5%

10K

402

MF-LF

1/16W

1/16W

5%

402

MF-LF

10K

PCH DMI/FDI/GRAPHICS

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

MAKE_BASE=TRUE

PCIE_WAKE_L

PM_RSMRST_PCH_L

PCH_SUSWARN_L

PCH_GPIO31_ACPRESENT

PCH_DF_TVS

PM_SLP_S4_L

PCH_GPIO29

PCH_DSWVRMEN

PCH_FDI_FSYNC<0>

DMI_N2S_N<2>

PCH_GPIO32

LPC_PWRDWN_L

PCIE_WAKE_L

PCH_FDI_LSYNC<1>

DP_IG_D_CTRL_DATA

TP_PCH_RESERVE_6

TP_PCH_RESERVE_14

DP_IG_D_CTRL_CLK

TP_PCH_RESERVE_11

TP_PCH_RESERVE_10

TP_PCH_RESERVE_9

DP_IG_B_MLN<2>

PCH_RI_L

=PP3V3_G3_PCH

TP_PM_SLP_A_L

DP_IG_C_MLP<3>

DP_IG_B_MLP<3>

PCH_DSWVRMEN

PCH_DF_TVS

TP_PCH_SUSACK_L

=PP3V3_S5_PCH

DMI_S2N_P<0>

PM_PCH_APWROK

=PP1V05_S0_PCH_VCCIO_PCIE

PM_PCH_PWROK

PM_MEM_PWRGD

PM_SYSRST_L

DMI_S2N_P<3>

PM_SLP_S5_L

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_N2S_P<0>
DMI_N2S_P<1>

DMI_S2N_N<1>

PCH_DMI2RBIAS

PCH_FDI_RX_N<0>

PM_SLP_S3_L

TP_PCH_SLP_SUS_L

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

CPU_PROC_SEL

=PP1V8_S0_PCH

DP_IG_D_MLN<3>

DP_IG_D_MLP<2>

DP_IG_D_AUXP

DP_IG_D_AUXN

DP_IG_C_MLN<3>

DP_IG_C_MLP<2>

DP_IG_C_MLN<2>

DP_IG_C_MLP<1>

DP_IG_C_MLN<1>

DP_IG_C_MLP<0>

DP_IG_B_MLP<2>

DP_IG_B_MLN<0>

DP_IG_B_DDC_DATA

DP_IG_B_DDC_CLK

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

DP_IG_D_MLP<3>

DP_IG_D_MLN<2>

DP_IG_D_MLP<1>

DP_IG_D_MLN<1>

DP_IG_D_MLP<0>

DP_IG_D_MLN<0>

DP_IG_D_HPD

DP_IG_C_MLN<0>

DP_IG_C_HPD

DP_IG_C_AUX_P

DP_IG_C_AUX_N

DP_IG_C_CTRL_DATA

DP_IG_C_CTRL_CLK

DP_IG_B_MLP<1>

DP_IG_B_AUX_P

DP_IG_B_MLP<0>

DP_IG_B_MLN<3>

DP_IG_B_MLN<1>

PM_PCH_SYS_PWROK

PCH_DMI_COMP

DMI_S2N_P<1>

DP_IG_B_HPD

DP_IG_B_AUX_N

DMI_N2S_P<2>

DMI_S2N_N<0>

TP_PCH_RESERVE_7

TP_PCH_RESERVE_5

TP_PCH_RESERVE_4

TP_PCH_RESERVE_3

TP_PCH_RESERVE_1
TP_PCH_RESERVE_2

TP_PCH_RESERVE_8

TP_PCH_RESERVE_12

TP_PCH_RESERVE_15
TP_PCH_RESERVE_16
TP_PCH_RESERVE_17

TP_PCH_RESERVE_0

TP_PCH_RESERVE_13

TP_PCH_RESERVE_20
TP_PCH_RESERVE_21

TP_PCH_RESERVE_19

TP_PCH_RESERVE_18

TP_PCH_RESERVE_26

TP_PCH_RESERVE_28

TP_PCH_RESERVE_27

TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK

TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC

=PP3V3_S0_PCH_GPIO

PCH_FDI_RX_N<1>

PM_SYNC

PCH_GPIO72

PM_PWRBTN_L

PM_CLK32K_SUSCLK_R

PCH_DAC_IREF

=PP3V3_S5_PCH

=TBT_WAKE_L

PCH_FDI_RX_N<5>

PCH_FDI_RX_N<4>

PCH_FDI_RX_N<3>

PCH_FDI_RX_N<2>

PCH_FDI_RX_N<6>
PCH_FDI_RX_N<7>

PCH_FDI_RX_P<6>

PCH_FDI_INT

PCH_FDI_FSYNC<1>

PCH_FDI_LSYNC<0>

PCH_FDI_RX_P<7>

PCH_FDI_RX_P<2>

PCH_FDI_RX_P<0>
PCH_FDI_RX_P<1>

PCH_FDI_RX_P<3>

TP_PCH_RESERVE_22
TP_PCH_RESERVE_23
TP_PCH_RESERVE_24
TP_PCH_RESERVE_25

PCH_FDI_RX_P<4>
PCH_FDI_RX_P<5>

TP_PCH_INIT3V3_L

TP_CRT_IG_DDC_DATA

R1900

1

2

R1905

1

2

R1925

1

2

R1951

1

2

R1909

1

2

R1915

1

2

R1920

1

2

R1981

1

2

R1980

12

U1800

BC46

R47

D33

B33

J36

H36

A36

B35

P38

R38

A32

B37

C36

H38

J38

E37

F38

M41

P41

B31

E31

BT37

BG46

BR42

B51
C52

H46

E49
D51

C42
F45
H41
C46
B45
B47
J43
M43

B43
F43
J41
D47
A46
C49
H43
P43

BG43

BC56

AV46

BN56

F55

BT43

BJ38

BJ48

BK38

BC41

BH49

BM53

BN52

BH50

BD43

BN54

BP45

BA47

BU46

BJ53

BE52 BC44

U1800

AM1

AW3
AW1

AN2

AR4

AM6

AN6

AR2

AT3

R12
R14
M12
M11
K8
H8
M3
L5

R9
R8
T1

J3
L2
G4
G2
F5
F3
E2
E4

U12
U14

AL12
AL14

N2

B5
D5
D7
C6
C9
B7
B11
E11

R6
N6

AL9
AL8

M1

J57
U43

R44

U49
AB44
AB49

E52

H52

F53

J55

L56

K46

M49

Y50
AB50

L53

Y44

G56
AB46

K49

K50

M48

M50

R50

Y41

H50

U44

U46

U50

AL15
AL17

T3
U2

U5
W3

U9
U8

R1999

1

2

R1998

1

2

051-9509

4.2.0

19 OF 113
19 OF 100

19 33 38

15

19

15

19

8

8

8

8

8

8

8

8

6

18

8

8

19

19

6

19 24 26

6

18 22

8

11

6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

90

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

15 20 36

8

15

6

19 24 26

34

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

BI

BI

BI

BI

BI
BI

IN

OUT

IN

OUT

OUT

IN

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

USB3TN1

USB3TP1

USB3RN1

USB3RN2

USB3RP2

CLKOUT_PCI0
CLKOUT_PCI1

USBP13P

AD0
AD1
AD2
AD3

AD18

USBP8P

USBP8N

USBP7P

AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17

AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28

PIRQD*

REQ0*

REQ2*/GPIO52
REQ3*/GPIO54

GNT0*

GNT3*/GPIO55

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

PCIRST*

SERR*
PERR*

IRDY*
PAR
DEVSEL*
FRAME*

PLOCK*

STOP*
TRDY*

PME*

PLTRST*

USBP0N
USBP0P

USBP1N
USBP1P

USBP2N
USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5N
USBP5P

USBP6N
USBP6P

USBP7N

USBP9N
USBP9P

USBP10N

USBP11N
USBP11P

USBP12N

USBP13N

USBRBIAS*

REQ1*/GPIO50

AD29
AD30
AD31

USBP12P

USBP10P

C/BE3*

C/BE0*
C/BE1*
C/BE2*

PIRQA*

GNT2*/GPIO53

GNT1*/GPIO51

PIRQC*

PIRQB*

USBRBIAS

USB3RP1

CLKOUT_PCI4

CLKOUT_PCI3

CLKOUT_PCI2

USB3TN2

USB3TP2

USB3RP3

USB3RN3

USB3TP3

USB3TN3

USB3RN4

USB3RP4

USB3TP4

USB3TN4

OC0*/GPIO59

OC2*/GPIO41

OC1*/GPIO40

OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9

OC7*/GPIO14

OC6*/GPIO10

USB

(5 OF 10)

PCI

IN

IN

IN
IN

OUT

IN
IN
IN
IN

OUT

IN
IN

IN

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI
BI

OUT

OUT

OUT

OUT

BI
BI

BI

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE THE RESISTOR CLOSE TO COMMON POINT

TIE TRACES TOGETHER CLOSE TO PINS

EXT A

EXT B

EXT C

EXT D

UNUSED

UNUSED

UNUSED

EHCI - EXT B

UNUSED

UNUSED

EHCI - EXT D

UNUSED

INTERNAL HUB (BT,SMC12)

CAMERA

42 93

42 93

8

8

42 93

42 93

42 93

42 93

42 93

42 93

42 93

42 93

42 93

42 93

43 93

43 93

43 93

43 93

43 93

43 93

43 93

OMIT_TABLE

PANTHER-POINT

FCBGA

43 93

10K

5%
1/16W
MF-LF

402

NOSTUFF

56

58

15 34

15 33

15 42

15 42

15 43

15 43

15 33

15

15

15 39

201

1/20W

5% MF

0

SIGNAL_MODEL=EMPTY

201

1/20W0MF

SIGNAL_MODEL=EMPTY

5%

201

1/20W

5% MF

0

SIGNAL_MODEL=EMPTY

1/20W

5%

0

MF

201

SIGNAL_MODEL=EMPTY

201

1/20W

5% MF

0

SIGNAL_MODEL=EMPTY

201

1/20W

5%

0

MF

SIGNAL_MODEL=EMPTY

201

1/20W

5%

0

MF

SIGNAL_MODEL=EMPTY

MF

201

1/20W

5%

0

SIGNAL_MODEL=EMPTY

42 93

42 93

43 93

43 93

43 93

8

43 93

8

8

8

8

8

40

40

43 93

43 93

8

8

1/16W

PLACE_NEAR=U1800.BM25:2mm

22.6

MF-LF
402

1%

10K

MF-LF

4025%

1/16W
1/16W MF-LF

4025%

10K

MF-LF

402

1/16W

10K

5%

402

MF-LF

5%

1/16W

10K

10K

MF-LF

5%

1/16W

402

10K

MF-LF1/16W

4025%

10K

MF-LF

4025%

1/16W

5%

10K

1/16W

402

MF-LF

5%

10K

1/16W MF-LF

402

10K

5%

1/16W

402

MF-LF

26

26 92

26 92

26 92

10K

5%

1/16W

402

MF-LF

402

10K

5%

1/16W MF-LF

1/16W MF-LF

4025%

10K

402

1/16W

10K

MF-LF

5%

402

1/16W

5%

10K

MF-LF

27 93

27 93

8

8

MF-LF

5%

1/16W

10K

402

SYNC_DATE=11/30/2011

SYNC_MASTER=K70_MLB

PCH PCI/USB

BLC_I2C_MUX_SEL

=PP3V3_S0_PCH_GPIO

USB3_EXTB_TX_N

USB3_EXTC_RX_F_P

USB3_EXTC_TX_N

USB_EXTA_OC_L

PCI_INTC_L

PCI_SERR_L

PCH_STRP_TOPBLK_SWP_L

USB3_EXTA_RX_F_N

USB3_EXTB_RX_F_N

USB3_EXTB_RX_F_P

TP_PCI_AD<1>

TP_PCI_AD<18>

USB_PCH_8_P

USB_PCH_8_N

USB_PCH_7_P

TP_PCI_AD<5>

TP_PCI_AD<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>

TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>

TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>

USB_PCH_0_N
USB_PCH_0_P

USB_PCH_1_N
USB_PCH_1_P

USB_PCH_2_N
USB_PCH_2_P

USB_PCH_3_N
USB_PCH_3_P

USB_PCH_4_N
USB_PCH_4_P

USB_PCH_5_N
USB_PCH_5_P

USB_PCH_6_N
USB_PCH_6_P

USB_PCH_7_N

USB_PCH_9_P

USB_PCH_10_N

USB_PCH_11_P

USB_PCH_13_N

USB_PCH_12_P

USB_PCH_10_P

USB3_EXTA_RX_F_P

USB3_EXTC_RX_F_N

PLT_RESET_L

USB3_EXTC_TX_P

USB_PCH_11_N

TP_PCI_CLK33M_OUT3

TP_PCI_AD<28>

JTAG_GMUX_TMS

TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L

BT_PWR_RST_L

TP_PCI_AD<6>

BLC_GPIO

PCI_STOP_L
PCI_TRDY_L

PCI_IRDY_L

TBT_PWR_REQ_L

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

AUD_I2C_INT_L

TP_PCH_PCI_GNT0_L

AUD_IP_PERIPHERAL_DET

TP_PCI_RESET_L

TP_PCI_AD<4>

TP_PCI_AD<3>

TP_PCI_AD<0>

TP_PCI_AD<2>

USB_PCH_12_N

USB_PCH_9_N

TP_PCI_AD<13>

TP_PCI_AD<12>

TP_PCI_AD<11>

PCI_PLOCK_L

PCI_INTB_L

TP_PCI_C_BE_L<1>

TP_PCI_AD<31>

TP_PCI_AD<30>

PCI_PERR_L

TP_PCI_PAR

PCI_FRAME_L

PCH_CLK33M_PCIOUT

USB3_EXTA_TX_P

TP_PCI_PME_L

USB_EXTB_OC_L

USB_EXTD_OC_L

USB_EXTC_OC_L

USB_EXTD_OC_EHCI_R_L

SDCONN_STATE_CHANGE_R

TP_PCI_AD<29>

PCH_USB_RBIAS

PCI_INTD_L

PCI_INTA_L

TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<0>

PCI_REQ0_L

USB3_EXTB_TX_P

PCI_DEVSEL_L

TP_PCI_CLK33M_OUT2

USB3_EXTD_RX_F_N

USB3_EXTD_RX_F_P

USB_EXTB_OC_EHCI_L
USB_EXTD_OC_EHCI_L
AP_PWR_EN
SDCONN_STATE_CHANGE

AP_PWR_EN_R

USB_EXTB_OC_EHCI_R_L

USB_EXTD_OC_R_L

USB_EXTC_OC_R_L

USB_EXTB_OC_R_L

USB_EXTA_OC_R_L

USB3_EXTD_TX_N

USB3_EXTD_TX_P

USB3_EXTA_TX_N

USB_PCH_13_P

R2070

1

2

R2010

1 2

R2011

1 2

R2012

1 2

R2013

1 2

R2015

1 2

R2016

1 2

R2017

1 2

R2020

1 2

R2021

1 2

R2022

1 2

R2023

1 2

R2024

1 2

R2026

1 2

R2025

1 2

R2027

1 2

R2030

1 2

U1800

BF15
BF17

BR9

BJ10

BM8
BF3
BN2
BE4
BE6

BG15

BC6

BT11

BT7

BA14

BL2
BC4
BL4
BC2

BM13

BA9
BF9
BA8
BF8

BT13

AV17
BK12

BG12
BN11
BJ12

BU9

BR12

BJ3

BN4
BP7
BG2

BP13

AT11
AN14
AT12
AT17
AT14

BH9

BC11

BA15

AV8

BU12

BE2

BF11

BM43
BD41
BG41
BK43
BP43
BJ41
BT45
BM45

BH8

AV14

BM3

BK10

BJ5

BM15

BP5

BN9
AV9

BT15

BR4

BA17

BK48

AV15

BG5
BT5
BK8

AV11

BR6

BC12

BC8

H31

J27

J25

L22

J31

L27

L25

J22

C29

F28

C26

B25

E29

E27

B27

D25

BF36
BD36

BK25
BJ25

BJ31
BK31

BF27
BD27

BJ27
BK27

BC33
BA33

BM33
BM35

BT33
BU32

BR32
BT31

BN29
BM30

BK33
BJ33

BF31
BD31

BN27
BR29

BR26
BT27

BM25

BP25

R2019

1

2

R2001

1 2

R2002

1 2

R2003

1 2

R2007

1 2

R2004

1 2

R2005

1 2

R2006

1 2

R2008

1 2

051-9509

4.2.0

20 OF 113
20 OF 100

6

15 19 36

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

25

25

8

93

8

8

8

8

25

25

25

25

25

25

OUT

IN

OUT

IN

NCTF

RSVD

GPIO

MISC

CPU

NCTF

(6 OF 10)

VSS_NCTF

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA4GP/GPIO16

PCIECLKRQ6*/GPIO45

TACH4/GPIO68

A20GATE

BMBUSY*/GPIO0 CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

GPIO27

GPIO28

GPIO35/NMI*

GPIO57

GPIO8

NC_5

PCIECLKRQ7*/GPIO46

PECI

PROCPWRGD

PWM0
PWM1
PWM2
PWM3

RCIN*

SATA3GP/GPIO37

SATA5GP_GPIO49

SCLOCK/GPIO22

SDATAOUT1/GPIO48

SST

STP_PCI*/GPIO34

TACH0/GPIO17

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

THRMTRIP*

TP1

TP10

TP11

TP12

TP13

TP14

TP16

TP17

TP18

TP19

TP2

TP20

TP3

TP4

TP5

TP6

TP7

TP8

TP9

NC_1
NC_2
NC_3
NC_4

VSSADAC

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO24/PROC_MISSING

SATA2GP/GPIO36

TP15

BI

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

IN

NC

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Place this near the T point

X

11 25

45

5%
1/16W
MF-LF

10K

402

402

MF-LF

1/16W

10K

5%

28 32

5%

100K

MF-LF

1/16W

402

46

NOSTUFF

0

5%

402

1/16W MF-LF

0

1/16W

5%

402

MF-LF

FCBGA

PANTHER-POINT

OMIT_TABLE

11 44 45

5

15 44

36

26

58 82

15 34

15 34

15 33

15 36

15 26

46 92

SIGNAL_MODEL=EMPTY

MF

1/20W

5%

0

201

SIGNAL_MODEL=EMPTY

201

5%

1/20W

MF

0

SIGNAL_MODEL=EMPTY

201

5% MF

1/20W

0

SIGNAL_MODEL=EMPTY

0

5%

201

MF

1/20W

0

5%

201

MF

1/20W

SIGNAL_MODEL=EMPTY

0

5%

1/20W

201

MF

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

0

MF

1/20W

5%

201

201

0

5%

1/20W

MF

SIGNAL_MODEL=EMPTY

MF

1/20W

201

5%

33

201

33

5% MF

1/20W

40

40

SYNC_MASTER=D7_TONY

SYNC_DATE=01/11/2012

PCH MISC

PCH_CAM_RESET_R

JTAG_TBT_TDO

TP_PCH_TP6

TP_PCH_TP5

=PP3V3_S0_PCH

TP_PCH_TP10

TP_PCH_TP11

PCH_CAM_RESET

PCH_CAM_EXT_BOOT

MLB_RAM_CFG1

PCH_CAM_EXT_BOOT_R

SPIROM_USE_MLB

MLB_RAM_CFG0

ENET_LOW_PWR_PCH

PCH_GPIO48

TP_PCH_TP14

TP_PCH_TP13

TBT_CLKREQ_L

TP_PCH_SST

TP_PCH_PWM3

JTAG_TBT_TCK

LPCPLUS_GPIO

JTAG_TBT_TCK_R

TBT_CIO_PLUG_EVENT

DP_GPU_TBT_SEL

GPU_GOOD

PCH_GPIO22

XDP_PIN03

WOL_EN

TBT_GO2SX_BIDIR

ENET_LOW_PWR_PCH_R

AUD_IPHS_SWITCH_EN_PCH_R

DP_GPU_TBT_SEL_R

TBT_CIO_PLUG_EVENT_R

TP_PCH_TP15

TP_PCH_TP17

TP_PCH_PWM0
TP_PCH_PWM1

SMC_RUNTIME_SCI_L

PCH_GPIO6

TP_PCH_GPIO8

PCH_A20GATE

PM_THRMTRIP_L

TP_PCH_TP1

TP_PCH_TP2

TP_PCH_TP9

AP_CLKREQ_L

JTAG_TBT_TDI

=PP3V3_S0_PCH

PCH_GPIO1

TP_PCH_TP16

TP_PCH_TP12

TP_PCH_TP4

TP_PCH_TP7

TP_PCH_TP8

CPU_PECI

CPU_PWRGD

TP_PCH_TP20

TP_PCH_TP19

PCH_PROCPWRGD

PCH_PECI

TP_PCIE_CLK100M_PE7P

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

TP_PCH_TP3

PCH_RCIN_L

TP_PCH_PWM2

TP_PCH_TP18

SMC_WAKE_SCI_L

TBT_SW_RESET_R_L

GPU_GOOD_R

TBT_SW_RESET_L

ISOLATE_CPU_MEM_L

ISOLATE_CPU_MEM_R_L

AUD_IPHS_SWITCH_EN_PCH

R2155

1

2

R2150

1

2

R2190

1

2

R2170

1 2

R2140

1 2

U1800

BB57

AW55

AB3
AA2

AE2
AF1

BM55

BP53

BJ43

BJ55

BJ57

BT53

BP51

BK50

A54
A52
F57
D57

AY20

AV44

BP55

H48

D53

BN21
BT21
BM20
BN19

BG56

BB55

BG53

AU56

BA56

BA53

BF55

AW53

BE54

BC43

BL56

BT17

BR19

BA22

BR16

BU16

BM18

BN17

BP15

E56

P22

BM46

BA27

BC49

AE49

AE41

AE43

AE50

BA36

AY36

Y14

L31

Y12

L33

M38

L36

Y18

Y17

AB18

AB17

A4
A6

BU54

BU6

D1
F1

B2

BM1

BM57

BP1

BP57

BT2
BU4

BU52

AU2

R2106

1 2

R2101

1 2

R2104

1 2

R2107

1 2

R2108

1 2

R2103

1 2

R2109

1 2

R2105

1 2

R2110

1 2

R2111

1 2

051-9509

4.2.0

21 OF 113
21 OF 100

8

8

6

18 21 24

8

8

15

15

15

15

15

8

8

8

8

25

15 34

15

25

15 38

15 34

25

25

25

25

8

8

8

8

15

8

8

8

8

15 34

6

18 21 24

15

8

8

8

8

8

8

8

8

8

8

8

8

8

8

15 44

25

15

25

VCCAPLLEXP

VCCCLKDMI

VCCAPLLDMI2

VCCIO

VCCADAC

VCCVRM1

VCCIO

VCC3_3_0

VCCVRM0

VCCASW

VCCCORE

VCC3_3

VCCAFDIPLL

VCCDMI

(7 OF 10)

VCCIO_DMI/CLK

VCC CORE

CRTDMI

FDI

VCCASW

VCCIO_PCIE

HVCMOS

V_PROC_IO_NCTF

VCCRTC

V5REF_SUS

VCCADPLLB

VCCSPI

VCCIO

V5REF

VCCAPLLSATA

VCC3_3

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA

DCPSST

V_PROC_IO

VCCDFTERM0
VCCDFTERM1

VCCDIFFCLKN

VCCDSW3_3

VCCIO

VCCVRM3

VCCSUSHDA

VCCVRM2

DCPRTC_NCTF

VCCSUS3_3

VCCSSC

VCC3_3

DCPSUS

SATA

PCI/GPIO/LPC

PCI/GPIO/LPC

(10 OF 10)

USB

CPURTC

HDA

CLOCK AND MISCELLANEOUS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Max and Idle = 1mA

1.61A Max, 433mA Idle

(VCC3_3[1-9] total)

10 mA Max, 1mA Idle

105mA Max, 90mA Idle

Max and Idle = 1mA

159mA Max, 114mA Idle
(VCCVRM 4 total)

97mA Max, 15mA Idle

Max and Idle = 1mA

40mA Max, 5mA Idle

40mA Max, 10mA Idle

Max and Idle = 1 MA

409 mA Max, 42mA Idle

Need to check layout decoupling

(VCCSUS3_3 - 11 TOTAL)

200 mA Max, 2mA Idle

3mA Max, 1mA Idle

20mA Max, 1mA Idle

55mA Max, 5mA Idle

1.44 A Max, 474mA Idle

57 mA Max, 30mA Idle

PCH output, for decoupling only

PCH output, for decoupling only

3.456A Max, 426mA Idle
(VCCIO[1-31] total)

20mA Max, 10mA Idle

This should stay as RTC, correct?

10V
CERM

20%

402

0.1UF

PLACE_NEAR=U1800.BR54:2mm

10%

201

X5R

6.3V

0.1UF

PLACE_NEAR=U1800.BA46:2mm

402

PLACE_NEAR=U1800.BU42:2mm

0.1UF

CERM

20%
10V

10%
CERM

402

PLACE_NEAR=U1800.BU42:2mm

6.3V

1UF

PANTHER-POINT

FCBGA

OMIT_TABLE

PANTHER-POINT

FCBGA

OMIT_TABLE

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

PCH POWER

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_S0_PCH_DCPSST

MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

TP_DCPSUS_1

=PP3V3_S5_PCH_VCCSUS_HDA

=PP1V05_S0_PCH_VCCIO_PCIE

PP1V05_S0_PCH_VCCAPLLDMI2

=PP1V05_S0_PCH_VCCCLKDMI

PP1V05_S0_PCH_FDIPLL

PP1V8_S0_PCH_VCCVRM_F

=PP1V05_S0_PCH_VCCIO_DMI

=PP5V_S5_PCH_V5REFSUS

=PP3V3_S0_PCH_VCC_GPIO

PP1V05_S0_PCH_VCCAPLL_SATA

TP_DCPSUS_2

=PP3V3_S5_PCH_VCCSUS_USB

=PP3V3_S0_PCH_VCC

=PP1V05_S0_PCH_VCC_DMI

PP1V05_S0_PCH_VCC_A_CLK

TP_PPVOUT_PCH_DCPSUSBYP

=PP5V_S0_PCH_V5REF

=PP1V05_S0_PCH_VCCIO_USB

PP3V3_S0_PCH_VCCA_DAC_F

PP1V8_S0_PCH_VCCVRM_F

=PP3V3_S5_PCH_VCC_SPI

PP1V05_S0_PCH_VCCADPLLA_F

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH_VCC_DIFFCLK

=PP3V3_S5_PCH_VCC_DSW

PP1V8_S0_PCH_VCCVRM_F

=PP1V05_S0_PCH_VCC_SSC

TP_DCPSUS_0

PP1V05_S0_PCH_VCCAPLL_EXP

PP1V8_S0_PCH_VCCVRM_F

=PP1V05_S0_PCH_V_PROC_IO

PP1V05_S0_PCH_VCCADPLLB_F

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_S0_PCH_VCC_HVCMOS

PP3V3_G3H_RTC

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCC_ASW

=PP3V3_S0_PCH_VCC_PCI

C2210

1

2

C2222

1

2

C2232

1

2

C2231

1

2

U1800

AF57

BC17
BD17
BD20

AT1

C54

A19

B53

AU32
AV36

AL28
AN22
AN24
AN26
AN28
AR24
AR26
AR28
AR30
AR36

AU34

AR38
AU30
AU36

AG24
AG26
AG28
AJ24
AJ26
AJ28
AL24

AJ20

AC24
AC26

AE36
AG32
AG34
AJ32
AJ34
AJ36
AL32
AL34
AN32
AN34

AC28

AR32
AR34

AC30
AC32
AE24
AE28
AE30
AE32
AE34

E41
B41

V36

Y28

AA34

AA36

F20

F30

V25
V27

V31

V33

Y24
Y26

Y30
Y32

Y34

V22

Y20
Y22

Y36

AJ1

R56

U1800

BR54

BT56

BA46

AA32
AT41

A39

AV41

BF1

BT25

D55
B56

AL38
AN38
AU22

A12
AU20
AV20

AL5

AB1

AC2

U56

T55
T57

AE15
AE17
AG15

AV40

AV24
AV26

AE40

BA38

AG38

AG40

AY25
AY27

AG41

AL40

AN40
AN41

AJ38

BU42

AN52

AC20
AE20

U31
AV30

BT35

AV32
AY31
AY33
BJ36
BK36
BM36
AT40
AU38

AV28

R54

R2

051-9509

4.2.0

22 OF 113
22 OF 100

6

24

6

18 19

8

24

8

22 24

6

24

6

24

8

6

24

6

24

6

24

8

8

24

6

17

22 24

6

24

17 24

6

24

6

6

24

22 24

6

8

22 24

6

24

17 24

6

24

6

24

6

26

6

18 24

6

24

6

24

VSS

VSS

(8 OF 10)

VSS

VSS

(9 OF 10)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OMIT_TABLE

PANTHER-POINT

FCBGA

OMIT_TABLE

PANTHER-POINT

FCBGA

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

PCH GROUNDS

U1800

AE56
BR36

AA22

AU28
AU5
AV12
AV18
AV22
AV34
AV38
AV47
AV6
AW57

AA24

AY38
AY6
B23
BA11
BA12
BA31
BA41
BA44
BA49
BB1

AA26

BB3
BB52
BB6
BC14
BC15
BC20
BC27
BC31
BC36
BC38

AA28

BC47
BC9
BD25
BD33
BF12
BF20
BF25
BF33
BF41
BF43

AA30

BF46
BF52
BF6
BG22
BG25
BG27
BG31
BG33
BG36

AA38
AB11
AB15
AB40
AB41

C12

AB43
AB47
AB52
AB57

AB6
AC22
AC34
AC36
AC38

AC4

AY22

AC54
AE14
AE18
AE22
AE26
AE38

AE4
AE47

AE8

AE9

A26

AF52

AF6
AG11
AG14
AG20
AG22
AG30
AG36
AG43
AG44

A29

AG46

AG5
AG50
AG53
AH52

AH6
AJ22
AJ30
AJ57
AK52

A42

AK6
AL11
AL18
AL20
AL22
AL26
AL30
AL36
AL41
AL46

A49

AL47

AM3
AM52
AM57
AN11

AN12
AN15
AN17
AN18
AN20

A9

AN30
AN36
AN4
AN43
AN47
AN54
AN9
AR20
AR22
AR52

AA20

AR6
AT15
AT18
AT43
AT47
AT52
AT6
AT8
AU24
AU26

U1800

BG38
BH52

BH6

BJ1
BJ15
BK20
BK41
BK52

BK6
BM10
BM12
BM16
BM22
BM23
BM26
BM28
BM32
BM40
BM42
BM48

BM5
BN31
BN47

BN6

BP3
BP33
BP35
BR22
BR52
BU19
BU26
BU29
BU36
BU39

C19

C32

C39

C4
D15
D23

D3
D35
D43
D45
E19
E39
E54

E6

E9
F10
F12
F16
F22
F26
F32
F33
F35
F36
F40
F42
F46
F48
F50

F8
G54
H15
H20
H22
H25
H27
H33

H6

J1
J33

J46
J48
J5
J53
K52
K6
K9
L12
L17
L38
L41
L43
M20
M22
M25
M27
M31
M33
M36
M46
M52
M57
M6
M8
M9
N4
N54
R11
R15
R17
R22
R4
R41
R43
R46
R49
T52
T6
U11
U15
U17
U20
U22
U25
U27
U33
U36
U38
U41
U47
U53
V20
V38
V6
W1
W55
W57
Y11
Y15
Y38
Y40
Y43
Y46
Y47
Y49
Y52
Y6
AL43
AL44
R36
P36
R25
P25

051-9509

4.2.0

23 OF 113
23 OF 100

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3V3 S0 Rails

3V3 S5 Rails

1V05 S0 Rails

1 mA S0-S5

1 mA

<1 MA

<1 MA S0-S5

PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)

Power Sequencing

1V8 S0 Rails

(PCH Reference for 5V Tolerance on PCI)

PCH V5REF Filter & Follower

X5R

10V

402

10%

PLACE_NEAR=U1800.BF1:2mm

1UF

100

5%

1/16W

402

MF-LF

20%
10V

0.1UF

CERM

402

PLACE_NEAR=U1800.BT25:2mm

10

1/16W
MF-LF

5%

402

5%

1/16W

402

MF-LF

0

PLACE_NEAR=U1800.AF57:2mm

0.1UF

402

X5R

16V

10%

0.1UF

402

10V
CERM

20%

PLACE_NEAR=U1800.T55:2mm

0.1UF

20%
CERM

402

10V

PLACE_NEAR=U1800.AV28:2mm

0.1UF

16V

10%
X5R

402

PLACE_NEAR=U1800.A12:2mm

PLACE_NEAR=U1800.AU20:2mm

CERM

1UF

6.3V

402

10%

PLACE_NEAR=U1800.BT35:2mm

10%

402

X5R

16V

0.1UF

PLACE_NEAR=U1800.AV30:2mm

2.2UF

603

X5R

10%
16V

PLACE_NEAR=U1800.D55:2mm

0.1UF

X5R

16V

10%

402

PLACE_NEAR=U1800.D55:2mm

4.7UF

6.3V

20%
X5R

402

PLACE_NEAR=U1800.U31:2mm

16V

0.1UF

10%
X5R

402

201

6.3V

0.1UF

10%
X5R

PLACE_NEAR=U1800.AL38:2mm

PLACE_NEAR=U1800.E41:2mm

6.3V

1UF

CERM
402

10%

10%

PLACE_NEAR=U1800.AG38:2mm

6.3V
402

CERM

1UF

PLACE_NEAR=U1800.AJ38:2mm

10%

6.3V
402

CERM

1UF

402

20%

CERM

10V

0.1UF

PLACE_NEAR=U1800.AV40:2mm

CERM

10%

1UF

402

6.3V

PLACE_NEAR=U1800.AN52:2mm

PLACE_NEAR=U1800.AJ1:2mm

CERM

6.3V

402

10%

1UF

PLACE_NEAR=U1800.R54:2mm

402

CERM

6.3V

10%

1UF

PLACE_NEAR=U1800.R56:2mm

0.1UF

10%

402

X5R

16V

0.1UF

16V

402

X5R

10%

PLACE_NEAR=U1800.BC17:2mm

0.1UF

X5R

16V

PLACE_NEAR=U1800.BC17:2mm

10%

402

6.3V
CERM

PLACE_NEAR=U1800.AC24:2mm

10%

1UF

402

PLACE_NEAR=U1800.F20:2mm

6.3V

1UF

10%
CERM

402

1UF

PLACE_NEAR=U1800.AC20:2mm

6.3V

10%
CERM

402

PLACE_NEAR=U1800.AN22:2mm

6.3V

10%

1UF

402

CERM

PLACE_NEAR=U1800.AJ24:2mm

1UF

402

10%

6.3V
CERM

10%
X5R

16V
402

1UF

PLACE_NEAR=U1800.AJ20:2mm

PLACE_NEAR=U1800.D55:2mm

0.1UF

402

10%
16V
X5R

20%

10UF

603

X5R

6.3V

PLACE_NEAR=U1800.AA34:2mm

20%

10UF

603

X5R

6.3V

PLACE_NEAR=U1800.Y20:2mm

10UF

20%

6.3V
X5R
603

PLACE_NEAR=U1800.AN24:2mm

X5R

6.3V
603

20%

10UF

PLACE_NEAR=U1800.AC2:2mm

1UF

402

10%

6.3V
CERM

PLACE_NEAR=U1800.AB1:2mm

CERM

6.3V

10%

402

1UF

PLACE_NEAR=U1800.AE15:2mm

1UF

CERM

6.3V

10%

402

22UF

20%

6.3V
CERM
805

20%

22UF

805

6.3V
CERM

0201-MUR

PLACE_NEAR=U1800.AN22:2mm

X5R

6.3V

20%

1.0UF

BAT54XV2T1

SOD-523

BAT54XV2T1

SOD-523

PCH DECOUPLING

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP1V8_S0_PCH_VCCVRM_F

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

PP5V_S5_PCH_V5REFSUS

=PP3V3_S5_PCH

=PP3V3_S0_PCH
=PP5V_S0_PCH

=PP1V05_S0_PCH_VCC_ASW

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_V_PROC_IO

=PP5V_S0_PCH_V5REF

PP1V05_S0_PCH_VCCADPLLA_F

=PP3V3_S0_PCH_VCC

=PP3V3_S0_PCH_VCC_PCI

=PP1V8_S0_PCH_VCC_VRM

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S5_PCH_VCCSUS_USB

=PP5V_S5_PCH

=PP5V_S5_PCH_V5REFSUS

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S5_PCH_VCCSUS_HDA

=PP3V3_S5_PCH_VCC_DSW

=PP3V3_S0_PCH_VCC_HVCMOS

=PP1V05_S0_PCH_VCCCLKDMI

=PP1V05_S0_PCH

PP1V05_S0_PCH_VCCADPLLB_F

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_S0_PCH_VCC_GPIO

C2439

1

2

R2405

2

1

C2438

1

2

R2404

2

1

R2400

1 2

C2423

1

2

C2440

1

2

C2441

1

2

C2421

1

2

C2422

1

2

C2413

1

2

C2455

1

2

C2417

1

2

C2416

1

2

C2484

1

2

C2485

1

2

C2487

1

2

C2452

1

2

C2453

1

2

C2499

1

2

C2442

1

2

C2443

1

2

C2436

1

2

C2447

1

2

C2424

1

2

C2427

1

2

C2482

1

2

C2481

1

2

C2483

1

2

C2456

1

2

C2426

1

2

C2411

1

2

C2430

1

2

C2445

1

2

C2460

1

2

C2461

1

2

C2428

1

2

C2491

1

2

C2490

1

2

C2400

1

2

C2471

1

2

C2470

1

2

C2496

1

2

D2400

A

K

D2401

A

K

051-9509

4.2.0

24 OF 113
24 OF 100

6

19 26

6

18 21

6

6

22

6

18 22

6

22

6

22

22

17 22

6

22

6

22

6

6

22

6

22

6

22

6

22

6

22

6

22

6

22

22

6

18

17 22

6

22

6

22

BI
IN

IN
IN

IN
IN

IN
IN

NC

IN

BI

OUT

IN
IN

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN
OUT
OUT
OUT

OUT

IN

IN

IN
IN
IN
IN

OUT

OUT

OUT

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

IN

OUT
OUT

IN
IN

IN
IN

NC

BI

IN

OUT

IN
IN

IN
IN

OUT

IN

NC
NC

NC
NC

NC
NC

NC

NC

NC

NC

NC

OUT

OUT

OUT
OUT

OUT

OUT

IN
OUT
OUT
IN
IN
IN
IN

IN

IN

IN

IN

IN

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH Micro2-XDP

1K series resistor on csa 26 (PCH Support)

obsdata_b0

xdp_present#

obsdata_c1

obsdata_c2
obsdata_c3

obsen_d1

vcc_obs_cd

obsen_c0

obsdata_c2

obsen_d0

obsdata_c1

obsdata_a2

trstn

itpclk/hook4

obsen_a1

998-2516

998-2516

obsdata_d3

itpclk#/hook5

reset#/hook6

obsdata_c3

obsen_d1

tms

tdi

tdo

dbr#/hook7

vcc_obs_cd

obsen_c0

obsen_d0

obsdata_c0

obsen_c1

itpclk/hook4

obsdata_d3

tdo

tdi
tms

obsdata_a2
obsdata_a3

obsen_b0

vcc_obs_ab

pwrgd/hook0

scl

sda

hook3

hook1

obsdata_b2

obsen_b1

hook2

obsdata_b0

tck1
tck0

and path to non-XDP signal destination.

tck0

tck1

scl

sda

vcc_obs_ab
hook2
hook3

hook1

pwrgd/hook0

obsdata_b3

obsdata_b2

obsdata_b1

obsdata_a1

obsdata_a0

obsdata_a0

obsen_a1

obsen_a0

obsdata_b1

obsdata_b3

CPU Micro2-XDP

- USB OC#’s not isolated, avoid USB port overcurrent

obsdata_a1

PCH/XDP Signal Isolation Notes:

events while using PCH XDP.

- MXM_GOOD not isolated as only LED is affected.

- For isolated GPIOs:

be replaced with aliases. Otherwise these R’s must

- ’Output’ PCH/XDP signals require pulls.

- Unused GPIOs 0 & 15 not isolated.

reset#/hook6

obsdata_d0
obsdata_d1

obsdata_d2

obsdata_c0

obsen_c1

obsen_a0

XDP Signals

- ’Output’ non-XDP signals require pulls.

If PCH XDP not implemented, all of R2524-R2537 can

R2524-R2537 should be placed where signal path

be stuffed even in production so that PCH pins
connect to appropriate non-XDP signals on PCB.

needs to split between route from PCH to J2550

obsen_b1

obsen_b0

oc3#/gpio42

oc2#/gpio41

oc0#/gpio59

oc6#/gpio10

oc5#/gpio9

sata1gp/gpio19

sata0gp/gpio21

gpio0

sata3gp/gpio37

gpio15

gpio35

sata2gp/gpio36

sata5gp/gpio49

sata4gp/gpio16

1K series resistor on csa 26 (PCH Support)

mgpio7/gpio28

Connects to PCH XDP Conn

Pull-up to 3.3V on csa 26 (PCH Support)

xdp_present#

trstn

dbr#/hook7

itpclk#/hook5

obsdata_d2

obsdata_d1

obsdata_d0

oc7#/gpio14

oc4#/gpio43

PCH Signals

oc1#/gpio40

obsdata_a3

X5R

16V

10%

0.1UF

XDP

402

16V
X5R

XDP

10%

0.1UF

402

11

11

11 91

11 91

11 91

11 91

10 91

10 91

25 47

25 47

11 25 91

10 91

10 91

10 91

10 25 91

10 15 91

10 15 91

10 91

10 91

10 15 91

10 91

10 15 91

10 91

26

11 25 91

11 25

11 25 91

11 25 91

1/16W

SW2800.2:10MM

0

5%

MF-LF

XDP

402

19 26 44

5%

XDP

402

MF-LF

1/16W

0

R1553.1:5MM

1/16W

XDP

0

MF-LF

402

5%

R1554.1:5MM

15 18 91

15 18 91

11 91

11 91

11 91

11 91

XDP

U1000.J40:10MM

1/16W

MF-LF

402

1K

5%

402

U4900.D10:10MM

MF-LF

1/16W

XDP

0

5%

U1000.H36:10MM

XDP

1/16W

MF-LF

402

5%

1K

5%

XDP

1/16W

402

J2500.47:10MM

MF-LF

0

61 62

10 25 91

15 19 25 44

11 21

J2500.52:10MM

402

1/16W

51

MF-LF

5%

XDP

MF-LF

U1000.L40:10MM

402

1/16W

5%

51

XDP

U1000.L38:10MM

402

MF-LF

1/16W

5%

51

XDP

U1000.J39:10MM

402

MF-LF

1/16W

5%

51

XDP

U1000.M40:10MM

402

MF-LF

1/16W

5%

51

XDP

25

25

25

25

25

25

25

25

25

25

26

18 25 91

18 25 91

18 25 91

0.1UF

402

10%
16V
X5R

XDP

25

25

25

25

X5R

16V

10%

402

0.1UF

XDP

25 47

25 47

18 25 91

25

25

25

25

15 19 25 44

XDP

402

MF-LF

1/16W

5%

1K

J2550.30:10MM

6

25

402

5%

U1800.BC50:10MM

200

1/16W
MF-LF

XDP

MF-LF

5%
1/16W

402

200

U1800.BC52:10MM

XDP

51

5%

402

1/16W
MF-LF

U1800.BA43:10MM

XDP

5%

200

XDP

MF-LF

1/16W
402

J2500.52:10MM

20

20

20

20

20

20

20

20

21

21

21

18

18

21

21

21

21

M-ST-SM

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

CRITICAL

DF40RC-60DP-0.4V

XDP_CONN

M-ST-SM

402

0

5%

MF-LF

1/16W

XDP_CONN

1/16W
MF-LF
402

5%

100

U1800.BA43:10MM

XDP

5%

402

MF-LF

1/16W

100

U1800.BA43:10MM

XDP

1/16W
MF-LF
402

100

XDP

5%

J2500.52:10MM

5%

402

MF-LF

1/16W

33

5%

402

MF-LF

33

1/16W

5%

MF-LF

33

402

1/16W

MF-LF

402

1/16W

5%

33

1/16W

5%

402

MF-LF

33

5%

1/16W

402

MF-LF

33

5%

1/16W

402

MF-LF

33

5%

1/16W

MF-LF

33

402

1/16W

MF-LF

33

402

5%

5%

1/16W

33

402

MF-LF

33

402

MF-LF

1/16W

5%

33

MF-LF

4025%1/16W

1/16W

5%

33

MF-LF

402
402

MF-LF335%

1/16W

402

MF-LF

5%

33

1/16W

MF-LF

1/16W

5%

33

402

21

MF-LF

33

402

1/16W

5%

402

MF-LF

1/16W

5%

33

11 25

11 25

5%

0

XDP

1/16W

MF-LF

U4900.D10:10MM

402

CPU and PCH XDP

MAX_NECK_LENGTH=3MM

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

VOLTAGE=3.3V

PP3V3_S5_XDP_R

ISOLATE_CPU_MEM_R_L

XDP_PIN03

ENET_LOW_PWR_PCH_R

XDP_DA3_USB_EXTD_OC_L

JTAG_TBT_TCK_R

SATARDRVR_EN_R

USB_EXTD_OC_R_L
USB_EXTB_OC_EHCI_R_L
USB_EXTD_OC_EHCI_R_L
AP_PWR_EN_R

USB_EXTA_OC_R_L
USB_EXTB_OC_R_L
USB_EXTC_OC_R_L

XDP_PCH_PWRBTN_L

PM_PWRBTN_L

=PP3V3_S5_XDP

XDP_PCH_PWRGD

CPU_CFG<2>

CPU_CFG<7>

XDP_FC0_PCH_GPIO15
XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_PCH_TDO

XDP_DD2_AUD_IPHS_SWITCH_EN_PCH
XDP_DD3_ENET_LOW_PWR_PCH

AUD_IPHS_SWITCH_EN_PCH_R

DP_AUXCH_ISOL_R

XDP_DB2_AP_PWR_EN

CPU_CFG<5>

XDP_DBRESET_L

CPU_CFG<3>

CPU_CFG<8>
CPU_CFG<9>

XDP_CPU_CLK100M_P

ITPXDP_CLK100M_N

=PPVCCIO_S0_XDP

CPU_CFG<6>

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_DBRESET_L

=PP3V3_S5_XDP

XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TCK

XDP_DA1_USB_EXTB_OC_L

XDP_FC0_PCH_GPIO15

GPU_GOOD_R

DP_GPU_TBT_SEL_R

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DA0_USB_EXTA_OC_L

CPU_CFG<0>

PM_PGOOD_REG_CPUCORE_S0

XDP_DA2_USB_EXTC_OC_L

XDP_DA1_USB_EXTB_OC_L

XDP_BPM_L<5>

XDP_BPM_L<4>

SDCONN_STATE_CHANGE_R

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_CPU_PLTRST_L

XDP_CPU_CLK100M_N

XDP_DA0_USB_EXTA_OC_L

CPU_PWRGD

XDP_BPM_L<6>
XDP_BPM_L<7>

XDP_VR_READY

XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L

XDP_PCH_TDO

XDP_DD3_ENET_LOW_PWR_PCH

XDP_DC1_GPU_GOOD

XDP_PCH_PLTRST_L

XDP_PCH_TMS

XDP_DB1_USB_EXTD_OC_EHCI_L

=SMBUS_XDP_SDA
=SMBUS_XDP_SCL

XDP_PCH_TCK

XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE

CPU_CFG<1>

CPU_CFG<17>

CPU_CFG<0>

XDP_BPM_L<0>
XDP_BPM_L<1>

XDP_BPM_L<2>

CPU_CFG<4>

XDP_CPU_PRDY_L

CPU_CFG<10>
CPU_CFG<11>

=SMBUS_XDP_SDA
=SMBUS_XDP_SCL

XDP_CPU_TCK

XDP_BPM_L<3>

XDP_CPU_PREQ_L

=PPVCCIO_S0_XDP

PM_PWRBTN_L

ITPXDP_CLK100M_P

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK

XDP_CPU_CFG<0>

PM_SYSRST_L

CPU_CFG<16>

XDP_DD2_AUD_IPHS_SWITCH_EN_PCH

XDP_DD1_JTAG_TBT_TCK

XDP_DD0_DP_GPU_TBT_SEL

XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_GPU_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_TBT_TCK

TBT_CIO_PLUG_EVENT_R

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_PCH_TDI

XDP_CPU_TMS

XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L

=PP3V3_S5_XDP

XDP_DC3_SATARDRVR_EN

XDP_DC2_DP_AUXCH_ISOL

XDP_DC0_ISOLATE_CPU_MEM_L

C2501

1

2

C2500

1

2

R2506

1 2

R2505

1 2

R2504

1 2

R2500

1 2

R2501

1 2

R2502

1 2

R2503

1 2

R2510

1

2

R2511

1

2

R2512

1

2

R2513

1

2

R2514

1

2

C2551

1

2

C2550

1

2

R2550

1 2

R2562

1

2

R2561

1

2

R2566

1

2

R2560

1

2

J2500

1

10

1112
1314
1516
1718
19

2

20

2122
2324
2526
2728
29

3

30

3132
3334
3536
3738
39

4

40

4142
4344
4546
4748
49

5

50

5152
5354
5556
5758
59

6

60

61

62

6364

78
9

J2550

1

10

1112
1314
1516
1718
19

2

20

2122
2324
2526
2728
29

3

30

3132
3334
3536
3738
39

4

40

4142
4344
4546
4748
49

5

50

5152
5354
5556
5758
59

6

60

61

62

6364

78
9

R2567

1 2

R2565

1

2

R2564

1

2

R2563

1

2

R2520

1 2

R2521

1 2

R2522

1 2

R2523

1 2

R2524

1 2

R2525

1 2

R2526

1 2

R2527

1 2

R2537

1 2

R2528

1 2

R2529

1 2

R2530

1 2

R2533

1 2

R2534

1 2

R2535

1 2

R2536

1 2

R2531

1 2

R2532

1 2

R2551

1 2

051-9509

4.2.0

25 OF 113
25 OF 100

18 25 91

25

25

25

91

6

25

6

25

18 25 91

18 25 91

18 25 91

25

25

25

25

25

25

91

6

25

11 25 91

11 25

11 25 91

11 25 91

11 25 91

25

25

25

25

25

25

25

25

25

6

25

OUT

NCNC

OUT

OUT

IN

OUT

IN

IN

NCNC

OUT

OUT

IN

OUT

IN

OUT

OUT

NC

OUT

OUT

OUT

OUT

NC

NC

OUT

GND

VDD

25MHZ_A

VDDIO_B

VDDIO_A

VDDIO_C

25MHZ_B
25MHZ_C

THRM

XIN

XOUT

PAD

NC

OUT

OUT

OUT

OUT

OUT

2A

VCC

GND

4Y

3Y

2Y

1Y

2B
3A
3B
4A
4B

08

1B

1A

OUT

OUT

OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Platform Reset Connections

Unbuffered

MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED

PCH RTC Crystal

OPEN-DRAIN BUFFER

From GreenClk @ 1.8V

PCH 25MHZ CLOCK

VTT VOLTAGE DIVIDER AND PU ON CPU PAGE

GreenClk 25MHz Power

Coin-Cell Holder

Buffered

To PCH @ 1.1V

511-0054

VDD must be powered if any VDDIO is.
ENET > S0 > TBT, so ENET is used here.

System 25MHz Clock Generator

Reset Button

Ethernet XTAL Power

NOTE: R2800 and D2800 form the double­ fault protection for RTC battery.

Clock series termination

SB XTAL Power
TBT XTAL Power

RTC Power Sources

NOTE: 30 PPM crystal required

GPIO Isolation to prevent glitches on critical core well GPIOs

19 25 44

1K

5%
1/16W
MF-LF

402

402

CERM

50V

5%

12pF

PLACE_NEAR=Y2810.3:2mm

5%

50V

CERM

402

12pF

PLACE_NEAR=Y2810.1:2mm

BAT54DW-X-G

SOT-363

33

MF-LF

402

5%

1/16W

33

402

5%

MF-LF

1/16W

46

71 78

18 92

18 92

20

PLACE_NEAR=U1800.AN14:10mm

MF-LF

33

5%

1/16W

402

201

1/20W

MF

5%

33

PLACE_NEAR=U1800.AT11:10mm

20 92

46 92

44 92

20 92

18 92

PLACE_NEAR=U1800.AT14:10mm

33

402

1/16W

5%

MF-LF

20 92

20%

0.1UF

10V

CERM

402

MF-LF

5%

100K

1/16W

402

BB10201-C1403-7H

SM

4.7K

5%

402

MF-LF

1/16W

402

10M

1/16W

5%

MF-LF

MC74VHC1G08

SOT23-5-HF

0.1UF

20%
10V

CERM

402

402

5%

MF-LF

1/16W

0

25

1/16W

402

5%

1K

XDP

MF-LF

33

402

1/16W
MF-LF

5%

33

33

1/16W

5%

MF-LF

402

74LVC1G07

SC70

1/16W
MF-LF

5%

1K

402

XDP

25

39

MF-LF

402

5%

1/16W

33

402

604

1/16W
MF-LF

1%

1K

1%

MF-LF
402

1/16W

18 92

34 92

10V

20%

CERM

402

0.1UF

20%

0.1UF

402

10V

CERM

0.1UF

CERM

402

20%

10V

MF-LF

402

1/16W

5%

0

1/16W

NO STUFF

5%

MF-LF
402

1M

CERM

402

12PF

50V

5%

CERM

50V

5%

12PF

402

37 92

PLACE_NEAR=U2800.4:10mm

MF-LF

1/16W

402

5%

33

CERM

6.3V

10%

1UF

402

CRITICAL

TDFN

SLG3NB146V

SILK_PART=SYS RESET

0

5%
MF-LF

402

NOSTUFF

1/16W

44

5%

33

402

1/16W
MF-LF

33

5%

MF-LF

1/16W

402

32

11

41

MF-LF

402

5%

1/16W

33

36

CRITICAL

TSSOP-HF

74LVC08

34

56

37 39

402

0.1UF

10V

20%
CERM

402

100K

5%

MF-LF

1/16W

SM-HF

CRITICAL

32.768K-12.5PF

PLACE_NEAR=U1800.BR39:10mm

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

CRITICAL

CHIPSET SUPPORT

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

PLT_RESET_L

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PPVBATT_G3_RTC_R

VOLTAGE=3.3V

PPVBATT_G3_RTC

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

MAKE_BASE=TRUE

SMC_LRESET_L

MAKE_BASE=TRUE

TBT_PLT_RST_L

PM_PCH_PWROK

ENET_LOW_PWR_PCH

AUD_IPHS_SWITCH_EN_PCH

TBT_PWR_EN_PCH

PM_PCH_PWROK

SYSCLK_CLK25M_X2

SYSCLK_CLK25M_X1

LPC_CLK33M_SMC_R

SYSCLK_CLK25M_SB

PCH_CLK32K_RTCX1

LPC_CLK33M_SMC

PCH_CLK32K_RTCX2

=PP3V3_RTC_D

PP3V3_G3H_RTC

AUD_IPHS_SWITCH_EN_PCH

TBT_PWR_EN

=PP3V3_S0_RSTBUF

LPC_CLK33M_LPCPLUS_R

=PP3V3_S5_PCH

LPC_PWRDWN_L

AUD_IPHS_SWITCH_EN

ENET_LOW_PWR

=PPVDDIO_ENET_CLK

=PP3V3_ENET_SYSCLK

PCA9557D_RESET_L

GPU_RESET_L

SYSCLK_CLK25M_TBT

CPU_RESET_L

=PPVDDIO_TBT_CLK

PM_SYSRST_L

=PP3V3_S0_PCH_PM

DEBUG_RESET_L

XDP_CPU_PLTRST_L

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_ENET

PCH_CLK33M_PCIOUT

=PPVDDIO_S0_SBCLK

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_X2_R

PCH_CLK25M_XTALIN

SYSCLK_CLK25M_SB

ENET_SD_RESET_L

SSD_RESET_L

=PP3V3_S0_RSTBUF

PCH_CLK32K_RTCX2_R

AP_RESET_L

=TBT_RESET_L

PLT_RST_BUF_L

XDP_PCH_PLTRST_L

R2602

2 1

C2610

1 2

C2611

1 2

D2600

1

4

6

3

R2681

1 2

R2690

1 2

R2626

1 2

R2625

1 2

R2627

1 2

C2680

1

2

R2680

1

2

J2600

2

1

R2697

1

2

R2611

1

2

U2680

3

2

1

4

5

C2690

1

2

R2610

1 2

R2699

1 2

R2688

1 2

R2655

1 2

U2690

2

3

5

4

R2698

1 2

R2692

1 2

R2671

1 2

R2672

1

2

C2620

1

2

C2622

1

2

C2624

1

2

R2605

1 2

R2606

1

2

C2605

12

C2606

1 2

R2628

1 2

C2602

1

2

U2600

5
4
8

9

11

263

7

1

10

R2696

1

2

R2691

1 2

R2694

1 2

R2693

1 2

U2650

7

13

10

4

1

12

9

5

2

11

8

6

3

14

C2650

1

2

R2650

1

2

Y2610

1 4

Y2605

2 4

1 3

051-9509

4.2.0

26 OF 113
26 OF 100

2

5

1

19 26 61

15 21

21 26

18

19 26 61

92

92

26 92

6

6

22

21 26

6

26

6

19 24

19 44 46

6

6

6

6

26 92

6

26 92

92

26 92

6

26

92

BI
BI

BI

BI

NC

BI
BI

NC
NC

NC
NC

TEST1

USBDM_DN1

USBDP_DN1

VBUS_DET

USBDP_DN2
USBDM_DN2

SUSP_IND/NON_REM0

VDD33

NC

XTALOUT

XTALIN/CLKIN

TEST

RESET*

HS_IND

NON_REM1

PLLFILT

CRFILT

VDD33

VDD33

VDD33

USBDM_UP

USBDP_UP

PRTPWR1
PRTPWR2

OCS1*
OCS2*

RBIAS

VDD33

EPAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

downstream ports have removable devices or not

NON_REM 0 and 1 are used to indicate whether the

NON_REM[1:0] = 00 ---> all ports removable
NON_REM[1:0] = 01 ---> port 1 is non-removable
NON_REM[1:0] = 1x ---> ports 1 and 2 are non-removable

1%
MF

402

1/16W

12K

50V

18PF

402

5%

CERM

20 93

20 93

33 93

33 93

50V
CERM
402

18PF

5%

5X3.2X1.4-SM

24.000M-60PPM-16PF

1/16W

402

MF-LF

5%

100K

MF-LF
402

1/16W

5%

10K

402

25V
X5R

10%

0.1UF

603

4.7UF

10%

6.3V

X5R-CERM

402

10%

0.1UF

X5R

25V

402

10%

0.1UF

X5R

25V
X5R
402

0.1UF

10%
25V

10%
25V
X5R
402

0.1UF

402

MF-LF

1/16W

1M

5%

NOSTUFF

5%

0

402

1/16W
MF-LF

NOSTUFF

5%

0

402

1/16W
MF-LF

MF-LF

10K

402

1/16W

5%

402

X5R

10%
16V

0.1UF

44 93

44 93

QFN

USB2412-DZK

MF-LF

1/16W

5%

0

402

0.1UF

10%
X5R

402

16V

10%
16V
X5R
402

0.1UF

100K

5%
MF-LF

402

1/16W

1/16W
402

MF-LF

5%

100K

402

X5R

25V

0.1UF

10%

USB HUB

SYNC_DATE=12/13/2011

SYNC_MASTER=D7_NICK

MAX_NECK_LENGTH=3MM

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.2V

PPUSB_HUB_VDD1V2

MIN_LINE_WIDTH=0.4MM
MAX_NECK_LENGTH=3MM

MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V

PPUSB_HUB_VDD1V2PLL

USB_HUB_VBUS_DET

USB_HUB_2_N

USB_PCH_7_P
USB_PCH_7_N

=PP3V3_S4_USB_HUB

USB_SMC_P

USB_BT_N

USB_BT_P

USB_HUB_RBIAS

USB_SMC_N

USB_HUB_2_P

USB_HUB_XTAL_R

=PP3V3_S4_USB_HUB

USB_HUB_HS_IND

USB_HUB_XTAL2

USB_HUB_XTAL1

USB_HUB_RESET_L

USB_HUB_NON_REM1

=PP3V3_S4_USB_HUB

USB_HUB_NON_REM0

Y2700

1 2

C2707

1

2

R2707

1

2

C2701

1

2

C2702

1

2

R2708

1

2

R2703

1

2

C2706

1

2

C2705

1

2

C2711

1

2

C2710

1

2

C2709

1

2

C2708

1

2

R2706

1 2

R2711

1

2

R2710

1

2

R2712

1

2

C2712

1

2

U2700

9

29

16

13

8

12

25

7

11

26

17

19

6

15

28

2

21

1

3

22

18

410142027

24
23

R2709

1 2

C2703

1

2

C2704

1

2

R2705

1

2

R2704

1

2

051-9509

4.2.0

27 OF 113
27 OF 100

5

93

6

27

93

93

6

27

93

93

6

27

IN

OUT

OUT

IN

IN

OUT

IN

IN

IN

D

SG

D

S G

D

SG

D

SG

D

SG

D

SG

NC

NC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ensures CKE signals are held low in S3

2 0 0 1 1 1 0

MEMVTT_EN = PM_PGOOD_FET_VDDQ_S0 * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN
0 1 1 1 1 CPU_MEM_RESET_L 1

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

75mA max load @ 0.75V

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

S0

S3

to

S0

60mW max power

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

6 0 1 1 1 1 1
7 1 1 1 1 CPU_MEM_RESET_L 1

to

1 0 1 1 1 1 1

3 0 0 0 X 1 0
4 0 0 1 X 1 0

5 0 1 1 0 (*) 1 1

must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

MEMVTT Clamp

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

1V5 S0 "PGOOD" for CPU

21 32

MF-LF

5%

1/16W

402

10K

28 60

402

MF-LF

100K

5%

1/16W

29 30 88

5%

402

MF-LF

20K

1/16W

28 60

1/16W

5%

402

MF-LF

100K

50V

20%

402

CERM

0.001UF

NO STUFF

5%

603

10

1/10W
MF-LF

11

11 19

402

X5R

16V

10%

0.1UF

6

28

MF-LF
402

5%

10K

1/16W

15 19 28 38 44 45 60

28 60 70

SOT563

SSM6N15AFE

CRITICAL

SOT563

SSM6N15AFE

CRITICAL

SOT563

CRITICAL

SSM6N15AFE

SOT563

SSM6N15AFE

CRITICAL

SOT563

SSM6N15AFE

CRITICAL

CRITICAL

SSM6N15AFE

SOT563

SC70

74LVC1G07

402

0.01UF

16V

CERM

20%

28 60 70

CPU Memory S3 Support

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

VTTCLAMP_L

MIN_LINE_WIDTH=0.25mm

MIN_NECK_WIDTH=0.25mm

MAKE_BASE=TRUE

CPU_MEM_RESET_L

PM_MEM_PWRGD

PM_PGOOD_FET_VDDQ_S0

=PP3V3_S4_PM

=PP3V3_S4_MEMRESET

PM_SLP_S3_L

=PP3V3_S4_MEMRESET

=PPVDDQ_S3_MEMRESET

=PP5V_S4_MEMRESET

ISOLATE_CPU_MEM_L

MEMRESET_ISOL_LS5V_L

MEMVTT_EN

VTTCLAMP_EN

MEMVTT_EN

=PPDDRVTT_S0_CLAMP

PM_PGOOD_FET_VDDQ_S0

PM_SLP_S3_L

MEMVTT_EN_L

MEM_RESET_L

R2802

1

2

R2815

1

2

R2816

1

2

R2851

1

2

C2851

1

2

R2850

1

2

C2816

1

2

R2810

1

2

Q2810

3

5

4

Q2815

6

2

1

Q2815

3

5

4

Q2850

6

2

1

Q2850

3

5

4

Q2810

6

2

1

U2820

2

3

5

4

C2821

1

2

051-9509

4.2.0

28 OF 113
28 OF 100

1

6

6

28

6

6

15 19 28 38 44 45 60

BI
BIBI

BI

IN

BI
BI

BI
BI

BI
BI

BI

IN

BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

IN
IN

IN

IN

IN

IN

IN
IN

IN
IN

IN

IN

IN

IN

BI
BI

BI
BI

BI
BI

IN

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

OUT

BI
IN

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

NC

NC

NC

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

VREFDQ
VSS_1

VSS_3

DQ0
DQ1

DM0
VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA
SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2
VSS_17

VSS_14

VSS_21

DQ24
DQ25

DQ19
VSS_19

VSS_24

DQ27

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

VTT_0 VTT_1

MTG_PINMTG_PIN

KEY

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

31

31

10V

20%
402

CERM

0.1UF

6.3V

20%
402-LF

CERM

2.2UF

31

31

12 88

31

31

31

31

31

31

31

28 30 88

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

31

31

31

31

31

31

12 88

31

31

31

31

31

31

31

31

31

10V

20%

402

CERM

0.1UF

6.3V

20%

402-LF

CERM

2.2UF

31

31

31

31

31

31

31

31

31

31

31

30 44 45

47

47

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

10K

MF-LF
402

5%
1/16W

10K

MF-LF
402

5%
1/16W

2.2UF

CERM
402-LF

20%

6.3V

10UF

X5R
603

20%

6.3V
603

X5R

6.3V

10UF

20%

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

CERM
402

20%
10V

0.1UF 0.1UF

CERM
402

20%
10V

0.1UF

20%
10V

402

CERM

20%

0.1UF

CERM
402

10V

CERM

10V

0.1UF

402

20%

CERM
402

10V

20%

0.1UF

402

CERM

0.1UF

20%
10V

0.1UF

CERM
402

20%
10V

10V

20%
402

CERM

0.1UF

1UF

X5R
402

10%
10V

1UF

X5R
402

10%
10V

1UF

X5R
402

10%
10V

1UF

X5R
402

10%
10V

F-RT-SM

2013311

402

CERM

10V

20%

0.1UF

0.1UF

CERM
402

20%
10V

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

DDR3 SO-DIMM Connector A

=PPVDDQ_S3_MEM_A

=MEM_A_DQS_P<0>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<10>

MEM_A_A<3>

=MEM_A_DQ<54>
=MEM_A_DQ<55>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<6>
=MEM_A_DQ<7>

=PPDDRVREF_DQ_MEM_A

=MEM_A_DQ<0>
=MEM_A_DQ<1>

=MEM_A_DQ<12>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<21>

=MEM_A_DQ<22>
=MEM_A_DQ<23>

=MEM_A_DQ<28>
=MEM_A_DQ<29>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30>

MEM_A_CKE<1>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<2>
MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_BA<1>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

=PPDDRVREF_CA_MEM_A

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

=MEM_A_DQ<2>
=MEM_A_DQ<3>

=MEM_A_DQ<8>
=MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQ<16>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQS_P<2>

=MEM_A_DQ<24>
=MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<27>

=MEM_A_DQ<26>

MEM_A_CKE<0>

MEM_A_A<5>

MEM_A_CLK_P<0>

MEM_A_A<1>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56>
=MEM_A_DQ<57>

=MEM_A_DQ<58>
=MEM_A_DQ<59>

MEM_A_SA<0>

MEM_A_SA<1>

=PPSPD_S0_MEM_A

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

MEM_RESET_L

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

MEM_A_CLK_N<0> MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<0>

MEM_A_CAS_L

MEM_A_CS_L<1>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

MEM_EVENT_L

=PPDDRVTT_S0_MEM_A

=PPDDRVTT_S0_MEM_A

=PPSPD_S0_MEM_A

MEM_A_SA<0>

MEM_A_SA<1>

=PPVDDQ_S3_MEM_A

C2931

1

2

C2930

1

2

C2936

1

2

C2935

1

2

R2941

1

2

R2940

1

2

C2940

1

2

C2900

1

2

C2901

1

2

C2910

1

2

C2911

1

2

C2912

1

2

C2913

1

2

C2914

1

2

C2915

1

2

C2916

1

2

C2917

1

2

C2918

1

2

C2919

1

2

C2920

1

2

C2921

1

2

C2922

1

2

C2923

1

2

C2953

1

2

C2952

1

2

C2951

1

2

C2950

1

2

J2900

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

33
35

22
24

34
36

39
41

51
53

15

40
42

50
52

57
59

67
69

56
58

17

68
70

129
131

141
143

130
132

140
142

4

147
149

157
159

146
148

158
160

163
165

6

175
177

164
166

174
176

181
183

191
193

16

180
182

192
194

18

21
23

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

205 206

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

1 2
3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

127 128

133 134

9

138

139

144

145

150

151

155 156

161 162

13

167 168

172

173

178

179

184

185

189 190

14

195 196

19 20

25 26

203 204

113

C2902

1

2

C2924

1

2

051-9509

4.2.0

29 OF 113
29 OF 100

6

29

6

6

29

29

6

29

6

29

6

29

6

29

29

29

6

29

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

NC

BI

BI

BI

BI

BI
BI

BI

IN

BI

BI

BI

BI
BI

BI
BI

BI

IN

BI

BI
BI

BI

BI

IN

IN

IN
IN

IN

IN
IN

IN
IN

IN
IN

IN

BI

A13

VDD_14

VDD_12

BA0

A10_AP

A3

DQ54
DQ55

VSS_44

VSS_0

VSS_2

VSS_5

DQS0

DQ5

DQ4

DQ6
DQ7

VREFDQ
VSS_1

VSS_3

DQ0
DQ1

DM0
VSS_4

VSS_7

DQ12

DQ20

VSS_13

DQ15

DQ14

VSS_11

VSS_9

DQ13

DM1

DQ21

VSS_15

DQ22

VSS_16

VSS_18

DQ23

DQ28

VSS_20

DQ29

DM2

VSS_23

DQS3

DQ30

VSS_25

VDD_1

CKE1

A15
A14

VDD_3

VDD_9

VDD_5

VDD_7

A7

A11

A4

A6

A2
A0

CK1

NC_1

ODT1

VDD_15

ODT0

VDD_13

VDD_11

BA1

DQ39

DQ38

VSS_30

VSS_29

DQ37

DQ36

VSS_27

VREFCA

VDD_17

DM4

VSS_32

DQ47

DQ44

DQ46

VSS_37

DQS5

VSS_39

VSS_34

DQ45

DQ52

VSS_46

DQ61

DQ60

VSS_42

VSS_41

DQ53

DM6

DQS7

VSS_51

DQ63

DQ62

VSS_49

SDA
SCL

DQ2
DQ3
VSS_6
DQ8
DQ9
VSS_8

DQS1
VSS_10

DQ16

VSS_12

DQ11

DQ10

DQ17

DQ18

DQS2
VSS_17

VSS_14

VSS_21

DQ24
DQ25

DQ19
VSS_19

VSS_24

DQ27

DQ26

DM3
VSS_22

CKE0

A5

VDD_4

CK0

VDD_8

A1

VDD_6

VDD_10

DQ33

VSS_26

VDD_16
TEST

DQ32

DQ34

VSS_31

DQS4

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43

DQ42

VSS_36

DQ48

VSS_43

DQS6

VSS_40

DQ49

DQ51

DQ50

VSS_45
DQ56
DQ57
VSS_47
DM7

DQ58

VSS_48

DQ59

SA0

SA1

VDDSPD

VSS_50

A8

A9

A12/BC*

VDD_2

BA2

NC_0

VDD_0

DQ31

DQS0*

DQS1*

RESET*

DQS2*

DQS3*

CK0* CK1*

RAS*

WE* S0*
CAS*

S1*

DQS4*

DQS5*

DQS6*

DQS7*

EVENT*

VTT_0 VTT_1

MTG_PINMTG_PIN

KEY

NC

NC

BI

BI
BI

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

OUT

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

1UF

X5R
402

10%
10V

47

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

31

31

31

31

31

31

31

CERM
402

20%
10V

0.1UF

12 88

31

31

31

31

31

31

31

6.3V

20%

402-LF

2.2UF

CERM

31

12 88

31

31

31

31

31

12 88

12 88

12 88

12 88

12 88

0.1UF

CERM
402

20%
10V

12 88

12 88

12 88

12 88

12 88

12 88

10V

20%

402

CERM

0.1UF

0.1UF

10V

20%

402

CERM

12 88

0.1UF

10V

20%

402

CERM

10V

20%

402

CERM

0.1UF

10V

20%

402

CERM

0.1UF

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

20%
CERM

10V

0.1UF

402

0.1UF

10V

20%

402

CERMCERM

10V

20%

402

0.1UF

31

0.1UF

CERM
402

20%
10V

10UF

X5R
603

20%

6.3V

10UF

X5R
603

20%

6.3V

F-RT-SM

2013290

10V

20%

402

CERM

0.1UF

402

10V

20%
CERM

0.1UF

31

31

31

31

31

31

31

31

31

31

10V

20%

402

CERM

0.1UF

31

31

31

31

31

31

31

31

31

6.3V

20%

402-LF

CERM

2.2UF

29 44 45

12 88

12 88

12 88

12 88

12 88

12 88

31

31

31

31

31

31

31

31

31

31

1UF

X5R
402

10%
10V

31

31

31

31

31

31

31

31

31

1UF

X5R
402

10%
10V

31

1/16W

5%

402

MF-LF

10K

1/16W

5%

402

MF-LF

10K

6.3V

20%

402-LF

CERM

2.2UF

31

31

31

31

1UF

X5R
402

10%
10V

31

31

31

31

31

28 29 88

31

31

47

31

31

31

31

31

31

31

31

31

12 88

DDR3 SO-DIMM CONNECTOR B

SYNC_DATE=11/30/2011SYNC_MASTER=K70_MLB

MEM_B_SA<0>

MEM_B_SA<1>

=PPSPD_S0_MEM_B

=PPSPD_S0_MEM_B

=PPDDRVTT_S0_MEM_B=PPDDRVTT_S0_MEM_B

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<4>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CLK_N<1>MEM_B_CLK_N<0>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

MEM_RESET_L

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>

=PPSPD_S0_MEM_B
MEM_B_SA<1>

MEM_B_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50>
=MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42>
=MEM_B_DQ<43>

=MEM_B_DQ<40>
=MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32>
=MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<0>

MEM_B_A<5>

MEM_B_CKE<0>

=MEM_B_DQ<26>
=MEM_B_DQ<27>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<10>
=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62>
=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQ<53>

=MEM_B_DQ<60>
=MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

=PPDDRVREF_CA_MEM_B

=MEM_B_DQ<36>
=MEM_B_DQ<37>

=MEM_B_DQ<38>
=MEM_B_DQ<39>

MEM_B_BA<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<13>

=MEM_B_DQ<14>
=MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=PPDDRVREF_DQ_MEM_B

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<4>
=MEM_B_DQ<5>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_A<13>

=PPVDDQ_S3_MEM_B=PPVDDQ_S3_MEM_B

C3153

1

2

C3136

1

2

C3135

1

2

C3152

1

2

C3151

1

2

C3150

1

2

R3141

1

2

R3140

1

2

C3140

1

2

C3131

1

2

C3130

1

2

C3117

1

2

C3123

1

2

C3116

1

2

C3115

1

2

C3114

1

2

C3113

1

2

C3122

1

2

C3121

1

2

C3120

1

2

C3119

1

2

C3112

1

2

C3111

1

2

C3110

1

2

C3118

1

2

C3101

1

2

C3100

1

2

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101
103

102
104

73 74

11

28

46

63

136

153

170

187

5
7

33
35

22
24

34
36

39
41

51
53

15

40
42

50
52

57
59

67
69

56
58

17

68
70

129
131

141
143

130
132

140
142

4

147
149

157
159

146
148

158
160

163
165

6

175
177

164
166

174
176

181
183

191
193

16

180
182

192
194

18

21
23

12

10

29

27

47

45

64

62

137

135

154

152

171

169

188

186

198

205 206

77

122

116

120

110

30

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

1 2
3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

127 128

133 134

9

138

139

144

145

150

151

155 156

161 162

13

167 168

172

173

178

179

184

185

189 190

14

195 196

19 20

25 26

203 204

113

C3124

1

2

C3102

1

2

051-9509

4.2.0

31 OF 113
30 OF 100

30

30

6

30

6

30

6

30

6

30

6

30

30

30

6

6

6

30

6

30

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_MASTER=K70_MLB

DDR3 ALIASES AND BITSWAPS

SYNC_DATE=11/30/2011

=MEM_A_DQ<15>

=MEM_A_DQ<13>

=MEM_A_DQ<9>

=MEM_B_DQ<0>

=MEM_B_DQS_N<0>
=MEM_B_DQS_P<0>

=MEM_B_DQ<7>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>

=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<2>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<5>

=MEM_A_DQS_P<1>

=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<5>

=MEM_B_DQS_N<2>

=MEM_A_DQS_N<1>

=MEM_B_DQ<29>
=MEM_B_DQ<28>

=MEM_B_DQ<25>

=MEM_B_DQ<36>
=MEM_B_DQ<35>
=MEM_B_DQ<34>
=MEM_B_DQ<33>

=MEM_B_DQ<31>
=MEM_B_DQ<30>

=MEM_B_DQ<37>

=MEM_B_DQ<39>

=MEM_B_DQ<32>

=MEM_B_DQ<38>

=MEM_B_DQ<23>

=MEM_B_DQ<21>

=MEM_B_DQ<18>

=MEM_B_DQ<41>

=MEM_B_DQ<46>

=MEM_B_DQ<47>

=MEM_B_DQ<17>

=MEM_B_DQ<20>

=MEM_B_DQ<40>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<16>

=MEM_B_DQ<19>

=MEM_B_DQ<22>

=MEM_B_DQ<14>

=MEM_B_DQ<54>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<11>

=MEM_B_DQ<13>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<15>

=MEM_B_DQ<9>

=MEM_B_DQ<55>

=MEM_B_DQ<8>

=MEM_B_DQ<5>

=MEM_B_DQ<58>

=MEM_B_DQ<62>

=MEM_B_DQ<1>

=MEM_B_DQ<3>
=MEM_B_DQ<2>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<63>

=MEM_B_DQ<6>

=MEM_B_DQ<4>

=MEM_A_DQ<37>

=MEM_A_DQ<27>

=MEM_A_DQ<31>

=MEM_A_DQ<36>

=MEM_A_DQ<32>

=MEM_A_DQ<26>

=MEM_A_DQ<30>

=MEM_A_DQ<33>

=MEM_A_DQ<38>

=MEM_A_DQ<25>

=MEM_A_DQ<29>

=MEM_A_DQ<35>

=MEM_A_DQ<39>

=MEM_A_DQ<24>

=MEM_A_DQ<34>

=MEM_A_DQ<45>

=MEM_A_DQ<41>
=MEM_A_DQ<40>

=MEM_A_DQ<44>

=MEM_A_DQ<19>

=MEM_A_DQ<23>

=MEM_A_DQ<43>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<52>

=MEM_A_DQ<11>

=MEM_A_DQ<14>

=MEM_A_DQ<53>

=MEM_A_DQ<10>

=MEM_A_DQ<50>

=MEM_A_DQ<55>

=MEM_A_DQ<12>

=MEM_A_DQ<51>

=MEM_A_DQ<54>

=MEM_A_DQ<8>

=MEM_A_DQ<7>

=MEM_A_DQ<57>
=MEM_A_DQ<56>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<59>

=MEM_A_DQ<62>

=MEM_A_DQ<1>

=MEM_A_DQ<4>

=MEM_A_DQ<58>

=MEM_A_DQ<63>

=MEM_A_DQ<5>

=MEM_A_DQ<0>

=MEM_A_DQ<6>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

=MEM_B_DQ<12>

=MEM_B_DQ<10>

=MEM_B_DQ<24>

=MEM_B_DQ<27>
=MEM_B_DQ<26>

=MEM_B_DQ<45>

=MEM_B_DQ<42>

=MEM_B_DQS_N<5>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<20>

=MEM_A_DQ<22>
=MEM_A_DQ<21>

=MEM_A_DQS_P<3>

=MEM_A_DQ<42>

MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<52>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<39>

MEM_B_DQ<13>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<5>

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<4>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<62>

MEM_A_DQ<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MEM_A_DQ<8>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<54>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<55>

MEM_A_DQ<10>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<11>

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<20>

MEM_A_DQ<17>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<47>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MEM_A_DQ<19>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MEM_A_DQ<29>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MEM_A_DQ<33>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<36>

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<2>

MEM_B_DQ<0>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<60>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MEM_B_DQ<62>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<8>

MEM_B_DQ<15>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<10>

MEM_B_DQ<11>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<12>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MEM_B_DQ<14>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<22>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<47>
MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<31>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQ<30>

MAKE_BASE=TRUE

MEM_B_DQ<29>
MEM_B_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<25>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MEM_B_DQ<35>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<34>
MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<51>
MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MEM_A_DQ<35>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<32>

MEM_A_DQ<37>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<56>

MEM_B_DQ<58>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<55>

MEM_B_DQ<50>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MEM_B_DQ<41>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<42>

MEM_B_DQ<45>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<0>

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQS_N<5>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MEM_A_DQ<23>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MEM_A_DQ<0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MEM_A_DQ<15>

MAKE_BASE=TRUE

051-9509

4.2.0

33 OF 113
31 OF 100

29

29

29

30

30

30

30

30

30

30

30

30

29

29

29

29

29

29

29

29

30

30

30

30

30

29

30

30

29

29

30

29

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

30

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

30

30

30

30

30

30

30

30

29

29

29

29

29

29

29

29

29

29

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

12 88

V-

V+

V-

V+

V-

V+

V-

V+

IN

D

S G

D

S G

NC
NC

NC
NC

RESET*

A0
A1
A2

SCL
SDA

P0
P1
P2

P5
P6
P7

P3
P4

THRM

VCC

GND

PAD

NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

CRITICAL

BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DAC Channel:
PCA9557D Pin:

DAC range:
VRef current:
DAC step size:

Currently unused
Function TBD

Margined target:

Nominal value

MEM A VREF CA

0.75V (DAC: 0x3A)

7.69mV / step @ output

0.300V - 1.200V (+/- 450mV)

+3.4mA - -3.4mA (- = sourced)

MEM B VREF CA

MEM VREG

8.59mV / step @ output

+61uA - -61uA (- = sourced)

1.5V (DAC: 0x3A)

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74)

GPU Frame Buffer (1.8V, 70% VRef)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)

0.000V - 3.300V (0x00 - 0xFF)

1.267V (DAC: 0x8B)

1.51mV / step @ output

NOTE: MEMVREG and FRAMEBUF share

(OD)

To be incorporated in design

Implementation TBD

RST* on ’platform reset’ so that system
watchdog will disable margining.

NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.

VRef DQ

Driven by CPU

NOTE: CPU DAC output step sizes:

DDR3 (1.5V) 7.70mV per step

Addr=0x98(WR)/0x99(RD)

0.000V - 1.501V (0x00 - 0x74)

Addr=0x30(WR)/0x31(RD)

both at the same time!

a DAC output, cannot enable

C C D D
3 4 5 6

VREFMRGN:EXT

0.1UF

CERM

402

20%
10V

VREFMRGN:EXT

402

1%

MF-LF

1/16W

33.2K

PLACE_NEAR=R7320.2:1mm

CRITICAL

MAX4253

UCSP

VREFMRGN:EXT

MAX4253

UCSP

CRITICAL

VREFMRGN:EXT

MAX4253

CRITICAL

UCSP

UCSP

MAX4253

402

OMIT

NONE

NONE
NONE

SHORT

NONE

OMIT

NONE
NONE

402

SHORT

26

VREFMRGN:EXT

1/16W

5%

402

MF-LF

0

VREFMRGN:EXT

5%
1/16W
MF-LF
402

0

0.1UF

X5R
402

10%
16V

PLACE_NEAR=Q3420.3:2mm

10%
16V
X5R

PLACE_NEAR=Q3420.6:2mm

402

0.1UF

PLACE_NEAR=R3421.2:1mm

1K

402

1/16W

1%
MF-LF

PLACE_NEAR=R3441.2:1mm

1/16W

1%

402

MF-LF

1K

PLACE_NEAR=Q3420.6:1mm

1K

MF-LF
402

1%
1/16W

PLACE_NEAR=Q3420.3:1mm

1K

MF-LF
402

1%
1/16W

0.1UF

16V
402

10%
X5R

0.1UF

16V

10%

402

X5R

VREFMRGN:EXT

MF-LF

1/16W

402

200

1%

1%

133

402

1/16W
MF-LF

VREFMRGN:EXT

VREFMRGN:EXT

MF-LF

1/16W

402

133

1%

VREFMRGN:EXT

1%

MF-LF

1/16W

402

200

VREFMRGN:EXT

100K

MF-LF
402

5%
1/16W

SSM6N15AFE

SOT563

CRITICAL

CRITICAL

SSM6N15AFE

SOT563

VREFMRGN:EXT

MF-LF
402

5%

100K

1/16W

VREFMRGN:EXT

1/16W

5%

402

MF-LF

100K

VREFMRGN:EXT

100K

MF-LF
402

5%
1/16W

VREFMRGN:EXT

CRITICAL

QFN

PCA9557

VREFMRGN:EXT

10V

20%

402

CERM

0.1UF

47

47

VREFMRGN:EXT

MSOP

CRITICAL

DAC5574

47

47

VREFMRGN:EXT

0.1UF

10V

20%

402

CERM

VREFMRGN:EXT

6.3V

20%

402-LF

CERM

2.2UF

VREFMRGN:EXT

0.1UF

CERM

402

20%
10V

SYNC_MASTER=K70_MLB

DDR3/FRAMEBUF VREF MARGINING

SYNC_DATE=11/30/2011

116S0004

2

R3403,R3405

RES,MTL FLM,0,5%,402,SM,LF

VREFMRGN:N

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm

PP3V3_S4_VREFMRGN_DAC

VOLTAGE=3.3V

PP3V3_S4_VREFMRGN_CTRL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VREFMRGN_CA_SODIMMA_EN

=PP3V3_S4_VREFMRGN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_CA_SODIMMB_EN

PPDDRVREF_CA_MEM_A

VREFMRGN_SODIMMS_CA

VREFMRGN_MEMVREG_EN

VREFMRGN_MEMVREG_FBVREF

ISOLATE_CPU_MEM_L

CPU_DIMM_VREF_DAC_A

ISOLATE_CPU_MEM_L

CPU_DIMM_VREF_DAC_B

PPDDRVREF_DQ_MEM_A

=PPVDDQ_S3_DDR_VREF

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

PCA9557D_RESET_L

VREFMRGN_MEMVREG_FBVREF_R

=PPDDRVTT_S3_VREFCA

VREFMRGN_MEMVREG_BUF

PPDDRVREF_CA_MEM_B

VREFMRGN_FRAMEBUF_BUF_R

TP_DDRREG_FB

VREFMRGN_FRAMEBUF_BUF

=PPVDDQ_S3_DDR_VREF

=I2C_PCA9557D_SDA

PPDDRVREF_DQ_MEM_B

U3401

3
4
5

8

6
7
9
10
11
12
13
14

15

1
2

17

16

C3403

1

2

C3402

1

2

R3402

1

2

R3401

1

2

R3407

1

2

C3404

1

2

U3400

9

10

3

6

7

8

1

2

4

5

C3401

1

2

C3400

1

2

R3414

1 2

U3402

C3

C2

C1

C4

B1

B4

U3403

A3

A2

A1

A4

B1

B4

U3402

A3

A2

A1

A4

B1

B4

U3403

C3

C2

C1

C4

B1

B4

R3418

1 2

R3419

1 2

R3417

1

2

R3416

1

2

C3440

1

2

C3420

1

2

R3422

1

2

R3442

1

2

R3421

1

2

R3441

1

2

C3421

1

2

C3441

1

2

R3403

1 2

R3404

1 2

R3406

1 2

R3405

1 2

R3408

1

2

Q3420

6

2

1

Q3420

3

5

4

051-9509

4.2.0

34 OF 113
32 OF 100

97

97

6

6

21 28 32

11 97

21 28 32

11 97

6

6

32

6

6

6

32

6

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

IN

OUT

IN

OUT

OUT
OUT

OUT

IN
IN

IN

IN

BI

D

GS

D

GS

OUT

IN

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

BI

BI

IN

VINONVOUT

GND

VINONVOUT

GND

S

G

G

S

D

D

N-CH

P-CH

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Wake from BT in G3H circuit

AIRPORT

514S0335

BLUETOOTH

Supervisor & CLKFREG # Isolation

Delay = 60 ms +/- 20%

RDS(ON)

LOADING

CHANNEL

SWITCH

N-TYPE

2 A (EDP)

18.4 MOHM @3.3V

TPS22924B

AP & BT Load Switch

SLG4AP016V

CRITICAL

TDFN

26

15 20 33

15 21

10V

20%
402

CERM

0.1uF

MF-LF

232K

402

1%
1/16W

100K

1/16W

1%

402

MF-LF

MF-LF
402

1%

100K

1/16W

15 20 33

33

10UF

20%
X5R

603

6.3V

0.1UF

16V
X5R
402

10%

18 90

18 90

SSD-K99

F-RT-SM1

CRITICAL

33

18 90

18 90

201

6.3V

X5R

PLACE_NEAR=J3500.4:3mm

0.1UF

10%

X5R

201

0.1UF

10%

6.3V

PLACE_NEAR=J3500.5:3mm

18 90

18 90

44 45

CRITICAL

220-OHM-1.4A

0603

CRITICAL

0603

220-OHM-1.4A

0.1UF

16V
402

X5R

10%

402

16V

0.1UF

X5R

10%

6.3V

20%

10UF

603

X5R

402

1/16W

5%

10K

MF-LF

SSM3K15FV

SOD-VESM-HF

SOD-VESM-HF

SSM3K15FV

44 45

201

1%

15K

1/20W

MF

201

15K

1%

1/20W

MF

0.1uF

CERM

20%
10V

NOSTUFF

402

15 19 44 60

402

CERM

10V

20%

0.1UF

CRITICAL

DFN

USB3740

SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

402

MF-LF

5%

0

1/16W

27 93

27 93

15 20

MF-LF

5%
1/16W

402

10K

402

10K

5%
1/16W
MF-LF

TPS22924B

CSP

CSP

TPS22924B

SSM6L36FE

SOT563

CRITICAL

SYNC_DATE=12/13/2011

AIRPORT/BT

SYNC_MASTER=D7_NICK

PP3V3_G3H_BT_FLT

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM

PP3V3_S4_AP_FLT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=3.3V

PP3V3_G3H_BT_FET

PP3V3_S4_AP_FET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

=PP3V3_S0_BT

BT_PWR_RST_L

BT_PWR_RST

BT_PWR_RST

BT_PWR_EN

PCIE_AP_R2D_C_P

=PP3V3_G3H_BT

PP3V3_S4_AP_FLT

AP_PWR_EN

=PP3V3_S4_AP

SMC_S4_WAKESRC_EN

PP3V3_G3H_BT_FET

PP3V3_S4_AP_FLT

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L

AP_RESET_CONN_L

P3V3AP_VMON

AP_CLKREQ_Q_L

=PP3V3_S4_AP

USB_BT_MUX_N

AP_RESET_CONN_L

AP_WAKE_L

PCIE_AP_D2R_N

AP_CLKREQ_Q_L

PCIE_AP_R2D_C_N

PCIE_AP_R2D_P

PCIE_AP_R2D_N

PCIE_CLK100M_AP_P

AP_EVENT_L

PCIE_CLK100M_AP_N

PCIE_AP_D2R_P

USB_BT_MUX_P

USB_BT_MUX_P

USB_BT_MUX_N

USB_BT_EN

USB_BT_N

SMC_PME_S4_WAKE_L

AP_WAKE_L

PCIE_WAKE_L

USB_BT_P
USB_BT_WAKEN

PM_SLP_S5_L

USB_BT_WAKEP

U3530

6

5

7

3

8

4

2

9

1

C3530

1

2

R3531

1

2

R3532

1

2

R3530

1

2

C3508

1

2

C3507

1

2

J3500

19
20
21

1

10
11
12

13
14
15
16
17
18

2
3
4
5
6
7
8
9

C3505

1 2

C3506

1 2

L3501

1 2

L3502

1 2

C3502

1

2

C3503

1

2

C3504

1

2

R3570

1

2

Q3570

3

1

2

Q3501

3

1

2

R3501

1

2

R3500

1

2

C3501

1

2

C3500

1

2

U3501

9

1

7

10

2

6

8

3

4

5

R3502

1 2

R3542

1

2

R3543

1

2

U3540

C1

C2

A2
B2

A1
B1

U3510

C1

C2

A2
B2

A1
B1

Q3540

6

3

2

5

1

4

051-9509

4.2.0

35 OF 113
33 OF 100

33

33

45

6

33

33

6

33

6

33

44 45

33

33

33

33

6

33

33 93

33

90

90

33 93

33 93

33 93

33 19 38

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT
OUT

IN

IN

IN

OUT

IN
IN

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT
IN

OUT

IN

IN

OUT
OUT

OUT
OUT

BI
BI

IN

IN
IN
IN
OUT

OUT
OUT

BI
BI

IN

OUT
OUT
OUT

OUT
OUT
OUT

OUT

OUT

PETN_3

PETN_2

PETP_2

PETP_1
PETN_1

PETP_0
PETN_0

MONOBS_N

MONDC0
MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0
PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P
PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI
EE_DO
EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P
REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS
TCK

TEST_EN
TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N
PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN
IN

OUT

IN

BI

IN

D

C

Q

S*

W*

HOLD*

PAD

VSS

THM

VCC

IN

OUT

OUT

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DEBUG: For monitoring clock

DEBUG: For monitoring current/voltage

Stuff one of R3861/2.

Divides 3.3V to 1.8V

5 - PCIE_RST_1_N
6 - PCIE_RST_2_N
7 - PCIE_RST_3_N

4 - GPIO_5

0 - GPIO_13
1 - GPIO_1
2 - GPIO_2
3 - GPIO_3

NOTE: The following pins require testpoints:

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

11 - GPIO_0

10 - GPIO_14

9 - GPIO_11

8 - GPIO_15

Not used in host mode.

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

(TBT_SPI_MOSI)

Use AA8 GND ball for THERM_DN

(TBT_SPI_CS_L)

(TBT_SPI_CLK)

(TBT_SPI_MISO)

(TBT_EN_CIO_PWR_L)

(FORCE_PWR)

if necessary.

of GPIO_2/GPIO_9

allows separation

R3681 for CYA,

SNK1 AC Coupling

SNK0 AC Coupling

3.3K

402

1/16W

5%

MF-LF

78

78

0

5%
1/16W
MF-LF

402

100K

5%
1/16W

402

MF-LF

84

84 98

84 98

84

84 98

84 98

84 98

84 98

84 98

84 98

85

85 98

85 98

85

85 98

85 98

85 98

85 98

85 98

85 98

100K

402

MF-LF

1/16W

5%

5%

MF-LF

100K

402

1/16W

84 98

84 98

MF-LF

5%

0

402

1/16W

3.3K

5%

402

MF-LF

1/16W

16V10%

X5R-CERM

0.1UF

0201

71 98

71 98

77 98

77 98

77 98

77 98

77 98

77 98

77 98

77 98

10% 16V
X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V
X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V
X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V
X5R-CERM

0.1UF

0201

1%

1K

MF

1/20W

201

16V

0.1UF

X5R-CERM

10%

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

77 98

77 98

77 98

77 98

77 98

77 98

77 98

77 98

402

CERM

10%

1UF

6.3V

71 98

71 98

84

84

85

85

36

85 98

85 98

85 98

85 98

85 98

85 98

85

15 21

15 18

15 21

15 21

84 98

84 98

84 98

84 98

84

34 84

84

34 84

34 85

85

34 85

36

19

CACTUSRIDGE4C

CRITICAL

OMIT_TABLE

FCBGA

36

26 92

5%

10K

402

MF-LF

1/16W

1/16W
MF-LF

1%

806

402

1K

402

5%
1/16W
MF-LF

10K

5%

1/16W

NO STUFF

MF-LF

402

18 90

18 90

36

47 98

47 98

36

OMIT_TABLE

M95256-RMC6XG

MLP

CRITICAL

100K

MF-LF

1/16W

5%

402

NONE

NOSTUFF

NONE

402

NONE

OMIT

10K

5%
1/16W
MF-LF

402

10K

5%
1/16W

402

MF-LF

10K

1/16W

402

MF-LF

5%

10K

5%

402

MF-LF

1/16W

10K

5%
1/16W

402

MF-LF

10K

5%
1/16W

402

MF-LF

NO STUFF

26

34 83

X5R

16V

0.1UF

402

10%

NO STUFF

47K

5%

1/16W

402

MF-LF

15 21

15 20

10K

5%
1/16W

402

MF-LF

402

1/16W

5%

0

MF-LF

15 21 34

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

MF-LF

1/16W

402

5%

3.3K

10% 16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

3.3K

402

MF-LF

5%
1/16W

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

18 90

SYNC_MASTER=D7_DOUG

SYNC_DATE=01/11/2012

Thunderbolt Host (1 of 2)

PCIE_TBT_R2D_P<0>
PCIE_TBT_R2D_N<0>

PCIE_TBT_D2R_C_P<1>

TBT_SPI_CLK

TBT_GO2SX_BIDIR

SYSCLK_CLK25M_TBT_R

DP_TBTSRC_HPD

DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_ML_P<1>

TBT_PWR_REQ_L

TP_DP_TBTSRC_ML_CP<3>

PCIE_CLK100M_TBT_P

TBT_GPIO_14

TBT_B_HV_EN

TBT_A_HV_EN

TBT_A_DP_PWRDN
TBT_B_DP_PWRDN

=I2C_TBTRTR_SDA

TBT_GPIO_9

TBT_DDC_XBAR_EN_L

TP_DP_TBTSRC_ML_CP<0>

PCIE_CLK100M_TBT_N

PCIE_TBT_R2D_C_P<2>

TP_TBT_PCIE_RESET2_L

TP_TBT_PCIE_RESET1_L

=PP3V3_TBTLC_RTR

DP_TBTPA_AUXCH_C_N

DP_TBTPA_ML_C_N<3>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

PCIE_TBT_D2R_C_P<3>

TBT_B_CONFIG1_BUF

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_HV_EN

DP_TBTPB_AUXCH_C_N

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_N<1>

TBT_B_D2R_P<1>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

TBT_B_CONFIG2_RC

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<0>

TP_DP_TBTSRC_ML_CP<2>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CN

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>

DP_TBTSNK1_HPD

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_P<1>

TBT_A_LSRX

TBT_A_LSTX

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG2_RC

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_P<0>

TP_TBT_THERM_DP

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_P<1>

TBT_RSENSE

TP_DP_TBTSRC_AUXCH_CP

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<1>

DP_TBTPA_ML_C_N<1>

TBT_A_D2R_N<0>

DP_TBTPB_AUXCH_C_P

DP_TBTPB_ML_C_N<3>

TBT_B_LSTX
TBT_B_LSRX

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

TP_TBT_PCIE_RESET0_L

TP_TBT_XTAL25OUT

PCIE_TBT_R2D_P<3>

=I2C_TBTRTR_SCL

DP_TBTSNK1_ML_P<0>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_N<3>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK1_ML_P<2>
DP_TBTSNK1_ML_N<2>

DP_TBTSNK0_HPD

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<3>

TP_TBT_PCIE_RESET3_L

TBT_A_CONFIG1_BUF

JTAG_TBT_TDO

JTAG_TBT_TDI
JTAG_TBT_TMS

TP_TBT_MONDC1

TP_TBT_MONDC0

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>

TBT_TEST_PWR_GOOD

JTAG_TBT_TCK

TBT_SPI_MOSI

TBTROM_WP_L

TBTROM_HOLD_L

TBT_A_DP_PWRDN

TBT_A_CIO_SEL

TBT_A_HV_EN

TBT_B_R2D_C_P<0>

DP_TBTSNK1_ML_N<0>

=PP3V3_S4_TBT

TBT_GPIO_14

=PP3V3_TBTLC_RTR

TBT_PWR_EN

=PP3V3_S4_TBT

TBT_CIO_PLUG_EVENT

TBT_SPI_MISO

TBT_TEST_EN

DP_TBTSNK0_ML_P<3>

=TBT_WAKE_L

DP_TBTPB_HPD

TBT_B_D2R_P<0>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<3>

=PP3V3_TBTLC_RTR

TBT_DDC_XBAR_EN_L

TBT_GPIO_9

TBT_GO2SX_BIDIR

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

TP_DP_TBTSRC_ML_CN<3>

DP_TBTSNK0_AUXCH_N

TBT_SPI_CS_L

SYSCLK_CLK25M_TBT

TBT_TMU_CLK_OUT
TBT_TMU_CLK_IN

=TBT_CLKREQ_L

TBT_EN_LC_PWR

TBT_MONOBSP

TBT_PCIE_RESET_L

TBT_PWR_ON_POC_RST_L

TBT_MONOBSN

TBT_RBIAS

R3690

1

2

C3690

1

2

R3692

1

2

R3691

1

2

R3655

1

2

C3601

1 2

C3600

1 2

C3602

1 2

C3603

1 2

C3604

1 2

C3605

1 2

C3606

1 2

C3607

1 2

C3640

1 2

C3641

1 2

C3642

1 2

C3643

1 2

C3645

1 2

C3644

1 2

C3646

1 2

C3647

1 2

R3625

1

2

R3632

1

2

R3630

1

2

R3631

1

2

R3629

1

2

R3693

1

2

C3629

1 2

C3628

1 2

C3627

1 2

C3626

1 2

C3625

1 2

C3624

1 2

C3623

1 2

C3622

1 2

C3621

1 2

C3620

1 2

C3630

1 2

C3631

1 2

C3632

1 2

C3633

1 2

C3634

1 2

C3635

1 2

C3636

1 2

C3637

1 2

C3638

1 2

C3639

1 2

U3600

D19

E20

D17

E18

D15

E16

D13

E14

B5

A6

U6

D11

E12

D9

E10

D7

E8

D5

E6

B3

A4

T5

B9

A8

B11

A10

B13

A12

B15

A14

D3

C2

V3

W4

AD3

R4

P5

K5

G2

M3 L2
H3 L4

T3

V5

M1

Y1

W2
J4

AA2
AB1

AC2

P3
M5

AD23

AC24

W16

W18

F1

F3

E22

G22

E24

G24

J22

L22

J24

L24

K1

G4

B17

A16

B19

A18

H1

J6

N2

E2

D1

N22

R22

N24

R24

U22

W22

U24

W24

P1

H5

B21

A20

B23

A22

K3

G6

L6

W6

N6
T1

Y5
U2

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

R6

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

J2

W20

AD21

AB21

U20

AA6

V1

R2

N4

AB5

Y7

AB3

Y3

AA4

AA24

AB23

R3698

1

2

R3695

1 2

R3696

1

2

R3699

1

2

U3690

6

5

7

2

1

9

8

4

3

R3697

1

2

R3615

1

2

R3688

1

2

R3687

1

2

R3686

1

2

R3685

1

2

R3680

1

2

R3682

1

2

C3610

1

2

R3610

1

2

R3683

1

2

R3681

1

2

051-9509

4.2.0

36 OF 113

34 OF 100

U4

90

90

90

98

15 21 34

92

82

34 98

34 98

82

34

34 85

34 84

34 84

34 85

34

82

6

34 35 36

90

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

82

82

82

82

82

82

90

90

90

90

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

90

82

34 98

34 98

34 98

34 98

34 98

90

34 98

90

90

34 98

34 98

34 98

34 98

34 98

90

90

90

90

98

34 98

6

34 35 36 84 85

34

6

34 35 36

6

34 35 36 84 85

98

34 98

6

34 35 36

34 83

34

82

34 98

98

VSSPE
VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE
VSSPE
VSSPE

VSSPE
VSSPE

VSS
VSS

VSS
VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VCC1P0_DPAUX

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

VCC1P0
VCC1P0

VCC3P3_DP
VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3_CIO

VCC3P3_CIO

VCC3P3

VCC3P3

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0
VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC3P3

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCCGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.

EDP: 1000 mA

250 mW (Dual Port)

??? mW (Single Port)

???? mW (Single-Port)
2700 mW (Dual-Port)
EDP: 3000 mA

250 mW (Dual-Port)
EDP: 240 mA

??? mW (Single-Port)

EDP: 10 mA

6.3V

1UF

X5R

0201

20%

6.3V

1UF

X5R
0201

20%

6.3V

20%

10UF

CERM-X5R
0402-1

6.3V

1UF

X5R

0201

20%

6.3V

1UF

X5R

0201

20%

1UF

6.3V
X5R
0201

20%

1UF

6.3V
X5R
0201

20%

10UF

6.3V

20%

CERM-X5R

0402-1

20%

6.3V

10UF

CERM-X5R

0402-1

6.3V

1UF

X5R
0201

20%

1UF

6.3V
X5R
0201

20%

CRITICAL

FCBGA

CACTUSRIDGE4C

OMIT_TABLE

20%

10UF

6.3V
CERM-X5R
0402-1

6.3V

1UF

X5R

0201

20%

1UF

6.3V
X5R

0201

20%

1UF

6.3V
X5R
0201

20%

1UF

6.3V
X5R

0201

20%

6.3V

1UF

X5R

0201

20%

6.3V

1UF

X5R
0201

20%

6.3V

1UF

X5R
0201

20%

1UF

6.3V
X5R

0201

20%

1UF

6.3V
X5R

0201

20%

1UF

6.3V
X5R

0201

20%

6.3V

1UF

X5R

0201

20%

1UF

6.3V
X5R

0201

20%

SYNC_DATE=01/11/2012

SYNC_MASTER=D7_DOUG

Thunderbolt Host (2 of 2)

=PP3V3_S4_TBT

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP3V3_TBTLC_RTR

C3714

1

2

C3715

1

2

C3710

1

2

C3711

1

2

C3712

1

2

C3716

1

2

C3717

1

2

C3713

1

2

C3700

1

2

C3701

1

2

U3600

K11
K15

R10

R14
T11

U10

V11
W10

L10

L14
M11

M15

N10
N14

P11
P15

G8

H9

J10
J12

J14

J16

J8

K17

T15
U14

V7
W8

G10

G12

V15
V19

W12

W14

G14
G16

G18

H19
K19

M19
P19

T19

M7
P7

T7

L18
N18

R18

H11

H13
H15

H17

H7

K7

AD1
K13

N16

N8
P13

P17

P9
R12

R16

R8
T13

T17

K9

T9
U12

U16

U8

V9

L12
L16

L8

M13
M17

M9

N12

A2

A24

AC12
AC14

AC16

AC18
AC20

AC22

AC4
AC6

AC8

B1

AA14

B7

C10
C12

C14

C16
C18

C20

C22
C24

C4

AA20

C6
C8

D21
D23

E4

F11
F13

F15

F17
F19

AA22

F21

F23
F5

F7
F9

G20

H21
H23

J18

J20

AA8

K21

K23

L20
M21

M23
N20

P21

P23
R20

T21

AB11

T23
U18

V13

V17
V21

V23
Y11

Y13

Y15
Y17

AB17

Y19

Y21
Y23

Y9

AB7

AC10

C3760

1

2

C3772

1

2

C3771

1

2

C3770

1

2

C3790

1

2

C3744

1

2

C3743

1

2

C3742

1

2

C3741

1

2

C3740

1

2

C3745

1

2

C3705

1

2

C3773

1

2

C3774

1

2

051-9509

4.2.0

37 OF 113
35 OF 100

6

34 36 84 85

6

6

36

6

34 36

GND

VOUT

ON

VIN

OUT

IN

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

VOUT

GND

ON

VIN

GND

VOUT

ON

VIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

OUT

IN

D

SG

IN

D

S G

OUT

D

GS

IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DLY = 60 ms +/- 20%

20.3 mOhm Typ

1.05V TBT "CIO" Switch

Supervisor & CLKREQ# Isolation

Pull-up provided by SB page.

Platform(PCIe) Reset

Platform (PCIe) Reset

@ 1.0V

R(on)

Part

Type

3.3V TBT "LC" Switch

1.05V TBT "LC" Switch

R(on)
@ 2.5V

Part

Type

Max Current = 2A (85C)

Max Current = 2A (85C)

28.6 mOhm Max

Load Switch

TPS22924C

U3815

25.8 mOhm Max

Load Switch

U3810

TPS22924C

18.5 mOhm Typ

Delay = 27.3ms

TPS3808G25

(IPU)

Max Current = 4A (85C)

Vt = 2.33V +/- 2%

Pull-up: R3610

@ 1.05V

R(on)

Type

Part

Load Switch

11.5 mOhm Max

8 mOhm Typ

U3820

TPS22920

BOM options provided by this page:

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP1V05_TBT_FET (1.05V FET Output)

TBTBST:Y - Stuffs 15V boost circuitry.

Signal aliases required by this page:

- =PP15V_TBT_REG (15V Boost Output)

Power aliases required by this page:

- =TBT_CLKREQ_L

- =TBT_RESET_L

Page Notes

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

Intel investigating whether RC is sufficient.

TBT "POC" Power-up Reset

TPS22924

CSP

CRITICAL

34

25V
X5R

0.1UF

10%

402

26

34

6.3V
CERM

402

10%

1UF

1UF

10%

6.3V
CERM

402

CRITICAL

TDFN

SLG4AP016V

402

100K

MF-LF

1/16W

5%

10%

6.3V
CERM

402

1UF

1%

36.5K

402

1/16W
MF-LF

CSP

CRITICAL

TPS22920

CSP

CRITICAL

TPS22924

402

CERM

6.3V

10%

1UF

CRITICAL

QFN

TPS3808

0.1UF

10%
X5R

25V
402

34

10%
25V

402

0.0047UF

CERM

21

SOT563

SSM6N37FEAPE

34

5%

402

1/16W
MF-LF

100K

SSM6N37FEAPE

SOT563

100K

MF-LF

1/16W

402

5%

15 21

SSM3K15AMFVAPE

VESM

34

10K

402

5%

MF-LF

1/16W

330PF

CERM

50V

10%

402

44 45 61

Thunderbolt Power Support

SYNC_MASTER=D7_DOUG

SYNC_DATE=01/11/2012

SMC_DELAYED_PWRGD

=PP3V3_S0_PCH_GPIO

TBTPOCRST_MR_L

=PP3V3_TBTLC_RTR

=PP3V3_TBTLC_RTR

=PP3V3_S4_TBT

=PP1V05_TBTCIO_FET

=PP1V05_S0_P1V05TBTFET

=PP3V3_TBTLC_FET

=PP1V05_TBTLC_FET

=PP3V3_S0_P3V3TBTFET

=PP1V05_S0_P1V05TBTFET

TBT_PWR_ON_POC_RST_L

TBTPOCRST_CT

TBT_EN_CIO_PWR

TBT_EN_CIO_PWR_L

TBT_EN_LC_PWR

TBT_EN_LC_RC

TBT_PCIE_RESET_L

=PP1V05_TBTLC_RTR

=PP3V3_S0_TBTPWRCTL

TBT_EN_LC_ISOL

=TBT_RESET_L

TBT_CLKREQ_L

TBT_CLKREQ_ISOL_L

MAKE_BASE=TRUE

=TBT_CLKREQ_L

TBT_SW_RESET_L

U3810

C1

C2

A2

B2

A1

B1

C3800

1

2

C3810

1

2

C3815

1

2

U3800

6

5

7

3

8

4

2

9

1

R3807

1

2

C3816

1

2

R3816

1

2

U3820

D1

D2

A2

B2
C2

A1

B1
C1

U3815

C1

C2

A2

B2

A1

B1

C3820

1

2

U3830

3

5

4

62

7

1

C3830

1

2

C3831

1

2

Q3825

6

2

1

R3820

1

2

Q3825

3

5

4

R3830

1

2

Q3840

3

1

2

R3840

1

2

C3825

1

2

36 OF 100

38 OF 113

4.2.0

051-9509

6

15 19 20

6

34 35 36

6

34 35 36

6

34 35 84 85

6

6

36

6

6

6

6

36

6

35

6

IN

IN

OUT

OUT

IN

OUT

OUT

IN

IN

BI

BI
BI

BI
BI
BI
BI
BI

BI

BI
BI

OUT

IN

IN

IN

OUT

OUT

IN

IN

OUT

IN

OUT

BI

BI
BI

IN

BI

BI

BI

BI
BI

NC

RESET*

CS*

SCK

SO

WP*

SI

GND

VCC

IN

IN

NC

WAKE*

CR_DATA4
CR_DATA5

CR_LED*/CR_BUS_PWR

MS_INS*

CR_DATA7

CR_DATA6

CR_DATA0

CR_WP*

CR_CLK

TRD3_N

TRD3_P

GPIO_0/CR_ACT_LED*

GPIO_1/LR_OUT

GPIO_2/MEDIA_SENSE

SD_DETECT

CR_CMD

PCIE_TXD_P

PCIE_RXD_P

CR_DATA3

CR_DATA2

CR_DATA1

SR_DISABLE

SCLK_SPD1000LED*

SO_LINKLED*
CS*/EECLK

LOW_PWR

SI/EEDATA

BIASVDDH

XTALVDDH

VDDO

SMB_DATA

PERST*

SMB_CLK

PCIE_TXD_N

PCIE_REFCLK_N

AVDDH

VDDC

SR_LX

SR_VFB

SR_VDDP

SR_VDD

SPD100LED*/SERIAL_DO
TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

VMAIN_PRSNT

PCIE_RXD_N

PCIE_REFCLK_P

CLKREQ*

THRM_PAD

XTALI
XTALO

RDAC

AVDDL

PCIE_PLLVDDL

GPHY_PLLVDDL

TRD2_P

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD)

(OD)

used, this pin can float (alias to
TP_). If not used, must be pulled
to 3.3V ENET via 1K resistor (not

(IPU-ENET)

Control signal to light LED or control SD bus power.

the card reader on-chip I/O.

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

Connect only to U3900 pin 20.

If ENET switching regulator is

Internal 1.2V Switching Regulator pins.

BCM requests SD CR[0:7], CMD, CLK termination.

ENET_SR_DISABLE

(IPD-ENETM)

NOTE: "IPx" == Programmable pull-up/down

(IPU-ENET)

Avoids need for EFI to program at startup.

info as well as code for Bonjour proxy.

Special Star routing needed on these pins. Decoupling on Pg 37.

NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures ENET for the

provided on this page).

(IPU-ENET)

=ENET_WAKE_L to PCIE_WAKE_L.

Limiting

(OD)

(See note)

WAKE#

ENET 1.2V SR IS ENABLED IF FLOATING.

(See note)

(IPU-ENET)

396mA (1000base-T, Caesar II)

(IPU)

Atmel AT45DB011D (1Mbit) ROM. If a different

(OD)

(IPx-ENET)

ENET supports both active-levels for WP.

o

(IPD)

(IPD)

ROM is used then the straps must change.

ENET_CR Signals

Resistor

Current

(Required ROM size 1 Mbit)

(IPU-ENET)

(NO IPU OR IPD-ENET)

Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard

If PHY is always powered then alias

N-channel FET isolation suggested.

281mA (1000base-T max power, Caesar IV)

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

VDD for Card Reader I/O

ROM contains MAC address, PCIe config

PHY Non-Volatile Memory

NOTE: ENETM requires SI pull-down instead of SO.

No MS (Memory Stick) Insert feature needed.

(OD)

SD_DETECT can only be used active low due to errata.

(IPD-ENET)

X5R
603

20%

10UF

6.3V

4.7UF

402

20%

6.3V
X5R-CERM1

FERR-600-OHM-0.5A

CRITICAL

SM

4.7UF

20%

6.3V
402

X5R-CERM1

1K

MF-LF
402

5%
1/16W

90 18

90 18

18 15

38

39 26

MF-LF
402

1%
1/16W

1.24K

90 18

90 18

90 18

90 18

93 38

93 38

93 38

93 38

93 38

93 38

93 38

93 38

4.7K

MF-LF
402

5%
1/16W

MF-LF

402

5%

1/16W

4.7K

93 39

93 39

93 39

93 39

93 39

NOSTUFF

4.7K

MF-LF
402

5%
1/16W

93 39

93 39

93 18 15

4.7K

MF-LF

402

5%

1/16W

38

93 37

93 37

93 37

93 37

39

93 37

93 37

93 37

93 37

93 39

93 39

93 39

93 39

93 39

5%

1K

MF-LF

402

1/16W

OMIT_TABLE

AT45DB011D

SOIC-8S1

39

92 26

33

1/20W

PLACEMENT_NOTE=PLACE R3961 NEAR U3900

2015% MF

0.1UF

X5R-CERM

0201

10%
16V

X5R-CERM

10%
16V

0201

0.1UF

0201

10%
16V
X5R-CERM

0.1UF

16V

0.1UF

10%
X5R-CERM

0201

16V

0.1UF

0201

10%

X5R-CERM

16V

X5R-CERM

10%

0.1UF

0201

0201

10%
16V

X5R-CERM

0.1UF

10%

0.1UF

0201

X5R-CERM

16V

0.1UF

X5R-CERM

0201

10%
16V

0201

0.1UF

10%
16V

X5R-CERM

X5R-CERM

0201

10%
16V

0.1UF

0.1UF

X5R-CERM

0201

10%
16V

0.1UF

X5R-CERM
0201

10%
16V

33

PLACEMENT_NOTE=PLACE R3979 NEAR U3900

MF 2015%

1/20W

PLACEMENT_NOTE=PLACE R3971 NEAR U3900

33

MF 2015%

1/20W
1/20W

PLACEMENT_NOTE=PLACE R3972 NEAR U3900

33

2015% MF

5%

PLACEMENT_NOTE=PLACE R3973 NEAR U3900

33

MF 201

1/20W

PLACEMENT_NOTE=PLACE R3974 NEAR U3900

33

MF5%

1/20W

201

PLACEMENT_NOTE=PLACE R3975 NEAR U3900

33

MF 2015%

1/20W

PLACEMENT_NOTE=PLACE R3976 NEAR U3900

33

MF5%

1/20W

201

PLACEMENT_NOTE=PLACE R3977 NEAR U3900

33

MF5%

1/20W

201

PLACEMENT_NOTE=PLACE R3978 NEAR U3900

MF

1/20W

33

5% 201

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

0402

FERR-600-OHM-300MA-0.85OHM

CRITICAL

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

FERR-600-OHM-300MA-0.85OHM

CRITICAL

0402

0402

CRITICAL

FERR-600-OHM-300MA-0.85OHM

BCM57766C0KMLG

QFN-8X8

OMIT_TABLE

0.1UF

X5R-CERM

0201

10%
16V

6.3V
X5R-CERM1

20%
402

4.7UF

X5R-CERM1

402

20%

6.3V

4.7UF

1/16W

5%

402

MF-LF

4.7K

SYNC_MASTER=D7_NICK

SYNC_DATE=01/12/2012

ETHERNET PHY (CAESAR IV)

ENET_CR_DATA<4>
ENET_CR_DATA<5>

ENET_CR_PWREN

ENET_CR_DATA<7>

ENET_CR_DATA<0>

ENET_SD_CMD

ENET_CR_DATA<3>

ENET_CR_DATA<2>

ENET_SR_DISABLE

ENET_LOW_PWR

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

ENET_CLKREQ_L

SYSCLK_CLK25M_ENET

ENET_RDAC

PCIE_ENET_R2D_C_P

=PP3V3_S0_ENET

=PP3V3_ENET_PHY

ENET_MISO

SDCONN_DATA<6>

SDCONN_DATA<5>

SDCONN_DATA<4>

SDCONN_DATA<1>

SDCONN_DATA<0>

SDCONN_CMD

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

ENET_CS_L

ENET_SCLK ENET_MOSI

PCIE_ENET_D2R_N

SDCONN_DATA<3>

ENET_CR_DATA<6>

SDCONN_WP

SDCONN_DATA<7>

ENETCONN_MDI_N<2>

PP1V2_ENET_PHY_GPHYPLL

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.15 mm

MIN_LINE_WIDTH=0.4 mm

SDCONN_DATA<2>

SDCONN_CLK

ENETCONN_MDI_N<1>

PP1V2_ENET_PHY_AVDDL

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm

=PP1V2_ENET_PHY

VOLTAGE=3.3V

PP3V3R1V8_CR_VDDIO

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.15 mm

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

PP1V2_ENET_PHY_PCIEPLL

MIN_LINE_WIDTH=0.4 mm

=PP3V3_ENET_PHY

ENETCONN_MDI_P<2>

ENETCONN_MDI_P<1>

ENET_SR_VFB

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=3.3V

ENET_XTALVDDH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_ENET_PHY_BIASVDDH

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

PP3V3_ENET_PHY_AVDDH

ENET_SR_LX

ENETCONN_MDI_N<0>

ENET_SD_CLK

ENET_MEDIA_SENSE

ENETCONN_MDI_P<0>

ENET_VMAIN_PRSNT

PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P

PCIE_ENET_R2D_P

=ENET_WAKE_L

ENET_TRAFFICLED_L

ENET_MOSI

ENET_CR_3V3_EN_L

ENET_CS_L

ENET_SCLK

SMB_ENET_SCL

ENET_MISO

ENET_CR_DATA<1>

ENET_SD_DETECT_L

PCIE_ENET_R2D_N

SMB_ENET_SDA

ENET_RESET_L

ENETCONN_MDI_P<3>
ENETCONN_MDI_N<3>

ENET_CR_1V8_EN

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.15 mm

PP3V3R1V8_ENET_LR_OUT

C3900

1

2

C3930

1

2

C3915

1

2

R3997

1

2

C3935

1

2

C3925

1

2

L3925

1 2

C3920

1

2

R3942

1

2

R3965

1

2

R3941

1

2

R3940

1

2

R3990

1

2

R3910

1

2

R3981

1 2

U3990

4

7

3

2 1

8

6

5

R3961

1 2

C3905

1

2

C3910

1

2

C3911

1

2

C3916

1

2

C3921

1

2

C3926

1

2

C3931

1

2

C3936

1

2

C3950

1 2

C3951

1 2

C3955

1 2

C3956

1 2

C3990

1

2

R3979

1 2

R3971

1 2

R3972

1 2

R3973

1 2

R3974

1 2

R3975

1 2

R3976

1 2

R3977

1 2

R3978

1 2

L3900

1 2

L3905

1 2

L3910

1 2

L3920

1 2

L3930

1 2

U3900

42

48

394551

37

12

21

26

25
24
23
22
52
53
54
55

60
57

63

36

5
8
9

4

59

29

32

30

31

34

33

27
28

11

38

66

1

64

6

10

65

2

68

161415

13

69

67

41

40

43

44

47

46

49

50

20

35

61

75662

58

3

18
19

17

37 OF 100

4.2.0

051-9509

39 OF 113

93

93

93

93

93

93

93

93

6

38 37

6

93

38

38

38 37

6

38

38

93

90

90

90

38

93

90

38

38

BI
BI
BI
BI

BI

BI

BI

BI

G

DS

IN

G

D

S

G

D

S

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

TX

RX

TX

RX

D

GS

ENET_MDI_TRAN2+
ENET_MDI_TRAN1+

ENET_MDI_TRAN3-

SHIELD

ENET_MDI_TRAN0­ENET_MDI_TRAN0+

ENET_MDI_TRAN2-

ENET_MDI_TRAN1-

ENET_MDI_TRAN3+

ENET_MDI

PINS

D

G

S

D

G

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Power decoupling

Feedback loop

CAESAR IV 1.2V INT.VR CMPTS

CAESAR IV ACTIVITY LED

SILKSCREEN:ENET ACT

3.3V ENET FET

157S0058

"ENET" = "S0" || ("S3/S5" && "WOL_EN")

ENET Enable Generation

CAESAR IV WAKE# ISOLATION

514-0822

93 38

93 38

93 38

93 38

93 38

93 38

93 38

93 38

402

10%

0.01UF

50V
X7R

SOT-23-HF

NTR4101P

CRITICAL

X5R
402

10%
16V

0.033UF

MF-LF

5%

1/16W

402

100K

MF-LF

402

5%

1/16W

10K

21 15

2N7002DW-X-G

SOT-363

2N7002DW-X-G

SOT-363

60 45 44 28 19 15

402

10%
X5R

16V

0.1UF

20%

4.7UF

402

X5R-CERM1

6.3V

MF-LF
402

5%
1/16W

10K

402

MF-LF

1/16W

5%

330

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

4.7UH-0.8A

PCAA031B-SM

603

10UF

20%
X5R

6.3V

0.1UF

402

X5R

10%
16V

93 38

93 38

93 38

93 38

93 38

93 38

MF-LF
402

1/16W

5%

75

93 38

93 38

75

1/16W
MF-LF
402

5%

MF-LF

75

5%
1/16W

402

75

5%
MF-LF

1/16W
402

1206

10%

NOSTUFF

2KV

1000PF

CERM

93 37

93 37

93 37

93 37

93 37

93 37

10V

0.1UF

20%

402

CERM

10V
CERM

0.1UF

20%

402

93 37

93 37

CERM

10V

0.1UF

20%

402

CERM

10V

0.1UF

20%

402

CRITICAL

SM

LFE8904CF

SM

CRITICAL

LFE8904CF

VESM

SSM3K15AMFVAPE

K70-K72

F-ANG-TH

CRITICAL

UFET-1.60X1.60

FDME1024NZT

OMIT_TABLE

FDME1024NZT

UFET-1.60X1.60

MF-LF

5%

1/16W

402

0

1/16W
MF-LF

5%

0

402

NOSTUFF

16V

10%

0201

X5R-CERM

0.1UF

X5R-CERM

0.1UF

10%
16V

0201

4.7UF

X5R-CERM1

20%

6.3V
402

1/20W

MF

10K

5%

201

1/20W

MF

10K

5%

201

1

CRITICAL

Q4030

MOSFET,COMP N-/P-CH,20V,3.8/2.6A

376S1092

Ethernet Support & Connector

SYNC_DATE=01/12/2012

SYNC_MASTER=D7_NICK

ENETCONN_MDI_T_N<2>

=PP3V3_S4_ENET_FET

PM_SLP_S3_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.15MM

PP3V3R1V8_CR_FET

MIN_LINE_WIDTH=0.3MM

PP3V3R1V8_CR_VDDIO

ENET_CR_1V8_EN

=PP3V3_S4_FET_ENET

=PP3V3_S4_ENET_FET

ENET_CR_3V3_EN_L

ENET_CR_3V3_EN_L

ENETCONN_MDI_T_N<1>

PM_EN_ENET_L

MAKE_BASE=TRUE

ENET_WAKE_L

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

VOLTAGE=1.2V

ENET_SR_LX

MIN_NECK_WIDTH=0.2MM

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 MM

ENETCONN_MCT_BS

MIN_NECK_WIDTH=0.2 mm

ENETCONN_MDI_T_P<2>
ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_N<0>
ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_P<1>

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_N<2>

ENETCONN_MDI_N<2>

ENETCONN_MDI_N<3>

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_P<1>

PP3V3_ENET_FET

P3V3ENET_SS

WOL_EN

=PP3V3_ENET_PHY

ENET_ACT

=PP3V3_ENET_PHY

=ENET_WAKE_L

ENET_SR_VFB

PP1V2_ENET_INTREG

ENETCONN_MDI_N<0>

=PP1V2_ENET_PHY

PCIE_WAKE_L

=PP3V3_ENET_PHY

ENETCONN_MCT1

ENETCONN_MDI_T_P<2>

ENETCONN_MDI_N<1>

ENETCONN_MDI_P<3>

ENETCONN_MDI_P<2>

ENETCONN_MDI_P<0>

ENETCONN_TCT

ENETCONN_MDI_T_P<0>

ENETCONN_MCT0

ENETCONN_MCT2

ENETCONN_MCT3

ENETCONN_MDI_T_P<3>

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V

PP1V2_ENET_INTREG

MAKE_BASE=TRUE

=PP1V8_S0_ENET

PP3V3R1V8_ENET_LR_OUT

ENET_CR_1V8_EN

ENET_TRAFFICLED_L

C4021

12

Q4020

3

1

2

C4020

1

2

R4021

1 2

R4020

1

2

Q4021

6

2

1

Q4021

3

5

4

C4011

1

2

C4010

1

2

R4070

1

2

R4050

1

2

LED3850

A

K

L4010

1 2

C4012

1

2

C4013

1

2

R4003

1

2

R4002

1

2

R4001

1

2

R4000

1

2

C4000

1

2

C4004

1

2

C4003

1

2

C4002

1

2

C4001

1

2

T4000

1

10

11

12

2

3

4

5

6 7

8

9

T4010

1

10

11

12

2

3

4

5

6 7

8

9

Q4070

3

1

2

J4000

1

10
11
12
13
14

2

3

4

5

6

7

8

9

Q4030

3 8

5

4

Q4030

6 7

2

1

R4030

1 2

R4031

1 2

C4032

1

2

C4031

1

2

C4030

1

2

R4032

1

2

R4033

1

2

051-9509

4.2.0

40 OF 113
38 OF 100

38

37

38 37

6

38

38 37

38 37

37

93

6

38 37

6

38 37

6

37

37

38

37

33 19

38 37

6

93

93

93

93

38

6

37

38 37

37

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

LOW_PWR

GND

THRM

VDD

RST_OUT*

DET_OUT

DET_CHNGD*

DET_LVL

DET_IN

RST_IN*

DET_CH_EN*

DLY

RST

LOGIC

XOR

(IPU)

XOR

(OD)

(OD)

PAD

BI
BI
BI

BI

BI
BI
BI
BI

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

SHLD_PIN

CRD_DETECT_SWITCH

SHLD_PIN

SHLD_PIN

SHLD_PIN

DAT6

DAT5

DAT7

DAT2

DAT1

DAT0

DAT4

VSS

CMD

CLK

VDD

VSS

CD/DAT3

WRITE_PROTECT_SWITCH

SHLD_PIN

THRML

OUT

GND

FAULT*

ILIM

EN

IN

PAD

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.

FROM SD CONN ->

regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms

-> TO ENET CHIP

DLY block is 20ms nominal

SD switch is normally connected (i.e. gnd)

SD CARD CONNECTOR

-> TO PCH GPIO

516-0249

353S2548

SD CARD 3.3V OVERCURRENT PROTECTION CHIP

93 37

93 37

93 37

20%

603

10UF

X5R

6.3V

16V

10%
X7R-CERM

0.1UF

402

47K

402

1/16W
MF-LF

5%

6.3V

20%

10UF

X5R
603

16V

10%

X7R-CERM

0.1UF

402

10K

5%
1/16W
MF-LF
402

37

402

1/16W
MF-LF

0

5%

20 15

93 37

402-1

X5R

10V

10%

1UF

37 26

1/16W
MF-LF

402

10K

5%

NOSTUFF

0

MF-LF

5%

1/16W

402

26

5%

0

MF-LF

1/16W

402

NOSTUFF

50V
CERM
402

5%

22PF

NOSTUFF NOSTUFF

402

50V

5%

15PF

CERM

SLG4AP026V

TDFN

CRITICAL

1/16W
MF-LF

10K

5%

402

MF-LF 1/16W

5%0402

1/16WMF-LF

402

5%

0

93 37

0

402

1/16WMF-LF

5%

1/16WMF-LF

5%0402

402

1/16WMF-LF

5%

0

5%

MF-LF 1/16W

402

0

402

1/16WMF-LF

5%

0

402

1/16WMF-LF

5%

0

0

5%

MF-LF 1/16W

402

402

MF-LF 1/16W

5%

0

93 37

93 37

93 37

93 37

93 37

93 37

93 37

SD-CARD-K70-K72

F-ANG-TH

SON

CRITICAL

TPS2553

26.1

1%
1/16W
MF-LF
402

37

CASE-B2-SM

NOSTUFF

20%

6.3V

POLY-TANT

100UF

CRITICAL

SYNC_DATE=01/12/2012

SD READER CONNECTOR

SYNC_MASTER=D7_NICK

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0_SW_SD_PWR

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

ENET_CR_PWREN

SDCONN_ILIM

SDCONN_OC_L

=PP3V3_S0_SW_SD_PWR

=PP3V3_S0_SDCARD

=PP3V3_S0_SDCARD

SDCONN_WP

SDCONN_CMD_R

SDCONN_CMD

SDCONN_DATA_R_<1>

SDCONN_DATA<1>

SDCONN_CLK

SDCONN_CLK_R

SDCONN_DATA_R_<4>

SDCONN_DATA<4>

SDCONN_DATA_R_<6>

SDCONN_DATA<6>

SDCONN_DATA_R_<7>

SDCONN_DATA<7>

SDCONN_DATA_R_<0>

SDCONN_DATA<0>

SDCONN_DATA_R_<2>

SDCONN_DATA<2>

SDCONN_DATA_R_<5>

SDCONN_DATA<5>

SDCONN_DATA_R_<3>

SDCONN_DATA<3>

SDCONN_DETECT_L

=PP3V3_S0_SW_SD_PWR

ENET_RESET_L

SDCONN_DETECT_L

ENET_SD_DETECT_L

SDCONN_STATE_CHANGE

SLG_ENET_RESET_L

SLG_ENET_RESET_R_L

ENET_LOW_PWR

SD_DETECT_LVL

ENET_SD_RESET_L

=PP3V3_S4_SDCARD

C4102

1

2

C4103

1

2

R4100

1

2

C4100

1

2

C4101

1

2

R4101

1

2

R4114

1 2

C4110

1

2

R4110

1

2

R4111

1 2

R4112

1 2

C4171

1

2

C4170

1

2

U4111

6

9

7

1

8

5

2

3

4

11

10

R4115

1

2

R4102

1 2

R4103

1 2

R4104

1 2

R4105

1 2

R4106

1 2

R4107

1 2

R4108

1 2

R4109

1 2

R4116

1 2

R4117

1 2

J4100

1

5

2

14

7
8

9
10
11
12
13

16
17
18
19
20
21
22
23
24
25
26
27

4

3

6

15

U4100

4 3

5

2

6

1

7

R4113

1

2

C4104

1

2

051-9509

4.2.0

41 OF 113
39 OF 100

39

39

6

39

6

93

93

93

93

93

93

93

93

93

93

39

39

39

15

6

DVSS3

OVSS1

SF_WP*

THRM

UART1_TX

UART1_RX

RST*

USB_VRES

TEST

CS_RSTB

CS_CLK

VDDA_PLL

USB_VDDL0

MAVDD33

DVDD6

DVDD4

DVDD3

VSSA_PLL

SF_CS*

CS_SDA

LED_FIXED

USB_PADP
USB_PADM

CS_SCK

CLKOUT

OVSS2

USB_VSDL0

MIPI_RESISTOR

SF_CLK

CS_PWDB

SF_DIN
SF_DOUT

MRXDATAINN

AUD_CLK0

CLKIN

MRXCLKINN

MRXCLKINP

MRXDATAINP

GPIO9

GPIO3

GPIO1

GPIO0

USB_VSSA0

DVSS4

DVSS6

MAVSS

USB_VDDA0

OVDD1

OVDD2

PAD

NC

NC

NC

EN

NC

NC

VO

VIN

GND

IN

NC
NC

HOLD*

SCLK

WP*

CS*

VCC

THRM

GND

SO/SIO1

SI/SIO0

PAD

SYM_VER-1

SYM_VER-1

A

B

Y

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SPI clock during power-on.

UART1_TX is strap for selection

335S0852

’0’= INT FW

’1’= EXT FW

337S4151

GPIO AFTER POWER ON

’1’ = POSITIVE EDGE
’0’ = NEGATIVE EDGE

of pos/neg edge sampling of

USB CAMERA CONTROLLER

SERIAL FLASH

Use 100 ohms and 150pF for 10MHz filter

Camera/ALS/DMIC connector

CRYSTAL

PP1V2_S0_CAMERA Vreg

STITCH THERMAL PAD TO INNER GROUND

GPIO3 CAN BE CONFIGED AS GENERAL

GPIO3, EXT/IN FIRMWARE BOOT SEL

X5R
201

10%

6.3V

0.1UF

0201-MUR

20%
X5R

6.3V

1.0UF

6.3V

20%
X5R

1.0UF

0201-MUR

24K

1%

201

MF

1/20W

PLACE_NEAR=U4200.33:5mm

201

1%
MF

1/20W

47

8.2K

PLACE_NEAR=U4200.24:5mm

1%
MF

201

1/20W

0201-MUR

1.0UF

X5R

20%

6.3V

SHORT-0201

SHORT-0201

X5R

10%

6.3V
201

0.1UF

10%

0.1UF

6.3V
X5R
201

PLACE_NEAR=U4200.24:5mm

0.1UF

10%

6.3V
X5R
201

201

X5R

6.3V

10%

0.1UF

0.1UF

X5R

10%

201

6.3V

10%

6.3V
X5R
201

0.1UF

201

0.1UF

10%

6.3V
X5R

6.3V
201

10%
X5R

0.1UF

FQFN

VC0359

201

1%
MF

1K

1/20W

201

MF

1K

1/20W

1%

20455-020E-32

F-RT-SM

0402

FERR-1000-OHM

0

0

MF

1/20W

1M

201

1%

SM-3.2X2.5MM

12.000MHZ-30PPM-10PF

18PF

201

25V

NP0-C0G

5%

47

1%

1/20W

MF

201

18PF

NP0-C0G

25V

5%

201

X5R

10%

6.3V

0.1UF

201

1/20W

201

10K

MF
1%

10K

MF
201

1/20W

1%

FERR-600-OHM-300MA-0.85OHM

0402

X5R

0.1UF

10%

6.3V
201

0402

FERR-1000-OHM

1/20W

MF5%

10

201

ISL9021AIRUWZ-T

DFN

10%

1UF

16V
X5R
402

60

6.3V
X5R-CERM1

4.7UF

20%

402

X5R
402

1UF

16V

10%

FERR-1000-OHM

0402

X5R

10%
16V

1UF

402

FERR-1000-OHM

0402

0402

FERR-1000-OHM

X5R

16V

10%

1UF

402

201

MF

1/20W

5%

0

5%
CERM

402

50V

150PF

NOSTUFF

5%
MF

1/20W

201

0

150PF

5%

402

CERM

NOSTUFF

50V

1MBIT-104MHZ

OMIT_TABLE

USON

CRITICAL

MX25L1006EZUI-10G

1/20W

10K

1%
MF

201

PLACE_NEAR=U4200.6:5mm

1%

1/20WMF201

33

PLACE_NEAR=U4200.5:5mm

1/20W

33

MF

201

1%

PLACE_NEAR=U4202.2:5mm

201

MF

1/20W

1%

33

10K

1%
1/20W

201

MF

4.7K

5%
1/20W
MF
201

120-OHM-90MA

DLP0NS

120-OHM-90MA

DLP0NS

402

16V

1UF

10%
X5R

74AHC1G08GV

SOT753

6.3V

10%
X5R

201

0.1UF

Camera Controller

VOLTAGE=1.2V

PP1V2_S0_CAMFILT

MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.6 MM

SMIA_DATA_P

TP_CAM_GPIO1

PCH_CAM_EXT_BOOT_R

=CAM_RESET_L

CAM_USB_VRES

CAM_TEST

I2C_CAMSENSOR_SDA

PP3V3_S0_CAMFILT

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM

PP1V2_S0_CAMERA

MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.2V

MIN_NECK_WIDTH=0.15 MM

PP1V2_S0_F_R

MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.2V

MIN_NECK_WIDTH=0.15 MM

MAKE_BASE=TRUE

USB_CAMERA_N

USB_CAMERA_P

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.15 MM

PP5V_S0_CAMERA_F

MIN_LINE_WIDTH=0.6 MM

PP1V8_S0_CAMERA_F

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.8V

PP3V3_S4_ALS_F

MIN_LINE_WIDTH=0.6 MM
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.15 MM

VOLTAGE=3.3V

PP3V3_DMIC_CONN

MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.4MM

CAM_XTAL_IN

CAM_RX

CAM_AGND

=PP3V3_S0_CAMERA

CAM_PROC_RESET_L

PCH_CAM_RESET_R

=PP3V3_S0_CAMERA

CAM_XTAL_OUT_R

CAM_XTAL_IN

CAM_XTAL_OUT

=PP3V3_S4_ALS

=PP1V8_S0_CAMERA

=PP5V_S0_CAMERA

=PP3V3_S0_AUDIO

AUD_DMIC_SDA1_CONN

AUD_DMIC_SDA1

=SMB_ALS_SCL

=SMB_ALS_SDA

AUD_DMIC_CLK_CONN

AUD_DMIC_CLK

PP3V3_S4_ALS_F

PP1V8_S0_CAMERA_F

SMB_ALS_F_SDA

I2C_CAMSENSOR_SDA
I2C_CAMSENSOR_SCL

SMB_ALS_F_SCL

SMIA_DATA_F_N
SMIA_DATA_F_P

PP5V_S0_CAMERA_F

SMB_ALS_F_SDA

SMB_ALS_F_SCL

GND_AUDIO_DMIC

SMIA_CLK_P

SMIA_CLK_N

SMIA_CLK_F_P

SMIA_CLK_F_N

SMIA_DATA_P

SMIA_DATA_N

CAM_SF_HOLD_L

CAM_PROC_RESET_L

TP_LED_PWM

SMIA_CLK_P

CAM_AGND

TP_ISM_CLK

PP1V2_S0_CAMERA

CAM_TX

CAM_SF_DOUT

CAM_SF_DIN

CAM_SF_DIN_R

CAM_SF_WP_L

=PP1V8_S0_CAMERA

PP1V2_S0_CAMERA

TP_ISM_RST_L

TP_CS_PWD_L

SMIA_CLK_N

=PP3V3_S0_CAMERA

CAM_SF_DOUT

CAM_SF_DIN

CAM_SF_CS_L

CAM_SF_WP_L

USB_PCH_8_N

USB_PCH_8_P

CAM_PLLGND

CAM_SF_CLK

CAM_AGND

I2C_CAMSENSOR_SCL

SMIA_DATA_N

CAM_XTAL_OUT

CAM_PLLGND

MIPI_RESISTOR

CAM_SF_CLK

CAM_SF_DOUT_R

CAM_SF_CLK_R

CAM_SF_CS_L

=PP1V8_S0_CAMERA

=PP3V3_S0_CAMERA

=PM_EN_REG_P1V2_S0

C4218

1

2

C4216

1

2

C4221

1

2

R4204

1

2

R4216

1

2

R4213

1

2

C4222

1

2

XW4202

1 2

XW4203

1

2

C4223

1

2

C4226

1

2

C4219

1

2

C4215

1

2

C4224

1

2

C4217

1

2

C4214

1

2

C4213

1

2

U4200

45

9
10

38

37

36
41
42

163443

15

35

44

48
47
46
12

17

32

31

33

29

30

27

28

7

40

8

39

1

6
3
5
4
2

11

49

14
13

21

20

23

19

24

18

22

26

25

R4218

1

2

R4219

1

2

J4200

21
22

23
24

1

10
11
12
13
14
15
16
17
18
19

2

20

3
4
5
6
7
8
9

L4200

1 2

R4260

1 2

R4264

1 2

R4214

1

2

Y4200

2 4

1 3

C4227

1 2

R4215

1 2

C4225

1 2

C4228

1

2

R4211

1

2

R4210

1

2

L4220

1 2

C4220

1

2

L4210

1 2

R4220

1 2

U4250

3

4

2
5

1

6

C4255

1

2

C4258

1

2

C4262

1

2

L4202

1 2

C4264

1

2

L4204

1 2

L4206

1 2

C4266

1

2

R4267

1 2

C4267

1

2

R4268

1 2

C4268

1

2

U4202

1

4

7

6

5

2

9

8

3

R4206

1

2

R4203

1 2

R4205

12

R4209

1 2

R4207

1

2

R4208

1

2

L4214

1 2

34

L4212

1 2

34

C4265

1

2

U4210

3

2

1

4

5

C4256

1

2

051-9509

4.2.0

42 OF 113
40 OF 100

40 93

21

61

40 93

40

93

93

40

40

40

40

40

6

40

40

21

6

40

40

40

6

6

40

6

6

52 54 55 58

52

47

47

52

40

40

40

40 93

40 93

40

93

93

40

40

40

52

40 93

40 93

93

93

40 93

40 93

40

40 93

40

40

40 93

40 93

93

40 93

6

40

40

40 93

6

40

40 93

40 93

40 93

40 93

20

20

40

40 93

40

40 93

40 93

40

40

40 93

93 93

40 93

6

40

6

40

OUT
IN

A1_P
A1_N

SEL

XSD

B0_P

B1_P

B0_N

B1_N

C0_P

C1_P

C0_N

C1_N

VDD

VDD

VDD

VSS

VSS

VSS

THRM

A0_P
A0_N

PAD

IN

IN

IN
IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

VCC+

GND

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

518S0812

353S3361

Drive asleep: HDD drives HDD_OOB_TEMP low

SATA Activity LED

Trip is 1.0V

0.0V to 0.3V

HDD Out-of-Band Temperature Sensing

GUMSTICK2 CONNECTOR

1.2V to 2.0V

HDD CONNECTORS

518S0251

High:

Notes:

From drive:

Drive disconnected: Pulled high

Low:

Drive active: Valid signal protocol

Node is at 1.5V

Temperature read from SATA power connecter pin 11

0603

FERR-70-OHM-4A

CRITICAL

SSD

PLACE_NEAR=J4500.1:3mm

20%
10V
CERM

0.1UF

402

SSD

SSD

0.1UF

CERM
402

20%
10V

41 45

41 45

CBTL02043ABQ

SSD

VQFN

CRITICAL

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

18 90

18 90

15 18

26

GND_VOID=TRUE

SSD

16V10%

0.1UF

0201X5R-CERM

10%0.1UF

X5R-CERM

SSD

16V

0201

GND_VOID=TRUE

18 90

18 90

18 90

18 90

SSD

10K

1/16W
MF-LF
402

5%

470K

5%
1/16W
MF-LF

SSD

402

SSD

20%
10V
CERM
402

0.1UF 0.1UF

SSD

20%
10V
CERM
402

SSD

10V

20%

0.1UF

CERM
402

SSD

16V

X5R-CERM 0201

0.1UF

10%

GND_VOID=TRUE

16V10%

0201

SSD

0.1UF

X5R-CERM

GND_VOID=TRUE

SSD

16V10%

0201

0.1UF

X5R-CERM

GND_VOID=TRUE

SSD

X5R-CERM

16V10%

0.1UF

0201

GND_VOID=TRUE

18 90

18 90

18 90

18 90

18 91

18 91

18 91

18 91

50293-00471-H01

M-ST-SM

CRITICAL

X5R

6.3V

20%

603

10UF

EP00-081-91

CRITICAL

SILK_PART=HDD

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

M-ST-SM

402

GND_VOID=TRUE

0.01UF

X7R25V10%

402

GND_VOID=TRUE

X7R25V10%

0.01UF

402X7R25V10%

GND_VOID=TRUE

0.01UF

402

GND_VOID=TRUE

X7R25V10%

0.01UF

18 91

18 91

18 91

18 91

SSD

5%

1/20W

MF

201

0

60 70

402

10%
X5R

16V

0.1UF

44

1K

5%
1/16W
MF-LF
402

SC70-5

LMV331

402

0.1UF

16V

10%
X5R

49.9K

402

1/16W

1%
MF-LF

100K

1%
1/16W
MF-LF
402

402

MF-LF

1/16W

5%

3.3K

100K

5%
1/16W

402

MF-LF

201

0

MF5%

1/20W

SSD

GND_VOID=TRUE
GND_VOID=TRUE

SSD

1/20W

5% MF

0

201

SSD

X5R-CERM

16V10%

0.1UF

GND_VOID=TRUE

0201

SSD

X5R-CERM

16V10%

0.1UF

GND_VOID=TRUE

0201

SSD

X5R-CERM

16V10%

0.1UF

GND_VOID=TRUE

0201

0.1UF

10% 16V

X5R-CERM

SSD

GND_VOID=TRUE

0201

0402

FERR-220-OHM

44

523

1%
1/16W
MF-LF

402

5%
1/16W
MF-LF
402

10K

402

10K

MF-LF

1/16W

5%

10K

402

MF-LF

1/16W

5%

SSD-K70

CRITICAL

SILK_PART=SSD

SSD

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

F-RT-SM1

5%

603

MF-LF

1/10W

330

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

SILK_PART=SATA ACTIVE

SATA Connectors

SYNC_DATE=12/16/2011

SYNC_MASTER=D7_NICK

MIN_NECK_WIDTH=0.4mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6mm

PP3V3_S0_SSD_FLT

MAKE_BASE=TRUE

SATALED_L

HDD_OOB1_RX_L

=PP3V3_S0_SENSE

SMC_OOB1_TX_L

HDD_OOB_1V00_REF

HDD_OOB1_RX_F_L

SATA_HDD_R2D_N

SMC_OOB1_TX_R_L

HDD_OOB1_RX_R_L

SATA_HDD_D2R_C_N

SATA_HDD_R2D_P

SATA_HDD_D2R_C_P

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_N

SATA_HDD_D2R_P

=PP3V3_S0_SENSE

=PP3V3_S0_SSD

=PP3V3_S0_SENSE

SMC_OOB1_RX_L

PCH_SATALED_L

SATALED_R_L

=PP3V3_S0_LED_SATA

PCIE_SSD_R2D_N<0>

SATA_SSD_D2R_C_N

SATA_SSD_D2R_C_P

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

SATA_SSD_R2D_C_N

SATA_SSD_R2D_C_P

SATA_SSD_D2R_N

SATA_SSD_D2R_P

SATAMUX_EN_L

=PP3V3_S0_SATAMUX

SATA_PCIE_SEL

PCIE_SATA_SSD_R2D_N
PCIE_SATA_SSD_R2D_P

PCIE_SATA_SSD_D2R_N
PCIE_SATA_SSD_D2R_P

SATA_SSD_R2D_P

PCIE_SSD_D2R_C_N<0>

SATA_SSD_R2D_N

PCIE_SSD_D2R_C_P<0>

PCIE_SSD_R2D_P<0>

=PP5V_S0_SATA

PCIE_SSD_R2D_P<1>

SMC_OOB2_TX_L

SMC_OOB2_RX_L

=PP3V3_S0_SENSE

PCIE_SSD_R2D_C_N<1>

PM_EN_FET_P3V3_S0

PCIE_SSD_R2D_C_P<1>

SSD_P3V3S0_EN

PCIE_SATA_SSD_D2R_P
PCIE_SATA_SSD_D2R_N

SMC_OOB2_TX_L

SMC_OOB2_RX_L

SSD_RESET_L

PCIE_SSD_R2D_N<1>

PCIE_SATA_SSD_R2D_P

PCIE_CLK100M_SSD_P

PCIE_SATA_SSD_R2D_N

PCIE_CLK100M_SSD_N

SATA_PCIE_SEL

SSD_CLKREQ_L

PCIE_SSD_D2R_C_N<1>

PCIE_SSD_D2R_C_P<1>

=PP1V5_S0_SENSE

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

R4599

1

2

DS4599

A

K

L4500

1 2

C4501

1

2

C4500

1

2

U4510

4

3

8

7

18

19

16

17

14

15

12

13

9

21

1610

5

11

20

2

C4504

1 2

C4505

1 2

R4511

1

2

R4510

1

2

C4510

1

2

C4511

1

2

C4512

1

2

C4513

1 2

C4514

1 2

C4515

1 2

C4516

1 2

J4530

1
2
3
4

C4530

1

2

J4520

1
2
3
4
5
6
7

C4521

1 2

C4522

1 2

C4523

1 2

C4524

1 2

R4504

12

C4507

1

2

R4505

1

2

U4500

2

3

1

4

5

C4506

1

2

R4500

1

2

R4501

1

2

R4503

1 2

R4502

1

2

R4506

12

R4507

12

C4517

1 2

C4518

1 2

C4519

1 2

C4520

1 2

L4530

1 2

R4508

1 2

R4514

1

2

R4512

1

2

R4513

1

2

J4500

27
28

37
38
39
40

29
30
31
32
33
34
35
36

1

10
11
12
13
14
15
16
17
18

19

2

20
21
22
23
24
25
26

3
4
5
6
7
8
9

051-9509

4.2.0

45 OF 113
41 OF 100

6

41 48 49 50

91

91

91

91

6

41 48 49 50

6

6

41 48 49 50

15 18

6

15

90

91

91

6

41

41 91

41 91

41 91

41 91

91

90

91

90

90

6

90

41 45

41 45

6

41 48 49 50

41 91

41 91

90

41 91

41 91

41

90

90

6

GND

THRM

OUT2

OUT1

ILIM

IN_0
IN_1

EN2

FAULT1*
FAULT2*

EN1

PAD

IN

IN

OUT

OUT

L2

L1

L2

L1

L2

L1

L2

L1

SYM_VER-1

SYM_VER-1

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

IN

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

BI

BI

IN

BI

BI

OUT

IN

BI

BI

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

D­D+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

D­D+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

NC

NC

GND

VBUS

IO

IO

NC

NC

GND

VBUS

IO

IO

OUT

IN

IN

OUT

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EXT PORT A

EXT PORT B

514-0817

EHCI

XHCI

514-0825

PCH GPIO60

TPS2561DR

SON

20%
10V

CERM

0.1UF

402

402

16V

CERM

20%

0.01UF

0.01UF

402

20%

CERM

16V

20 93

20 93

20 93

20 93

0504

80OHM-25%-100MA

GND_VOID=TRUE

80OHM-25%-100MA

0504

GND_VOID=TRUE

0504

80OHM-25%-100MA

GND_VOID=TRUE

0504

80OHM-25%-100MA

GND_VOID=TRUE

CRITICAL

DLP0NS

120-OHM-90MA

120-OHM-90MA

DLP0NS

CRITICAL

6.3V

10% X5R

0.1UF

201

201

0.1UF

6.3V

10% X5R

0.1UF

201

6.3V

X5R10%

201

0.1UF

6.3V

10% X5R

330UF-25MOHM

CASE-D2E

TANT

6.3V

20%

SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

DFN

USB3740

CRITICAL

10K

5%
1/16W
MF-LF

402

20%
10V

CERM

402

0.1UF

44

MF-LF

1/16W

5%

10K

402

402

CERM

10V

0.1UF

20%

CRITICAL

USB3740

DFN

20 93

20 93

18

20 93

20 93

44 45

44 45

20 93

20 93

USB-NO1-K70

F-ANG-TH

CRITICAL

F-ANG-TH

USB-NO2-K70

CRITICAL

SLP1210N6

NOSTUFF

RCLAMP0582N

CRITICAL

RCLAMP0582N

CRITICAL

NOSTUFF

SLP1210N6

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

FERR-120-OHM-3A

0603

10V
CERM

20%

402

0.1UF

15 20

20 93

20 93

20 93

20 93

FERR-120-OHM-3A

0603

CERM

10V

20%

402

0.1UF

402

MF-LF

23.2K

1/16W

1%

15 20

SYNC_MASTER=D7_NICK

EXTERNAL USB PORTS A & B

SYNC_DATE=01/04/2012

USB3_EXTA_TX_F_N

USB3_EXTA_TX_F_P

USB3_EXTA_TX_C_P

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

PP5V_S4_EXTB_ILIM

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

PP5V_S4_EXTA_F

USB3_EXTA_RX_F_N

USB_DEBUGPRT_EN_L

USB3_EXTA_RX_F_P

=PP3V3_S5_USBMUX

USB_EXTB_SEL_XHCI

USB_PCH_9_P

USB2_EXTB_MUXED_P

USB_PCH_1_P

USB_PCH_1_N

PM_EN_USB_PWR

=PP5V_S4_USB

USB3_EXTB_TX_C_N

USB3_EXTA_TX_P

USB3_EXTB_TX_P

USB3_EXTB_TX_C_P

USB3_EXTA_TX_C_N

USB3_EXTB_RX_F_N

USB_EXTA_OC_L

USB_ILIM1

USB_EXTB_OC_L

USB3_EXTB_RX_F_P

USB3_EXTB_TX_N

USB3_EXTA_TX_N

=PP3V3_G3H_SMC_USBMUX

USB_PCH_9_N

USB_PCH_0_N

MOJO_TX_L

MOJO_RX_L

USB_PCH_0_P

USB2_EXTB_MUXED_N

USB2_EXTA_N
USB2_EXTA_P

USB3_EXTB_TX_F_P

USB3_EXTB_TX_F_N

USB3_EXTA_RX_N
USB3_EXTA_RX_P

USB3_EXTB_RX_N

USB2_EXTB_P

USB3_EXTB_RX_P

USB2_EXTB_N

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S4_EXTB_F

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

PP5V_S4_EXTA_ILIM

VOLTAGE=5V

L4611

1 2

C4617

1

2

L4601

1 2

C4607

1

2

R4602

1

2

U4600

4
5

10

6

1

7

2
3

9
8

11

C4601

1

2

C4605

1

2

C4615

1

2

L4603

1

2

3

4

L4604

1

2

3

4

L4613

1

2

3

4

L4614

1

2

3

4

L4602

1 2

34

L4612

1 2

34

C4608

1 2

C4609

1 2

C4618

1 2

C4619

1 2

C4602

1

2

U4610

9

1

7

10

2

6

8

3

4

5

R4605

1

2

C4606

1

2

R4615

1

2

C4616

1

2

U4630

9

1

7

10

2

6

8

3

4

5

J4600

2
3
4

10
11

20
21
22

12
13
14
15
16
17
18
19

7

5
6

8
9

1

J4610

2
3
4

10
11

20
21
22

12
13
14
15
16
17
18
19

7

5
6

8
9

1

D4601

1

452 3

6

D4611

1

452 3

6

D4604

1

2

D4605

1

2

D4602

1

2

D4603

1

2

D4615

1

2

D4614

1

2

D4613

1

2

D4612

1

2

051-9509

4.2.0

46 OF 113
42 OF 100

93

93

93

93

93

6

43

93

43 60

6

43

93

93

93

6

93

93

93

93

93

93

93

93

93

93

93

OUT

OUT

OUT

OUT

L2

L1

L2

L1

SYM_VER-1

SYM_VER-1

L2

L1

IN

IN

L2

L1

IN

IN

BI

BI

BI

BI

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

IN

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

D­D+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

D­D+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

NC

NC

GND

VBUS

IO

IO

NC

NC

GND

VBUS

IO

IO

BI

BI

GND

THRM

OUT2

OUT1

ILIM

IN_0
IN_1

EN2

FAULT1*
FAULT2*

EN1

PAD

OUT
OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EXT PORT D

514-0827

514-0826

EXT PORT C

EHCI

XHCI

PCH GPIO74

20 93

20 93

20 93

20 93

80OHM-25%-100MA

0504

GND_VOID=TRUE

80OHM-25%-100MA

0504

GND_VOID=TRUE

DLP0NS

120-OHM-90MA

CRITICAL

DLP0NS

CRITICAL

120-OHM-90MA

80OHM-25%-100MA

0504

GND_VOID=TRUE

201

0.1UF

6.3V

10% X5R

0.1UF

6.3V

20110% X5R

20 93

20 93

80OHM-25%-100MA

0504

GND_VOID=TRUE

X5R10%

6.3V

0.1UF

201

201

0.1UF

6.3V

10% X5R

20 93

20 93

FERR-120-OHM-3A

0603

330UF-25MOHM

TANT

6.3V

20%

CASE-D2E

20%

0.1UF

10V

CERM

402

402

MF-LF

1/16W

5%

10K

20 93

20 93

20 93

20 93

USB3740

CRITICAL

DFN

18

F-ANG-TH

USB-NO3-K70

CRITICAL

F-ANG-TH

USB-NO4-K70

CRITICAL

SLP1210N6

RCLAMP0582N

CRITICAL

NOSTUFF

RCLAMP0582N

CRITICAL

SLP1210N6

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

TSSLP-2-1

ESD0P2RF-02LS

FERR-120-OHM-3A

0603

20 93

20 93

402

CERM

10V

20%

0.1UF

402

0.01UF

CERM

16V

20%

CERM
402

10V

0.1UF

20%

0.01UF

402

16V

CERM

20%

MF-LF

402

1%

1/16W

23.2K

SON

TPS2561DR

0.1UF

402

20%

CERM

10V

15 20

15 20

EXTERNAL USB PORTS C & D

SYNC_DATE=01/04/2012

SYNC_MASTER=D7_NICK

USB3_EXTD_RX_N
USB3_EXTD_RX_P

USB3_EXTD_TX_F_N
USB3_EXTD_TX_F_P

USB3_EXTC_TX_F_P

USB3_EXTC_TX_F_N

USB3_EXTC_RX_P

USB3_EXTC_RX_N

USB2_EXTD_P

USB3_EXTC_TX_C_N

USB2_EXTD_N

USB2_EXTC_P

USB2_EXTC_N

USB_ILIM2

USB2_EXTD_MUXED_P

USB2_EXTD_MUXED_N

USB_PCH_10_P

USB_PCH_3_N

USB_PCH_3_P

USB3_EXTC_RX_F_P

USB3_EXTC_TX_C_P

USB_PCH_2_N

USB3_EXTD_TX_P

USB3_EXTD_TX_N

USB3_EXTD_TX_C_P

USB3_EXTD_TX_C_N

USB3_EXTC_TX_P

USB_PCH_2_P

USB_EXTC_OC_L

PM_EN_USB_PWR

USB3_EXTD_RX_F_P

USB_EXTD_OC_L

USB_PCH_10_N

USB3_EXTC_TX_N

USB3_EXTC_RX_F_N

USB3_EXTD_RX_F_N

=PP5V_S4_USB

USB_EXTD_SEL_XHCI

=PP3V3_S5_USBMUX

PP5V_S4_EXTC_ILIM

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

PP5V_S4_EXTC_F

PP5V_S4_EXTD_ILIM

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V
MIN_LINE_WIDTH=0.6MM

PP5V_S4_EXTD_F

L4701

1 2

L4711

1 2

C4707

1

2

C4705

1

2

C4717

1

2

C4715

1

2

R4702

1

2

U4700

4
5

10

6

1

7

2
3

9
8

11

C4701

1

2

L4703

1

2

3

4

L4713

1

2

3

4

L4702

1 2

34

L4712

1 2

34

L4704

1

2

3

4

C4708

1 2

C4709

1 2

L4714

1

2

3

4

C4718

1 2

C4719

1 2

C4702

1

2

C4716

1

2

R4715

1

2

U4730

9

1

7

10

2

6

8

3

4

5

J4700

2
3
4

10
11

20
21
22

12
13
14
15
16
17
18
19

7

5
6

8
9

1

J4710

2
3
4

10
11

20
21
22

12
13
14
15
16
17
18
19

7

5
6

8
9

1

D4701

1

452 3

6

D4711

1

452 3

6

D4705

1

2

D4704

1

2

D4703

1

2

D4702

1

2

D4715

1

2

D4714

1

2

D4713

1

2

D4712

1

2

051-9509

4.2.0

47 OF 113
43 OF 100

93

93

93

93

93

93

93

93

93

93

93

93

93

93

93

93

93

93

42 60

6

42

6

42

LPC0AD3
LPC0CLK
LPC0FRAME*

LPC0AD1
LPC0AD2

AIN08

AIN07
LPC0CLKRUN*
LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX
PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119
PP4/IRQ120

C0-

WT2CCP0/PH0
WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2
SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127
PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4
PF5

T1CCP0/PJ0

T2CCP0/PJ2
T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK
SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI
BI
BI
BI
IN
IN
IN
BI
OUT
IN
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

OUT

IN

OUT

OUT
OUT
OUT

IN

OUT

IN

IN

OUT

OUT
OUT
OUT

NC

OUT

IN
OUT

IN
OUT

BI
BI

OUT
IN

IN

OUT

OUT

IN

OUT

IN
IN

IN

IN
IN
IN
IN
IN
IN
IN

IN
OUT

OUT

BI

OUT
OUT
IN
IN
OUT

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN
IN

IN

IN

IN

IN

IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

arch

arch

arch

arch

arch

arch

arch

proj

(OD)

those designated as inputs require pull-ups.

analog

arch
arch

proj

arch

proj

int

arch

analog

analog

od

analog

proj

analog

proj

proj

arch

arch

proj

arch

proj

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

proj

arch

arch
arch

arch

int
int

int

int

proj

arch

int

int

int

int

proj

proj
proj

od

proj

arch

arch

arch
arch

od

od

arch

arch

arch

arch

arch

proj
proj

pwm

arch

analog

proj

analog

analog

proj

analog

analog
analog

analog

analog

proj

analog

proj

analog
analog

proj

proj

proj

analog
analog
analog

proj

analog
analog

proj

proj

arch

analog

od

arch
arch

arch

od
od

od

arch

arch

arch

int
int

int

int

analog

proj

analog

analog

arch

arch

arch

proj

proj

proj

proj
proj

arch
arch

analog

int

proj

od

proj

proj

arch

arch

arch

arch

proj

proj
proj

arch

arch

arch

arch

arch

arch

arch

arch

arch

arch

arch

arch

od

arch
arch
arch
arch

int

arch

analog

od

od

arch

od

analog

analog

od

od

arch

arch

arch

arch

arch

proj

proj

proj

arch

proj

proj

od

od

od

arch

arch

arch

OMIT_TABLE

BGA

LM4FSXAH5BB

BGA

OMIT_TABLE

LM4FSXAH5BB

SM

PLACE_NEAR=U4900.A1:4MM

45 46

45 92

1M

MF

1/20W

5%

201

1UF

603

10V

20%

CERM

18 46 92

18 46 92

18 46 92

18 46 92

26 92

18 46 92

26

18 46

45 46

19 26 46

15 21

47 94

47 94

47 94

47 94

47 94

47 94

47 94

47 94

45

45

45 94

45 94

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45

45 69

45 61

36 45 61

45

42 45

42 45

45

45 92

45 92

45 92

45 92

42

45 78

5

61

45

15 19 25

19 25 26

29 30 45

15 21

11 21 45

45

45 46

45 46

27 93

27 93

51

51

45

45

45

51

51

45

33 45

45

45

45

45

15 19 28 38 45 60

15 19 60

15 19 33 60

45

45

33 45

45

33 45

45

45

45

45

45

45

45

78

61

15

30-OHM-1.7A

0402

11 45 62

41

45

41

X5R

20%

402

25V

1.0UF1.0UF

20%

402

25V
X5R

1.0UF

X5R

20%
25V

402

45

61

X5R

6.3V

10%

201

0.1UF

6.3V

10%

201

0.1UF

X5R X5R

10%

201

0.1UF

6.3V

0.1UF

201

10%

6.3V
X5R X5R

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

0.1UF

X5R

6.3V

10%

201

0.1UF0.1UF

10%

6.3V
X5R
201

0.1UF

201

10%

6.3V
X5R

45

45

45

45

45

45

45

0.01UF

201

X5R

10V

10%

PLACE_NEAR=U4900.D2:4mm

6.3V
X5R

20%

0201

1UF

PLACE_NEAR=U4900.D1:4mm

SMC

SYNC_DATE=01/11/2012

SYNC_MASTER=D7_DOUG

LPC_CLK33M_SMC

LPC_AD<3>

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_2_S4_SDA

SMC_FAN_0_CTL

SMC_FAN_1_TACH

SMC_PN3

SMC_PN4
SMC_PN5

SMC_PH3

SMC_PECI_L

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_3_SDA

SMC_PN2

SMC_PH2

SMC_PME_S4_DARK_L

SMC_ADC3

SPI_SMC_MISO

SPI_SMC_CLK
SPI_SMC_CS_L
S5_PWRGD

USB_DEBUGPRT_EN_L

PM_SYSRST_L
MEM_EVENT_L
SMC_PH7

SMC_OOB1_TX_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.25 MM

PP3V3_G3H_SMC_VDDA

CPU_PECI

SMC_PP0

SMC_PM_PCH_SYS_PWROK

SMC_S5_PWRGD_VIN

SMC_ADC17

SPI_DESCRIPTOR_OVERRIDE_L

PM_DSW_PWRGD

SMC_GFX_OVERTEMP

ALL_SYS_PWRGD
SMC_THRMTRIP

PM_PWRBTN_L

SMC_SYS_LED

SMC_FAN_0_TACH

SMC_ONOFF_L

PM_SLP_S5_L

SMS_INT_L

SMC_ADC13

SMBUS_SMC_2_S4_SCL

SMC_ADC20

SMC_ADC15

SMC_ADC1

SMC_ADC6

SMC_ADC10

SMC_VCCIO_CPU_DIV2

SMC_WAKE_SCI_L

SMBUS_SMC_0_S0_SDA

SMC_PN6

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_4_ASF_SDA

LPC_FRAME_L

SMC_RUNTIME_SCI_L

SMC_LRESET_L

LPC_AD<2>

SMBUS_SMC_1_S0_SDA

LPC_AD<0>

USB_SMC_P

PM_SLP_S3_L

LPC_AD<1>

SMC_ADC8

SMC_ADC4

SMC_ADC2

SMC_ADC11

SMC_PP7

PM_SLP_S4_L

USB_SMC_N

SMBUS_SMC_5_G3H_SDA

SMC_PME_S4_WAKE_L

SMC_ADC14

LPC_PWRDWN_L

PM_CLKRUN_L

LPC_SERIRQ

SMC_OOB1_RX_L

SMC_PJ2

SMC_BATLOW_L

SMC_PJ3

G3_POWERON_L

SMC_BC_ACOK

ENET_ASF_GPIO

SMC_PP5

SMC_DP_HPD_L

SMC_PN7

SMC_PM_G2_EN

CPU_THRMTRIP_3V3

SMC_ADC22

SMC_ADC21

SMC_ADC0

MOJO_TX_L

SPI_SMC_MOSI

MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 MM

PP1V2_G3H_SMC_VDDC

NC_SMC_HIB_L

NO_TEST=TRUE

SMC_CLK32K

AP_EVENT_L

SMC_EXTAL

NC_SMC_XOSC1

NO_TEST=TRUE

SMC_XTAL

SMC_WAKE_L

SMC_S4_WAKESRC_EN

SMC_TMS

SMC_RESET_L

SMC_ADC5

SMC_GFX_THROTTLE_L

SMC_ADC19

SMC_ADC12

SMC_ADC9

SMC_ADC7

SMC_FAN_1_CTL

SMC_TX_L

SMC_RX_L

SMC_PP6

SMC_DELAYED_PWRGD
SMC_PROCHOT

MOJO_RX_L

SMC_CPU_CATERR_L

SMC_ADC23

SMC_ADC18

SMC_ADC16

SMBUS_SMC_5_G3H_SCL

SMC_TDI

SMBUS_SMC_3_SCL

CPU_PROCHOT_L

=PP3V3_G3H_SMC

SMC_TDO

SMC_TCK

PP3V3_G3H_AVREF_SMC

GND_SMC_AVSS

U4900

E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8

K2
K1
L2

E10
D13

M4
N2
N8
M8
L8
K8
N7
M7
N4
N3

B13
A13
C12
D11
H12

G11

D12

F13

C13

F12

H13

L1

C4
C6

L9
K9

J4
J2

B12

C11

A12

H11
L13

G3

D10

L11
N12
N11
M11

M13
L12

M5

J12

J13

L5
D8
K6

D4
E4
F5

N5
N6
K5
M6
L6

M2
M3
L4
N1

L10
K10

M9
N9

F4
F3

C9
B9
A9
C8

D5

C5

L3
M1

F11
E11

E13
E12

K7
L7

K3
K4

J3
H4
H3
G4

H10

U4900

A1
C7

K11

D9
E5
F9
H5
H9
J5
J8
J11

C3
E3

M12

G12

G13

B11

G10 C10

A10
A11
B10

K12

D7
E6
E8
E9

F10

J7
J9

J10

D3

J1
J6

K13

D6

D1

D2

N13

M10

N10

XW4900

12

R4902

1

2

C4902

1

2

L4901

1 2

C4911

1

2

C4910

1

2

C4912

1

2

C4917

1

2

C4913

1

2

C4914

1

2

C4915

1

2

C4916

1

2

C4903

1

2

C4904

1

2

C4905

1

2

C4906

1

2

C4909

1

2

C4908

1

2

C4907

1

2

C4901

1

2

C4921

1

2

C4920

1

2

051-9509

4.2.0

49 OF 113
44 OF 100

A2

45 94

45 94

45 46

45 46

6

45

45 46

45 46

45

45 48 49 94

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

NC
NC

OUT

IN

BI

IN

BI

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

D

SG

IN

D

SG

IN

IN

BI

D

SG

D

SG

IN

OUT

IN

D

G S

D

G S

D

G S

OUT

OUT

IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC Supervisor and AVREF Supply

Enable TBT S4 Wake Sources

PECI Support

Level-shifter that allows SMC to drive PECI

Place this circuit near the Tee point to minimize reflections

Project-specific Aliases

SMC Controlled RTC Reset

Note: IPU are pulled to VIN rail

Arch Pull Up/Down

TP for access if ZPB re-intstated

ADC Channel Aliases

Unused ADC Channels

SMC Crystal

Power Button

AC/DC Burst Mode Enable

Open-drain stage on S4 to account
case when SMC is initializing in S5,

and ACDC_BURST_EN_L could be floating.

SMC SPI Support

(ipu)
(ipu)

and chip is not yet configured.

Series R are NOSTUFF until topology of 2 SPI masters is verified

Note:

Note: For SMC recovery mode

Serial/JTAG Interface Pull-ups

FIXME!!! - Is 1.0uF the right value?

To absorb current from discharging RTC Reset CAP

Pull-down needed for SMC SSI signals

Note:

Comparator Reference

Platform Thermal Control

Level-shifter that allows SMC to drive PROCHOT

PROCHOT Support

SMC 32KHz Clock

NOTE: SMC team wants 12MHz for this Xtal

FIXME!!! - Get final cap values for NX5032GB 8PF Xtal

Unused Project-specific

CRITICAL

DFN

VREF-3.3V-VDET-3.0V

6.3V

0.47UF

CERM-X5R

10%

402

CERM

10%
16V

0.01UF

402 603

6.3V

20%
X5R

10UF

10%

402

0.01UF

CERM

16V

44 46

MF-LF

1/16W

5%

402

1K

SILK_PART=SMCReset

0

5%
1/10W
MF-LF

OMIT

603

SILK_PART=PwrBtn

DEVELOPMENT

SM

NTC020AA1JB260T

44

402

5%

CERM

50V

12PF

402

CERM

50V

5%

12PF

1/16W

0

5%

MF-LF

402

44

11 44 62

100K

1/20W

MF

201

5%

5%

MF-LF

402

0

1/16W

44

NONE

NONE

NOSTUFF

OMIT

402

NONE

5%
MF-LF

1/16W
402

330

11 21 44

10K

1%

402

MF-LF

1/16W

PLACE_NEAR=U4900.K1:5MM

10K

1/16W
MF-LF

1%

402

PLACE_NEAR=U4900.K1:5MM

44

201

5%

1/20W

MF

10K

PLACE_NEAR=U5110.2:1MM

NOSTUFF

MF-LF

1/16W

0

5%

402

44 92 46 92

46 92

PLACE_NEAR=U5110.5:1MM

5%

0

NOSTUFF

MF-LF

1/16W

402

44 92

NOSTUFF

1/16W
MF-LF

0

5%

PLACE_NEAR=U5110.6:1MM

402

46 92 44 92

46 92

NOSTUFF

0

MF-LF

5%

402

1/16W

PLACE_NEAR=U5110.1:1MM

44 92

5%

1/20W

MF

201

10K

5%
MF

201

1/20W

10K

44 92

1/16W

22

402

5%

MF-LF

PLACE_NEAR=U1800.BA47:5MM

19 92

201

MF

1/20W

5%

10K

100K

1/20W

MF5%201

6

84

100K

1/20W
201

5%
MF

MF

5%

10K

1/20W
201
1/20W

100K

5%
MF

201

10K

201

1/20W

5%
MF

10K

1/20W

5%
MF

201

10K

MF5%201

1/20W

10K

1/20W

5%

201

MF

100K

201

5%MF1/20W

5%

10K

201

MF

1/20W

100K

201

5%

1/20W

MF

10K

201

MF

1/20W

5%

85

0

5%

1/20W

MF

201

19 61 44

44

0

5%
MF

1/20W

201

11

CRITICAL

SSM6N15AFE

SOT563

44 78

1/20W

201

MF

5%

10K

SOT563

SSM6N15AFE

CRITICAL

46

44

1K

1/20W

5%
MF

201

21

SSM6N15AFE

SOT563

CRITICAL

201

MF

1/20W

5%

10K

SSM6N15AFE

CRITICAL

SOT563

45

MF

5%

10K

201

1/20W

6

67

43

5%

402

1/16W
MF-LF

CRITICAL

MMDT3904-X-G

SOT-363-LF

MMDT3904-X-G

CRITICAL

SOT-363-LF

201

1/20W

MF

51

5%

1/20W

3.3K

5%
MF

201

11

1/20W

201

MF

5%

3.3K

SSM3K15AMFVAPE

VESM

CRITICAL

SSM3K15AMFVAPE

VESM

CRITICAL

16V

10%

402

X5R

0.1UF

PLACE_NEAR=U4900.K1:3MM

SSM3K15AMFVAPE

VESM

CRITICAL

18

402

1/16W

5%

10K

MF-LF

20%

NOSTUFF

0402

X5R-CERM

6.3V

1.0UF

402

5%

1/16W

330

MF-LF

10K

5%

1/20W

201

MF

10K

201

MF

1/20W

5%
5%

1/20W

MF

201

10K

I939

402

MF-LF

1/16W

5%

1M

NOSTUFF

100K

5%

MF-LF

1/16W
402

MF-LF

402

1/16W

5%

100K

10K

1/20W
201

MF

5%

44

5X3.2X1.2-SM

CRITICAL

12.000MHZ-50PPM-8PF

100K

5%MF1/20W

201

6

84

6

85

SMC Support

SYNC_MASTER=D7_DOUG

SYNC_DATE=01/11/2012

SMC_MANUAL_RST_L

SMC_GFX_OVERTEMP

SMC_THRMTRIP

SMC_S4_WAKESRC_EN

PM_CLKRUN_L

SMC_BC_ACOK

SMC_DELAYED_PWRGD

SMC_PH7

SMC_PP5

SMC_ADC21

SMC_PN3

NO_TEST=TRUE

NC_SMC_PN6

MAKE_BASE=TRUE

PM_THRMTRIP_L

NC_SMBUS_SMC_5_G3H_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_SMBUS_SMC_5_G3H_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PP7

NC_SMC_PN4

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_PN3

NO_TEST=TRUE

NO_TEST=TRUE

NC_SMC_PN2

MAKE_BASE=TRUE

SMC_PN2

SMC_XTAL_R

SMC_ADC18

SMC_ADC11

AP_EVENT_L

CPU_PECI

MEM_EVENT_L

SMC_TDI

CPU_THRMTRIP_3V3

CPU_THRMTRIP_L

CPU_TT_OC_L

CPU_CATERR_L

PM_PCH_SYS_PWROK

SMC_CPU_CATERR_L

SMC_PM_PCH_SYS_PWROK

SMC_PROCHOT

CPU_PROCHOT_L

SMC_PJ2

SMC_OOB2_RX_L

MAKE_BASE=TRUE

SMC_PH3

ENET_ASF_GPIO

SMC_SYS_LED

SMC_PME_S4_WAKE_L

=PP3V3_G3H_SMC

SMS_INT_L

SMC_PM_G2_EN

PM_DSW_PWRGD

PP3V3_S4_AP_FET

SMC_BATLOW_L

ACDC_BURST_EN_L

MAKE_BASE=TRUE

SMBUS_SMC_4_ASF_SDA

SMC_PN4

=PP3V3_S5_SMC

PM_SLP_S3_L

ACDC_BURST

=PPVCCIO_S0_SMC

SMBUS_SMC_5_G3H_SCL

NC_SMBUS_SMC_4_ASF_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_5_G3H_SDA

ISNS_CPUAXG

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PP5

=PP3V3_G3H_SMC

SMC_RX_L

SMC_TCK

SMC_TDO
SMC_TMS

SMC_PH2

SMC_ROMBOOT

RTC_RESET_L

RTC_RESET_L_R

MIN_LINE_WIDTH=0.4MM
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM

PP3V3_G3H_AVREF_SMC

=PPVCCIO_S0_SMC

SMC_PECI_L_R

=PPVCCIO_S0_SMC

SPI_MLB_CLK

SPI_MLB_CS_L

SMC_PJ3

SMC_OOB2_TX_L

MAKE_BASE=TRUE

BDV_BKL_PWM

MAKE_BASE=TRUE

BURSTMODE_EN_L

=PP3V3_S4_SMC

SMC_CLK32K

SPI_SMC_CS_L

SPI_SMC_MOSI

SPI_SMC_MISO SPI_MLB_MISO

SPI_MLB_MOSI

=PP3V3_G3H_SMC

ACDC_BURST_EN_L

SMC_TX_L

MOJO_RX_L

MOJO_TX_L

SMC_PP0

SMC_ASSERT_RTCRST

=PP3V3_S0_SMC

G3_POWERON_L

=PP3V3_S0_SMC

SMC_VCCIO_CPU_DIV2

SMC_PECI_L

SPI_SMC_CLK

PM_CLK32K_SUSCLK_R

SMC_XTAL

MAKE_BASE=TRUE

SMC_ASSERT_RTCRST

SMC_ACDC_ID

MAKE_BASE=TRUE

SMC_RESET_L

VSNS_HDDS0

MAKE_BASE=TRUE

SMC_ADC14

ISNS_HDDS0

MAKE_BASE=TRUE

SMC_ADC15

ISNS_SSDS0

MAKE_BASE=TRUE

SMC_ADC17

VSNS_SSDS0

MAKE_BASE=TRUE

SMC_ADC16

MAKE_BASE=TRUE

NC_SMC_ADC4

NO_TEST=TRUE

SMC_ADC4

NC_SMC_ADC5

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_ADC18

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC20

NO_TEST=TRUE

SMC_ADC20

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC19

SMC_ADC19

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_ADC21

NC_SMC_ADC22

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_ADC23

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_ADC23

VSNS_P12VG3H

MAKE_BASE=TRUE

SMC_ADC1

SMC_ADC3

SMC_ADC2

MAKE_BASE=TRUE

ISNS_VDDQS3_DDR

SMC_ADC7

VSNS_VDDQS3_DDR

MAKE_BASE=TRUE

VSNS_P12VS0_GPUUNCORE

MAKE_BASE=TRUE

SMC_ADC8

VSNS_CPUCORE

MAKE_BASE=TRUE

SMC_ADC10

ISNS_P12VS0_GPUUNCORE

MAKE_BASE=TRUE

SMC_ADC9

MAKE_BASE=TRUE

VSNS_CPUAXG

SMC_ADC12

MAKE_BASE=TRUE

ISNS_CPUCORE

SMC_ADC13

SMC_PN6

NC_SMC_PN7

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_PN7

NO_TEST=TRUE

NC_SMC_PP6

MAKE_BASE=TRUE

SMC_PP6

NO_TEST=TRUE

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

SMC_DP_HPD_L

SMC_PP7

SMC_PME_S4_DARK_L

TP_SMC_PH7

MAKE_BASE=TRUE

SMBUS_SMC_4_ASF_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_PME_S4_DARK_L

SMC_ADC6

MAKE_BASE=TRUE

ISNS_P12VS0_GPUCORE

VSNS_P12VS0_GPUCORE

MAKE_BASE=TRUE

ISNS_P12VG3H

MAKE_BASE=TRUE

SMC_ADC0

SMC_ADC5

=TBTAPWRSW_EN

=TBTBPWRSW_EN

=PP3V3_S4_TBTBPWRSW

SMC_ADC22

SMC_EXTAL

CPU_PECI_R

=PP3V3_S4_TBTAPWRSW

PWR_BTN

MAKE_BASE=TRUE

SMC_ONOFF_L

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=0V

=PPVIN_G3H_SMCVREF

=PP3V3_G3H_SMC

SMC_PN5

U5000

4

2

6
7

8

5

9

1

3

C5000

1

2

C5001

1

2

C5005

1

2

C5006

1

2

R5005

1

2

R5001

1

2

J5020

1 2

3 4

C5065

1

2

C5066

1

2

R5065

12

R5078

1 2

R5035

1

2

R5036

1

2

R5037

1

2

R5030

1

2

R5031

1

2

R5085

1 2

R5050

12

R5051

12

R5052

12

R5053

12

R5075

1 2

R5080

1 2

R5060

12

R5020

1

2

R5077

1 2

R5079

1 2

R5090

1 2

R5091

1 2

R5095

1 2

R5096

1 2

R5097

1 2

R5098

1 2

R5093

1 2

R5092

1 2

R5087

1 2

R5076

1 2

R5048

12

R5049

12

Q5023

6

2

1

R5026

1

2

Q5023

3

5

4

R5025

12

Q5040

6

2

1

R5040

1

2

Q5040

3

5

4

R5041

1

2

R5038

12

Q5027

2

6

1

Q5027

5

3

4

R5023

1

2

R5027

12

R5028

1

2

Q5035

3

1

2

Q5025

3

1

2

C5031

1

2

Q5099

3

1

2

R5099

1

2

C5099

1

2

R5094

1 2

R5024

1

2

R5070

1 2

R5071

1 2

R5066

1

2

R5084

1 2

R5086

1 2

R5081

1 2

Y5065

1 2

R5017

1 2

051-9509

4.2.0

50 OF 113
45 OF 100

33 44

44 46

44

36 44 61

44

44

44

44

44

44

44

33 44

29 30 44

44 46

44 41

44

44

44

33 44

6

44 45

44

44 69

44 61

33

44

45

44

44

6

15 19 28 38 44 60

6

45

44 94

44 94

48 94

6

44 45

44 46

44 46

44 46

44 46

44

44

6

45

6

45

44 41

82

6

6

44 45

44 46

42 44

42 44

44

45

6

45

44

6

45

44 94

45

6

48 94 44

48 94 44

49 94 44

49 94 44

44

44

44

44

48 94

44

44

44

49 94 44

49 94

48 94 44

48 94 44

48 94 44

48 94 44

48 94

44

44

44

44

44

44

44

44

44

48 94

48 94

48 94

44

44

44

44 94

44 48 49 94

6

6

44 45

44

IN

OUT

IN

OUT

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

IN

IN

OUT

IN

IN

OUT

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

IN

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

BI
BI
BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MATT CONNECTOR

LPC+SPI Connector

998-4235

SPI Series Termination

SPI BootROM

44 45

44 45

26

21

18 44 92

26 92

44 45

44 45

45

44 45

44 45

44 45

19 26 44

18 44

46 92

46 92

44 45

46 92

45 46 92

45 46 92

6.3V
CERM

402

10%

1UF

SST25VF064C

64MBIT

CRITICAL

SOIC

OMIT_TABLE

5%

3.3K

402

1/16W
MF-LF

45 46 92

45 46 92

33

402

5%

MF-LF

1/16W

PLACE_NEAR=R5124.2:5mm

PLACE_NEAR=U5110.2:5mm

402

15

1/16W
MF-LF

5%

MF-LF

1/16W

5%

0

402

PLACE_NEAR=J5100.11:5mm

5%
1/16W
MF-LF
402

PLACE_NEAR=J5100.9:5mm

33

18 92

18 92

45 46 92

45 46 92

45 46 92

45 46 92

33

402

5%
1/16W
MF-LF

PLACE_NEAR=R5125.2:5mm

33

402

5%
1/16W
MF-LF

PLACE_NEAR=R5126.2:5mm

402

15

1/16W
MF-LF

5%

PLACE_NEAR=U1800.AR54:5mm

402

15

1/16W
MF-LF

5%

PLACE_NEAR=U1800.AU53:5mm

33

PLACE_NEAR=J5100.12:5mm

5%
1/16W
MF-LF
402

33

402

MF-LF

1/16W

5%

PLACE_NEAR=J5100.14:5mm

21 46 92

18 92

PLACE_NEAR=U1800.AT57:5mm

5%

MF-LF

1/16W

15

402

18 92

402

10K

5%
1/16W
MF-LF

DF40C-30DP-0.4V

M-ST-SM

LPCPLUS
CRITICAL

18 44 92

18 44 92

18 44 92

46 92

21 46 92

18 44 92

SPI and Debug Connector

SYNC_DATE=12/13/2011

SYNC_MASTER=D7_NICK

SPI_ALT_MOSI

SPI_CS0_L

SPI_ALT_CS_L

SPI_CLK_R

SPI_CS0_R_L

SPI_MOSI_R

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_ALT_CLK

SPI_MLB_MOSI

SPI_WP_L

=PP3V3_S5_ROM

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_CLK

SPI_MISO

SPI_MLB_CLK

SPI_MLB_MISO

SPI_ALT_MISO

SPI_MOSI

=PP5V_S0_LPCPLUS

=PP3V3_S5_LPCPLUS

SMC_TMS

SMC_RX_L

SMC_ROMBOOT

SMC_RESET_L

SMC_TDI

LPC_PWRDWN_L

SPI_ALT_CS_L

SPI_ALT_CLK

PM_CLKRUN_L

SPI_ALT_MISO

TP_SMC_MD1

TP_SMC_TRST_L

LPCPLUS_GPIO

SMC_TDO

DEBUG_RESET_L

SMC_TX_L

LPC_CLK33M_LPCPLUS
LPC_AD<0>

LPC_AD<2>
LPC_AD<1>
LPC_AD<3>
SPI_ALT_MOSI

SPIROM_USE_MLB

LPC_FRAME_L

SMC_TCK

LPC_SERIRQ

C5110

1

2

U5110

1

7

6

5

2

8

4

3

R5111

1

2

R5129

1 2

R5130

1 2

R5123

1

2

R5124

1

2

R5128

1 2

R5127

1 2

R5121

1 2

R5122

1 2

R5125

1

2

R5126

1

2

R5120

1 2

R5112

1

2

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

051-9509

4.2.0

51 OF 113
46 OF 100

46 92

92

46 92

46 92

6

92

46 92

92

6

6

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH (SML 1)

Mux

Unused PCH SM Link

K60 Panel Requires these pullups - Can NOSTUFF when we get K70 panels

U1800

BLC Control from TCon

U9700

U9700

J9100

J9100

TCon has 4.7K pullup

0x9F Read

0x9E Write

GPU Die Temp

Temp Sensors (Prod)

LCD Temp IRemote (Dev4Now)

Display TCon

Display TCon

0x88 Write
0x89 Read

SMC (SMBus 1)

SMC (SMBus 0)

DIMM 0:

Backlight Control

0x?? Write

CHS

0x77 Read

0x76 Write

0x?? Read

U9700

PCH (SMBus)

U1800

Line Legend

Master
Slave

0x73 Read

0x72 Write

Mikey

U6551

U6550

VRef DAC

U3400

0x31 Read

0x99 Read

U8000

0xA4 Write

DIMM 3:

DIMM 2:

J3100 A/B

0xA5 Read

0xA0 Write
0xA1 Read

0xA3 Read

0xA2 Write

Memory Channel B

J3200 A/B

DIMM 1:

U1800

Memory Channel A

0xA7 Read

0xA6 Write

U4900

U5500

0x98 Write
0x99 Read

U5500

TMP006 (Prod):

U5590

0x8B Read

0x8A Write

U5590

0x1B Read

0x1A Write

0x9F Read

0x9E Write

Panel/Vendor ID:

TMP421:

U4900

0x53 Read

0x52 Write

ALS

PCH

U1800

SMC (SMBus 2)

SMC (SMBus 3)

SMC multi-master experiment

U4900

U4900

J2550

XDP

0x95 Read

0x94 Write

U4900

SMC (SMBus 3)

U3600

TBT

0x?? Write
0x?? Read

Vref Control

0x98 Write

EMC1414 (Prod):

U5550

Temp Sensors (Dev)

U5550
TMP423B (Dev):
0x9A Write
0x9B Read

0x?? Write
0x??+01 Read

U3401

0x30 Write

J3510

2.2K

MF-LF
402

1/16W

5%

2.2K

5%
1/16W
MF-LF

402

402

MF-LF

5%

8.2K

1/16W

8.2K

1/16W
MF-LF

402

5%

MF-LF

5%
1/16W

402

2.2K

MF-LF

5%

402

1/16W

2.2K

1/16W

5%

MF-LF
402

4.7K

1/16W

5%

MF-LF

402

4.7K

402

5%

4.7K

1/16W
MF-LFMF-LF

4.7K

402

1/16W

5%

MF-LF

1/16W

5%

4.7K

402402

MF-LF

1/16W

5%

4.7K

5%

0

NOSTUFF

1/16W
MF-LF

402

NOSTUFF

1/16W

5%

0

MF-LF
402

402

5%

MF-LF

1/16W

2.2K

5%

402

MF-LF

1/16W

2.2K

SYNC_DATE=01/03/2012SYNC_MASTER=D7_DOUG

SMBus Connections

=PP3V3_S0_SMBUS_SMC_1

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMB_0_S0_CLK

MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMB_DP_TCON_SDA

MAKE_BASE=TRUE

SMB_DP_TCON_SCL

MAKE_BASE=TRUE

=SMB_SNS3_SCL

=SMB_SNS3_SDA

MAKE_BASE=TRUE

SMBUS_PCH_CLK

SMB_3_DATA

MAKE_BASE=TRUE

SMB_3_CLK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMB_2_S4_DATA

=SMBUS_PCH_SDA

=SMBUS_PCH_SCL

=SMB_ALS_SDA

=SMB_ALS_SCL

=PP3V3_S4_SMBUS_SMC_2

MAKE_BASE=TRUE

SMB_1_S0_CLK

SMB_DP_TCON_SLA_SDA

SMB_DP_TCON_SLA_SCL

=SMB_SNS1_SCL

GPU_SMB_CLK_R

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS_SMC_0

MAKE_BASE=TRUE

SMB_0_S0_DATA

=SMB_DP_BLC_SCL

=SMBUS_XDP_SDA

=I2C_VREFDACS_SDA

=I2C_TBTRTR_SDA

=I2C_SODIMMB_SDA

=I2C_SODIMMA_SDA

=I2C_PCA9557D_SDA

=I2C_MIKEY_SDA

=I2C_CHS_SDA

=I2C_BKLT_SDA

=SMBUS_XDP_SCL

=I2C_VREFDACS_SCL

=I2C_TBTRTR_SCL

=I2C_SODIMMB_SCL

=I2C_PCA9557D_SCL

=I2C_MIKEY_SCL

=I2C_CHS_SCL

=I2C_BKLT_SCL

=SMBUS_PCH_SDA

=SMBUS_PCH_SCL

=I2C_SODIMMA_SCL

MAKE_BASE=TRUE

SMB_1_S0_DATA

MAKE_BASE=TRUE

SMB_2_S4_CLK SMBUS_SMC_2_S4_SCL

=PP3V3_S0_SMBUS_SMC_3

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

SMBUS_SMC_2_S4_SDA

=SMB_SNS2_SDA

=SMB_SNS2_SCL

=PP3V3_S0_DP

SML_PCH_1_DATA

=SMB_SNS1_SDA

GPU_SMB_DAT_R

SML_PCH_1_CLK

=SMB_DP_BLC_SDA

MAKE_BASE=TRUE

SML_PCH_0_CLK

MAKE_BASE=TRUE

SML_PCH_0_DATA

=PP3V3_S0_SMBUS

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

R5261

1

2

R5260

1

2

R5265

1

2

R5264

1

2

R5201

1

2

R5200

1

2

R5211

1

2

R5210

1

2

R5221

1

2

R5220

1

2

R5231

1

2

R5230

1

2

R5262

1

2

R5263

1

2

R5291

1

2

R5290

1

2

051-9509

4.2.0

52 OF 113
47 OF 100

6

44 94

44 94

18
94

81
94

81
94

50

50

18
94

47

47

40

40

6

81

81

50

78
99

6

47

6

86

25

32

34
98

30

29

32

56

56

86

25

32

34
98

30

32

56

56

86

47

47

29

44 94

6

44 94

44 94

44 94

50

50

6

81 83

18

50

78
99

18

86

18
94

18
94

6

47

44 94

44 94

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

V+

REFIN+

IN-

OUT

GND

GND

IN+
IN-

OUT

V+

REFIN+

IN-

OUT

GND

OUT

OUT

IN-

IN+ REF

V+

GND

TABLE_5_ITEM

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU highside sense for GPU Frame Buffer 1.5V and 1.05V Regulators(Uncore)

NOTE:VSNS on S5 to avoid burning G3H Power

TDP: ~0.9A

PEAK: ~1.2A

Voltage sense and IMON amp (VC0G, IC0G)

CPU AXG

Voltage sense and IMON amp (VC0C, IC0C)

CPU Core

VMax = 0.9V

VMax = 0.9V

12V S0

Gain: 200 V/V

PEAK: ~3.1A
TDP: ~2.8A

PEAK: ~2.5A
TDP: ~1.85A

TDP: ~15.4A

353S2073

Highside sense for HDD

Gain: 200 V/V

353S2073

Gain: 200 V/V

353S3597

12V S0

GPU highside sense for GPU Core Regulator

HDD S0

PEAK: ~17.1A

AC/DC lowside sense (System total)

353S2208
Gain: 100 V/V

12V G3H

45 94

U4900.E2:10mm

0.22UF

402

X5R

6.3V

20%

45 94

U4900.E1:10mm

402

X5R

6.3V

0.22UF

20%

U4900.E2:10mm

402

MF-LF

1/16W

1%

18.2K

6

1%

1/16W

U4900.E1:10mm

MF-LF

4.53K

402

6.3V

0.22UF

X5R
402

20%

CRITICAL

0.002

1%

MF-1

1W

0612

402

6.04K

1/16W
MF-LF

1%

U4900.E2:10mm

SC70-5

OPA348

CRITICAL

0.01UF

20%
CERM

402

16V

1/16W

402

MF-LF

1%

OMIT_TABLE

9.31K

10K

1%

1/16W

402

MF-LF

U4900.A6:10mm

5.1K

MF-LF

402

1/16W

5%

U4900.A6:10mm

402

10%

6.3V

0.22UF

CERM-X5R

1/16W
MF-LF
402

1%

10K

45 94

62 96

45 94

U4900.B6:10mm

402

X5R

6.3V

20%

0.22UF

U4900.B6:10mm

1/16W

1%

MF-LF

402

4.53K

45 94

45 94

402

6.3V

U4900.C1:10mm

0.22UF

X5R

20%

U4900.C1:10mm

4.53K

1/16W

1%

MF-LF

402

U4900.C2:10mm

5.1K

MF-LF

5%

1/16W

402

CERM

0.01UF

16V

20%

402

1%
1/16W
MF-LF

21K

402

10K

1%

1/16W

402

MF-LF

U4900.C2:10mm

0.22UF

CERM-X5R

10%

6.3V

402

CRITICAL

SC70-5

OPA348

10K

1%
1/16W
MF-LF
402

62 96

45 94

U4900.F2:10mm

20%

6.3V
402

0.22UF

X5R

U4900.F2:10mm

1/16W

6.04K

1%

402

MF-LF

U4900.F1:10mm

0.22UF

6.3V
X5R
402

20%

402

MF-LF

1%

U4900.F1:10mm

1/16W

4.53K

MF-LF

402

U4900.F2:10mm

18.2K

1/16W

1%

6.3V
X5R
402

20%

0.22UF

1%

0.005

CRITICAL

MF

1W

0612

45 94

45 94

0.22UF

20%

6.3V
X5R
402

U4900.E2:10mm

MF-LF

1%
1/16W

402

6.04K

U4900.E2:10mm

U4900.E1:10mm

4.53K

402

1%

MF-LF

1/16W

U4900.E2:10mm

4.02K

1%

402

MF-LF

1/16W

6

U4900.E1:10mm

20%

0.22UF

6.3V
X5R
402

0805

1%

0.010

MF

CRITICAL

1/4W

45 94

0.22UF

20%

6.3V
X5R
402

U4900.F2:10mm

1/16W

6.04K

1%
MF-LF

402

U4900.F2:10mm

6

U4900.F2:10mm

18.2K

402

MF-LF

1%

1/16W

0.22UF

6.3V

20%
X5R

402

U4900.F1:10mm

0.22UF

6.3V
X5R
402

20%

U4900.F1:10mm

4.53K

1%
1/16W
MF-LF

402

0.005

MF

1W

0612

CRITICAL

1%

INA210

CRITICAL

SC70

CRITICAL

OMIT_TABLE

INA216

WCSP-4

SM

CDZ3.0B

INA210

CRITICAL

SC70

6

SC70

CRITICAL

INA214

I and V Sense(Production)

SYNC_MASTER=D7_DOUG

SYNC_DATE=01/06/2012

U5320

1

INA216A4 200V/V Current Sense

353S3597

R5364

SNS_CPUCORE:3PHASE

1

RES,MTL FILM,1/16W,9.31K,0402

114S0312

R5364

SNS_CPUCORE:4PHASE

1

114S0345

RES,MTL FILM,1/16W,21K,0402

ISNS_P12VG3H_R

SNS_P12VG3H_N

SNS_P12VG3H_P

=PP3V3_S5_SENSE

GND_SMC_AVSS

VSNS_P12VG3H

VSNS_P12VS0_GPUCORE

ISNS_P12VG3H

SNS_HDD_N

ISNS_HDDS0_R

SNS_HDD_P

VSNS_P12VS0_GPUUNCORE

ISNS_P12VS0_GPUUNCORE

ISNS_P12VS0_GPUUC_R

SNS_P12VS0_GPUUC_P

SNS_P12VS0_GPUUC_N

=PP12V_S0_SNS_GPUUNCORE_R

=PPVAXG_S0_CPU

SNS_P12VS0_GPUCORE_P

=PP12V_S0_SNS_GPUCORE_R

PPHDD_S0_SNS

=PP3V3_S0_SENSE

SNS_P12VS0_GPUCORE_N

ISNS_P12VS0_GPUCORE_R

GND_SMC_AVSS

GND_SMC_AVSS

PP12V_S0_SNS_GPUCORE

GND_SMC_AVSS

ISNS_P12VS0_GPUCORE

GND_SMC_AVSS

GND_SMC_AVSS

VSNS_CPUCORE

ISNS_CPUCORE

GND_SMC_AVSS

GND_SMC_AVSS

VSNS_CPUAXG

ISNS_CPUAXG

REG_CPUAXG_IMON

=PP5V_S0_ISENSE

ISNS_CPUCORE_P

=PPVCORE_S0_CPU

=PP5V_S0_ISENSE

ISNS_CPUAXG_FB

ISNS_CPUAXG_N

ISNS_CPUAXG_P

REG_CPUCORE_IMON

ISNS_CPUCORE_FB

ISNS_CPUCORE_N

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_HDDS0

VSNS_HDDS0

=PPHDD_S0_SNS_R

PP12V_G3H_SNS

=PP12V_S5_SNS

=PP12V_G3H_SNS_R

PP12V_S0_SNS_GPUUNCORE

=PP3V3_S0_SENSE

C5302

1

2

C5305

1

2

R5301

1 2

R5305

1 2

C5300

1

2

R5300

1 2
3 4

R5302

1

2

U5360

3

1

4

2

5

C5360

1

2

R5364

1 2

R5362

1 2

R5365

1 2

C5365

1

2

R5363

1

2

C5361

1

2

R5361

1 2

C5371

1

2

R5371

1 2

R5375

1 2

C5370

1

2

R5374

1 2

R5372

1 2

C5375

1

2

U5370

3

1

4

2

5

R5373

1

2

C5312

1

2

R5312

1

2

C5315

1

2

R5315

1 2

R5311

1 2

C5310

1

2

R5310

1 2
3 4

C5322

1

2

R5322

1

2

R5325

1 2

R5321

1 2

C5325

1

2

R5320

1 2
3 4

C5352

1

2

R5352

1

2

R5351

1 2

C5350

1

2

C5355

1

2

R5355

1 2

R5350

1 2
3 4

U5350

2

5

4

6

1

3

U5320

B1

A2

A1 B2

DZ5320

A

K

U5310

2

5

4

6

1

3

U5300

2

5

4

6

1

3

051-9509

4.2.0

53 OF 113
48 OF 100

94

94

94

6

44 45 48 49
94

94

94

94

94

94

94

6

6

13 17 62

94

6

6

41 48 49 50

94

94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

6

48

94

6

13 16 62

6

48

94

94

94

94

94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

44 45 48 49
94

6

6 6

6

41 48

49 50

OUT

OUT

OUT

V+

REFIN+

IN-

OUT

GND

OUT

OUT

OUT

GND

IN+
IN-

OUT

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

353S3597

TDP: ~2.1 A

Peak: ~3 A(Connector Supports 5A)

VDDQ S3

Peak: ~12 A
TDP: ~6 A

VDDQ lowside sense for SO-DIMM modules

Gain: 500 V/V

353S2216

SSD S0

Highside sense for SSD

Gain: 200 V/V

45 94

OMIT_TABLE
U4900.B4:10mm

0.22UF

20%
X5R

402

6.3V

45 94

OMIT_TABLE
U4900.A4:10mm

20%

6.3V
X5R

0.22UF

402

MF-LF

1/16W

4.53K

U4900.A4:10mm

1%

SNS_VDDQS3_DDR:Y

402

6

402

MF-LF

SNS_VDDQS3_DDR:Y

1%
1/16W

U4900.B4:10mm

4.53K

20%

402

0.22UF

X5R

6.3V

SNS_VDDQS3_DDR:Y

SNS_VDDQS3_DDR:Y

INA211

SC70

0.0005

0612

1W
MF

1%

CRITICAL

45 94

45 94

0.22UF

20%

6.3V
X5R
402

U4900.E2:10mm

SSD

1%

402

MF-LF

1/16W

4.53K

U4900.E1:10mm

SSD

1/16W
MF-LF

1%

U4900.E2:10mm

4.53K

402

SSD

6

U4900.E1:10mm

20%

0.22UF

6.3V

402

X5R

SSD

0612

CRITICAL

0.002

1W

MF-1

1%

SSD

WCSP-4

CRITICAL

OMIT_TABLE

INA216

SYNC_MASTER=K70_MLB

SYNC_DATE=11/30/2011

I and V Sense(Development)

353S3597

INA216A4 200V/V Current Sense

1

U5420

SSD

116S0004

2

RES,0 OHM,402

SNS_VDDQS3_DDR:N

C5441,C5445

SNS_VDDQS3_DDR:Y

CAP,0.22UF,402

132S0080

2

C5441,C5445

=PPSSD_S0_SNS_R

SNS_SSD_N

SNS_SSD_P

PPSSD_S0_SNS

PPVDDQ_S3_SNS_DDR

SNS_VDDQS3_DDR_N

=PPVDDQ_S3_SNS_DDR_R

GND_SMC_AVSS

ISNS_SSDS0

VSNS_VDDQS3_DDR

ISNS_VDDQS3_DDR_R

=PP3V3_S0_SENSE

GND_SMC_AVSS

GND_SMC_AVSS

SNS_VDDQS3_DDR_P

GND_SMC_AVSS

ISNS_SSDS0_R

VSNS_SSDS0

ISNS_VDDQS3_DDR

C5441

1

2

C5445

1

2

R5445

1 2

R5441

1 2

C5440

1

2

U5440

2

5

4

6

1

3

R5440

1 2
3 4

C5422

1

2

R5425

1 2

R5421

1 2

C5425

1

2

R5420

12
34

U5420

B1

A2

A1 B2

051-9509

4.2.0

54 OF 113
49 OF 100

6

94

94

94

6

44 45 48 49
94

94

6

41 48

50

44 45 48 49
94

44 45 48 49
94

94

44 45 48 49
94

94

IN
IN

GND

V+

SCL
SDA

DXP1
DXP2
DXP3
DXN

IN

BI

NC

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

BI

IN

AGNDDGND

SCL

SDA

ADR0
ADR1

DRDY*

V+

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

Make sure these caps are OK with U5500 Vendor!

I2C Address (EMC1414-1):

BLC Proximity

CPU Prox

GPU Prox

AC/DC

will be used as the ambient sensor.
Place U5500 at the coolest location
on the MLB.

NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!

I2C Address (TMP006):

0x8A (Write)
0x8B (Read)

0x9A (Write)
0x9B (Read)

I2C Address (TMP432B):

Temperature Sensor T1: Production Bound

Skin

SO-DIMM

518S0698

Skin

Diode on supply

Internal sensor of the EMC 1414

AC/DC

Note:

0x99 (Read)

0x98 (Write)

Temperature Sensor T3: LCD Remote Sensor(Dev4Now)

BLC Prox

GPU Proximity

SO-DIMM Proximity

Temperature Sensor T2: Development Only

CPU Proximity

50V
C0G-CERM
402

2.2PF

+/-0.25PF

Q5510.3:2MM

1UF

X5R

10V

10%

402-1

L5514.2:2MM

402

0.0022UF

CERM

50V

10%

0402

FERR-220-OHM

FERR-220-OHM

0402

6

94

6

94

X5R

10V
402-1

10%

1UF

SIGNAL_MODEL=EMPTY

OMIT

SM

U5550.4:2MM

TMP423

SOT23-8

SIGNAL_MODEL=EMPTY

SM

OMIT

U5550.4:2MM

U5550.4:2MM

SM

OMIT

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY
Q5560.3:2MM

+/-0.25PF
C0G-CERM

2.2PF

50V
402

402

50V

2.2PF

Q5564.3:2MM

C0G-CERM

+/-0.25PF

SIGNAL_MODEL=EMPTY

10K

5%
1/16W
MF-LF
402

47

47

10%

402

CERM

TEMPSNSDEV

0.0022UF

L5562.2:2MM

SIGNAL_MODEL=EMPTY

50V

0402

FERR-220-OHM

TEMPSNSDEV

0402

FERR-220-OHM

TEMPSNSDEV

CRITICAL

53780-8602

M-RT-SM

TEMPSNSDEV

SILK_PART=SkinTemp

402

50V

2.2PF

+/-0.25PF
C0G-CERM

Q5512.3:2MM

EMC1414-1-AIZL

MSOP

47

47

TMP0006AIYZER

TEMPSNSDEV

WCSP

TEMPSNSDEV

16V
CERM
402

0.01UF

10%

47

47

TEMPSNSDEV

402

MF-LF

1/16W

5%

10K

402

CERM

50V

47PF

5%

U5500.5:2MM

NOSTUFF

402

CERM

50V

47PF

5%

U5500.4:2MM

NOSTUFF

PLACEMENT_NOTE=Place Q5512 in CPU socket cavity

BC846BLP

DFN1006H4-3

CRITICAL

CRITICAL

PLACEMENT_NOTE=Place Q5510 near GPU and GDDR5

DFN1006H4-3

BC846BLP

CRITICAL

DFN1006H4-3

BC846BLP

PLACEMENT_NOTE=Place Q5550 near SO-DIMM connectors

CRITICAL

DFN1006H4-3

BC846BLP

PLACEMENT_NOTE=Place Q5554 near BLC controller

ALL

Alternate Temp Diode

372S0185372S0186

SYNC_MASTER=D7_DOUG

Temperature Sensors

SYNC_DATE=12/13/2011

SNS_T1_2_N

MAKE_BASE=TRUE

SNS_T1_2_P

MAKE_BASE=TRUE

SNS_SKIN_N

DIFFERENTIAL_PAIR=SNS_SKIN

SNS_SKIN_P

DIFFERENTIAL_PAIR=SNS_SKIN

SNS_T2_1_N

DIFFERENTIAL_PAIR=SNS_T2

DIFFERENTIAL_PAIR=SNS_T2

SNS_T2_1_P

SNS_T2_3_N

DIFFERENTIAL_PAIR=SNS_T3

DIFFERENTIAL_PAIR=SNS_T3

SNS_T2_3_P

SNS_T1_1_P

SNS_T1_1_N

SNS_T2_3_N SNS_T2_DXN

SNS_T2_3_P

SNS_T2_2_P

SNS_T1_3_N

=SMB_SNS1_SDA

=SMB_SNS1_SCL

SNS1_ALERT_L

SNS_ACDC_P
SNS_ACDC_N

SNS_T2_2_P

SNS_T2_2_N

SNS_T2_1_P

SNS_T2_1_N

SNS_T2_2_N

SNS_T1_3_P

=PP3V3_S0_SENSE

=SMB_SNS2_SCL
=SMB_SNS2_SDA

=SMB_SNS3_SCL

=SMB_SNS3_SDA

=PP3V3_S0_SENSE

TMP006_DRDY

=PP3V3_S0_SENSE

SNS_T1_3_P

SNS_T1_3_N

SNS_T1_1_P

SNS_T1_1_N

SNS_T1_2_N

SNS_T1_2_P

C5510

1

2

C5500

1

2

C5514

1

2

L5514

1 2

L5515

1 2

C5550

1

2

XW5551

1 2

U5550

4

1
2
3

5

7
6

8

XW5552

1 2

XW5553

1 2

C5560

1

2

C5564

1

2

R5500

1

2

C5562

1

2

L5562

1 2

L5563

1 2

J5562

3

4

1
2

C5512

1

2

U5500

83

5

2

4

6

10

9

7

1

U5590

C1
B1

A2

A1

C2

B3

C3

A3

C5590

1

2

R5590

1

2

C5505

1

2

C5504

1

2

Q5512

1

3

2

Q5510

1

3

2

Q5560

1

3

2

Q5564

1

3

2

051-9509

4.2.0

55 OF 113
50 OF 100

50 94

50 94

94

94

50 94

50 94

50 94

50 94

50 94

50 94

50 94

50 94

50 94

50

50 94

50 94

50 94

50 94

50 94

50

6

41 48 49 50

6

41 48 49 50

6

41 48 49 50

50

50

50 94

50 94

50 94

50 94

IN

IN

OUT

OUT

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC Fan 1 (Unused)

the fan acts as a non-inverting

present on the SMC pin! Then by
definition, the drain of Q5610 is
at common and the SMC sinks current

This resembles an open-drain if

Otherwise, this is simply a pass-FET.

level-shifter to protect the SMC.

FET input.

Note:

The circuit for the PWM input to

It is assumed there is a pull-up to

when Q5610 is on.

Tach
GND
12V DC

518S0730

there is a pull-up, going to a Hi-Z

SMC Fan 0 (System)

turns on, there would be 5V/12V

when the SMC PWM goes low and Q5610

5V/12V inside the fan, otherwise

CRITICAL

220-OHM-1.4A

0603

20%
16V
CERM
402

0.01UF

4.7UF

20%
16V
CERM
1206-1

44

CRITICAL

53780-8604

M-RT-SM

44

44

CRITICAL

0402

FERR-220-OHM

CRITICAL

0402

FERR-220-OHM

100PF

CERM

50V

5%

402

CERM
402

50V

5%

100PF

47K

MF-LF

1/16W

5%

402

5%

MF-LF

1/16W

47K

402

44

10K

1/16W
MF-LF

5%

402

CRITICAL

SSM3K15AMFVAPE

VESM

SYNC_DATE=11/30/2011

System Fan

SYNC_MASTER=K70_MLB

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM
FAN_0_PWM_FILT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=12V

PP12V_S0_FAN_0_FILT

=PP12V_S0_FAN

SMC_FAN_1_CTL

SMC_FAN_1_TACH

FAN_0_TACH_FILT

SMC_FAN_0_TACH

=PP3V3_S0_FAN

FAN_0_TACH_FET

FAN_0_PWM_FETSMC_FAN_0_CTL

=PP3V3_S0_FAN

L5600

1 2

C5601

1

2

C5600

1

2

J5600

5

6

1
2
3
4

L5620

1 2

L5610

1 2

C5620

1

2

C5610

1

2

R5626

1

2

R5625

1 2

R5610

1

2

Q5610

3

1

2

051-9509

4.2.0

56 OF 113
51 OF 100

6

6

51

6

51

OUT

OUT

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC
FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+
MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI
SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+
LINEOUT_L2­LINEOUT_R2+

OUT

OUT

IN

OUT

NC
NC

OUT

G

D

S

P-CHN

D

S

G

N-CHN

G

D

S

P-CHN

NC
NC

D

S

G

N-CHN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

NR/FB

NC

IN

EN

GND

IN

OUT

OUT

OUT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2456

TWEETERS

NC

NC

NC

NC

DMICS 1 & 2

NC

PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE

SE FSINPUT= 1.22VRMS

VD MUST BE LESS THAN OR EQUAL TO VL_HD

APPLE P/N 353S2592

AUDIO CODEC

PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5

WIN SPKR AMP CNTRL

DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA

NC
NC

WOOFERS

HP AMP/LINE OUT

RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT

DAC2/3 FSOUTPUTSE= 1.34VRMS

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

DAC1 FSOUTPUT= 1.34VRMS

DIFF FSINPUT= 2.45VRMS

PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

HP AMP CNTRL

MAC SPKR AMP CNTRL

NC

NC

56 92

52 54

QFN

CRITICAL

CS4206B

X5R-1

4V

402

4.7UF

20%

53

40

1/16W
MF-LF

402

5%

22

52 54

40

BAT54XV2T1

SOD-523

SM

MF-LF

1/16W
402

0

5%

DEVEL_AUDIO

20%

10UF

0402-1

X5R-CERM

10V

CRITICAL

402

X5R

10V

0.47UF

10%

SM

40

SOT563

CRITICAL

DMC2400UV

DEVEL_AUDIO

0

402

MF-LF

1/16W

5%

DEVEL_AUDIO

CRITICAL

DMC2400UV

SOT563

DEVEL_AUDIO

DEVEL_AUDIO

DMC2400UV

CRITICAL

SOT563

DEVEL_AUDIO

5%
1/16W
MF-LF
402

0

DEVEL_AUDIO

5%

0

402

1/16W
MF-LF

1/16W

5%

22

402

MF-LF

DMC2400UV

DEVEL_AUDIO

SOT563

CRITICAL

22

1/16W

402

MF-LF

5%

1%
1/16W
MF-LF

402

100K

2.2UF

CERM

20%

6.3V
402-LF

18 92

6.3V
CERM

2.2UF

402-LF

20%

52 56 58

402

MF-LF

2.67K

1%
1/16W

CERM
402-LF

2.2UF

6.3V

20%

0.47UF

402

10%
X5R

10V

402-LF

2.2UF

CERM

6.3V

20%

16V

20%

10UF

POLY-TANT

CASE-B2-SM

20V

10%
TANT

CASE-P3-HF

CRITICAL

1UF

18 92

CRITICAL

10UF

20%
POLY-TANT

CASE-B2-SM

16V

56 59

56 59

81 98

55 59

55 59

54 59

54 59

53 55 59

53 55 59

53 54 59

POLY-TANT

16V

20%

10UF

CASE-B2-SM

X5R

10%
10V

402

0.47UF

18 92

1UF

402-1

X5R

10%
10V

402

10V

10%

0.47UF

X5R

10%

0.47UF

10V
X5R
402

53 54 59

402

MF-LF

0

1/16W

5%

15 18 92

52 56 58

6

40 52 54 55 58

52 53

6

40 52 54 55
58

6

59

18 92

402

5%

1/16W

0

MF-LF

SM

1UF

10%
10V
X5R

402-1

CRITICAL

SON

TPS71745

0402

FERR-220-OHM

0402

FERR-220-OHM

X7R-CERM

10%
16V

402

0.1UF

10V

10%

1UF

402-1

X5R

58 59

52 53

52 56 58

54

AUDIO: CODEC/REGULATORS

SYNC_MASTER=D7_BREECE

SYNC_DATE=01/03/2012

C6113

127S0111127S0134

THAILAND ALTERNATE

GND_AUDIO_CODEC

DP_INT_SPDIF_AUDIO

HDA_RST_L

AUD_SDI_R

HDA_BIT_CLK

AUD_SENSE_A

TP_DMIC_SDA2

AUD_DMIC_SDA1

AUD_LO1_L_P

AUD_GPIO_2

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM

CS4206_HPREF

AUD_LO2_R_N

CS4206_FLYP
CS4206_FLYC

CS4206_FLYN

AUD_GPIO_3

AUD_CODEC_MICBIAS

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

NO_TEST=TRUE

NC_AUD_LI_P_R

GND_AUDIO_CODEC

AUD_LO1_L_N

AUD_LO2_L_N

AUD_CODEC_MICBIAS

AUD_LO2_L_P

AUD_LO2_R_P

VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.15MM

HDA_SDOUT

HDA_SYNC

HDA_SDIN0

AUD_MIC_INL_N

AUD_LO1_R_N

AUD_LO1_R_P

PP5V_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

CS4206_FN

=PP1V5_S0_AUD_DIG

CS4206_FP

VBIAS_DAC

AUD_SPDIF_OUT

=PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

GND_AUDIO_HPAMP

AUD_DMIC_CLK

NC_AUD_LI_COM

NO_TEST=TRUE

MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

TP_AUD_HP_R

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.1MM

TP_AUD_HP_L

=PP3V3_S0_AUDIO

GND_AUDIO_DMIC

MIN_LINE_WIDTH=0.20MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.15MM

MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V

MIN_LINE_WIDTH=0.40MM

4V5_REG_IN

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

4V5_NR

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V

PP5V_AUDIO_HPAMP

VOLTAGE=0V

MIN_LINE_WIDTH=0.5MM

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.2MM

4V5_REG_EN

AUD_SPDIF_CHIP

NO_TEST=TRUE

NC_AUD_LI_P_L

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_VCOM

NO_TEST=TRUE

NC_AUD_MIC_INP_R

CS4206_DMIC_SCL

MIN_LINE_WIDTH=0.20MM

CS4206_VREF_ADC

MIN_NECK_WIDTH=0.15MM

AUD_MIC_INL_P

Q6171_P_S

Q6171_P_G

Q6171_N_G

Q6171_N_S

Q6170_N_S

Q6170_N_G

Q6170_P_G

Q6170_P_S

NO_TEST=TRUE

NC_AUD_MIC_INN_R

D6100

A K

R6102

1 2

R6101

1 2

R6103

1

2

C6111

1

2

C6112

1

2

R6100

1

2

C6109

1

2

C6100

1

2

C6110

1

2

C6108

1

2

C6113

1

2

C6114

1

2

C6103

1

2

C6102

1

2

C6105

1

2

C6104

1

2

C6106

1

2

R6105

1

2

R6120

1 2

XW6111

1

2

C6122

1

2

VR6101

4

2

6

3

1

L6110

1 2

L6111

1 2

C6123

1

2

C6124

1

2

U6101

26

6

7

4

43
42

45

2

12

14
15

38
40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

11

8
5

13

47
48

10

49

25

46

24

29

28

9

41

44

3

1

27

C6101

1

2

R6104

1 2

XW6110

1

2

R6171

1

2

C6107

1

2

C6115

1

2

XW6100

1

2

Q6170

3

5

4

R6170

1

2

Q6170

6

2

1

Q6171

3

5

4

R6172

1

2

R6173

1

2

Q6171

6

2

1

051-9509

4.2.0

61 OF 113
52 OF 100

5

52 56 58 59

92

52 56 58 59

52 56 58 59

52 56 58 59

6

53

52 56 58 59

92

PGND

SGND

PVSS

THM_PAD

PVDD

SVDD

BIAS

OUTL

OUTR

C1P
C1N

SVDD2
INL­INL+

INR-

INR+

SHDN*

IN

IN

IN

IN

IN
IN

IN
IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

G

D

S

IN

IN

OUT

G

D

S

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

NCNC

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

1UF

10%
10V
X5R
402-1

10V

10%

1UF

X5R

402-1

X5R

1UF

10%
10V

402-1

10V

1UF

10%
X5R

402-1

0.1UF

10%
16V

402

X7R-CERM

MAX97220AETE

CRITICAL

TQFN

52 55 59

52 55 59

52 54 59

52 54 59

53 59

53 59

53 59

53 59

53 59

53 59

53 56

53 59

53 59

53 56

53 56

53 56

402-1

10%
10V

1UF

X5R

20%

6.3V
TANT

CASE-A

33UF

CRITICAL

33UF

CRITICAL

6.3V
TANT

20%

CASE-A

TANT

33UF

CASE-A

6.3V

20%

CRITICAL

20%

CRITICAL

33UF

CASE-A

TANT

6.3V

402

220PF

5%

25V

CERM

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

5%
25V
CERM
402

220PF

SIGNAL_MODEL=EMPTY

5%
25V
CERM
402

220PF

5%

25V

CERM

402

220PF

SIGNAL_MODEL=EMPTY

X7R-CERM

0.1UF

10%
16V

402

X7R-CERM

16V
402

10%

0.1UF

402

1/16W

5%

33

MF-LF

33

402

MF-LF

1/16W

5%

10UF

20%
10V
X5R-CERM
0402-1

NOSTUFF
CRITICAL

SOT23

MMBFJ201

0402

FERR-220-OHM

201

1/20W

MF

5%

100K

52

53

53

NOSTUFF

402

MF-LF

1/16W

5%

2.0K

NOSTUFF

1/16W

2.0K

402

MF-LF

5%

NOSTUFF
CRITICAL

SOT23

MMBFJ201

NOSTUFF

1/16W
MF-LF

0

402

5%

NOSTUFF

0

5%

402

MF-LF

1/16W

201

1/20W

MF

1%

10K

201

1/20W

MF

1%

10K

201

1/20W

MF

10K

1%

1/20W

201

MF

10K

1%

201

1/20W

MF

1%

7.87K

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

201

1/20W

MF

1%

7.87K

201

1/20W

MF

SIGNAL_MODEL=EMPTY

7.87K

1%

201

1/20W

MF

1%

7.87K

SIGNAL_MODEL=EMPTY

AUDIO: HEADPHONE AMP

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_BREECE

127S0120127S0135

C6273

THAILAND ALTERNATE

C6271

127S0120127S0135

THAILAND ALTERNATE

127S0120127S0135

C6263

THAILAND ALTERNATE

127S0135

C6261

127S0120

THAILAND ALTERNATE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAX97220_C1N

AUD_LO1_L_P

AUD_LO1_L_C_P

AUD_HP_PORT_REF

AUD_GPIO_2

MAX97220_PVSS

MAX97220_INR_N

MAX97220_OUTL_ZOBEL

MIN_NECK_WIDTH=0.2MM

MAX97220_OUTR

MIN_LINE_WIDTH=0.4MM

MIN_NECK_WIDTH=0.2MM

MAX97220_OUTL

MIN_LINE_WIDTH=0.4MM

MAX97220_OUTR_ZOBEL

MAX97220_INL_N

MAX97220_INL_P

MAX97220_SHDN_L

MAX97220_INR_P

GND_AUDIO_HPAMP

MAX97220_SHDN_L

MAX97220_OUTR

MAX97220_INL_P

AUD_LO1_R_C_N

AUD_LO1_R_C_P

AUD_LO1_R_N

AUD_LO1_R_P

AUD_LO1_L_N

MIN_NECK_WIDTH=0.2MM

MAX97220_BIAS

MIN_LINE_WIDTH=0.4MM

MAX97220_INR_P

GND_AUDIO_HPAMP

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

MAX97220_C1P

PP5V_AUDIO_HPAMP

VOLTAGE=0V

MAX97220_PVSS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

HPOUT_JFET_G

MAX97220_INR_N

GND_AUDIO_HPAMP

PP5V_AUDIO_HPAMP

AUD_LO1_L_C_N

MAX97220_OUTL

MAX97220_INL_N

R6261

1 2

R6263

1 2

R6273

1 2

R6271

1 2

R6264

1

2

R6274

1

2

R6262

1 2

R6272

1 2

C6254

1

2

C6252

1

2

C6256

1

2

C6255

1

2

C6250

1

2

U6250

11

4

2

14
15

8

7

12

10

315

6

16

13

9

17

C6253

1

2

C6261

1 2

C6263

1 2

C6273

1 2

C6271

1 2

C6262

1 2

C6264

1

2

C6274

1

2

C6272

1 2

C6257

1

2

C6258

1

2

R6252

1

2

R6251

1

2

C6251

1

2

Q6251

1

3

2

L6250

1 2

R6250

1

2

R6253

1

2

R6254

1

2

Q6250

1

3

2

R6255

1 2

R6256

1 2

051-9509

4.2.0

62 OF 113
53 OF 100

59

56

53

52 53

59

59

52 53

52 53

53

52 53

52 53

59

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

INL+

BOOTL-

GAIN

MONO

OUTR+

INR+

INL-

BOOTL+

OUTL+

OUTL-

EDGE

STDNR*

AGND

NC

THERM

INR-

BOOTR-

OUTR-

PVDD

THRM_PAD

BOOTR+

STDNL*

PGND

VREG/AVDD

REGEN

OUT OUT OUT

IN

IN

OUT

OUT

NC
NC

OUT

OUT

IN

IN

SYM_VER-2

SYM_VER-2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAKE LAYOUT MORE LOGICAL

OUTPUT POLARITY FLIP TO

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

WOOFERS & TWEETERS ON UNDER MAC OS

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

OUTPUT POLARITY FLIP TO
MAKE LAYOUT MORE LOGICAL

PINS 14 & 15 ARE TEST PINS AND

LEFT CH SPEAKER AMP

APPLE P/N 353S3163

GAIN R6306 R6307

+18 DB NOSTUFF 47 KOHM
+24 DB 47 KOHM NOSTUFF

+15 DB 0 OHM NOSTUFF

HIGH = MONO OPERATION

CONTROL R6304 R6305

EDGE RATE

+9 DB NOSTUFF 0 OHM

OFF NOSTUFF 0 OHM

AUD_RAMP_MONO NET:

FC_HPF, WOOFERS = ~18 HZ (0.22 UF)

SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
FC_HPF, TWEETERS = ~847 HZ (4700 PF)

LOW = STEREO OPERATION

SHOULD BE TIED TO GND

NC

ON 0 OHM NOSTUFF

+12 DB NOSTUFF NOSTUFF

ONLY WOOFERS ON UNDER WINDOWS

20%
10V

X5R-CERM

402

2.2UF

54

54 55

54

54 55

52 53 59

6

55

0402

FERR-1000-OHM

52 59

10UF

805

10%
X5R

25V

X5R

10UF

25V
805

10%

X5R

25V

20%

603

0.22UF

54

25V
X5R
603

0.22UF

20%

0.22UF

X5R

25V
603

20%

X5R

20%

0.22UF

25V
603

NP0-C0G

SIGNAL_MODEL=EMPTY

25V
402

1000PF

5%

CRITICAL

52 59

CRITICAL

5%

1000PF

SIGNAL_MODEL=EMPTY

25V
402

NP0-C0G

1000PF

CRITICAL

SIGNAL_MODEL=EMPTY

402

5%
25V
NP0-C0G

402

NP0-C0G

25V

5%

1000PF

CRITICAL

SIGNAL_MODEL=EMPTY

0.1UF

10%
X5R

402

25V 25V

X5R

10%

1UF

603-1

10%
X5R

0.1UF

402

25V

52 53 59

57 59

57 59

57 59

57 59

25V
X5R

1UF

10%

603-1

LFCSP

CRITICAL

SSM3302

5%

0

402

1/16W
MF-LF

NOSTUFF

1/16W

0

402

5%
MF-LF

0402

FERR-1000-OHM

54

MF-LF

5%

0

402

1/16W

54

1/16W
402

0

5%
MF-LF

402

0

NOSTUFF

5%
1/16W
MF-LF

54

52

0

MF-LF

402

5%

1/16W

FERR-1000-OHM

0402

52

MF-LF

1/16W

5%

402

100K

NOSTUFF

5%
CERM

402

100PF

50V

54 55

5%

MF-LF

402

100K

1/16W

CERM

50V

100PF

402

NOSTUFF

5%

54 55

5%
25V

402

1000PF

CRITICAL

NP0-C0G

SIGNAL_MODEL=EMPTY

0402

FERR-1000-OHM

1000PF

5%
25V

402

NP0-C0G

CRITICAL

SIGNAL_MODEL=EMPTY

CRITICAL

16V

POLY

SM

470UF

20%

54

54

54

54

0402

FERR-1000-OHM

SIGNAL_MODEL=EMPTY

CRITICAL

110-OHM-3A

DLY5ATN111SQ2

CRITICAL

SIGNAL_MODEL=EMPTY

110-OHM-3A

DLY5ATN111SQ2

4700PF

NPO-C0G

5%

50V
805

50V
805

5%

NPO-C0G

4700PF

10%
16V

402

CERM

0.22UF

0.22UF

16V

CERM

402

10%

AUDIO: LEFT SPKR AMP

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_BREECE

AUD_LAMP_RINC_P

AUD_LAMP_RIN_P

AUD_LAMP_RINC_N

AUD_LAMP_RIN_N

AUD_LAMP_MONO

=PP3V3_S0_AUDIO

AUD_LAMP_LINC_P

AUD_LAMP_LIN_P

AUD_LAMP_LINC_N

AUD_LAMP_LIN_N

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BOOTRP

AUD_SPKR_LWFR_OUT_P

AUD_LAMP_OUTNR

AUD_LAMP_OUTPR

AUD_SPKRAMP_MAC_SHDN_L

AUD_CODEC_MICBIAS

AUD_LO2_L_N

AUD_LAMP_AVDD

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM
VOLTAGE=5V

AUD_LAMP_AVDD

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BOOTLN

MIN_NECK_WIDTH=0.15MM

AUD_LAMP_MONO

AUD_GPIO_3

AUD_SPKRAMP_WIN_SHDN_L

AUD_LAMP_EDGE

AUD_LAMP_GAIN

AUD_LO1_L_P

AUD_LO2_L_P

AUD_LAMP_GAIN

AUD_LAMP_EDGE

AUD_SPKRAMP_WIN_SHDN_L

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

AUD_LAMP_BOOTRN

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_LAMP_OUTNL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_SPKR_LWFR_OUT_N

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

AUD_LAMP_BOOTLP

AUD_SPKRAMP_MAC_SHDN_L

AUD_LO1_L_N

AUD_LAMP_OUTPL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTNR

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTPR

MIN_NECK_WIDTH=0.25MM

TP_AUD_LAMP_THERM

=PP12V_S0_AUDIO_SPKRAMP

L6301

1 2

L6300

1 2

L6302

1 2

C6317

1

2

L6303

1 2

C6300

1

2

C6301

1

2

C6316

1 2

C6315

1 2

C6314

1 2

C6313

1 2

C6319

1

2

C6320

1

2

C6321

1

2

C6322

1

2

C6302

1

2

C6303

1

2

C6304

1

2

C6305

1

2

U6300

7

24

6

1

25

30

10

21

12

11

19

20

16

13

14

15

18

4

5

2

3

26

27

28

29

3132333839

40

343536

37

23

9

22

17

41

8

R6305

1

2

R6304

1

2

R6303

1

2

R6307

1

2

R6306

1

2

R6308

1 2

R6309

1

2

C6318

1

2

R6301

1

2

C6312

1

2

C6323

1

2

C6324

1

2

C6306

1

2

L6308

1 2

L6305

1 2

34

L6307

1 2

34

C6309

1 2

C6308

1 2

C6311

1 2

C6310

1 2

051-9509

4.2.0

63 OF 113
54 OF 100

59 59

59 59

6

40 52 55 58

59 59

59 59

54

54

IN

IN

IN

INL+

BOOTL-

GAIN

MONO

OUTR+

INR+

INL-

BOOTL+

OUTL+

OUTL-

EDGE

STDNR*

AGND

NC

THERM

INR-

BOOTR-

OUTR-

PVDD

THRM_PAD

BOOTR+

STDNL*

PGND

VREG/AVDD

REGEN

IN

IN

IN

OUT OUT OUT

IN

IN

NC
NC

IN

OUT

IN

OUT

SYM_VER-2

SYM_VER-2

IN

IN

OUT

OUT

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NC

AUD_RAMP_MONO NET:
HIGH = MONO OPERATION

RIGHT CH SPEAKER AMP

ONLY WOOFERS ON UNDER WINDOWS

APPLE P/N 353S3163

SPEAKER AMP GAIN = +9 DB
SPEAKER AMP RIN = 40K NOMINAL
FC_HPF, TWEETERS = ~847 HZ (4700 PF)

EDGE RATE
ON 0 OHM NOSTUFF

OFF NOSTUFF 0 OHM

LOW = STEREO OPERATION

+15 DB 0 OHM NOSTUFF

+12 DB NOSTUFF NOSTUFF

FC_HPF, WOOFERS = ~18 HZ (0.22 UF)

+18 DB NOSTUFF 47 KOHM

PINS 14 & 15 ARE TEST PINS AND
SHOULD BE TIED TO GND

CONTROL R6404 R6405

OUTPUT POLARITY FLIP TO
MAKE LAYOUT MORE LOGICAL

GAIN R6406 R6407

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

+24 DB 47 KOHM NOSTUFF

+9 DB NOSTUFF 0 OHM

WOOFERS & TWEETERS ON UNDER MAC OS

6

54

CRITICAL

SIGNAL_MODEL=EMPTY

402

1000PF

5%
25V
NP0-C0G

CRITICAL

25V
NP0-C0G
402

1000PF

5%

SIGNAL_MODEL=EMPTY

CRITICAL

NP0-C0G

5%

402

25V

SIGNAL_MODEL=EMPTY

1000PF 1000PF

5%

25V

NP0-C0G

402

CRITICAL

SIGNAL_MODEL=EMPTY

603

20%

0.22UF

25V
X5R

52 53 59

52 59

20%
25V

0.22UF

X5R
603

X5R

20%
25V

603

0.22UF

X5R

0.22UF

25V

20%

603

CRITICAL

SSM3302

LFCSP

55

20%
10V

X5R-CERM

402

2.2UF

54

54

10UF

25V
X5R
805

10%

16V

0.22UF

CERM

402

10%

0.22UF

CERM

10%
16V

402

4700PF

NPO-C0G

5%

805

50V

4700PF

805

50V

5%

NPO-C0G

1/16W

0

402

MF-LF

5%

5%

0

402

1/16W
MF-LF

NOSTUFF

55 55

MF-LF

5%

0

402

1/16W

55

0

5%
MF-LF

402

NOSTUFF

1/16W

MF-LF

1/16W
402

0

5%

55

10%
X5R

25V
805

10UF

55

SIGNAL_MODEL=EMPTY
CRITICAL

402

5%
25V
NP0-C0G

1000PF

5%
25V
NP0-C0G

CRITICAL

1000PF

402

SIGNAL_MODEL=EMPTY

20%

470UF

SM

POLY

16V

CRITICAL

55

55

55

55

SIGNAL_MODEL=EMPTY

CRITICAL

110-OHM-3A

DLY5ATN111SQ2

DLY5ATN111SQ2

CRITICAL

SIGNAL_MODEL=EMPTY

110-OHM-3A

FERR-1000-OHM

0402

0.1UF

10%
X5R

402

25V

0402

FERR-1000-OHM

FERR-1000-OHM

0402

0402

FERR-1000-OHM

X5R
402

25V

10%

0.1UF

603-1

25V
X5R

10%

1UF

25V

10%

603-1

X5R

1UF

52 59

52 53 59

57 59

57 59

57 59

57 59

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_BREECE

AUDIO: RIGHT SPKR AMP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BOOTLN

AUD_RAMP_MONO

=PP12V_S0_AUDIO_SPKRAMP

AUD_RAMP_LINC_P

AUD_RAMP_LIN_P

MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTPR

MIN_LINE_WIDTH=0.6MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTNR

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BOOTLP

AUD_LO2_R_N

MIN_NECK_WIDTH=0.15MM

AUD_RAMP_BOOTRN

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_RINC_P

AUD_RAMP_GAIN

AUD_RAMP_AVDD

AUD_RAMP_MONOAUD_RAMP_EDGE

TP_AUD_RAMP_THERM

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

AUD_RAMP_BOOTRP

AUD_RAMP_EDGE

AUD_RAMP_AVDD

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

AUD_SPKRAMP_WIN_SHDN_L

AUD_SPKRAMP_MAC_SHDN_L

AUD_RAMP_RIN_P

AUD_RAMP_RINC_N

AUD_RAMP_LINC_N

AUD_LO2_R_P

AUD_LO1_R_N

AUD_LO1_R_P

AUD_RAMP_RIN_N

=PP3V3_S0_AUDIO

AUD_RAMP_LIN_N

AUD_RAMP_GAIN

AUD_SPKR_RWFR_OUT_N

AUD_RAMP_OUTPR

AUD_SPKR_RWFR_OUT_P

AUD_RAMP_OUTNR

AUD_SPKR_RTWT_OUT_N

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTNL

AUD_SPKR_RTWT_OUT_P

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_OUTPL

C6404

1

2

C6402

1

2

C6415

1 2

C6416

1 2

C6413

1 2

C6414

1 2

C6400

1

2

L6400

1 2

L6401

1 2

L6402

1 2

L6403

1 2

C6403

1

2

C6405

1

2

C6421

1

2

C6419

1

2

C6420

1

2

C6422

1

2

U6400

7

24

6

1

25

30

10

21

12

11

19

20

16

13

14

15

18

4

5

2

3

26

27

28

29

3132333839

40

343536

37

23

9

22

17

41

8

C6417

1

2

C6401

1

2

C6408

1 2

C6409

1 2

C6410

1 2

C6411

1 2

R6404

1

2

R6405

1

2

R6403

1

2

R6406

1

2

R6407

1

2

C6423

1

2

C6424

1

2

C6406

1

2

L6405

1 2

34

L6407

1 2

34

051-9509

4.2.0

64 OF 113
55 OF 100

59 59

59

55

55

59

59

59

59

6

40 52 54 58

59

OUT

OUT

IN

BI

OUT

IN

IN

CS

HDET

ENABLE

INT*

SDA

SCL

AGND

MICBIAS

DETECT

BYPASS

AVDD

DGND

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

I2C PULLUPS ON SOUTHBRIDGE PAGE

(SEE RADAR # 6210118)

MIKEY 1A
APN:353S2640
MIKEY ADDRESS: WRITE=72H, READ=73H

PORT B LEFT(HEADSET MIC)

MIKEY U6751 READ 0111 0011 0X73
MIKEY U6751 WRITE 0111 0010 0X72

CHS U6750 WRITE 0111 0110 0X76

I2C ADDRESSES

APN 353S2640

PLACE XWS 6500 & 6501 AT J6500 PINS

CHS U6750 READ 0111 0111 0X77

AUDIO JACK: HP CONNECTOR WITH MIKEY

WRITE: 0X72 READ: 0X73

MIKEY RECEIVER CKT

HP=80HZ, LP=10.63KHZ

NOISE ISSUE SEEN ON EARLY HEADSETS

R/C6750 FILTER TO ADDRESS OUT-OF-BAND

52 59

52 59

47

47

20

26

58

1/16W

5%

MF-LF

47K

402

NOSTUFF

MQFN-RSV

CRITICAL

CD3285A0

10%

402

X7R-CERM

0.1UF

16V

201

1/20W

MF

100K

5%

MF-LF

2.2K

402

1/16W

5%

0.0082UF

402

25V
X7R

10%

CRITICAL

50V

5%

402

CERM

27PF

CRITICAL

0.1UF

402

16V

10%

X7R-CERM

1/16W
MF-LF

402

5%

1K

SIGNAL_MODEL=EMPTY

0.01UF

25V
402

X7R

10%

X7R-CERM
402

16V

10%

0.1UF

0402

10V

X5R-CERM

20%

4.7UF

CRITICAL

56

56 59

56 59

FERR-1000-OHM

0402

52 56 58 59

58

0402

FERR-1000-OHM

0402

FERR-1000-OHM

58

56 59

0402

FERR-1000-OHM

0402

FERR-1000-OHM

58

1/16W

0

402

5%

MF-LF

SIGNAL_MODEL=EMPTY

402

MF-LF

1/16W

NOSTUFF

5%

1K

54722-0224

F-ST-SM

SIGNAL_MODEL=EMPTY

0402

CRITICAL

FERR-120-OHM-2.0A

52 92

FERR-1000-OHM

0402

FERR-120-OHM-2.0A

0402

CRITICAL

53

47

CRITICAL

FERR-120-OHM-2.0A

0402

FERR-120-OHM-2.0A

CRITICAL

0402

47

53

53

56

56 59

0

MF-LF

1/16W

402

5%

10K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

AUDIO: Jack, Mikey, CHS Switch

SYNC_MASTER=D7_BREECE

SYNC_DATE=01/03/2012

=I2C_MIKEY_SDA

AUD_IPHS_SWITCH_EN

=PP3V3_S0_AUDIO_DIG

HS_HDET

AUD_J1_HP_PORT_REF

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_HP_OUTR

=I2C_CHS_SDA

GND_AUDIO_CODEC

AUD_TIPDET1_R

MAX97220_OUTR

=I2C_CHS_SCL

MIN_NECK_WIDTH=0.20MM

HS_MIC_BIAS

MIN_LINE_WIDTH=0.25MM

AUD_MIC_INL_P

PP4V5_AUDIO_ANALOG

AUD_MIC_INL_N

AUD_PORTD_DET_L

AUD_HS_MIC_RC_P

HS_SW_DET

GND_AUDIO_CODEC

AUD_HS_MIC_N

GND_AUDIO_CODEC

AUD_HS_MIC_RC_N

AUD_SPDIF_OUT

AUD_TYPEDET_R

=PP3V3_S0_AUDIO_DIG

AUD_TIPDET2_R

MAX97220_OUTL

AUD_HP_PORT_REF

HS_MIC_BIAS

AUD_HS_MIC_P

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_PP3V3_S0

AUD_J1_TIPDET2_R AUD_J1_TIPDET1_R

AUD_J1_GND_ANALOG

MIN_LINE_WIDTH=0.50MM
VOLTAGE=0V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

AUD_J1_HP_OUTL

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_MIC_BIAS

AUD_J1_MIC_P

AUD_HS_MIC_N

AUD_J1_TYPEDET_R
AUD_J1_MIC_N

AUD_HS_MIC_P

HS_RX_BP

=I2C_MIKEY_SCL

AUD_I2C_INT_L

R6561

1 2

U6551

7

8

12

14

15

9

16

11

5

6

1

13

4

10

3

2

C6552

12

R6556

1

2

R6550

1 2

C6550

1

2

C6558

1

2

C6553

12

R6554

1

2

C6556

1

2

C6560

1

2

C6555

1

2

L6505

1 2

L6501

1 2

L6500

1 2

L6510

1 2

L6508

1 2

R6551

1 2

R6553

1

2

J6500

1

10
11 12
13 14
15 16
17 18
19

2

20
21 22

3 4
5 6
7 8
9

L6507

1 2

L6502

1 2

L6509

1 2

L6504

1 2

L6503

1 2

R6506

1 2

R6562

1

2

R6555

1

2

051-9509

4.2.0

65 OF 113
56 OF 100

6

56

52 58

59

52 56 58 59

52 56 58 59

59

6

56

59

59

OUT

IN

IN

IN
IN

OUT

IN
IN

IN
IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SPEAKER CABLE CONNECTORS

WOOFER (BL)

APPLE P/N 998-4119

WOOFER (BR)

TWEETER (FR)TWEETER (FL)

APPLE P/N 998-4119

59

54 59

54 59

54 59

54 59

59

55 59

55 59

55 59

55 59

504050-0691

CRITICAL

M-RT-SMM-RT-SM

504050-0691

CRITICAL

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_BREECE

Audio: Spkr/Mic Conn.

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LTWT_OUT_P
AUD_SPKR_LTWT_OUT_N

AUD_SPKR_RWFR_OUT_P
AUD_SPKR_RWFR_OUT_N
AUD_SPKR_VENDOR_ID_R

AUD_SPKR_RTWT_OUT_P
AUD_SPKR_RTWT_OUT_N

AUD_SPKR_VENDOR_ID_L

J6602

7

8

1
2
3
4
5
6

J6603

7

8

1
2
3
4
5
6

051-9509

4.2.0

66 OF 113
57 OF 100

OUT

IN

NC

IN

OUT

IN

OUT

IN

IN

OUT

D

SG

D

SG

D

SG

D

SG

D

S

G

N-CHN

G

D

S

P-CHN

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

PLACE C6700 CLOSE TO Q6700 PIN 4

PORT D DETECT (HEADPHONES)

AUD_J1_TYPEDET_R 1 1 0

AUD_OUTJACK_INSERT_L 1 0 0

TBT/DP Audio Enable

NC

PORT B DETECT(SPDIF DELEGATE)

NOTHING SPDIF HEADPHONE

AUD_J1_TIPDET_R 0 1 1

AUDIO CONNECTOR DETECT STATES

NC

(DETECT A)

LI Insert Detect

IPHS HS Detect Debounce CKT

APN:376S1032

20

5%

1/16W

402

MF-LF

0

NOSTUFF

10%

0.1UF

16V
402

X5R

52 58 59

201

1/20W

MF

5%

100K

0402

FERR-1000-OHM

56

52 58 59

402

1/16W
MF-LF

5%

47K

0.1UF

402

10V

20%
CERM

20.0K

1%
1/16W
MF-LF
402

201

1/20W

MF

10K

5%

FERR-1000-OHM

0402

21 82

56

1/16W

5.11K

MF-LF
402

1%

1/16W
402

MF-LF

39.2K

1%

56

58

58

SSM6N15AFE

SOT563

SSM6N15AFE

SOT563

SSM6N15AFE

SOT563

SOT563

SSM6N15AFE

SOT563

DMC2400UV

SOT563

DMC2400UV

56

270K

201

MF

1/20W

5%

201

MF

1/20W

5%

100K

100K

1/20W
201

5%
MF

0.1UF

16V
402

X7R-CERM

10%

SSM6N15AFE

SOT563

SSM6N15AFE

SOT563

SSM6N15AFE

SOT563

SOT-563-HF

NTZD3152P

SOT-563-HF

NTZD3152P

47K

5%

1/20W

MF

201

201

MF

1/20W

5%

47K

100K

5%

1/20W

MF

201

47K

5%

1/20W

MF

201

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_BREECE

AUDIO: Detects/Grounding

AUD_PORTD_DET_L

AUD_OUTJACK_INSERT_L

AUD_TYPEDET_OD

AUD_TYPEDET_OD_INV

AUD_OUTJACK_INSERT

AUD_TIPDET1_R

AUD_TIPDET2_R

AUD_IP_PERPH_DET_R

AUD_J1_DET_RC

AUD_IP_PERPH_DET_DB

AUD_SENSE_A

AUD_IP_PERIPHERAL_DET

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_PORTB_DET_L

GND_AUDIO_CODEC

AUD_PORTA_DET_L

AUD_LI_TIPDET

AUD_J1_DET_RC

GND_AUDIO_CODEC

AUD_TYPEDET_R

DP_GPU_TBT_SEL

AUD_SENSE_A

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

AUD_TIPDET_INV

PP4V5_AUDIO_ANALOG

R6745

1 2

C6741

1

2

R6744

1

2

L6743

1 2

R6792

1 2

C6791

1

2

R6796

1

2

R6730

1

2

L6732

1 2

R6795

1

2

R6731

1

2

Q6797

3

5

4

Q6796

3

5

4

Q6741

3

5

4

Q6741

6

2

1

Q6700

6

2

1

Q6700

3

5

4

R6701

1

2

R6702

1

2

R6703

1

2

C6700

1

2

Q6797

6

2

1

Q6796

6

2

1

Q6800

3

5

4

Q6740

6

2

1

Q6740

3

5

4

R6741

1

2

R6742

1

2

R6791

1

2

R6743

1

2

051-9509

4.2.0

67 OF 113
58 OF 100

6

40 52 54 55

52 56 58 59

52 56 58 59

52 56 58 59

52 56 58 59

52 56 58

52 56 58

OUT

IN IN

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0x10 (16)

PIN COMPLEX

0X0A (DET D)GPIO_2

MAC SHDN

CODEC OUTPUT SIGNAL PATHS

0X03 (3)

DET ASSIGNMENT

0X09 (DET A)

DET ASSIGNMENT

PANTHER POINT GPIO 3 (PERIPH DET)

0X0D (DET B)

0X0D (13,V22,B,LEFT)

CONVERTER

ENABLE/CONTROL

0X0C (DET C)

PANTHER POINT GPIO 5 (RCVR INT)

N/A

PORT C DETECT(SPEAKER MISMATCH)

ENABLE/CONTROL

N/A

N/A

DET ASSIGNMENT

CONVERTER

0X0B (11)

WIN SHDN

0X12 (18,LEFT)

0X06 (6)

N/A

0X0E (14,LEFT & RIGHT)

MICBIAS

0X0A (10,D)

PIN COMPLEX

PANTHER POINT GPIO 16

SECONDARY SPKRS (TWT)

FUNCTION

GPIO_2

N/A

MICBIAS

N/A N/A

0X05 (5)
0X06 (6)

0x0F (15)

0X0A (10,V24)

PRIMARY SPKRS (WFR)

0X03 (3)

GPIO_3

0X04 (4)

CODEC INPUT SIGNAL PATHS

0X08 (8)

0X03 (3)0X03 (3)

SPDIF OUT

HP/LINE OUT

MULTIPLE SPKR VENDORS

FUNCTION

N/A

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

N/A

FUNCTION

INTERNAL MIC ARRAY

SPDIF IN

N/A

CONVERTER

EXTERNAL MIC

OTHER DETECT

0X07 (7)

PIN COMPLEX

N/A

0X04 (4)

VOLUME/MUTE

N/A

NC

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I215

I216

I217
I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I236

I237

I238

I239

I240
I241

I242
I243

I244

I245

I246

I247

I254

I255

I263

I264

402

MF-LF

1/16W

1%

100K

SPEAKERID

1/16W
402

1%
MF-LF

100K

SPEAKERID

1/16W

SPEAKERID

1%

100K

402

MF-LF

100K

1/16W
MF-LF

1%

SPEAKERID

402

SPEAKERID

MF-LF

402

1/16W

1%

100K

52 58

SPEAKERID

SC70-5

CRITICAL

MAX9119EXK-T

57 57

FERR-1000-OHM

0402

SPEAKERID

SPEAKERID

5%

1/16W

33

MF-LF

402

16V

10%
X7R-CERM

402

SPEAKERID

0.1UF

1%

1/16W

10K

402

MF-LF

SPEAKERID

SPEAKERID

16V
X7R-CERM
805

2.2UF

10%

SPEAKERID

75K

1%
1/16W
MF-LF

402

SPEAKERID

MF-LF

1/16W

402

37.4K

1%

SPEAKERID

226K

1%
1/16W
MF-LF

402

I324
I325

I326

I327
I328

I329

SSM6N15AFE

SOT563

SPKROUTDIFF

0.2 MM

0.6 MM

0.25 MM

0.2 MM

10 MM

Y

*

0.1 MM 0.1 MM

0.1 MM

10 MM

0.1 MM

*

Y

AUDIODIFF

SPKROUTDIFF

*

SPKROUTDIFF

AUDIO

0.1 MM

*

?
?

*

SPKROUT

0.2 MM

AUDIODIFF

*

AUDIODIFF

AUDIO: Speaker ID

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_BREECE

AUD_PORTC_DET_L

GND_AUDIO_CODEC

AUD_MIC_INL_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_HS_MIC_RC_N

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_HS_MIC_N

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUDIODIFF

AUD_HS_MIC_P

AUDIO_DIFFPAIR

AUDIO

AUD_HS_MIC_RC_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_J1_MIC_P

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_J1_MIC_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_MIC_INL_N

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

SPKROUT_DIFFPAIR

SPKROUTDIFF

SPKROUT

AUD_SPKR_LWFR_OUT_N

SPKROUT_DIFFPAIR

SPKROUTDIFF

SPKROUT

AUD_SPKR_RTWT_OUT_N

SPKROUTDIFF

AUD_SPKR_LTWT_OUT_P

SPKROUT

SPKROUT_DIFFPAIR

SPKROUTDIFF

SPKROUT

SPKROUT_DIFFPAIR

AUD_SPKR_LTWT_OUT_N

SPKROUT_DIFFPAIR

SPKROUTDIFF

SPKROUT

AUD_SPKR_LWFR_OUT_P

SPKROUT_DIFFPAIR

SPKROUTDIFF

AUD_SPKR_RTWT_OUT_P

SPKROUT

SPKROUTDIFF

AUD_SPKR_RWFR_OUT_N

SPKROUT

SPKROUT_DIFFPAIR

AUD_SPKR_RWFR_OUT_P

SPKROUTDIFF

SPKROUT

SPKROUT_DIFFPAIR

MAX97220_INR_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

MAX97220_INL_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LAMP_LIN_N

AUDIO

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LAMP_RIN_P

AUDIO_DIFFPAIR

AUD_LAMP_RINC_N

AUDIO

AUDIODIFF

AUD_LAMP_RINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIO_DIFFPAIR

AUD_LAMP_LINC_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_RAMP_RIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_RIN_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_RAMP_LIN_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_LIN_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_RINC_N

AUDIODIFF

AUDIO

MAX9119_POS

AUD_SPKR_VENDOR_ID_RAUD_SPKR_VENDOR_ID_L

MAX9119_NEG

MAX9119_OUT

=PP5V_S0_AUDIO

MAX97220_INR_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_RAMP_LINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_RAMP_LINC_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LAMP_RIN_N

AUDIO

AUD_LO2_R_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO2_R_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO2_L_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO2_L_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_C_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_L_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO1_L_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO1_R_C_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_L_C_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_L_C_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_RAMP_RINC_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUDIO_DIFFPAIR

AUDIODIFF

AUD_LAMP_LIN_P

AUDIO

AUDIODIFF

AUD_LAMP_LINC_N

AUDIO

AUDIO_DIFFPAIR

MAX97220_INL_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

SPKR_MATCH_DRV_R

=PP5V_S0_AUDIO

AUD_SENSE_A

=PP5V_S0_AUDIO

SPKR_MATCH_DRV

R6812

1

2

R6813

1

2

R6810

1

2

R6811

1

2

R6816

1 2

U6800

3

4

1

5

2

L6802

1 2

R6820

1 2

C6810

1

2

R6894

1

2

C6811

1

2

R6815

1

2

R6817

1 2

R6814

1

2

Q6800

6

2

1

051-9509

4.2.0

68 OF 113
59 OF 100

52 56 58

52 56

56

56

56

56

56

56

52 56

54 57

55 57

54 57

54 57

54 57

55 57

55 57

55 57

53

53

54

54

54

54

54

55

55

55

55

55

6

52 59

53

55

55

54

52 55

52 55

52 54

52 54

53

52 53 54

52 53 54

53

52 53 55

52 53 55

53

53

55

54

54

53

6

52 59

6

52 59

OUT

OUT

08

IN

08

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

08

IN

IN

OUT

IN

OUT

IN

IN

08

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

D

G S

OUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Notes on sequencing requirements

2. IFPA/B_IOVDD (1.8 V) can ramp simultaneously or after 3V3_S0 (unused)

6. All rails must reach their target voltages in more than 40 uS

VccSA, VDDQ, VccA (1.8 V), VccIO (VccSA, VccA, and VccIO must ramp within 50 ms of each other)

Rail definitions

S0 Enables

Note:

Halt power sequencing at S5
if there is no processor.
Remove Q6900 to circumvent

S4 Enables

0.0

4. VDDQ must ramp after CPU_CORE

Intel:

Platform:
Uncore:

NVIDIA:

1. 3V3_S0 must ramp first

2. SMC guarantees timing on PCH DPWROK and PWROK

1. No hard specification on platform rails

3. NVVDD (GPU_CORE) must ramp after IFPA/B_IOVDD

S3 VDDQ Enable

S4 USB Enable

S5 Soft Enable

5. PEX_VDD with IFPC/D/E/F_IOVDD (1.05V) must ramp after VDDQ

All processor non-Core and non-Graphics (5 V, 3.3 V, 1.8 V 1.5 V, PCH Core/PLL/VRM)

tau (RC delay, ms):

0.0

or short gate to source.

CPU/PCH Sequencing

GPU Sequencing

MF-LF

1/16W

5%

68K

402

33K

1/16W

5%
MF-LF

402

67

0.1UF

16V
X5R

10%

402

70

402

CERM-X5R

NOSTUFF

0.47UF

6.3V

10%

CERM-X5R
402

6.3V

0.47UF

10%

NOSTUFF

TSSOP-HF

74LVC08

1/16W

33K

MF-LF

5%

402

NOSTUFF

6.3V

CERM-X5R

10%

402

0.47UF

70

74LVC08

TSSOP-HF

15 19 44

60 67

68

402

1/16W
MF-LF

5%

0

60 67 42 43

402

NOSTUFF

0.47UF

CERM-X5R

6.3V

10%

MF-LF

5%

33

1/16W
402

MF-LF

5%
1/16W

33

402

67

80

70

74LVC08

TSSOP-HF

68

15 19 28 38 44 45

62

0

5%

MF-LF

1/16W

402

61 66

1/16W
MF-LF

402

100

5%

70

15 19 33 44

11

5%

10K

402

MF-LF

1/16W

5%

MF-LF

1/16W

402

100K

PLACE_SIDE=BOTTOM

74LVC08

TSSOP-HF

84 85

402

0

5%

MF-LF

1/16W

60 70 68

5%

0

1/16W
MF-LF

402

60 70

70

5%

402

0

1/16W
MF-LF

68

65

MF-LF

1/16W

5%

0

402

28 70

66

1/16W
MF-LF

5%

0

402

65

SSM3K15AMFVAPE

VESM

PLACE_SIDE=BOTTOM

40

74

MF-LF

5%

0

402

1/16W

80

74

0

5%

MF-LF

402

1/16W

74

41 70

1/16W
MF-LF

5%

0

402

70

68 28

SYNC_DATE=12/13/2011

PM Regulator Enables

SYNC_MASTER=D7_NICK

PM_EN_LDO_DDRVTT_S0

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PM_EN_FET_P5V_S0

MAKE_BASE=TRUE

PM_EN_FET_VDDQ_S0

=TBT_S0_EN

PM_EN_REG_VCCSA_S0

PM_PGOOD_REG_GPU_VDDQ_S0

=PM_EN_REG_P1V2_S0

PM_EN_REG_CPUCORE_S0

PM_PGOOD_REG_GPUCORE_S0

PM_EN_REG_GPU_P1V05_S0

PM_EN_REG_GPU_VDDQ_S0

PM_PGOOD_REG_VCCSA_S0

PM_PGOOD_REG_P1V05_S0

PM_PGOOD_FET_VDDQ_S0

CPU_SKTOCC_L

CPU_SKTOCC

=PP3V3_S5_PWRCTL

PM_EN_REG_P3V3_S5

=PP12V_S5_PWRCTL

PM_EN_USB_PWR

PM_PGOOD_REG_P5V_S4

PM_SLP_S4_L

=PP3V3_S5_PWRCTL

PM_EN_S4

=PP3V3_S5_PWRCTL

PM_EN_REG_P5V_S4

PM_EN_FET_P3V3_S4

PM_SLP_S5_L

=PP3V3_S5_PWRCTL

PM_SLP_S3_L

=PP3V3_S5_PWRCTL

PU_U6900

PM_PGOOD_FET_P12V_S0

PM_EN_S0_R

PM_EN_FET_P12V_S0

PM_PGOOD_FET_P3V3_S0 PM_EN_REG_GPUCORE_S0

PM_EN_FET_P3V3_S0

PM_PGOOD_FET_P5V_S0

PM_PGOOD_FET_P3V3_S0

PM_EN_REG_P1V05_S0

PM_PGOOD_REG_P1V8_S0

PM_PGOOD_REG_P5V_S4

PM_EN_REG_VDDQ_S3

PM_PGOOD_REG_VDDQ_S3

MEMVTT_EN

PM_EN_REG_P1V8_S0

R6990

1

2

R6991

1

2

C6900

1

2

C6910

1

2

C6911

1

2

U6900

7

13

12

11

14

R6902

1

2

C6901

1

2

U6900

7

4

5

6

14

R6920

1 2

C6920

1

2

R6910

1

2

R6911

1

2

U6900

7

10

9

8

14

R6936

1 2

R6930

1 2

R6901

1

2

R6900

1

2

U6900

7

1

2

3

14

R6937

1 2

R6932

1 2

R6933

1 2

R6934

1 2

R6935

1 2

Q6900

3

1

2

R6938

1 2

R6939

1 2

R6931

1 2

051-9509

4.2.0

69 OF 113
60 OF 100

6

60 61 70 78

6

61 70

6

60 61 70 78

6

60 61 70 78

6

60 61 70 78

6

60 61 70 78

IN

IN

OUT

OUT

IN

IN

IN

OUT

OUT

IN

OUT

OUT

08

IN

IN

OUT

08

08

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

First

Second

Third

To PCH

To PCH

To PCH

Platform and UnCore Power Good

Note: GPU power goods are implicitly included because the power goods for VDDQ, DPVDDC, and GPU Core are wired-or together

to meet Intel spec.

RSMRST# is asserted when power good from regulator is de-asserted in the

To PCH

From SMC

To SMC

To SMC

SMC de-asserts RSMRST# (PM_DSW_PWRGD) when S5_PWRGD input is asserted and

SMC asserts RSMRST# (PM_DSW_PWRGD) when SMC_S5_PWRGD_VIN input drops from

1.8 V to 1.5 V (as implemented) when 12 V S5 rail drops to 10 V.

Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V

Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8

Intel Doc# 29517 Maho Bay PDG, Section 22.13

RSMRST# signals are shorted together

Asserted at least 10 ms after all suspend well power is valid

Primary method:

normal operation.

Power off or loss of AC:

Power on:

Resume Reset

Requirements:

Note:

Derive SMC ALL_SYS_PWRGD

From SMC

To PCH

Secondary method:

event AC is lost. Power good de-assertion should happen quickly enough

normal operation via PM_DSW_PWRGD.

The SMC guarantees proper assertion and de-assertion of RSMRST# for

To SMC, for 99ms delay

The iMac K70K72 designs does not support Deep Sx modes so both DPWROK and

to allow PCH to switch suspend well to battery without excessive loading

The SMC guarantees proper assertion and de-assertion of RSMRST# for

SMC_S5_PWRGD_VIN input is above comparator input level of 1.5 V.

PCH Power Goods

25 62

36 44 45

5%

MF-LF

402

0

1/16W

5%

0

1/16W

402

MF-LF

NOSTUFF

0

MF-LF

1/16W

5%

402

402

MF-LF

1/16W

5%

0

NOSTUFF

19 45

44 61 67

10%

402

0.1UF

X5R

16V

44 45 61

61 67

44

MF-LF

1/16W

5%

68K

402

RSMRST:SMC

RSMRST:SMC

402

MF-LF

5%
1/16W

33K

19 61 44 45 61

RSMRST:SMC

MF-LF

1/16W

5%

402

0

5

44

19 61

MF-LF

1/16W

402

0

5%

RSMRST:GATE

PLACE_SIDE=BOTTOM

74LVC08

TSSOP-HF

74

60 66

40

TSSOP-HF

74LVC08

PLACE_SIDE=BOTTOM

TSSOP-HF

74LVC08

PLACE_SIDE=BOTTOM

19 26

402

1K

1/16W
MF-LF

5%

19

16V

10%

402

0.1UF

X5R

SYNC_MASTER=D7_NICK

SYNC_DATE=12/13/2011

PM Power Good

=PP3V3_S5_PWRCTL

PM_DSW_PWRGD

S5_PWRGD

SMC_S5_PWRGD_VIN

PM_RSMRST_PCH_L

=PP12V_S5_PWRCTL

PM_RSMRST_PCH_L

=PP3V3_S5_PWRCTL

PM_RSMRST_PCH_L_R

PM_PGOOD_REG_P3V3_S5

PM_DSW_PWRGD

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD

PM_PGOOD_REG_P1V05_GPU

PM_PGOOD_REG_VCCSA_S0

PM_PGOOD_REG_CPUCORE_S0

SYS_PWROK_R

SMC_DELAYED_PWRGD

=CAM_RESET_L

PM_PCH_PWROK

PM_PCH_SYS_PWROK

PM_PCH_APWROK

MAKE_BASE=TRUE

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

C7000

1

2

R7021

1 2

R7020

1 2

R7023

1

2

R7022

1 2

C7021

1

2

R7030

1

2

R7031

1

2

R7032

1 2

R7035

1 2

U7000

7

13

12

11

14

U7000

7

4

5

6

14

U7000

7

1

2

3

14

R7024

1 2

051-9509

4.2.0

70 OF 113
61 OF 100

6

60 61 70 78

6

60 70

6

60 61 70 78

6

60 61 70 78

VR_RDYS

IMONS

FS_DRP

VCC

ISEN1+

PWM1

ISEN1-

PWM2
ISEN2+
ISEN2-

PWM3

ISEN3-

ISEN3+

TMS

ISEN4-

ISEN4+

PWM4

FSS_DRPS

EN_VTT

RSET

VSENS

RAMP_ADJ

FBS

RGNDS

VR_RDY

COMPS

SVCLK

SVDATA

SVALERT*

VSEN

FB

RGND

PSICOMP

COMP

IMON

VR_HOT*
TM

THRM

ISENS-

ISENS+

PWMS

HFCOMPS/DVCS

EN_PWR

ADDR_IMAXS_TMAX

NPSI_DE_IMAX

BT_FDVID_TCOMP

BTS_DES_TCOMPS

SICI

HFCOMP

PAD

IN

IN

OUT

IN

BI

NC

OUT

OUT

OUT

NC

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(straps 1)

(axg vsen in)

Core sense from CPU

AXG sense from CPU

CPU Core S0 Regulator

Core compensation and feedback

? A (design)/ 30 A (budget)

? A (design)/ 10 A (budget)

? A (design)/75.05 A (budget)

? A (design)/ 41.05 A (budget)

AXG voltage sense input

Core voltage sense input

To XDP

AXG temp measurement

To Core voltage sense

AXG IMON output

To sense amps

290 kHz

? A (nom)/? A (min)

(pgood)

To sense amps

To AXG VSense

(axg fb in)

Core IMON output

(straps 2)

OC trip point:

Max avg current:
Max peak current:

(pu 2)

(pu 2)

(pu 2)

(pu 2)

(pu 2)

Pull-ups 1 Pull-ups 2

? A (nom)/? A (min)

CPU AXG S0 Regulator

(pgood)

(pu 1)

(core fb in)
(core psi comp)

(axg hf comp)

(straps 1)

(straps 1)

(axg comp out)

(vr hot out)

(core hf comp)

(pu 1)

(core imon out)

(straps 2)

To AXG HF comp

Straps 2

290 kHz

To Core VSense

To Core feedback

To Core HF comp

To Core PSI comp

Switching freq:

Max avg current:
Max peak current:
OC trip point:

(pu 1)

(core vsen in)

(straps 1)

(straps 2)

Straps 1

(core comp out)

Core temp measurement

VRHot to ProcHot

To AXG voltage sense

(axg imon out)

AXG compensation and feedback

Switching freq:

Power goods

To AXG feedback

ISL6364

QFN

64 96

13 96

0

5%
1/16W
MF-LF

402

1/16W

0

5%
MF-LF

402

L7330.2:10MM

SM

OMIT

5%

1K

402

1/16W
MF-LF

10

5%
1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

MF-LF

402

5%
1/16W

10

SIGNAL_MODEL=EMPTY

402

CERM

50V

10%

0.0012UF

0.0012UF

10%
CERM

402

50V

NOSTUFF

402

50V

0.0012UF

CERM

10%

MF-LF

5%

1K

402

1/16W

402

MF-LF

1/16W

1%

2.26K

10%
X7R-CERM

0.001UF

0402

50V

8.06K

1%

402

MF-LF

1/16W

50V
CERM

5%

402

39PF

50V
402

CERM

10%

390PF

1/16W

1%

249

402

MF-LF

2.0K

402

MF-LF

1%
1/16W

1%
MF-LF

402

301

1/16W

MF-LF

10

402

1%

1/16W

0.01UF

402

20%
16V

NOSTUFF

CERM

OMIT

U7100.49:1MM

SM

0603

6.8K

16V

10%
X5R

402

0.1UF

1K

402

MF-LF

5%

1/16W

1/16W
MF-LF

402

5%

1K

X5R

10%

402

0.1UF

16V

6.8K

0603

805

1/8W

2.2

5%
MF-LF

25V

10UF

X5R
805

10%

201

1/20W
MF

1%

17.8K

201

1/20W
MF

255K

1%

201

1/20W
MF

1%

953K

MF

1%

23.2K

1/20W
201 201

MF

1%
1/20W

49.9K

1%
MF

1/20W
201

953K

13 62 96

13 62 96

13 62 96

5%

0

402

MF-LF

1/16W

201

MF

255K

1%
1/20W

MF

1%

12.4K

1/20W
201

10%
16V

0.1UF

402

X5R

2.74K

1/16W
MF-LF

1%

402

402

1/16W

6.65K

1%
MF-LF

1%

110

1/16W
MF-LF
402

1%

402

MF-LF

1/16W

NOSTUFF

90.9

1%

54.9

MF-LF
402

1/16W

402

10%
16V
X5R

0.1UF

0

1/16W
MF-LF

402

5%

11 44 45

48 62 96

48 62 96

1/16W

1K

5%
MF-LF

402

10K

MF-LF

1/16W

5%

402

25 61

402

MF-LF

1/16W

5%

0

MF-LF

0

402

1/16W

5%

402

MF-LF

1/16W

5%

0

402

MF-LF

1/16W

5%

0

64 96

63 96

63 96

63 96

MF-LF

0

1/16W
402

5%

NOSTUFF

63 96

MF-LF

1/16W

NOSTUFF

0

5%

402

0

5%

402

MF-LF

1/16W

NOSTUFF

0

5%
1/16W
MF-LF
402

NOSTUFF

0

5%
1/16W
MF-LF
402

60

63 96

1/16W

1%

402

1.18M

MF

201

1/20W
MF

5%

0

NOSTUFF

201

1/20W
MF

NOSTUFF

5%

0

12.1K

MF-LF
402

1/16W

1%

201

1/20W
MF

1%

105K

201

1/20W
MF

1%

124K

63 96

201

1/20W
MF

5%

NOSTUFF

10K

CERM-X7R

0.082UF

402

10%
16V

1/16W
MF-LF

402

1%

90.9

15.4K

1/16W
MF-LF

402

1%

1/16W

NOSTUFF

MF-LF

402

100K

5%

NOSTUFF

100K

MF-LF

5%

402

1/16W

CERM-X7R

0.082UF

10%

402

16V

MF-LF

402

0

1/16W

5%

1/16W

402

1%

12.4K

MF-LF

63 96

402

1/16W
MF-LF

100K

5%

63 96

0.0012UF

50V

10%
CERM

402

402

1%
MF-LF

1/16W

4.99K

82PF

50V

5%
CERM

402

249

1%
1/16W

402

MF-LF

1.21K

1/16W

1%

402

MF-LF

402

50V
CERM

390PF

10%

402

1%
1/16W
MF-LF

499

1%

1/16W

100

402

MF-LF

0.0033UF

402

CERM

10%
50V

402

MF-LF

10

1%

1/16W

63 96

1%

1.74K

1/16W
MF-LF

402

402

CERM

16V

20%

0.01UF

MF-LF

1/16W

402

5%

0

SIGNAL_MODEL=EMPTY

10

MF-LF

1/16W

5%

402

1K

402

MF-LF

1/16W

5%

R7230.2:10MM

OMIT

SM

13 96

0.0012UF

NOSTUFF

10%
50V

402

CERM

10%
50V

0.0012UF

402

CERM

64 96

0.0012UF

10%
50V
CERM
402

402

MF-LF

1/16W

5%

10

SIGNAL_MODEL=EMPTY

402

MF-LF

1/16W

0

5%

13 96

MF-LF

1/16W

402

1K

5%

XW7142.2:2MM

OMIT

SM

XW7172.2:2MM

SM

OMIT

13 96

VReg CPU Core/AXG Cntl

SYNC_DATE=01/04/2012

SYNC_MASTER=D7_NICK

PM_PGOOD_REG_CPUCORE_S0

MAKE_BASE=TRUE

CPUCORE_PSICOMP_RC

CPUCORE_FB_R_2

CPUCORE_FB_R_1

CPUCORE_COMP_RC

AGND_CPU

REG_CPUCORE_RAMPADJ

AGND_CPU

REG_PWM_CPUCORE_3_R
REG_PWM_CPUCORE_4_R

REG_PWM_CPUAXG_R

REG_ISENAXG_NR

REG_PWM_CPUCORE_1_R

REG_PWM_CPUCORE_2_R
REG_ISENCORE_2_P
REG_ISENCORE_2_NR

REG_ISENCORE_3_P
REG_ISENCORE_3_NR

REG_VCC_U7100

REG_ISENAXG_PR

REG_PWM_CPUCORE_3_R

REG_PWM_CPUCORE_3

REG_PWM_CPUCORE_2

REG_PWM_CPUCORE_1

REG_PWM_CPUAXG_R

REG_PWM_CPUCORE_2_R

REG_CPUCORE_RAMPADJ

REG_CPUAXG_SW_FREQ
REG_CPUCORE_SW_FREQ

REG_CPUAXG_HFCOMP

REG_PWM_CPUCORE_1_R

REG_VCC_U7100

REG_CPUCORE_VSEN

CPU_VIDSCLK

REG_CPUCORE_NPSI

REG_CPUAXG_TCOMP
REG_CPUCORE_SUTH

REG_CPUCORE_RGND

REG_CPUCORE_COMP

REG_CPUCORE_HFCOMP

REG_CPUCORE_VSEN

AGND_CPU

CPUCORE_FB_RC

PP12V_S0_CPUCORE_FLT

REG_VCC_U7100

AGND_CPU

REG_CPUAXG_SW_FREQ

PP12V_S0_CPUCORE_FLT

AGND_CPU

REG_CPUCORE_TM

REG_CPUCORE_FDVID

REG_CPUCORE_SW_FREQ

REG_CPUCORE_HFCOMP

CPU_VIDSOUT

REG_CPUCORE_IMON

REG_CPUCORE_TM

REG_CPUCORE_IAUTO

REG_CPUCORE_FB

REG_CPUAXG_HFCOMP

REG_CPUCORE_COMP

REG_CPUAXG_FB

REG_CPUAXG_RGND

REG_CPUCORE_PGOOD

REG_CPUCORE_PSICOMP

REG_CPUAXG_COMP

REG_CPUCORE_VRHOT_L

REG_CPUAXG_TM

REG_CPUAXG_VSEN

REG_CPUAXG_TM

AGND_CPU

REG_CPUCORE_IMON

REG_VCC_U7100

=PPVCORE_S0_CPU

SNS_CPU_VCORE_N

REG_CPUCORE_RGND

SNS_CPU_VAXG_N

SNS_VAXG_XW_N

SNS_VAXG_R_N

REG_CPUAXG_RGND

REG_CPUAXG_IMON

SNS_VAXG_XW_P

SNS_CPU_VCORE_P

SNS_VCORE_XW_P

SNS_VAXG_R_P

CPUAXG_IMON_R

CPUCORE_IMON_R

REG_PWM_CPUCORE_4_R

REG_CPUAXG_VSEN

AGND_CPU

REG_PWM_CPUAXG

REG_CPUCORE_RSET

REG_CPUAXG_COMP

AGND_CPU

=PPVCCIO_S0_CPU

REG_ISENCORE_1_NR

REG_ISENCORE_1_P

REG_CPUCORE_EN_PWR

=PP5V_S0_REG_CPUCORE_S0

REG_VCC_U7100

REG_CPUAXG_PGOOD

PM_EN_REG_CPUCORE_S0

CPU_VIDSCLK

CPU_VIDALERT_L

CPUAXG_FB_R_2

REG_VCC_U7100

REG_CPUAXG_TCOMP

REG_CPUCORE_VRHOT_L

CPU_PROCHOT_L

=PPVAXG_S0_CPU

SNS_VCORE_XW_N

SNS_VCORE_R_N

REG_CPUAXG_IMON

REG_VCC_U7100

REG_CPUCORE_NPSI

REG_CPUCORE_SUTH

REG_CPUCORE_FDVID

AGND_CPU

AGND_CPU

REG_CPUAXG_PGOOD

=PP3V3_S0_VRD

REG_CPUCORE_PGOOD

CPUCORE_EN_PWR_R

SNS_VCORE_R_P

REG_CPUAXG_VSEN

SNS_CPU_VAXG_P

REG_CPUAXG_FB

CPUAXG_COMP_RC

REG_CPUCORE_FB

REG_CPUCORE_PSICOMP

CPUAXG_FB_R_1

CPU_VIDALERT_L
CPU_VIDSOUT

AGND_CPU

AGND_CPU

AGND_CPU

AGND_CPU

REG_VCC_U7100

REG_CPUCORE_VSEN

=PP3V3_S0_VRD

CPUAXG_FB_RC

U7100

27

29

30

8

18

1

40

7

19

34

22

5

16

9

14

45

46

41

42

47

48

43

44

25

24

28

6

38

36

39

37

26

2

3

21

33

32

11

12

10

49

31

23

35

15

13

17

4

20

R7125

1 2

R7120

1

2

R7121

1

2

R7122

1

2

R7123

1

2

R7124

1

2

R7114

1

2

R7112

1

2

R7110

1

2

R7116

1

2

R7111

1

2

R7113

1

2

R7115

1

2

C7180

1

2

R7180

1

2

R7181

1

2

R7182

1

2

R7152

1

2

C7150

1

2

R7150

1

2

R7151

1

2

R7197

1

2

C7130

1

2

R7130

1

2

C7131

1

2

R7133

1

2

R7131

1

2

C7133

1

2

R7132

1

2

R7134

1 2

C7134

1 2

R7135

1 2

R7136

1 2

C7135

1

2

R7140

1 2

R7141

1 2

R7142

1 2

XW7142

1 2

C7148

1

2

C7141

1

2

C7146

1

2

R7146

1 2

R7145

1 2

R7147

1 2

XW7147

1 2

XW7177

1 2

R7175

1 2

R7170

1 2

XW7172

1 2

R7172

1 2

R7176

1 2

R7171

1 2

C7171

1

2

C7178

1

2

C7176

1

2

R7177

1 2

R7166

1 2

C7160

1

2

R7160

1

2

C7161

1

2

C7163

1

2

R7163

1

2

R7161

1

2

R7162

1

2

R7165

1 2

C7165

1

2

XW7100

1 2

RT7190

1

2

C7190

1

2

R7190

1

2

R7192

1

2

C7192

1

2

RT7192

1

2

R7100

1

2

C7100

1

2

R7106

1

2

R7102

1

2

R7103

1

2

R7105

1

2

R7107

1

2

R7101

1

2

R7109

1

2

R7104

1

2

R7108

1

2

C7195

1

2

R7195

1

2

R7196

1

2

R7119

1

2

R7118

1

2

R7117

1

2

C7117

1

2

R7193

1 2

R7198

1

2

R7199

1

2

R7126

1 2

R7127

1 2

R7128

1 2

051-9509

4.2.0

71 OF 113
62 OF 100

96

96

96

96

62 63 64 96

62 96

62 63 64 96

62 96

62

62

96

62

96

62

96

62 96

62

96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 96

62 63 64 96

96

62 63 64 96

62 96

62 63 64 96

62 96

62 63 64 96

62 63 64 96

62 96

62 96

62 96

62 96

48
62 96

62 96

96

62 96

62 96

62
96

62 96

62 96

62

62
96

62 96

62

62 96

62 96

62 96

62 63 64 96

62 96

6

13 16

48

62 96

96

96

62 96

48 62
96

96

96

96

96

96

62

62 96

62 63 64 96

96

62 96

62 63 64 96

6

10 11 13 16

96

6

62 96

62

13 62 96

96

62 96

62 96

62

6

13 17

48

96

96

62 96

62 96

62 96

62 96

62 63 64 96

62 63 64 96

62

6

62 65 66 68 74

62

96

96

62 96

62 96

96

62 96

62 96

96

13 62 96

13 62 96

62 63 64 96

62 63 64 96

62 63 64 96

62 63 64 96

62 96

62 96

6

62 65 66 68 74

96

OUT

OUT

OUT

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

OUT

OUT

S

D

G

S

D

G

S

D

G

D

S

G

D

S

G

D

S

G

NC

NC

NC

NC

NC

NCNC

NCNC

NCNC

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Phase 3

CPU Phase 2

CPU Output Decoupling

CPU Phase 1

Filtered 12V Rail

62 96

C7241.1:2MM

SIGNAL_MODEL=EMPTY

X5R

16V

10%

0.1UF

402

SIGNAL_MODEL=EMPTY

C7241.2:2MM

1%

MF-LF

402

1.02K

1/16W

SIGNAL_MODEL=EMPTY
U7100.42:3MM

10%
50V
X7R-CERM

220PF

402

62 96

ELEC

20%

8X9-TH1

16V

270UF

CRITICAL

CRITICAL

MF

1%

0.0005

0612

1W

62 96

6

63

DFN

CRITICAL

ISL6622

OMIT_TABLE

62 96

U7250.9:3MM

1UF

603

10%
16V
X5R

U7250.7:3MM

1UF

603

10%
16V
X5R

10

5%
1/10W
MF-LF
603

CPUCOREDRV:ISL6612

0.22UF

603

20%
X5R

25V

Q7250.7:3MM

EMC

402

5%

1000PF

NP0-C0G

25V

5%
1/8W
MF-LF
805

1

SIGNAL_MODEL=EMPTY
C7261.1:2MM

X5R

16V

10%

0.1UF

402

SIGNAL_MODEL=EMPTY

1%
1/16W
MF-LF

1.02K

402

C7261.2:2MM

SIGNAL_MODEL=EMPTY

10%
50V
X7R-CERM

220PF

402

U7100.48:3MM

62 96

8X9-TH1

CRITICAL

270UF

20%
16V
ELEC

CRITICAL

MF

1W

1%

0.0005

0612

62 96

6

63

CRITICAL

IRF6802SDTRPBF

DIRECTFET-SA

DIRECTFET-SA

IRF6802SDTRPBF

CRITICAL

IRF6802SDTRPBF

CRITICAL

DIRECTFET-SA

IRF6892STR1PBF

CRITICAL

DIRECTFET_S3C

DIRECTFET_S3C

CRITICAL

IRF6892STR1PBF

IRF6892STR1PBF

CRITICAL

DIRECTFET_S3C

SDP110808MR36MF-TH

CRITICAL

0.36UH-28A-0.66MOHM

603

20%
X5R

25V

0.22UF

25V
X5R

20%

603

0.22UF

Q7210.8:3MM

25V
NP0-C0G

1000PF

5%

EMC

402

Q7210.5:3MM

402

EMC

5%

1000PF

25V
NP0-C0G

Q7210.6:3MM

25V
NP0-C0G

5%

EMC

402

1000PF

EMC
Q7210.7:3MM

5%
NP0-C0G

25V
402

1000PF

Q7250.8:3MM

25V
NP0-C0G

1000PF

5%

402

EMC

CRITICAL

SDP110808M-TH

0.24UH-30A-0.38MOHM

CRITICAL

0.24UH-30A-0.38MOHM

SDP110808M-TH

402

Q7210.7:3MM

25V

EMC

X5R

10%

1UF

10%
X5R

EMC

402

25V

Q7210.8:3MM

1UF

25V
402

X5R

10%

EMC
Q7210.6:3MM

1UF1UF

10%
X5R

402

25V

Q7210.5:3MM

EMC

25V
402

EMC

X5R

10%

1UF

Q7250.8:3MM

1UF

EMC
Q7250.7:3MM

402

X5R

25V

10%

CRITICAL

10UF

25V
0603

X5R-CERM

20%

603

MF-LF

1/10W

5%

1

CRITICAL

0603

10UF

20%
25V
X5R-CERM

CRITICAL

0603

10UF

20%
25V
X5R-CERM

CRITICAL

10UF

20%
25V
X5R-CERM
0603

CRITICAL

X5R-CERM
0603

10UF

20%
25V

CRITICAL

0603

10UF

20%
25V
X5R-CERM

0.0022UF

402

10%
50V
CERM

CERM

50V

10%

402

0.0022UF

CERM

50V

10%

402

0.0022UF

1

805

MF-LF

1/8W

5%

1

805

MF-LF

1/8W

5%

1

5%
1/10W
MF-LF

603

1

5%
1/10W
MF-LF

603

CRITICAL

SDP110808M-TH

0.24UH-30A-0.38MOHM

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

20%
2V
POLY
CASE-D2-SM

330UF-0.006OHM

CRITICAL

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

NOSTUFF

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

CRITICAL

20%
16V

8X9-TH1

270UF

ELEC

8X9-TH1

ELEC

16V

270UF

CRITICAL

20%

ISL6622

DFN

CRITICAL

1UF

603

X5R

16V

10%

U7210.7:3MMU7210.9:3MM

603

X5R

16V

1UF

10%

X5R

U7210.8:3MM

16V

10%

603

1UF

62 96

MF

0612

0.0005

CRITICAL

1%
1W

MF-LF

402

1/16W

1%

1.02K

C7221.2:2MM

SIGNAL_MODEL=EMPTY

C7221.1:2MM

10%
X5R

16V
402

0.1UF

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY
U7100.46:3MM

220PF

50V
X7R-CERM

10%

402

62 96

DFN

ISL6622

OMIT_TABLE

CRITICAL

62 96

6

63

U7230.9:3MM

1UF

10%
16V
X5R
603

10%

U7230.7:3MM

603

1UF

16V
X5R

CPUCOREDRV:ISL6612

10

5%
MF-LF

603

1/10W

SYNC_MASTER=D7_NICK

SYNC_DATE=01/04/2012

VReg CPU Core Phases

353S1733

CPUCOREDRV:ISL6612

CRITICAL

U7230,U7250

2

IC,ISL6612,FET DRV,DFN10,LF

REG_BOOT_CPUCORE_3_RC

REG_BOOT_CPUCORE_3

REG_BOOT_CPUCORE_2_RC

REG_BOOT_CPUCORE_2

REG_BOOT_CPUCORE_1_RC

REG_UGATE_CPUCORE_1

REG_UGATE_CPUCORE_2

PP12V_S0_CPUCORE_FLT

REG_BOOT_CPUCORE_1

PP12V_S0_CPUCORE_FLT

PPCPUCORE_S0_REG

REG_ISENCORE_1_P

PPCPUCORE_S0_SENSE_1

REG_SNUBBER_CPUCORE_1

REG_SNUBBER_CPUCORE_2

REG_SNUBBER_CPUCORE_3

REG_PHASE_CPUCORE_3

REG_PHASE_CPUCORE_2

REG_PHASE_CPUCORE_1

REG_PWM_CPUCORE_3

REG_LGATE_CPUCORE_1

REG_LGATE_CPUCORE_2

PPCPUCORE_S0_SENSE_2

REG_ISENCORE_3_N

PPCPUCORE_S0_SENSE_3

REG_ISENCORE_2_NR

REG_ISENCORE_3_P

REG_ISENCORE_1_NR

PPCPUCORE_S0_REG

REG_ISENCORE_2_P

PP12V_S0_CPUCORE_FLT

PP12V_S0_CPUCORE_FLT

REG_PWM_CPUCORE_2

REG_LVCC_U7230

REG_LVCC_U7210

REG_LGATE_CPUCORE_3

REG_UGATE_CPUCORE_3

REG_PWM_CPUCORE_1

REG_LVCC_U7250

PPCPUCORE_S0_REG

PP12V_S0_CPUCORE_FLT

AGND_CPU

AGND_CPU

REG_ISENCORE_3_NR

PPCPUCORE_S0_REG

AGND_CPU

REG_ISENCORE_1_N

=PP12V_S0_REG_CPUCORE_S0

REG_ISENCORE_2_N

L7210

1 2

R7210

1 2
3 4

C7218

1

2

R7216

1

2

C7280

1

2

C7281

1

2

C7282

1

2

C7285

1

2

C7284

1

2

C7283

1

2

C7211

1

2

C7210

1

2

U7210

23

5

6

7

10

4

11

1

8

9

C7227

1

2

C7225

1

2

C7226

1

2

R7221

1 2

C7220

1

2

C7221

1

2

U7230

23

5

6

7

10

4

11

1

8

9

C7245

1

2

C7247

1

2

R7247

1

2

C7240

1

2

R7241

1 2

C7241

1

2

C7230

1

2

R7230

1 2
3 4

U7250

23

5

6

7

10

4

11

1

8

9

C7265

1

2

C7267

1

2

R7267

1

2

C7256

1

2

C7258

1

2

R7257

1

2

C7260

1

2

R7261

1 2

C7261

1

2

C7250

1

2

R7250

1 2
3 4

Q7210

7

8

2

3

Q7210

5

6

1

4

Q7250

7

8

2

3

Q7211

128

7

4

3

5

6

Q7231

128

7

4

3

5

6

Q7251

128

7

4

356

L7200

1 2

C7236

1

2

C7216

1

2

C7219

1

2

C7238

1

2

C7239

1

2

C7259

1

2

L7230

1 2

L7250

1 2

C7214

1

2

C7215

1

2

C7235

1

2

C7234

1

2

C7255

1

2

C7254

1

2

C7212

1

2

C7213

1

2

C7232

1

2

C7233

1

2

C7252

1

2

C7253

1

2

C7217

1

2

C7237

1

2

C7257

1

2

R7237

1

2

R7217

1

2

R7236

1

2

R7256

1

2

051-9509

4.2.0

72 OF 113
63 OF 100

96

96

96

96

96

96

96

62 63 64 96

96

62 63 64 96

96

96

96

96

96

96

96

96

96

96

96

96

62 63 64 96

62 63 64 96

96

96

96

96

96

6

63

62 63 64 96

62 63 64 96

62 63 64 96

62 63 64 96

96

6

96

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

S

D

G

D

S

G

NC

NCNC

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AXG Phase

AXG Phase

402

EMC

5%

1000PF

NP0-C0G

25V

Q7250.5:3MM

0.22UF

25V
X5R

20%

603

1UF

X5R

16V

10%

603

U7330.7:3MM

1/10W

NOSTUFF

603

MF-LF

10

5%

603

MF-LF

5%
1/10W

1

U7330.8:3MM

1UF

X5R

16V

10%

603

U7330.9:3MM

X5R
603

16V

10%

1UF

CRITICAL

ISL6622

DFN

62 96

10V

10UF

20%
X5R

603 603

X5R

20%

10UF

10V

301

MF-LF

1/16W

1%

C7342.1:2MM

402

SIGNAL_MODEL=EMPTY

62 96

CERM

50V

5%

120PF

U7100.24:3MM

SIGNAL_MODEL=EMPTY

402

CRITICAL

DIRECTFET-SA

IRF6802SDTRPBF

CRITICAL

DIRECTFET_S3C

IRF6892STR1PBF

270UF

CRITICAL

16V
8X9-TH1

20%
ELEC

Q7250.6:3MM

402

NP0-C0G

25V

5%

1000PF

EMC

25V
402

EMC

10%

1UF

X5R

Q7250.6:3MM

EMC
Q7250.5:3MM

1UF

10%
X5R

402

25V

CRITICAL

0603

10UF

20%
25V
X5R-CERM X5R-CERM

25V

20%

CRITICAL

10UF

0603

330UF-0.006OHM

CRITICAL

POLY

2V

20%

CASE-D2-SM

CRITICAL

330UF-0.006OHM

POLY

2V

20%

CASE-D2-SM

50V

10%
CERM

402

0.0022UF

330UF-0.006OHM

CASE-D2-SM

20%
2V
POLY

CRITICAL

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICALCRITICAL

330UF-0.006OHM

POLY

2V

20%

CASE-D2-SM

CRITICAL

330UF-0.006OHM

2V
CASE-D2-SM

POLY

20%

6

64

62 96

R7342.1:2MM

X7R-CERM

10%

220PF

50V
402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1%

MF-LF

1.02K

1/16W

402

C7341.2:2MM

CRITICAL

1%

0.0005

0612

1W
MF

SIGNAL_MODEL=EMPTY
R7342.1:2MM

402

10%
16V
X5R

0.1UF

CRITICAL

0.24UH-30A-0.38MOHM

SDP110808M-TH

8X9-TH1

16V
ELEC

270UF

20%

CRITICAL

MF-LF
805

1/8W

5%

1

SYNC_MASTER=D7_NICK

SYNC_DATE=01/04/2012

VReg CPU AXG Phases

PP12V_S0_CPUCORE_FLT

REG_PWM_CPUAXG

REG_BOOT_CPUAXG_RC

REG_LVCC_U7330

REG_BOOT_CPUAXG

PPCPUAXG_S0_SENSE

AGND_CPUAGND_CPU

REG_ISENAXG_PR

REG_LGATE_CPUAXG

REG_ISENAXG_NR

REG_ISENAXG_P

PPCPUAXG_S0_REG

PPCPUAXG_S0_REG

PP12V_S0_CPUCORE_FLT

REG_ISENAXG_N

REG_SNUBBER_CPUAXG

REG_PHASE_CPUAXG

REG_UGATE_CPUAXG

C7393

1

2

C7392

1

2

C7391

1

2

C7390

1

2

C7341

1

2

R7341

1 2

R7330

1 2
3 4

C7340

1

2

L7330

1 2

C7330

1

2

R7337

1

2

C7338

1

2

C7336

1

2

C7347

1

2

R7347

1

2

R7336

1

2

C7346

1

2

C7345

1

2

U7330

23

5

6

7

10

4

11

1

8

9

C7394

1

2

C7395

1

2

R7342

1 2

C7342

1

2

Q7250

5

6

1

4

Q7331

128

7

4

356

C7331

1

2

C7339

1

2

C7335

1

2

C7334

1

2

C7332

1

2

C7333

1

2

C7397

1

2

C7396

1

2

C7337

1

2

051-9509

4.2.0

73 OF 113
64 OF 100

62 63 64 96

96

96

96

96

62 63 64 96 62 63 64 96

96

96

6

64

62 63 64 96

96

96

96

96

OUT

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

OUT

IN

IN

VSW

PGND

TGR

TG

BG

VIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

? A (design)/ 18.38 A (budget)

? A (design)/ 14.38 A (budget)

CPU VccIO/PCH (1.05V) S0 Regulator

? A (min)/? A (max)

prevent noise in the

Max peak current:
OC trip point:
Switching freq:

Note:

a minimum load to

audio frequencies

Regulator requires

To regulator:

Max avg current:

Vout = 0.5 * (1 + Ra / Rb)

<Rb>

500 kHz

<Rb>

<Ra><Ra>

6

3.40K

L7410.2:3MM

1%
1/16W
MF-LF
402

R7450.2:3MM

10%
16V
X7R

0.22UF

603

3.40K

L7410.1:3MM

402

1/16W
MF-LF

1%

2.2

603

5%

1/10W

NOSTUFF

MF-LF

10UF

X5R
603

6.3V

20%

0.001UF

NOSTUFF

CERM

50V
402

10%

X7R-CERM

10%

0.1UF

16V
402

805

1%

1

1/8W

MF-LF

603

2.2UF

X5R

10%
16V

805

1/8W
MF-LF

5%

2.2

805

1/8W

10

MF-LF

5%

10%
X5R

402

1UF

16V

CRITICAL

ELEC

16V

20%

8X9-TH1

270UF

CRITICAL

UTQFN

ISL95870

MF-LF

0

5%

1/16W

402

U1000.AB4:1MM

SM

MF-LF
402

3.01K

1%
1/16W

SIGNAL_MODEL=EMPTYSIGNAL_MODEL=EMPTY

3.01K

1%

MF-LF

402

1/16W

60

0.047UF

X7R
402

16V

10%

2.74K

1%
1/16W

402

MF-LF

10PF

CERM

50V

5%

402

10PF

CERM

50V

5%

402

MF-LF

2.74K

402

1%

1/16W

U7400.3:1MM

SM

60

402

MF-LF

1/16W

5%

20K

SM

U1000.AB3:1MM

13 95

13 95

CRITICAL

330UF-0.009OHM

POLY

2V

20%

CASE-D2-HF

CRITICAL

330UF-0.009OHM

POLY

2V

20%

CASE-D2-HF

805

1/8W

MF-LF

1%

3.32

CSD58872Q5D

SON5X6

CRITICAL

SDP1182-SM

1.0UH-22A-1.15MOHM

CRITICAL

X5R

25V

10%

402

1UF

Q7410.2:3MM

EMC

X5R

25V

10%

402

1UF

Q7410.2:3MM

EMC

0603

CRITICAL

25V
X5R-CERM

10UF

20%

0603

CRITICAL

25V
X5R-CERM

10UF

20%

CASE-D2-HF

20%

CRITICAL

330UF-0.009OHM

POLY

2V

MF-LF

5%
1/10W

603

200

402

25V

NP0-C0G

1000PF

5%

SYNC_DATE=01/04/2012

VReg CPU/PCH 1.05V S0

SYNC_MASTER=D7_NICK

PM_PGOOD_REG_P1V05_S0

MAKE_BASE=TRUE

REG_LGATE_P1V05S0

REG_PHASE_P1V05S0

REG_UGATE_P1V05S0

REG_P1V05S0_SREF

REG_P1V05S0_RTN

SNS_P1V05S0_XW_N

REG_P1V05S0_FB

SNS_P1V05S0_XW_P

SNS_CPU_VCCIO_P

AGND_P1V05S0

REG_SNUBBER_P1V05S0

REG_P1V05S0_PGOOD

REG_VCC_U7400

REG_PHASE_P1V05S0_L

PM_EN_REG_P1V05_S0

=PP3V3_S0_VRD

=PP5V_S0_REG_P1V05_S0

REG_P1V05S0_FSEL

REG_P1V05S0_OCSET

REG_P1V05S0_VO

SNS_CPU_VCCIO_N

REG_P1V05S0_PGOOD

REG_BOOT_P1V05S0

REG_BOOT_P1V05S0_RC

REG_UGATE_P1V05S0_R

REG_PVCC_U7400

PP1V05_S0_REG

=PP12V_S0_REG_P1V05_S0

REG_P1V05S0_VO

REG_P1V05S0_OCSET

C7423

1

2

C7410

1

2

C7421

1

2

C7420

1

2

R7418

1

2

C7418

1

2

R7451

1

2

C7450

1 2

R7450

1

2

R7417

1

2

C7417

1

2

C7416

1

2

R7416

1

2

C7401

1

2

R7401

1

2

R7400

1

2

C7400

1

2

U7400

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

R7460

1

2

XW7435

1

2

R7435

1

2

R7430

1

2

C7440

1

2

R7436

1

2

C7435

1

2

C7430

1

2

R7431

1

2

XW7400

1

2

R7480

1

2

XW7430

1

2

C7422

1

2

R7411

1

2

Q7410

5

9

3

4

1

6
7
8

L7410

1 2

C7480

1

2

C7481

1

2

C7411

1

2

C7412

1

2

051-9509

4.2.0

74 OF 113
65 OF 100

95

95

95

95

95

95

95

95

95

95

65

95

95

6

62 66 68 74

6

95

65 95

65 95

65

95

95

95

95

6

65 95

65 95

OUT

PHASE

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Ra> <Ra>

Vout = 0.5 * (1 + Ra / Rb)

Max peak current:
Switching freq:

Max avg current:

(reg_phase_vccsas0)

OC trip point:

To regulator:

Regulator requires

<Rb>

<Rb>

audio frequencies

prevent noise in the

a minimum load to

Note:

CPU VccSA (0.925V) S0 Regulator

? A (min)/? A (max)
500 kHz

? A (design)/ 1.51 A (budget)
? A (design)/ 8.76 A (budget)

402

25V

NP0-C0G

1000PF

5%

PIC0605H-SM

1.0UH-20%-15A-0.0065OHM

CRITICAL

6

603

1/10W

5%
MF-LF

2.2

NOSTUFF

CERM

10%

402

NOSTUFF

50V

0.001UF

X7R-CERM

16V
402

10%

0.1UF

0

603

1/10W

5%

MF-LF

16V
X5R

2.2UF

10%

603

CRITICAL

POWER56

FDMS3602S

2.2

5%
MF-LF

1/8W
805

X5R
603

10UF

20%

6.3V

5%

MF-LF

10

1/8W

805

402

16V
X5R

1UF

10%

POLY

2V
CASE-D2-HF

20%

330UF-0.009OHM

CRITICAL

60 61

MF-LF
402

5%
1/16W

20K

ELEC

16V

20%

CRITICAL

270UF

8X9-TH1

SM

U1000.T2:1MM

SIGNAL_MODEL=EMPTY

SM

XW7535.2:1MM

SIGNAL_MODEL=EMPTY

13 95

402

1%
1/16W
MF-LF

L7510.2:3MM

12.1K

603

10%

0.012UF

CER-X7R

50V

R7550.2:3MM

L7510.1:3MM

MF-LF

1/16W

1%

402

12.1K

UTQFN

ISL95870

CRITICAL

60

10%
16V

402

X7R

0.047UF

2.32K

MF-LF

1/16W

1%

402

SIGNAL_MODEL=EMPTY

MF-LF

1/16W

402

1%

SIGNAL_MODEL=EMPTY

2.32K

402

MF-LF

1/16W

1%

2.74K

402

MF-LF

1/16W

5%

0

50V
402

5%
CERM

10PF10PF

402

5%

CERM

50V

2.74K

1%
1/16W
MF-LF

402

CASE-D2-HF

20%
POLY

2V

CRITICAL

330UF-0.009OHM

U7500.3:1MM

SM

1UF

10%
25V
X5R
402

Q7510.2:3MM

EMC

X5R

25V

10%

1UF

402

Q7510.2:3MM

EMC

1/10W
MF-LF

5%

200

603

VReg CPU VccSA S0

SYNC_DATE=01/04/2012

SYNC_MASTER=D7_NICK

REG_PHASE_VCCSAS0

REG_VCCSAS0_OCSET

REG_LGATE_VCCSAS0

REG_BOOT_VCCSAS0

REG_VCCSAS0_OCSET

REG_VCCSAS0_VO

PPVCCSA_S0_REG

REG_UGATE_VCCSAS0

REG_VCCSAS0_PGOOD

REG_VCCSAS0_SREF

REG_VCCSAS0_FSEL

REG_PVCC_U7500

REG_VCCSAS0_VO

REG_SNUBBER_VCCSAS0

REG_BOOT_VCCSAS0_RC

=PP5V_S0_REG_VCCSA_S0

=PP3V3_S0_VRD

REG_VCCSAS0_PGOOD

REG_VCCSAS0_RTN

SNS_VCCSAS0_XW_N SNS_VCCSAS0_XW_P

REG_VCCSAS0_FB

AGND_VCCSAS0

PM_EN_REG_VCCSA_S0

=PP12V_S0_REG_VCCSA_S0

SNS_CPU_VCCSA

REG_VCC_U7500

MAKE_BASE=TRUE

PM_PGOOD_REG_VCCSA_S0

C7522

1

2

C7521

1

2

C7510

1

2

C7520

1

2

R7518

1

2

C7518

1

2

L7510

1 2

R7517

1

2

C7517

1

2

C7516

1

2

R7516

1

2

C7501

1

2

Q7510

2

1

6

7

3 4 5

R7501

1

2

R7500

1

2

C7500

1

2

R7580

1

2

XW7535

1

2

XW7530

1

2

R7551

1

2

C7550

1 2

R7550

1

2

U7500

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C7540

1

2

R7535

1

2

R7530

1

2

R7536

1

2

R7560

1

2

C7535

1

2

C7530

1

2

R7531

1

2

XW7500

1

2

C7580

1

2

C7581

1

2

051-9509

4.2.0

75 OF 113
66 OF 100

95

66 95

95

95

66 95

66 95

95

66

95

95

95

66 95

95

95

6

6

62 65 68 74

66

95

95 95

95

95

6

95

PGOOD2

FCCM

VIN

FB1

FSET1

EN2

FSET2

BOOT2

THRM

PGND

EN1

FB2

VOUT2VOUT1

ISEN2ISEN1

OCSET1

OCSET2

LGATE1

LGATE2

PHASE2

BOOT1

UGATE1

LDO5

PGOOD1

VCC1

VCC2

UGATE2

PHASE1

PAD

OUT

IN

OUT

OUT

OUTOUT

IN

PHASE

S

G

G

S

D

D

N-CH

P-CH

IN

G

D

S

G

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(reg_p5vs4_isen)

(reg_p5vs4_ocset)

(reg_p3v3s4_isen)

(reg_phase_p5vs4)

? A (design)/ 6.9 A (budget)

10 A (design)/ 6.08 A (budget)

? A (design)/ 6.6 A (budget)

6 A (design)/ 4.85 A (budget)

350 kHz

? A (nom)/? A (min)

(reg_phase_p3v3s5)

Vout = 0.6 * (1 + Ra / Rb)

Max avg current:

3.3V S5 Regulator

Max avg current:

Switching freq:

OC trip point:

Max peak current:

OC trip point:

Max peak current:

5V S4 Regulator

? A (nom)/? A (min)
350 kHz

(reg_p5vs4_vout)

<Rb>

<Ra>

(reg_p3v3s4_ocset)

(reg_p3v3s4_vout)

<Ra>

Switching freq:

<Rb>

Vout = 0.6 * (1 + Ra / Rb)

BURSTMODE_EN_L

Vreg Mode

1

0 PWM

DCM

modes based on load requirements

between PWM and ultrasonic DCM

This circuit toggles the Vreg

CRITICAL

QFN

ISL62383CRTZ

603

0

5%
MF-LF

1/10W

402

0.1UF

10%
25V
X5R

10%
50V
CERM

0.001UF

402

NOSTUFF

603

MF

1/10W

1%

NOSTUFF

0.499

9.76K

402

1%
1/16W
MF-LF

27.0NF

402

10%
10V
X5R

MF-LF

402

1%

1/16W

9.76K

OMIT

SM

L7650.2:1MM

CERM

50V

10%

402

0.001UF

NOSTUFF

MF-LF

1/16W

1%

402

75K

10K

1/16W
MF-LF
402

1%

MF-LF

1/16W

976

402

1%

NP0-C0G

25V

5%

1000PF

402

10%

0.01UF

402

16V
CERM

16.5K

402

MF-LF

1/16W

1%

1/16W
402

MF-LF

16.5K

1%

10%

402

CERM

0.01UF

16V

1%

402

45.3K

MF-LF

1/16W

25V

NP0-C0G

5%

402

1000PF

976

1%
1/16W
MF-LF

402

MF

1/16W

10.0K

0.5%

402

L7610.1:1MM

SM

OMIT

2.2UH-10A-12.5MOHM

PAB0705AR-SM

CRITICAL

402

16V

CERM

0.01UF

10%

1/16W
MF-LF

1%

402

15.8K

1%

402

MF-LF

1/16W

15.8K

603

1/10W

5%

0

MF-LF

0.1UF

402

25V
X5R

10%

402

1UF

10%
16V
X5R

X5R

10%

402

16V

1UF

X5R

10%

402

1UF

16V

2.2

5%
1/8W
MF-LF
805

6

CERM

20%

603

6.3V

4.7UF

805

1/8W

1

5%
MF-LF

60

25V

NP0-C0G

1000PF

5%

L7610.1:3MM

402

EMC

CERM

10%

402

0.001UF

50V

NOSTUFF

0.499

603

1%

NOSTUFF

MF

1/10W

60

20K

MF-LF

1/16W

5%

402

402

5%
1/16W
MF-LF

20K

61

6 6

CRITICAL

20%
16V
ELEC
8X9-TH1

270UF

8X9-TH1

ELEC

16V

20%

CRITICAL

270UF

CRITICAL

20%
16V

8X9-TH1

270UF

ELEC

60

25V
NP0-C0G

5%

402

EMC
L7650.2:3MM

1000PF

150UF

POLY

6.3V

20%

CRITICAL

B1A-SM

150UF

POLY

6.3V

20%

B1A-SM

CRITICAL

X5R

6.3V

10UF

20%

603

CRITICAL

FDMS3602S

POWER56

20%

10UF

6.3V
603

X5R

CRITICAL

20%

6.3V
POLY-TANT

330UF

CASE-D3L-SM

2.2UH+/-20%-0.0069OHM-16A

CRITICAL

PIC1005H-SM

EMC

402

L7610.1:3MM

5%

1000PF

NP0-C0G

25V

EMC

402

L7650.2:3MM

5%

1000PF

NP0-C0G

25V

CASE-D3L-SM

330UF

POLY-TANT

6.3V

20%

CRITICAL

X5R

25V

10%

1UF

Q7650.5:3MM

EMC

402

X5R

10%

Q7650.5:3MM

EMC

402

1UF

25V

Q7610.2:3MM

402

EMC

1UF

10%
25V
X5R

Q7610.2:3MM

402

EMC

1UF

10%
25V
X5R

SSM6L36FE

SOT563

NOSTUFF

6

45

1/16W

5%

10K

MF-LF

402

NOSTUFF

1/16W
MF-LF

5%

1K

402

NOSTUFF

FDMC0223S

CRITICAL

MLP3.3X3.3

MLP3.3X3.3

FDMC0223

CRITICAL

VReg 3.3V S5/5V S4

SYNC_DATE=01/04/2012

SYNC_MASTER=D7_NICK

REG_BOOT_P5VS4_RC

BURSTMODE_EN

REG_U7600_FCCM_R

REG_P3V3S5_OCSET

REG_P3V3S5_ISEN

REG_BOOT_P3V3S5

REG_P3V3S5_VOUT_R

BURSTMODE_EN_L

BURSTMODE_EN

=PP5V_S5_PWRCTL

PM_EN_REG_P3V3_S5

REG_P3V3S5_FSET

REG_P3V3S5_VOUT

PP3V3_S5_REG

REG_LGATE_P3V3S5

REG_P3V3S5_PGOOD

REG_P5VS4_PGOOD

=PP3V3_S5_VRD

=PP3V3_S5_VRD

REG_P3V3S5_PGOOD

REG_U7600_FCCM

REG_P5VS4_PGOOD

REG_SNUBBER_P3V3S5

REG_BOOT_P3V3S5_RC

REG_P5VS4_FSET

REG_P5VS4_VOUT_R

REG_SNUBBER_P5VS4

PM_EN_REG_P5V_S4

REG_P5VS4_ISEN

REG_P5VS4_FB

PP5V_S4_REG

PP5V_S5_LDO

REG_P3V3S5_FB

REG_U7600_FCCM

=PP5V_S5_PWRCTL

REG_PHASE_P3V3S5

REG_UGATE_P3V3S5

REG_VCC1_U7600

REG_P5VS4_VOUT

REG_P5VS4_OCSET

REG_BOOT_P5VS4

REG_VCC2_U7600

REG_VIN_U7600

REG_LGATE_P5VS4

REG_UGATE_P5VS4

REG_PHASE_P5VS4

=PP12V_S5_REG_P3V3P5V_S5

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PM_PGOOD_REG_P5V_S4

U7600

15

21

12 24

8

28

3

6

2

10

26

18

16 20

11 25

19

7

1

13 23

29

14 22

5

4

17

9 27

R7656

1

2

C7656

1

2

C7657

1

2

R7657

1

2

R7658

1 2

C7658

1 2

R7659

1

2

XW7650

1

2

C7675

1

2

R7670

1

2

R7671

1

2

R7672

1

2

C7672

1

2

C7673

1

2

R7673

1

2

R7633

1

2

C7633

1

2

R7630

1

2

C7632

1

2

R7632

1

2

R7631

1

2

XW7610

1

2

L7610

1 2

C7618

1 2

R7618

1 2

R7619

1

2

R7616

1

2

C7616

1

2

C7600

1

2

C7602

1

2

C7603

1

2

R7602

1

2

C7601

1

2

R7603

1

2

C7640

1

2

C7617

1

2

R7617

1

2

R7680

1

2

R7640

1

2

C7650

1

2

C7610

1

2

C7651

1

2

C7680

1

2

C7620

1

2

C7621

1

2

C7622

1

2

Q7610

2

1

6

7

345

C7662

1

2

C7660

1

2

L7650

1 2

C7641

1

2

C7681

1

2

C7661

1

2

C7682

1

2

C7683

1

2

C7643

1

2

C7642

1

2

Q7600

6

3

2

5

1

4

R7601

1

2

R7600

12

Q7655

5

4

1 2 3

Q7650

5

4

1 2 3

67 OF 100

76 OF 113

4.2.0

051-9509

97

67

97

97

97

97

67

6

67 70

97

97

97

67

67

6

67 68

6

67 68

67

67

67

97

97

97

97

97

97

97 97

67

6

67 70

97

97

97

97

97

97

97

97

97

97

97

6

V5IN

REFIN

S5

VREF

S3

MODE
TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

IN

OUT

OUT

OUT

OUT

NC
NC

IN

OUT

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

NC

VSW

PGND

TGR

TG

BG

VIN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

3 A (design)/ 0.61 A (budget)

? A (design)/ 17.8 A (budget)

? A (design)/ 8 A (budget)

? A (design)/ 1.83 A (budget)

Vout = 1.8 * (Ra / (Ra + Rb))

? A (nom)/? A (min)

to sink heat

<Rb>

Max peak current:

Need copper around Q7710

Critical:

10mA (max)

Vout = 0.8 * (1 + Ra / Rb)

Switching freq:

OC trip point:

PU: PWM

? kHz

VDDQ (1.5V) S3 Regulator

<Ra>

1.8V S0 Regulator

Max avg current:

<Ra>

<Rb>

400 kHz

? A (nom)/? A (min)

Switching freq:

OC trip point:

Max peak current:

Max avg current:

PD: PFM (SKIP mode)

CRITICAL

QFN

TPS51916

1.0UH-22A-1.15MOHM

SDP1182-SM

CRITICAL

NOSTUFF

1000PF

402

5%
25V
NP0-C0G

1/10W
603

NOSTUFF

0.499

1%
MF

402

X5R

25V

10%

0.1UF

603

0

5%

MF-LF

1/10W

OMIT

SM

L7710.2:1MM

6.3V
603

22UF

20%
X5R-CERM-1

CRITICAL

SM

OMIT

C7725.1:3MM

20%

603

6.3V

22UF

CRITICAL

X5R-CERM-1

U7700.21:1MM

SM

OMIT

CERM

10%
16V

402

0.22UF

75K

402

1%

MF-LF

1/16W1/16W

MF-LF

1K

1%

402

49.9K

402

MF-LF

1/16W

1%

MF-LF

402

1%

1/16W

10K

0.01UF

402

X7R

10%
50V

0.1UF

X7R-CERM

402

16V

10%

60

CRITICAL

CASE-D2-HF

POLY

2V

20%

330UF-0.009OHM

CASE-D2-HF

POLY

20%
2V

CRITICAL

330UF-0.009OHM

NP0-C0G

25V

EMC

402

1000PF

L7710.2:3MM

5%

20%

10UF

603

X5R

6.3V

603

2.2UF

X5R

16V

10%

805

1/8W

MF-LF

5%

2.2

60

1/16W
402

5%
MF-LF

20K

6

6

CERM

50V
402

47PF

5%

59.0K

1/16W
MF-LF
402

1%

1/16W
402

1%
MF-LF

47.0K

603

22UF

X5R-CERM-1

20%

6.3V

100K

402

5%
1/16W
MF-LF

402

5%
1/16W
MF-LF

100K

NOSTUFF

10UF

603

20%

6.3V
X5R

6.3V

20%
X5R-CERM-1

22UF

603

6

60

60

402

5%
1/16W
MF-LF

10K

603

10UF

X5R

6.3V

20% 20%

603

X5R

10UF

6.3V

20%

8X9-TH1

ELEC

16V

270UF

CRITICAL

1/10W

3.9

MF-LF

603

5%

8X9-TH1

270UF

20%
16V

ELEC

CRITICAL

CRITICAL

ISL8014A

QFN

NP0-C0G

25V

1000PF

EMC

402

Q7710.1:3MM

5%

CRITICAL

SON5X6

CSD58872Q5D

402

EMC
Q7710.1:3MM

1UF

10%
25V
X5R X5R

25V

10%

1UF

Q7710.1:3MM

EMC

402

60

Q7750.1:3MM

402

EMC

1UF

10%
25V
X5R

402

EMC

X5R

25V

10%

1UF

Q7750.1:3MM

PCMB042T-IHLP1616BZ

CRITICAL

1.0UH-4.5A

SYNC_DATE=01/04/2012

VReg VDDQ and 1.8V S0

SYNC_MASTER=D7_NICK

REG_LGATE_VDDQS3

PPDDRVTT_S0_LDO

REG_UGATE_VDDQS3

=PP12V_S5_REG_VDDQ_S3

REG_BOOT_VDDQS3

LDO_DDRVTTS0_SNS

REG_VDDQS3_PGOOD

REG_PHASE_VDDQS3

REG_SNUBBER_VDDQS3

REG_UGATE_VDDQS3_RREG_BOOT_VDDQS3_RC

=PP5V_S0_VRD

REG_P1V8S0_SYNCH

=PP3V3_S0_VRD

REG_P1V8S0_PGOOD

PM_EN_REG_P1V8_S0

REG_P1V8S0_PGOOD

=PP3V3_S5_VRD

REG_PHASE_VDDQS3_L

=PP5V_S4_REG_VDDQ_S3

PM_EN_REG_VDDQ_S3

PPDDRVTT_S3_LDO

REG_V5IN_U7700

REG_VDDQS3_PGOOD

PPVDDQ_S3_REG

REG_VDDQS3_REFIN

REG_VDDQS3_TRIP

PM_EN_LDO_DDRVTT_S0

REG_VDDQS3_VDDQSNS

REG_VDDQS3_VREF

=PPVDDQ_S3_LDO_DDRVTT

AGND_VDDQS3

REG_P1V8S0_VFB

REG_PHASE_P1V8S0

=PP5V_S0_REG_P1V8_S0

REG_VDDQS3_MODE

PP1V8_S0_REG

PM_PGOOD_REG_P1V8_S0

MAKE_BASE=TRUE

PM_PGOOD_REG_VDDQ_S3
MAKE_BASE=TRUE

U7700

14

11

7

19

10

20

8

17
16

13

21

18

12 15

9

2

6

3

4

5

1

L7710

1 2

C7717

1

2

R7717

1

2

C7716

1

2

R7716

1

2

XW7710

1 2

C7725

1

2

XW7725

1 2

C7726

1

2

XW7700

1

2

C7727

1

2

R7736

1

2

R7735

1

2

R7731

1

2

R7730

1

2

C7731

1

2

C7730

1

2

C7721

1

2

C7720

1

2

C7740

1

2

C7701

1

2

C7700

1

2

R7700

1

2

R7740

1

2

C7758

1

2

R7758

1

2

R7759

1

2

C7760

1

2

R7770

1

2

R7771

1

2

C7722

1

2

C7761

1

2

R7780

1

2

C7750

1

2

C7751

1

2

C7710

1

2

R7711

1

2

C7711

1

2

U7750

5 14

15

6

16

13

7

11

12

9

10

4

17

3

8

1

2

C7741

1

2

Q7710

5

9

3

4

1

6
7
8

C7742

1

2

C7743

1

2

C7752

1

2

C7753

1

2

L7750

1 2

051-9509

4.2.0

77 OF 113
68 OF 100

95

95

6

95

95

68

95

95

95 95

6

97

6

62 65 66 74

68

68

6

67

95

6

6

95

68

95

95

95

95

6

95

97

97

6

95

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

OUT

THRM

GND

PG

ON

NC

D1

D2

G

VCC

PAD

NC

IN

G

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Max avg current:

Max peak current:

12V S5 FET

Input: 2.4V to 5.5V

<Rb>

<Ra>

Max avg current:

Vout = 1.25V * (1 + Ra / Rb)

3.425V "G3Hot" Regulator

Vout = 3.425
(Switcher limit)

250mA max output

Max peak current:

7.03 A (budget)

9.69 A (budget)

? A (design)/ 0 A (budget)
? A (design)/ 0.06 A (budget)

Switching freq:

? kHz

DFN

LT3470A

200K

402

1%
1/16W
MF-LF

10UF

0805

X5R

25V

10%

402

MF-LF

1/16W

1%

6.98K

402

1%
1/16W
MF-LF

2.1K

NOSTUFF

6

CDPH4D19FHF-SM

33UH

TDFN

SLG5AP026

603

1/10W

5%

MF-LF

100

16V
603

X5R

10%

1UF

100K

MF-LF
402

1/16W

5%

44 45

0.22UF

402

16V
CERM

10%

IRFH3702TRPBF

PQFN

1UF

10%
X5R

25V
402

25V
X5R

10%

1UF

402

402

22PF

5%
50V
CERM

0603

X5R-CERM1

6.3V

20%

22UF

402

1000PF

5%
25V
NP0-C0G

NOSTUFF

402

MF-LF

1/16W

1%

348K

VReg G3Hot

SYNC_DATE=01/04/2012

SYNC_MASTER=D7_NICK

P3V42G3H_BOOST

PP3V42_G3H_REG

P3V42G3H_SW

P3V42G3H_FB

FET_VCC_U7970

P3V42G3H_SHDN_L

=PP12V_G3H_REG_3V42_G3H

=PP12V_G3H_FET_P12V_S5

PP12V_S5_FET

FET_EN_P12V_S5

SMC_PM_G2_EN

NC_PM_PGOOD_FET_P12V_S5

NO_TEST=TRUE

U7800

2

3

1

5

8 4

9

6

L7801

1 2

C7803

1

2

C7804

1

2

C7805

1

2

C7801

1

2

R7803

1

2

R7804

1

2

C7802

1

2

R7801

1

2

R7802

1

2

U7870

5

6

7

4

2

8

9

1

R7870

1 2

C7870

1

2

R7871

1

2

Q7870

5

4

1

C7806

1

2

C7807

1

2

051-9509

4.2.0

78 OF 113
69 OF 100

7

3

97

6

97

97

97

6

6

IN

OUT

OUT

OUT

NC

OUT

THRM

GND

PG

ON

NC

D1

D2

G

VCC

PAD

OUT

OUT

NC

IN

GND

THRM

ON_MOS1

CAP_MOS1

5_VDD

MOS2_D

MOS2_S

CAP_MOS2

ON_MOS2

MOS1_D

MOS1_S

PAD

D

S

G

D

S

G

IN IN

ININ

OUT

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

OUT

IN

IN

08

Y1

Y2

GND

B2

VCC

A1
B1
A2

IN

IN

OUT

OUT

GND

VDD

D

SON

CAP

GND

VDD

D

SON

CAP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

2.2V / ms ramp rate

23 A (budget)

14.3 A (budget)

5V / 3V3 S0 PGOODs

5V S0 FET

4nF corresponds to

2.2V / ms ramp rate

12V S0 FET

Max peak current: Max peak current:

Max avg current:

3.3V S4 FET

Max avg current:

Max avg current:

Max avg current:
Max peak current:

1.5V S0 FET

Input: 2.4V to 5.5V

3V3 S0 SSD

Max peak current:

Max avg current:

Max peak current:

Max peak current:

4.8 A (budget)

1.7 A (budget)

0.85 A (budget)

1.48 A (budget)

1.26 A (budget)

2.08 A (budget)3.03 A (budget)

2.12 A (budget)

Max avg current:

1.82 A (budget)

3.3V S0 FET

1.27 A (budget)

4nF corresponds to

0.1UF

X5R

10%

402

16V

60
70

6

70

X5R

10%

0.1UF

402

16V

6

6

X5R

16V

10%

402

0.1UF

402

MF-LF

5%

10K

1/16W

28 60

TDFN

SLG5AP026

1/10W

5%

MF-LF

100

603

X5R
603

16V

10%

1UF

5%
1/16W
MF-LF

402

10K

100K

5%
1/16W
MF-LF
402

6

60

60

SLG5AP439

TDFN

DIRECTFET_S3C

IRF6892STR1PBFIRF6892STR1PBF

DIRECTFET_S3C

60 41 60 70

402

25V
X7R

0.01UF

10%

X7R

25V

10%

0.01UF

402

6

70

6

6

70

DFN

SLG5AP004

CRITICAL

10%

402

CERM

25V

0.0047UF

6

16V

SSD

402

10%

0.1UF

X5R

25V
402

10%

SSD

0.0047UF

CERM

41 60 70

60

74LVC2G08GT

SOT833

60 70

41 60 70

60

60

X5R

10%

0.1UF

402

16V

CRITICAL

SSD

TDFN

SLG5AP304V

CRITICAL

TDFN

SLG5AP304V

FET-Controlled S0 and S4

SYNC_DATE=01/04/2012

SYNC_MASTER=D7_NICK

PP5V_S0_FET

P12V_S0_FET_GATE

PM_PGOOD_FET_P12V_S0

PM_EN_FET_VDDQ_S0

PP1V5_S0_FET

=PP12V_S5_PWRCTL

=PP3V3_S0_PWRCTL

FET_RAMP_P3V3_S0

=PP3V3_S5_FET_P3V3_S0

PP3V3_S0_FET

PM_EN_FET_P3V3_S0

PP3V3_S4_FET

=PP3V3_S5_FET_P3V3_S4

FET_RAMP_P3V3_S4

=PP3V3_S4_PWRCTL

=PP5V_S5_PWRCTL

PM_PGOOD_FET_VDDQ_S0

=PPVDDQ_S3_FET_VDDQ_S0

P1V5_S0_FET_GATE

=PP3V3_S5_PWRCTL

PM_PGOOD_FET_P3V3_S0

PM_PGOOD_FET_P5V_S0

PP3V3_S0_FET

PM_EN_FET_P5V_S0

PM_EN_FET_P3V3_S0

PM_EN_FET_P3V3_S4

PM_EN_FET_P12V_S0

PP12V_S0_FET

=PP12V_G3H_FET_P12V_S0

FET_VCC_U7950

MIN_LINE_WIDTH=0.3mm
VOLTAGE=12V

MIN_NECK_WIDTH=0.15mm

P3V3_S0_SSD_FET_RAMP

PM_EN_FET_P3V3_S0

PP3V3_S0_SSD_FET

=PP3V3_S5_FET_P3V3_S0

=PP3V3_S5_PWRCTL

P5V_S0_FET_RAMP

PM_EN_FET_P5V_S0

PP5V_S0_FET

=PP5V_S4_FET_P5V_S0

=PP5V_S4_PWRCTL

C7920

1

2

C7900

1

2

C7930

1

2

R7930

1

2

U7950

5

6

7

4

2

8

9

1

R7950

1 2

C7950

1

2

R7952

1

2

R7951

1

2

U7900

4

12

10

11

1

13

6

8

3

5

15

Q7950

1

2

8

7

4

3

5

6

Q7930

1

2

8

7

4

3

5

6

C7902

1

2

C7901

1

2

U7930

5

7

4

2

8

6

9

1

C7921

1

2

C7910

1

2

C7911

1

2

U7940

1

5

2

6

4

8

7

3

C7940

1

2

U7910

7 3

8

2 5

1

U7920

7 3

8

2 5

1

051-9509

4.2.0

79 OF 113
70 OF 100

3

3

6

70

6

60 61

6

80

6

6

67

6

6

60 61 70 78

6

70

6

6

70

6

60 61 70 78

6

6

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

PEX_SVDD_3V3

PEX_TX0*

PEX_TX0PEX_RX0

PEX_RX1

PEX_RX6*

PEX_REFCLK*

PEX_WAKE*

PEX_CLKREQ*

PEX_RST*

PEX_REFCLK

PEX_RX15
PEX_RX15*

PEX_RX14*

PEX_RX14

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7
PEX_RX7*

PEX_RX6

PEX_RX5
PEX_RX5*

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2
PEX_RX2*

PEX_RX1*

PEX_TSTCLK_OUT*

PEX_TERMP

PEX_TX15

PEX_TX15*

PEX_TSTCLK_OUT

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX13

PEX_TX12

PEX_TX12*

PEX_TX11

PEX_TX11*

PEX_TX10

PEX_TX10*

PEX_TX9*

PEX_TX8*

PEX_TX9

PEX_TX8

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2

PEX_TX2*

PEX_TX1*

PEX_TX1

PEX_TX4*

PEX_RX0*

PEX_RX13*

PEX_RX13

PEX_TX7*

(1 OF 10)

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Polarity swaps intended on Lanes 0, 5, 8, 9, and 11.

Polarity swapped!!

Polarity swapped!!

BOM options provided by this page:

(NONE)

(NONE)

Signal aliases required by this page:

Polarity swapped!!

Page Notes

- =PP3V3_GPU_VDD33

Power aliases required by this page:

Polarity swapped!!

Polarity swapped!!

Polarity swapped!!

Polarity swapped!!

Polarity swapped!!

Polarity swapped!!

Polarity swapped!!

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

GND_VOID=TRUE

6.3V X5R 020120%

0.22UF

26 78

15 18

9

89

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

9

89

GND_VOID=TRUE

X5R 0201

0.22UF

20% 6.3V

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

GND_VOID=TRUE

6.3V X5R 020120%

0.22UF

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

0.22UF

20% 0201X5R6.3V

GND_VOID=TRUE

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

GND_VOID=TRUE

0.22UF

20% 0201X5R6.3V

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

GND_VOID=TRUE

0.22UF

20% 0201X5R6.3V

20% X5R6.3V

GND_VOID=TRUE

0.22UF

0201

NV-GK107

BGA

OMIT_TABLE

1/20W1%201

MF

200

NOSTUFF

2.49K

201

1%

1/20W

MF

MF 5%

1/20W

201

0

GND_VOID=TRUE

20% 0201X5R6.3V

0.22UF

20% 0201X5R6.3V

GND_VOID=TRUE

0.22UF

20% 0201X5R6.3V

GND_VOID=TRUE

0.22UF

20% 0201X5R6.3V

0.22UF

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

9

89

9

89

9

89

9

89

9

89

9

89

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

02016.3V

GND_VOID=TRUE

X5R

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20%

0.22UF

02016.3V X5R

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20% 02016.3V

0.22UF

X5R

GND_VOID=TRUE

20% 0201X5R6.3V

GND_VOID=TRUE

0.22UF

20% 02016.3V X5R

GND_VOID=TRUE

0.22UF

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

20% 0201X5R6.3V

0.22UF

GND_VOID=TRUE

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

20% 02016.3V X5R

0.22UF

GND_VOID=TRUE

0.22UF

0201X5R

GND_VOID=TRUE

6.3V20%

20% 0201X5R6.3V

GND_VOID=TRUE

0.22UF

0201X5R6.3V

GND_VOID=TRUE

0.22UF

20%

20% 02016.3V

GND_VOID=TRUE

X5R

0.22UF

20%

0.22UF

0201

GND_VOID=TRUE

6.3V X5R

GND_VOID=TRUE

0.22UF

20% 0201X5R6.3V

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

X5R6.3V20%

0.22UF

0201

GND_VOID=TRUE

20%

0.22UF

X5R6.3V

GND_VOID=TRUE

0201

X5R20%

0.22UF

02016.3V

GND_VOID=TRUE

0.22UF

20% 0201X5R

GND_VOID=TRUE

6.3V

0.22UF

GND_VOID=TRUE

20% 0201X5R6.3V

20%

0.22UF

0201X5R6.3V

GND_VOID=TRUE

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

9

89

18 89

18 89

9

89

9

89

KEPLER PCI-E

SYNC_MASTER=D7_TONY

SYNC_DATE=01/10/2012

PEG_R2D_C_N<6>

PEG_R2D_N<0>

PEG_R2D_P<0>

PEG_R2D_N<2>

PEG_R2D_N<4>

PEG_R2D_N<5>

PEG_R2D_N<13>

PEG_R2D_N<10>

PEG_R2D_P<9>

PEG_R2D_N<9>

PEG_R2D_P<8>

PEG_R2D_N<8>

PEG_D2R_C_N<8>

PEG_R2D_C_N<15>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_C_P<13>

PEG_D2R_N<7>

PEG_D2R_P<6>

PEG_D2R_C_N<9>

PEG_D2R_C_P<10>

PEG_D2R_P<0>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_N<4>

PEG_D2R_N<5>

PEG_D2R_N<0>

DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK1_EG_AUXCH_P

PEG_D2R_C_P<15>

PEG_R2D_C_P<11>

PEG_D2R_P<4>

PEG_R2D_P<12>

PEG_D2R_C_N<12>

PEG_D2R_C_N<13>

PEG_D2R_C_P<14>

PEG_D2R_P<15>

=PP3V3_GPU_VDD33

PEX_TSTCLK_O_PL

PEX_TSTCLK_O_NG

PEG_CLK100M_N

PEG_CLK100M_P

PEG_R2D_N<14>

PEG_R2D_N<11>

PEG_R2D_N<10>

PEG_D2R_C_P<15>

PEG_R2D_N<12>

PEG_D2R_C_N<4>

PEG_D2R_C_P<4>

PEG_R2D_P<10>

PEG_R2D_P<15>

PEG_R2D_P<4>

PEG_D2R_C_N<3>

PEG_D2R_C_P<3>

PEG_D2R_C_P<6>

PEG_R2D_P<7>

PEG_R2D_C_P<1>

PEG_R2D_C_P<4>

PEG_R2D_C_N<5>

PEG_R2D_C_P<10>

PEG_R2D_N<6>

PEG_CLKREQ_L

GPU_RESET_R_L

PEG_R2D_N<15>

PEG_R2D_P<14>

PEG_R2D_P<12>

PEG_R2D_N<9>

PEG_R2D_P<9>

PEG_R2D_P<7>

PEG_R2D_P<6>

PEG_R2D_P<5>

PEG_R2D_N<3>

PEG_R2D_P<2>

PEG_R2D_N<2>

PEG_R2D_N<1>

PEG_D2R_C_N<15>

PEG_D2R_C_N<14>

PEG_D2R_C_P<14>

PEG_D2R_C_N<13>

PEG_D2R_C_P<13>

PEG_D2R_C_P<12>

PEG_D2R_C_N<12>

PEG_D2R_C_P<11>

PEG_D2R_C_N<11>

PEG_D2R_C_P<10>

PEG_D2R_C_N<10>

PEG_D2R_C_N<9>

PEG_D2R_C_P<8>

PEG_D2R_C_P<7>

PEG_D2R_C_N<6>

PEG_D2R_C_N<5>

PEG_D2R_C_P<5>

PEG_D2R_C_P<2>

PEG_D2R_C_N<2>

PEG_D2R_C_N<1>

PEG_D2R_C_P<1>

PEG_D2R_P<10>

PEG_R2D_P<5>

PEG_R2D_C_P<15>

PEG_D2R_C_N<6>

PEG_D2R_C_N<14>

PEG_D2R_N<12>

PEG_D2R_N<9>

PEG_D2R_C_N<15>

PEG_R2D_C_N<3>

PEG_R2D_C_P<3>

PEG_R2D_N<3>

PEG_D2R_N<15>

PEG_R2D_C_N<9>

PEG_D2R_C_P<8>

PEG_R2D_C_N<12>

PEG_R2D_P<6>

PEG_R2D_C_P<6>

PEG_D2R_C_P<12>

PEG_D2R_P<13>

PEG_D2R_C_P<6>

PEG_D2R_P<5>

PEG_D2R_C_P<3>

PEG_D2R_C_N<1>

PEG_D2R_N<1>

PEG_D2R_C_P<2>

PEG_D2R_P<2>

PEG_D2R_C_N<2>

PEG_D2R_N<2>

PEG_D2R_P<1>

PEG_R2D_C_N<7>

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_C_N<2>

PEG_R2D_P<4>

PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_N<4>

PEG_R2D_P<13>

GPU_RESET_L

PEG_D2R_C_N<3>

PEG_D2R_C_P<4>

PEG_D2R_C_N<4>

PEG_D2R_C_N<5>

PEG_R2D_P<1>

PEG_R2D_N<0>

PEG_R2D_P<13>

PEG_R2D_N<8>

PEG_R2D_P<3>

PEG_R2D_P<0>

PEG_R2D_N<5>

PEG_R2D_N<6>

PEG_R2D_N<11>

PEG_R2D_C_N<8>

PEG_R2D_P<8>

PEG_R2D_N<7>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

PEG_R2D_P<11>

PEG_R2D_P<10>

PEG_R2D_P<14>

PEG_R2D_N<13>

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_C_N<1>

PEG_R2D_C_P<2>

GPU_PEX_TERMP

PEG_R2D_N<4>

PEG_R2D_P<11>

PEG_R2D_C_P<8>

PEG_R2D_C_P<9>

PEG_R2D_C_P<13>

PEG_R2D_C_N<13>

PEG_R2D_C_N<14>

PEG_R2D_C_P<14>

PEG_R2D_N<12>

PEG_R2D_C_N<11>

PEG_R2D_C_P<12>

PEG_D2R_C_N<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<11>

PEG_D2R_C_N<11>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_N<14>

PEG_D2R_N<6>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

PEG_D2R_C_P<1>

PEG_D2R_C_P<7>

PEG_D2R_P<7>

PEG_D2R_C_P<5>

PEG_D2R_C_N<7>

DP_TBTSNK0_EG_AUXCH_P

DP_TBTSNK0_EG_AUXCH_N

PEG_D2R_C_N<7>

PEG_D2R_C_N<8>

PEG_D2R_C_P<9>

PEG_R2D_P<15>

PEG_D2R_P<8>

PEG_R2D_N<7>

PEG_R2D_P<1>

PEG_R2D_P<2>

PEG_R2D_P<3>

PEG_R2D_C_N<10>

PEG_R2D_N<1>

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

C8020

1 2

C8021

1 2

C8022

1 2

C8023

1 2

C8024

1 2

C8025

1 2

C8026

1 2

C8027

1 2

C8028

1 2

C8029

1 2

C8030

1 2

C8031

1 2

C8032

1 2

C8033

1 2

C8034

1 2

C8035

1 2

C8056

1 2

C8057

1 2

C8058

1 2

C8059

1 2

C8060

1 2

C8061

1 2

C8063

1 2

C8064

1 2

C8065

1 2

C8066

1 2

C8068

1 2

C8069

1 2

C8070

1 2

C8062

1 2

C8067

1 2

C8055

1 2

U8000

AK12

AL13
AK13

AJ12

AN12

AM12

AN14
AM14

AN23
AM23

AP23

AP24

AN24

AM24

AN26

AM26

AP26

AP27

AN27

AM27

AP14
AP15

AN15
AM15

AN17

AM17

AP17

AP18

AN18

AM18

AN20

AM20

AP20
AP21

AN21
AM21

AG12

AP29

AJ26
AK26

AK14

AJ14

AH14
AG14

AK21
AJ21

AL22

AK22

AK23

AJ23

AH23

AG23

AK24

AJ24

AL25

AK25

AK15
AJ15

AL16
AK16

AK17

AJ17

AH17

AG17

AK18

AJ18

AL19

AK19

AK20
AJ20

AH20
AG20

AJ11

R8002

1 2

R8005

1 2

R8000

1 2

C8039

1 2

C8036

1 2

C8037

1 2

C8038

1 2

C8040

1 2

C8041

1 2

C8043

1 2

C8042

1 2

C8045

1 2

C8044

1 2

C8046

1 2

C8048

1 2

C8047

1 2

C8050

1 2

C8049

1 2

C8051

1 2

C8071

1 2

C8073

1 2

C8072

1 2

C8076

1 2

C8075

1 2

C8074

1 2

C8078

1 2

C8077

1 2

C8080

1 2

C8079

1 2

C8082

1 2

C8081

1 2

C8083

1 2

C8085

1 2

C8084

1 2

C8086

1 2

051-9509

4.2.0

80 OF 113
71 OF 100

71 89

71 89

71 89

71 89

71 89 71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

77

77

71 89

71 89

71 89

71 89

71 89

6

77 78 79

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89 71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

77

77

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

71 89

34 98

34 98 34 98

34 98

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

XVDD

VDD

VDD

(10 OF 10)

FBVDDQFBVDDQ

(7 OF 10)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM options provided by this page:

Signal aliases required by this page:

(NONE)

(NONE)

Page Notes

- =PP1V35_GPU_FBVDDQ

- =PPVCORE_GPU

Power aliases required by this page:

EDP = 6500 MA

GPU FB DE-COUPLING

GPU VCORE DE-COUPLING

EDP = 30 A

1UF

10%

0603

X7R

25V25V
X7R
0603

1UF

10%

4V
X5R
0402

20%

22UF

X5R

20%

0402

4V

22UF

20%

X5R

6.3V

0603

22UF

4.7UF

X6S-CERM

10%
4V

0603

4.7UF

4V

0603

10%

X6S-CERM

0.1UF

10%
16V

402

X7R-CERM

0.1UF

16V

10%

402

X7R-CERM

0.1UF

10%
16V

402

X7R-CERM

0.1UF

10%
16V

402

X7R-CERM

0.1UF

10%

402

16V
X7R-CERM X7R-CERM

10%

0.1UF

402

16V

0.1UF

10%
16V
X7R-CERM
402

4.7UF

10%

0603

X6S-CERM

4V

0603

X6S-CERM

4.7UF

10%
4V 4V

0603

10%

4.7UF

X6S-CERM4VX6S-CERM

0603

4.7UF

10%

4V
X6S-CERM
0603

10%

4.7UF

X6S-CERM

4V

0603

10%

4.7UF

402

X5R-CERM1

20%

6.3V

4.7UF

X5R-CERM1

4.7UF

20%

402

6.3V

NV-GK107

BGA

OMIT_TABLE

NV-GK107

BGA

OMIT_TABLE

X5R-CERM

47UF

0805

20%

6.3V

10%

0603

X7R

25V

1UF

4.7UF

20%

6.3V
X5R-CERM1
402

X5R-CERM1
402

4.7UF

20%

6.3V

4.7UF

402

20%

6.3V
X5R-CERM1

6.3V
X5R-CERM1
402

20%

4.7UF

16V

0.1UF

10%

X7R-CERM

402

0603

X6S-CERM

4.7UF

10%
4V

X6S-CERM

4V

0603

10%

4.7UF

10%

402

X7R-CERM

16V

0.1UF

16V

402

10%

X7R-CERM

0.1UF

10%
16V

402

0.1UF

X7R-CERM

402

0.1UF

10%

X7R-CERM

16V

4.7UF

402

20%

6.3V
X5R-CERM1

1UF

16V
X5R
603

10%

20%

47UF

0805

X6S

4V 4V

X6S-CERM
0603

22UF

20%20%

22UF

0603

X6S-CERM

4V

4.7UF

402

20%

6.3V
X5R-CERM1

4.7UF

20%

X5R-CERM1
402

6.3V

20%

402

10UF

X5R

4V

402

X5R

20%

10UF

4V

KEPLER CORE/FB POWER

SYNC_MASTER=D7_TONY

SYNC_DATE=01/10/2012

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ =PP1V35_GPU_FBVDDQ

=PPVCORE_GPU

=PPVCORE_GPU

=PPVCORE_GPU

C8102

1

2

C8101

1

2

C8112

1

2

C8111

1

2

C8125

1

2

C8126

1

2

C8162

1

2

C8181

1

2

C8185

1

2

C8191

1

2

C8192

1

2

C8193

1

2

C8194

1

2

C8122

1

2

C8123

1

2

C8124

1

2

C8171

1

2

C8172

1

2

C8173

1

2

C8175

1

2

C8176

1

2

C8177

1

2

C8166

1

2

C8167

1

2

U8000

AA12

AB18
AB20

AB22

AC12
AC14

AC16

AC19
AC21

AC23

M12

AA14

M14

M16
M19

M21

M23
N13

N15

N17
N18

N20

AA16

N22
P12

P14
P16

P19

P21
P23

R13

R15
R17

AA19

R18

R20
R22

T12
T14

T16

T19
T21

T23

U13

AA21

U15

U17

U18
U20

U22
V13

V15

V17

V18
V20

AA23

V22

W12
W14

W16

W19
W21

W23
Y13

Y15

Y17

AB13

Y18

Y20

Y22

AB15
AB17

U1

V2

V3

V4
V5

V6
V7

V8

W2
W3

W4

U2

W5
W7

W8

Y1
Y2

Y3
Y4

Y5

Y6
Y7

U3

Y8

AA1
AA2

AA3

AA4
AA5

AA6
AA7

AA8

U4

U5

U6
U7

U8

V1

U8000

AA27

B13
B16

B19
E13

E16

E19
H10

H11

H12
H13

AA30

H14

H15
H16

H18
H19

H20

H21
H22

H23

H24

AB27

H8

H9

L27
M27

N27
P27

R27

T27
T30

T33

AB33

V27
W27

W30

W33
Y27

AC27

AD27

AE27
AF27

AG27

C8161

1

2

C8113

1

2

C8105

1

2

C8106

1

2

C8107

1

2

C8168

1

2

C8130

1

2

C8180

1

2

C8178

1

2

C8182

1

2

C8199

1

2

C8198

1

2

C8183

1

2

C8132

1

2

C8131

1

2

C8184

1

2

C8179

1

2

C8174

1

2

C8170

1

2

C8169

1

2

051-9509

4.2.0

81 OF 113
72 OF 100

6

72 75 76

6

72 75 76

6

72 75 76

6

72 79

6

72 79

6

72 79

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN
IN
IN
IN
IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI

BI
BI

BI
BI

IN
IN
IN
IN
IN
IN
IN
IN

NC
NC
NC
NC
NC
NC

NC

NC

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

NC

NC

NC

NC

NC

NC

NC
NC

NC
NC

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC

OUT

OUT

OUT
OUT

OUT

OUT

OUT
OUT

NC

NC

NC
NC

NC
NC

NC
NC

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT
OUT

D

GS

IN

OUT

FBA_CMD5

FBA_CMD0

FBA_CLK1*

FBA_CLK1

FBA_CLK0*

FB_GND_SENSE

FBA_WCKB67

FBA_D0

FBA_WCKB67*

FBA_WCKB45*

FBA_WCKB23*

FBA_WCKB45

FBA_WCKB01*

FBA_WCKB23

FBA_WCK67*

FBA_WCKB01

FBA_WCK67

FBA_WCK45*

FBA_WCK23*

FBA_WCK45

FBA_WCK01*

FBA_WCK23

FBA_WCK01

FBA_D63

FBA_D62

FBA_D60
FBA_D61

FBA_D57
FBA_D58
FBA_D59

FBA_D56

FBA_D55

FBA_D54

FBA_D52
FBA_D53

FBA_D50
FBA_D51

FBA_D47

FBA_D49

FBA_D48

FBA_D45
FBA_D46

FBA_D42
FBA_D43
FBA_D44

FBA_D40
FBA_D41

FBA_D39

FBA_D37
FBA_D38

FBA_D34
FBA_D35
FBA_D36

FBA_D32
FBA_D33

FBA_D31

FBA_D30

FBA_D29

FBA_D27
FBA_D28

FBA_D24
FBA_D25
FBA_D26

FBA_D22

FBA_D19
FBA_D20

FBA_D16
FBA_D17
FBA_D18

FBA_D14
FBA_D15

FBA_D11
FBA_D12
FBA_D13

FBA_D9
FBA_D10

FBA_D8

FBA_D7

FBA_D6

FBA_D4
FBA_D5

FBA_D3

FBA_D2

FBA_D1

FB_VDDQ_SENSE

FBA_CMD_RFU

FB_CLAMP

FBA_CMD_RFU

FB_CAL_PU_GND

FB_CAL_TERM_GND

FBA_DEBUG

FB_CAL_PD_VDDQ

FBA_PLL_AVDD

FBA_DEBUG

FBA_DQS_WP7

FB_DLL_AVDD

FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6

FBA_DQS_WP3

FBA_DQS_WP2

FBA_DQS_WP1

FBA_DQS_WP0

FBA_DQS_RN7

FBA_DQS_RN6

FBA_DQS_RN5

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN1
FBA_DQS_RN2

FBA_DQS_RN0

FBA_DQM7

FBA_DQM5
FBA_DQM6

FBA_DQM4

FBA_DQM3

FBA_DQM2

FBA_DQM0
FBA_DQM1

FBA_CLK0

FBA_CMD31

FBA_CMD29
FBA_CMD30

FBA_CMD27
FBA_CMD28

FBA_CMD24
FBA_CMD25
FBA_CMD26

FBA_CMD22
FBA_CMD23

FBA_CMD21

FBA_CMD19
FBA_CMD20

FBA_CMD16
FBA_CMD17
FBA_CMD18

FBA_CMD14
FBA_CMD15

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD4

FBA_CMD1

FBA_CMD3

FBA_CMD2

FBA_D23

FBA_D21

FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9

FBA_CMD10

(3 OF 10)

MEM INTERFACE A

FBB_CMD31

FBB_CMD10

FBB_CMD14

FBB_CMD24
FBB_CMD25

FBB_CMD_RFU1

FBB_CMD_RFU0

FBB_D12

FBB_D10

FBB_D7

FBB_D1
FBB_D2
FBB_D3

FBB_CMD16

FBB_DQS_RN4

FBB_DQM4

FBB_CLK1

FBB_CMD22

FBB_CLK0

FBB_CLK0*

FBB_CLK1*

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9

FBB_CMD11
FBB_CMD12
FBB_CMD13

FBB_CMD15

FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21

FBB_CMD23

FBB_CMD26
FBB_CMD27

FBB_CMD29
FBB_CMD30

FBB_D0

FBB_D4
FBB_D5
FBB_D6

FBB_D8
FBB_D9

FBB_D11

FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29

FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63

FBB_DEBUG0
FBB_DEBUG1

FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3

FBB_DQM5
FBB_DQM6
FBB_DQM7

FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3

FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7

FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7

FBB_PLL_AVDD

FBB_WCK01
FBB_WCK01*

FBB_WCK23
FBB_WCK23*

FBB_WCK45
FBB_WCK45*

FBB_WCK67
FBB_WCK67*

FBB_WCKB01*

FBB_WCKB23
FBB_WCKB23*

FBB_WCKB45
FBB_WCKB45*

FBB_WCKB67
FBB_WCKB67*

FB_VREF

FBB_WCKB01

FBB_D31

FBB_D30

FBB_CMD28

(4 OF 10)

MEM INTRERFACE B

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ESR = 0.05OHM

ESR = 0.05OHM

(NONE)

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V35_GPU_S0_FB

- =PP1V05_GPU_PEX_IOVDD

Power aliases required by this page:

(NONE)

Page Notes

NOTE:GDDR5 MODE H MAPPING

PLACE CLOSE TO BGA

FB VREF GEN (TEST ONLY)

FB PLL & DLL VDD

MEM VREFC & VREFD SWITCH

75 99

75 99

75 99

75 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

0.1UF

10%

X5R

NOSTUFF

PLACE_NEAR=U8000.H26:8.4MM

6.3V

201

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

PLACE_NEAR=U8000.H25:8.4MM

MF

201

1%

1/20W

60.4

PLACE_NEAR=U8000.H27:8.4MM

201

MF

1%
1/20W

40.2

PLACE_NEAR=U8000.J27:8.4MM

40.2

201

MF

1/20W

1%

NOSTUFF

60.4

MF
201

1/20W

1%

NOSTUFF

1/20W

1%

MF
201

60.4

22UF

20%

402

4V
X5R

402

X7R-CERM

16V

10%

0.1UF

1UF

20%

6.3V

0201

X5R

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

10K

1%
1/20W
MF
201

10K

1%
1/20W
MF
201

MF

1/20W

201

1%

10K

1/20W

10K

MF
201

1%

76 99

76 99

76 99

76 99

X5R

10%

6.3V

201

0.1UF

0201

X5R

1UF

6.3V

20%

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

NOSTUFF

60.4

201

1%
1/20W
MF

NOSTUFF

60.4

1%
1/20W

201

MF

201

MF

1%

10K

1/20W1/20W

1%

10K

201

MF

PLACE_NEAR=U8000.H26:8.4MM

MF

NOSTUFF

1.33K

1%
1/20W

201

MF
201

1/20W

1%

1.33K

NOSTUFF

PLACE_NEAR=U8000.H26:8.4MM

201

10K

MF 1%

1/20W

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

73 75 99

73 75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

75 99

73 75 99

73 75 99

75 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

73 76 99

73 76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

76 99

73 76 99

76 99

73 76 99

76 99

VESM

SSM3K15AMFVAPE

CRITICAL

78

75 76

4V

402

22UF

20%

X5R

1UF

0201

X5R

20%

6.3V

16V
X7R-CERM
402

10%

0.1UF

NOSTUFF

100

1/20W
MF
201

5%

100

NOSTUFF

201

MF

5%
1/20W

NV-GK107

OMIT_TABLE

BGA

NV-GK107

OMIT_TABLE

BGA

16V
X7R-CERM
402

0.1UF

10%

10K

1%

MF

1/20W

201

10K

201

MF

1/20W

1%

74 97

74 97

30-OHM-25%-5A-0.01-OHM

CRITICAL

0603

30-OHM-25%-5A-0.01-OHM

0603

CRITICAL

5%

10K

1/20W
MF
201

KEPLER FRAME BUFFER I/F

SYNC_MASTER=D7_TONY

SYNC_DATE=01/10/2012

FB_A0_DQ<8>

FB_B1_DQ<27>

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

PP1V05_GPU_FB_DLL_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_GPU_FB_PLL_AVDD

SNS_GPUVDDQ_P

=PP1V35_GPU_S0_FB

SNS_GPUVDDQ_N

GPU_FBA_DEBUG1

GPU_FBA_DEBUG0

FB_CAL_TERM_GND

FB_A1_WCLK_P<0>

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B0_CKE_L

=PP1V35_GPU_S0_FB

FB_B1_RESET_L

FB_A1_CKE_L

FB_B0_RESET_L

FB_B0_RESET_L

FB_A1_DQ<4>

FB_A1_DQ<6>

FB_A1_DQ<11>

FB_A1_DQ<14>

FB_A0_DBI_L<2>

=PP1V35_GPU_S0_FB

FB_CAL_PU_GND

FB_CLAMP

FB_B1_DQ<3>

GPU_FBB_DEBUG0
GPU_FBB_DEBUG1

FB_A0_DQ<6>

FB_A1_A<4>
FB_A1_A<5>

FB_A1_A<7>

=PP1V35_GPU_S0_FB

FB_A0_CKE_L

FB_B0_DQ<9>

FB_B0_DQ<8>

FB_A0_WE_L

FB_A0_A<5>

FB_A0_A<4>

FB_A0_A<2>

FB_A0_A<3>

FB_A0_CS_L

FB_A0_CKE_L

FB_A0_CAS_L

FB_A0_DBI_L<1>

FB_A0_EDC<0>

FB_B1_A<0>

FB_B1_A<1>

FB_A1_WE_L

FB_A0_DQ<16>
FB_A0_DQ<17>

FB_A0_ABI_L

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_DQ<20>

FB_A0_DQ<23>

FB_A0_DQ<28>

FB_A0_RESET_L

FB_VREF

=PP1V35_GPU_S0_FB

=PP1V35_GPU_S0_FB

FB_A1_RESET_L

FB_A0_A<8>

FB_A0_A<6>

FB_A0_A<7>

FB_A0_DQ<21>

FB_A0_A<1>
FB_A0_RAS_L

FB_A0_RESET_L

FB_A1_A<2>

FB_A1_A<3>

FB_A1_CS_L

FB_A1_A<0>

FB_A1_A<8>

FB_A1_ABI_L

FB_A1_RAS_L

FB_A1_A<1>

FB_A1_CKE_L

FB_A1_RESET_L

FB_A0_DBI_L<0>

FB_A0_DBI_L<3>

FB_A1_DBI_L<0>

FB_A1_DBI_L<1>

FB_A1_DBI_L<3>

FB_A0_EDC<1>
FB_A0_EDC<2>

FB_A0_EDC<3>
FB_A1_EDC<0>

PP1V05_GPU_FB_DLL_AVDD

FB_A1_EDC<3>

PP1V05_GPU_FB_PLL_AVDD

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_A0_DQ<2>
FB_A0_DQ<3>

FB_A0_DQ<5>

FB_A0_DQ<4>

FB_A0_DQ<13>

FB_A0_DQ<12>

FB_A0_DQ<15>

FB_A0_DQ<14>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<22>

FB_A0_DQ<24>

FB_A0_DQ<27>

FB_A0_DQ<29>

FB_A0_DQ<30>
FB_A0_DQ<31>

FB_A1_DQ<1>

FB_A1_DQ<0>

FB_A1_DQ<3>

FB_A1_DQ<2>

FB_A1_DQ<5>

FB_A1_DQ<7>

FB_A1_DQ<9>

FB_A1_DQ<8>

FB_A1_DQ<12>

FB_A1_DQ<10>

FB_A1_DQ<13>

FB_A1_DQ<16>

FB_A1_DQ<17>

FB_A1_DQ<15>

FB_A1_DQ<19>

FB_A1_DQ<18>

FB_A1_DQ<21>

FB_A1_DQ<20>

FB_A1_DQ<22>

FB_A1_DQ<23>
FB_A1_DQ<24>

FB_A1_DQ<27>

FB_A1_DQ<26>

FB_A1_DQ<25>

FB_A1_DQ<29>

FB_A1_DQ<28>

FB_A1_DQ<31>

FB_A0_WCLK_P<0>

FB_A0_WCLK_P<1>

FB_A0_WCLK_N<0>

FB_A0_WCLK_N<1>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

FB_A0_CLK_N

FB_A1_CLK_P

FB_B0_DQ<30>

FB_B0_DQ<31>

FB_B1_WCLK_N<1>

FB_B1_WCLK_P<1>

FB_B1_WCLK_P<0>

FB_B0_WCLK_N<1>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<0>

FB_B1_EDC<2>

FB_B1_EDC<1>

FB_B1_EDC<0>

FB_B0_EDC<3>

FB_B0_EDC<2>

FB_B0_EDC<1>

FB_B0_EDC<0>

FB_B1_DBI_L<3>

FB_B1_DBI_L<2>

FB_B0_DBI_L<2>

FB_B0_DBI_L<1>

FB_B0_DBI_L<0>

GPU_FBB_DEBUG1

FB_B1_DQ<30>

FB_B1_DQ<29>

FB_B1_DQ<28>

FB_B1_DQ<26>

FB_B1_DQ<25>

FB_B1_DQ<24>

FB_B1_DQ<23>

FB_B1_DQ<22>

FB_B1_DQ<21>

FB_B1_DQ<20>

FB_B1_DQ<17>

FB_B1_DQ<16>

FB_B1_DQ<9>

FB_B1_DQ<8>

FB_B1_DQ<7>

FB_B1_DQ<6>

FB_B1_DQ<5>

FB_B1_DQ<2>

FB_B1_DQ<1>

FB_B1_DQ<0>

FB_B0_DQ<29>

FB_B0_DQ<28>

FB_B0_DQ<27>

FB_B0_DQ<26>

FB_B0_DQ<24>

FB_B0_DQ<23>

FB_B0_DQ<22>

FB_B0_DQ<20>

FB_B0_DQ<19>

FB_B0_DQ<18>

FB_B0_DQ<17>

FB_B0_DQ<16>

FB_B0_DQ<15>

FB_B0_DQ<14>

FB_B0_DQ<13>

FB_B0_DQ<11>

FB_B0_DQ<6>

FB_B0_DQ<5>

FB_B0_DQ<4>

FB_B0_DQ<0>

FB_B1_CKE_L

FB_B1_RESET_L

FB_B1_WE_L

FB_B1_A<5>

FB_B1_A<4>

FB_B1_A<2>

FB_B1_A<3>

FB_B0_A<8>

FB_B0_ABI_L

FB_B0_WE_L

FB_B0_A<3>

FB_B0_CS_L

FB_B1_CLK_N

FB_B0_CLK_N

FB_B0_CLK_P

FB_B1_A<7>

FB_B1_CLK_P

FB_B1_CS_L

FB_B0_DQ<3>

FB_B0_DQ<2>

FB_B0_DQ<1>

FB_B0_DQ<7>

FB_B0_DQ<10>

FB_B0_DQ<12>

FB_B1_A<8>

FB_B1_ABI_L

FB_B0_CKE_L

FB_B1_CAS_L

FB_A1_DQ<30>

FB_CAL_PD_VDDQ

FB_B1_DQ<19>

FB_B1_DQ<18>

PP1V05_GPU_FB_PLL_AVDD

FB_B1_DQ<15>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_A0_DQ<25>

FB_A1_CLK_N

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A0_DQ<26>

FB_B0_DQ<25>

FB_B0_A<0>

FB_B0_A<6>

FB_B0_A<7>

FB_B0_A<5>

FB_B0_A<4>

FB_B0_A<2>

FB_B1_DQ<10>

GPU_FBB_DEBUG0

FB_VREF

FB_B1_RAS_L

FB_B0_DQ<21>

FB_A0_DQ<9>

FB_A0_DQ<7>

FB_A1_DBI_L<2>

FB_A1_CAS_L

FB_B1_DQ<12>

FB_A0_CLK_P

FB_A1_A<6>

FB_A0_DQ<0>

FB_B1_EDC<3>

FB_B0_A<1>

=PP1V05_GPU_PEX_IOVDD

=PP1V05_GPU_PEX_IOVDD

FB_B1_A<6>

FB_B0_RAS_L

FB_B0_CAS_L

FB_A0_DQ<1>

FB_SW_LEG

FB_B1_WCLK_N<0>

FB_B0_WCLK_P<1>

FB_B1_DQ<31>

FB_B1_DQ<11>

FB_B0_DBI_L<3>

FB_B1_CKE_L

GPU_ALT_VREF

FB_A0_A<0>

FB_B1_DQ<4>

C8260

1

2

R8201

1 2

R8204

1

2

R8205

1

2

R8202

1

2

R8203

1

2

C8201

1

2

C8203

1

2

C8202

1

2

R8250

1

2

R8251

1

2

R8252

1

2

R8253

1

2

C8207

1

2

C8206

1

2

R8207

1

2

R8206

1

2

R8255

1

2

R8254

1

2

R8258

1

2

R8259

1

2

R8261

1 2

Q8265

3

1

2

C8208

1

2

C8209

1

2

C8205

1

2

R8270

1

2

R8271

1

2

U8000

J27
H27

H25

E1

K27

F2

F1

R30
R31

AB31
AC31

U30
T31

V30

U34
U31

V34

V33
Y32

AA31

AA29
AA28

AC34

U29

AC33
AA32

AA33
Y28

Y29

W31
Y30

AA34

Y31
Y34

R34

Y33

V31

R33

U32

U33
U28

V28

V29

R32

AC32

L28
M29

J29

H28
G29

E31

E32
F30

C34

D32
B33

C33

L29

F33
F32

H33
H32

P34

P32
P31

P33

L31
L34

M28

L32

L33
AG28

AF29
AG29

AF28

AD30
AD29

AC29

AD28

N31

AJ29

AK29

AJ30
AK28

AM29
AM31

AN29

AM30
AN31

AN32

P29

AP30
AP32

AM33

AL31
AK33

AK32
AD34

AD32

AC30
AD33

R29

AF31

AG34
AG32

AG33

P28

J28

H29

R28

AC28

P30
F31

F34

M32
AD31

AL29

AM32
AF34

M30

H30

E34
M34

AF30

AK31
AM34

AF32

M31

G31
E33

M33

AE31
AK30

AN33

AF33

U27

K31

L30

H34

J34

AG30

AG31

AJ34
AK34

J30

J31

J32
J33

AH31

AJ31

AJ32

AJ33

U8000

H26

D12
E12

E20

F20

D13

E14

D15

A14

D14
A15

B15

C17
D18

E18

F18
A20

F14

B20
C18

B18

G18
G17

F17

D16
A18

D17

A17

A12

B17

E17

B12
C14

B14

G15
F15

E15

C12

C20

G9

E9

E6

F6

F4
G4

E2

F3
C2

D4

D3
C1

G8

B3
C4

B5

C5
A11

C11

D11
B11

D8

A8

F9

C8

B8
F24

G23

E24
G24

D21

E21
G21

F21

F11

G27
D27

G26
E27

E29

F29
E30

D30

A32
C31

G11

C32

B32
D29

A29
C29

B29

B21
C23

A21

C21

F12

B24

C24

B26
C26

G12

G6

F5

G14

G20

E11

E3
A3

C9

F23
F27

C30
A24

D9
E4

B2

A9
D22

D28

A30
B23

D10

D5

C3
B9

E23

E28
B30

A23

H17

F8

E8

A5

A6

D24

D25

B27

C27

D6

D7

C6

B6

F26
E26

A26

A27

C8204

1

2

R8256

1

2

R8257

1

2

L8201

1 2

L8202

1 2

R8260

1

2

051-9509

4.2.0

82 OF 113
73 OF 100

73

73

6

73

73 76 99

6

73

73 76 99

73 75 99

73 76 99

6

73 73

73

73

6

73

73 75 99

73 75 99

73

6

73

6

73

73 75 99

73

73

73

73

73

73

73

73

73

6

73 79

6
73
79

73 76 99

BG

TGR

TG

PGND

VIN

VSW

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

IN

IN

OUT

OUT

PHASE

OUT

IN

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

IN

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Ra> <Ra>

3.43 A MAX OUTPUT

10 A MAX OUTPUT

1.35 V

F = 500 KHZ

Vout = 0.5 * (1 + Ra / Rb)

VID 0

GPIO_16 VID 1

GPU VDDQ SUPPLY

F = ??? KHZ

GPU VDDQ
0
0

1.5 V

1

0

<Rb>

<Ra>

<Rb>

<Ra>

Vout = 0.5V * (1 + Ra / Rb)

VOUT = 1.05V

VOUT = 1.5V / 1.35V

GPU 1V05 SUPPLY

<Rb> <Rb>

376S1038

To regulator:

0.1UF

X5R
402

10%
16V

603

MF-LF

1/10W

5%

OMIT_TABLE

1

MF-LF

402

5%

1/16W

1

5%

1000PF

NP0-C0G

402

25V

PLACE_NEAR=L8310.2:1.5MM

CRITICAL

SON

CSD598873D

10V

20%

603

X5R

10UF

CRITICAL

1/16W

5%

402

MF-LF

2.2

ISL95870

UTQFN

CRITICAL

SM

PLACE_NEAR=U8310.1:1mm

60

SIGNAL_MODEL=EMPTY

3.01K

MF-LF
402

1%
1/16W

SIGNAL_MODEL=EMPTY

1/16W

1%

MF-LF

402

3.01K

2.2UF

X5R
603

10%
16V

1/20W

5%

201

MF

0

NOSTUFF

0.047UF

X7R
402

10%
16V50V

5%

402

CERM

10PF

10PF

CERM

402

5%

50V

1/16W

1%

402

MF-LF

2.74K

1%

402

MF-LF

1/16W

2.74K

79 97

79 97

1/20W

1%

201

MF

6.98K

0402

X5R-X7R-CERM

16V

10%

0.022UF

6.98K

MF
201

1%
1/20W

SM

SM

61

MF-LF

5%

1/16W

10K

402

330UF-0.009OHM

CASE-D2-HF

PLACE_NEAR=L8310.2:3MM

20%

CRITICAL

2V

POLY

330UF-0.009OHM

CASE-D2-HF

CRITICAL

PLACE_NEAR=L8310.2:3MM

20%
2V
POLY

1.0UH-20%-15A-0.0065OHM

PIC0605H-SM

CRITICAL

6

X5R
603

20%

6.3V

10UF

ELEC

16V

20%

270UF

8X9-TH1

CRITICAL

CRITICAL

POLY

2V
CASE-D2-HF

20%

330UF-0.009OHM

CRITICAL

20%

CASE-D2-HF

POLY

2V

330UF-0.009OHM

MF-LF

1/10W

5%

200

603

1000PF

NP0-C0G

402

25V

5%

402

L8360.1:3MM

MF-LF

1/16W

1%

12.1K

MF-LF

1/16W
402

1%

12.1K

L8360.2:3MM

25V
X7R

10%

R8391.2:3MM

0.012UF

402

Q8360.2:3MM

X5R

25V

10%

1UF

402

EMCEMC

402

X5R

25V

10%

1UF

Q8360.2:3MM

POWER56

CRITICAL

FDMS3602S

CERM

10%

402

50V

0.001UF

NOSTUFF

603

MF-LF

1/10W

5%

2.2

NOSTUFF

16V
402

10%
X7R-CERM

0.1UF

MF-LF

5%

1/10W

603

2.2

603

16V

10%
X5R

2.2UF

60

2.2

5%
1/8W
MF-LF
805

10

5%

805

MF-LF

1/8W

1UF

402

16V

10%
X5R

0

5%
1/16W
MF-LF
402

60

1/16W
402

1%
MF-LF

2.32K

SIGNAL_MODEL=EMPTYSIGNAL_MODEL=EMPTY

2.32K

1%

402

1/16W
MF-LF

0.047UF

X7R
402

16V

10%

MF-LF

2.74K

1%
1/16W

402

NOSTUFF

10PF

5%
50V
CERM
402

10PF

402

5%

CERM

50V

2.74K

1%
1/16W
MF-LF

402

NOSTUFF

20K

1/16W

5%

402

MF-LF

73 97

CRITICAL

ISL95870AH

UTQFN

SM

U8360.3:1MM

1%

MF-LF

1/16W

402

301K

402

150K

1%

MF-LF

1/16W

402

MF

1%

27K

1/16W

5%

MF-LF

1/16W

0

402

78

1.0UH-20%-15A-0.0065OHM

CRITICAL

PIC0605H-SM

Q8310.1:3MM

X5R

25V

10%

1UF

402

EMC

Q8310.1:3MM

X5R

25V

10%

1UF

402

EMC

73 97

180UF

16V

20%

POLY

TH

CRITICAL

1%

200

1/16W

MF-LF

402

CERM

10%

402

50V

0.001UF

NOSTUFF

NOSTUFF

603

MF-LF

1/10W

5%

2.2

SYNC_MASTER=D7_NICK

SYNC_DATE=01/03/2012

1V05 GPU POWER SUPPLY

CRITICAL

1

R8311

110S0568

RES,MF,3.32 OHM,1/10W,1,603,LF

PP1V5R1V35_S0_GPU_REG

REG_GPUVDDQ_OCSET

=PP12V_S0_REG_GPU_P1V05_S0

REG_GPU_P1V05S0_FSEL

REG_PHASE_GPUVDDQ

REG_SNUBBER_GPUVDDQ

REG_BOOT_GPU_P1V05S0

REG_UGATE_GPU_P1V05S0

REG_GPU_P1V05S0_SREF

AGND_GPUVDDQ

REG_GPUVDDQ_SET1_R

REG_GPU_P1V05S0_OCSET_R

REG_GPU_P1V05S0_OCSET

REG_PHASE_GPU_P1V05S0_L

REG_GPU_P1V05S0_VO_R

PP1V05_S0_GPU_REG

REG_SNUBBER_GPU_P1V05S0

REG_BOOT_GPU_P1V05S0_RC

REG_UGATE_GPU_P1V05S0_R

REG_GPUVDDQ_FSEL

SNS_GPU_PEX_IOVDD_N

SNS_GPU_PEX_IOVDD_P

PM_EN_REG_GPU_VDDQ_S0

REG_GPUVDDQ_PGOOD

REG_BOOT_GPUVDDQ_RC

PM_PGOOD_REG_P1V05_GPU

REG_GPU_P1V05S0_PGOOD

=PP5V_S0_REG_GPU_VDDQ_S0

=PP12V_S0_REG_GPU_VDDQ_S0

REG_UGATE_GPUVDDQ

REG_PVCC_U8350

REG_GPUVDDQ_PGOOD

REG_GPUVDDQ_VO

REG_BOOT_GPUVDDQ

FBVDD_ALTVO

REG_GPU_P1V05S0_VO

REG_VCC_U8300

REG_GPUVDDQ_SET1

REG_GPUVDDQ_OCSET

REG_GPUVDDQ_SET0

=PP5V_S0_REG_GPU_P1V05_S0

REG_VCC_U8350

REG_GPUVDDQ_SREF

REG_LGATE_GPUVDDQ

=PP3V3_S0_VRD

REG_GPU_P1V05S0_OCSET

REG_GPU_P1V05S0_RTN

PM_EN_REG_GPU_P1V05_S0

REG_GPU_P1V05S0_FB

REG_GPU_P1V05S0_VO

REG_GPU_P1V05S0_PGOOD

REG_GPUVDDQ_FB

REG_GPUVDDQ_RTN

SNS_GPUVDDQ_P

SNS_GPUVDDQ_N

PM_PGOOD_REG_GPU_VDDQ_S0

MAKE_BASE=TRUE

REG_GPUVDDQ_VO

P1V05_GPU_AGND

REG_PHASE_GPU_P1V05S0

REG_LGATE_GPU_P1V05S0

=PP3V3_S0_VRD

C8316

1

2

R8311

12

R8316

1

2

C8320

1

2

Q8310

5

9

3

4

1

6
7
8

C8301

1

2

R8300

1

2

U8300

123

6

5

1

15

7

16

9

10

14

2

4

11

13

8

XW8300

1 2

R8335

1

2

R8330

1

2

C8300

1

2

R8340

1

2

C8340

1

2

C8335

1

2

C8330

1

2

R8336

1

2

R8331

1

2

R8341

1

2

C8341

12

R8342

1

2

XW8301

1

2

XW8302

1

2

R8343

1

2

C8321

1

2

C8322

1

2

L8310

1 2

C8372

1

2

C8360

1

2

C8371

1

2

C8370

1

2

R8368

1

2

C8368

1

2

R8391

1

2

R8392

1

2

C8391

1 2

C8362

1

2

C8361

1

2

Q8360

2

1

6

7

3 4 5

C8367

1

2

R8367

1

2

C8366

1

2

R8366

1

2

C8351

1

2

R8351

1

2

R8350

1

2

C8350

1

2

R8390

1

2

R8385

1

2

R8380

1

2

C8390

1

2

R8386

1

2

C8385

1

2

C8380

1

2

R8381

1

2

R8393

1

2

U8350

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

XW8350

12

R8387

1

2

R8388

1

2

R8389

1

2

R8394

1 2

L8360

1 2

C8311

1

2

C8312

1

2

C8310

1

2

R8320

1

2

C8317

1

2

R8317

1

2

051-9509

4.2.0

83 OF 113
74 OF 100

74 97

6

97

97

97

97

97

97

97

97

74 97

97

97

6

97

97

97

74

97

74

6

6

97

97

74

74 97

97

74 97

97

97

74 97

97

6

97

97

97

6

62 65 66 68 74

74 97

97

97

74 97

74

97

97

74 97

97

97

97

6

62 65 66 68 74

A11/A6

SEN

WCK01*

WCK01

EDC3

EDC0

A10/A0

DQ0

DQ13

DQ12

DQ24

CK

A9/A1

BA1/A5
BA2/A4

CAS*

CK*

CKE*

CS*

DQ9

DQ11

DQ14

DQ16

DQ19

DQ23

DQ25
DQ26
DQ27

DQ31

EDC1
EDC2

MF

RAS*

WCK23
WCK23*

WE*

ZQ

BA0/A2

DQ28
DQ29

DQ22

DQ21

DQ17

DQ15

DQ10

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DBI3*

DBI0*

DBI2*

DBI1*

BA3/A3

A8/A7

ABI*

RESET*

DQ18

DQ20

NC

A12/RFU/NC

DQ30

NC

(MF=1)

(1 OF 2)

IN IN

IN

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

MF
SEN

CAS*

A11/A6

BA1/A5

DQ29

WCK01*

WCK23
WCK23*

RESET*

EDC1
EDC2

NC

DQ28

A10/A0

CKE*

BA0/A2

DQ3
DQ4
DQ5
DQ6

DQ8

DQ9
DQ10
DQ11

BA3/A3

BA2/A4

WE*

DBI2*

A9/A1

A8/A7

CK*

DQ30

ABI*

CK

CS*

DBI1*

DBI3*

DQ0

DQ1

DQ2

DQ7

DQ12

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ25
DQ26

EDC0

EDC3

RAS*

DQ13

DQ15

DQ27

DBI0*

DQ14

DQ31

DQ24

WCK01

ZQ

A12/RFU/NC

NC

(1 OF 2)

(MF=0)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

NC

NC

BI
BI
BI
BI

IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN
IN
IN

IN

IN

BI
BI
BI
BI

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI
BI

BI

BI

IN

IN

IN
IN

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

IN

IN

IN

IN

NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Signal aliases required by this page:

This memory device is in Mirrored Mode.

PLACE CLOSE TO U8450

Power aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

Page Notes

BOM options provided by this page:

CK TERMINATION - A0

(NONE)

CK TERMINATION - A1

PLACE CLOSE TO U8400

FBA

20%

402

X5R

4.7UF

6.3V

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

6.3V

20%

402

X5R

4.7UF

FBA

1/20W

1%

201

MF

120

FBA

1/20W

1%

201

MF

120

FBA

1/20W

1%

201

MF

120

FBA

1/20W

1%

201

MF

120

FBA

1/20W

1%

201

MF

120

BGA

K4G10325FG-HC03

32MX32-1.5GHZ-MFH

OMIT_TABLE

FBA

PLACE_NEAR=U8400.J12:8.4MM

1/20W

1%

201

MF

40.2

FBA

201

MF

40.2

1%

1/20W

PLACE_NEAR=U8450.J12:8.4MM

FBA

PLACE_NEAR=U8400.J11:8.4MM

10V

10%

201

X5R

0.01UF

FBA

PLACE_NEAR=U8450.J11:8.4MM

10V

10%

201

X5R

0.01UF

FBA

1/20W

1%

MF

40.2

PLACE_NEAR=U8400.J11:8.4MM

201

FBA

PLACE_NEAR=U8450.J11:8.4MM

1/20W

1%

201

MF

40.2

FBA

PLACE_NEAR=U8400.J14:8.4MM

1/20W

1%

201

MF

931

FBA

PLACE_NEAR=U8400.J14:8.4MM

1/20W

1%

201

MF

549

FBA

PLACE_NEAR=U8400.J14:8.4MM

1/20W

1%

201

MF

1.33K

FBA

PLACE_NEAR=U8400.J14:8.4MM

50V

10%

402

CERM

820PF

73 75 76

FBA

1.33K

PLACE_NEAR=U8450.J14:8.4MM

1/20W

1%

201

MF

73 75 76

FBA

1/20W

1%

931

201

MF

PLACE_NEAR=U8450.J14:8.4MM

FBA

201

PLACE_NEAR=U8450.J14:8.4MM

1/20W

1%

MF

549

FBA

10%
50V

402

CERM

820PF

PLACE_NEAR=U8450.J14:8.4MM

FBA

50V

10%

402

CERM

820PF

PLACE_NEAR=U8400.U10:8.4MM

FBA

PLACE_NEAR=U8400.U10:8.4MM

1/20W

1%

201

MF

549

73 75
76

FBA

PLACE_NEAR=U8400.U10:8.4MM

1/20W

1%

201

MF

931

FBA

PLACE_NEAR=U8400.U10:8.4MM

1/20W

1%

201

MF

1.33K

FBA

PLACE_NEAR=U8400.A10:8.4MM

10V

10%

201

X5R

0.01UF

FBA

PLACE_NEAR=U8450.U10:8.4MM

1/20W

1%

201

MF

1.33K

73 75 76

FBA

1/20W

1%

201

MF

931

PLACE_NEAR=U8450.U10:8.4MM

FBA

201

1/20W

1%

MF

549

PLACE_NEAR=U8450.U10:8.4MM

FBA

50V

10%

402

CERM

820PF

PLACE_NEAR=U8450.U10:8.4MM

FBA

PLACE_NEAR=U8450.A10:8.4MM

10V

10%

201

X5R

0.01UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

1UF

6.3V

20%

0201

X5R

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

FBA

6.3V

20%

0201

X5R

1UF

BGA

32MX32-1.5GHZ-MFH

K4G10325FG-HC03

OMIT_TABLE

FBA

1/20W

MF

1K

5%

201

BGA

K4G10325FG-HC03

32MX32-1.5GHZ-MFL

OMIT_TABLE

BGA

OMIT_TABLE

K4G10325FG-HC03

32MX32-1.5GHZ-MFL

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 75 99

73 75 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 75 99

73 75 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

FBA

6.3V

10%

201

X5R

0.1UF

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

SYNC_DATE=12/13/2011

GDDR5 Frame Buffer A

SYNC_MASTER=D7_TONY

FB_A0_VREFC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm

FB_A0_VREFD

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A1_VREFC

MIN_NECK_WIDTH=0.1 mm

FB_A1_VREFD

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm

FB_A1_DQ<13>

FB_A1_DQ<12>

=PP1V35_GPU_FBVDDQ

FB_A0_A<8>

FB_A0_DQ<25>

FB_A0_DQ<24>

FB_A0_DQ<23>

FB_A0_DQ<22>

FB_A0_DQ<21>

FB_A0_DQ<20>

FB_A0_DQ<19>

FB_A0_DQ<17>

FB_A0_DQ<16>

FB_A0_DQ<15>

FB_A0_DQ<14>

FB_A1_VREFD

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FBA1_CK_MID

FB_A0_SEN

FB_A0_MF

FB_A0_ZQ

FB_A0_ABI_L

FB_A0_WCLK_P<1>

=PP1V35_GPU_FBVDDQ

FB_A0_CKE_L

FBA0_CK_MID FB_A0_CLK_NFB_A0_CLK_P

FB_A1_CLK_P

FB_A1_DQ<0>
FB_A1_DQ<1>
FB_A1_DQ<2>

FB_A1_DQ<6>

FB_A0_CLK_N

FB_A0_VREFD

FB_A0_VREFC

FB_A0_CAS_L

FB_A0_A<6>

FB_A0_DQ<29>

FB_A0_WCLK_N<0>

FB_A0_WCLK_N<1>

FB_A0_RESET_L

FB_A0_EDC<1>
FB_A0_EDC<2>

FB_A0_DQ<28>

FB_A0_A<0>

FB_A0_A<2>

FB_A0_DQ<3>
FB_A0_DQ<4>
FB_A0_DQ<5>
FB_A0_DQ<6>

FB_A0_DQ<8>
FB_A0_DQ<9>
FB_A0_DQ<10>
FB_A0_DQ<11>

FB_A0_A<3>

FB_A0_A<4>

FB_A0_WE_L

FB_A0_DBI_L<2>

FB_A0_A<1>

FB_A0_A<7>

FB_A0_DQ<30>

FB_A0_CLK_P

FB_A0_CS_L

FB_A0_DBI_L<1>

FB_A0_DBI_L<3>

FB_A0_DQ<0>
FB_A0_DQ<1>
FB_A0_DQ<2>

FB_A0_DQ<7>

FB_A0_DQ<12>

FB_A0_DQ<18>

FB_A0_DQ<26>

FB_A0_EDC<0>

FB_A0_EDC<3>

FB_A0_RAS_L

FB_A0_DQ<13>

FB_A0_DQ<27>

FB_A0_DBI_L<0>

FB_A0_DQ<31>

FB_A0_WCLK_P<0>

FB_A1_A<0>

FB_A1_CKE_L

=PP1V35_GPU_FBVDDQ

FB_A1_WCLK_N<0>

FB_A1_DQ<21>

FB_A1_DQ<26>

FB_A1_WCLK_P<0>

FB_A1_CAS_L

FB_A1_RESET_L

FB_A1_CLK_N

FB_SW_LEG FB_SW_LEG

FB_SW_LEG

FB_SW_LEG

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_A1_DQ<30>

FB_A1_A<8>

FB_A1_ABI_L

FB_A1_A<7>

FB_A1_A<3>

FB_A1_DBI_L<2>
FB_A1_DBI_L<0>
FB_A1_DBI_L<3>

FB_A1_DQ<3>
FB_A1_DQ<4>
FB_A1_DQ<5>

FB_A1_DQ<7>
FB_A1_DQ<8>

FB_A1_DQ<17>

FB_A1_DQ<22>

FB_A1_DQ<29>

FB_A1_DQ<28>

FB_A1_A<2>

FB_A1_WE_L

FB_A1_WCLK_N<1>

FB_A1_WCLK_P<1>

FB_A1_RAS_L

FB_A1_EDC<2>

FB_A1_EDC<1>

FB_A1_DQ<31>

FB_A1_DQ<27>

FB_A1_DQ<25>

FB_A1_DQ<23>

FB_A1_DQ<16>

FB_A1_CS_L

FB_A1_CLK_N

FB_A1_A<4>

FB_A1_A<5>

FB_A1_A<1>

FB_A1_CLK_P

FB_A1_DQ<24>

FB_A1_EDC<0>

FB_A1_SEN

FB_A1_A<6>

FB_A1_DQ<20>

FB_A1_DQ<19>

FB_A1_DQ<18>

FB_A1_DQ<10>
FB_A1_DQ<11>

FB_A1_DQ<15>

FB_A1_DQ<14>

FB_A1_DQ<9>

FB_A1_DBI_L<1>

FB_A1_VREFC

FB_A1_EDC<3>

FB_A0_A<5>

FB_A1_MF

FB_A1_ZQ

U8400

H4
K5

J5

K4
H5

J4

H11
K10
K11
H10

L3

J12
J11

J3

G12

D2
D13
P13
P2

A4
A2

B11
B13
E11
E13
F11
F13
U11
U13
T11
T13

B4

N11
N13
M11
M13
U4
U2
T4
T2
N4
N2

B2

M4
M2

E4
E2
F4
F2
A11
A13

C2
C13
R13

R2

J1

A5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

U8400

C5

C10

L14
P11

R5

R10

D11

G1

G4
G11
G14

L1

L4
L11

B1

B3

F1

F3
F12
F14

G2
G13

H3
H12

K3
K12

B12

L2
L13

M1

M3
M12
M14

N5
N10

P1

P3

B14

P12
P14

T1

T3
T12
T14

D1

D3
D12
D14

E5
E10

J14
A10
U10

B5
B10

L10
P10
T5
T10

D10
G5
G10
H1
H14
K1
K14
L5

A1
A3

E1
E3
E12
E14
F5
F10
H2
H13
K2
K13

A12

M5
M10
N1
N3
N12
N14
R1
R3
R4
R11

A14

R12
R14
U1
U3
U12
U14

C1
C3
C4
C11
C12
C14

C8416

1

2

C8417

1

2

C8418

1

2

C8419

1

2

C8420

1

2

C8421

1

2

C8422

1

2

C8423

1

2

C8424

1

2

C8425

1

2

C8467

1

2

C8466

1

2

C8471

1

2

C8475

1

2

C8470

1

2

C8474

1

2

C8469

1

2

C8473

1

2

C8468

1

2

C8472

1

2

C8400

1

2

C8401

1

2

C8402

1

2

C8403

1

2

C8404

1

2

C8405

1

2

C8450

1

2

C8451

1

2

C8452

1

2

C8453

1

2

C8454

1

2

C8455

1

2

R8403

1

2

R8404

1

2

R8400

1

2

R8453

1

2

R8450

1

2

U8450

K4
H5

J5

H4
K5

J4

K11
H10
H11
K10

G3

J12
J11

J3

L12

P2

P13
D13

D2

U4
U2

T11
T13
N11
N13
M11
M13
A11
A13
B11
B13

T4

E11
E13
F11
F13
A4
A2
B4
B2
E4
E2

T2

F4
F2

N4
N2
M4
M2
U11
U13

R2
R13
C13

C2

J1

A5

U5

L3

J2

J10

P4

P5

D4

D5

G12

J13

R8401

1 2

R8451

1 2

C8490

1

2

C8491

1

2

R8402

1 2

R8452

1 2

R8434

1

2

R8430

1

2

R8431

1

2

C8431

1

2

R8481

1

2

R8484

1

2

R8480

1

2

C8481

1

2

C8433

1

2

R8432

1

2

R8435

1

2

R8433

1

2

C8432

1

2

R8483

1

2

R8485

1

2

R8482

1

2

C8483

1

2

C8482

1

2

C8456

1

2

C8457

1

2

C8458

1

2

C8459

1

2

C8460

1

2

C8461

1

2

C8462

1

2

C8463

1

2

C8464

1

2

C8465

1

2

C8406

1

2

C8407

1

2

C8408

1

2

C8409

1

2

C8410

1

2

C8411

1

2

C8412

1

2

C8413

1

2

C8414

1

2

C8415

1

2

U8450

C5

L11

G11
G14

L1
L4

L14
P11

R5
R10
C10
D11

G1

G4

B1
E10

K3

B3
K12

L2
L13

M1

M3
M12
M14

N5

F1

N10

P1
B12

P3
P12
P14

T1

T3
T12
T14

F3

B14

D1

D3
D12
D14

E5

F12
F14

G2
G13

H3
H12

J14
A10
U10

B5
L5

H1
H14
K1
K14

L10
P10
T5
T10
B10
D10
G5
G10

A1
C14

K2
A3
K13
M5
M10
N1
N3
N12
N14
R1

E1

R3
R4
A12
R11
R12
R14
U1
U3
U12
U14

E3

A14
C1
C3
C4
C11
C12

E12
E14
F5
F10
H2
H13

R8454

1

2

051-9509

4.2.0

84 OF 113
75 OF 100

75

75

75

75

6

72 75 76

75

6

72 75 76

6

72

75 76

6

72 75 76

73 75 99 73 75

99

73
75

99

75

75

6

72 75 76

73
75

99

6

72 75 76

6

72 75 76

75

IN

BI

IN

IN

IN

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

MF
SEN

CAS*

A11/A6

BA1/A5

DQ29

WCK01*

WCK23
WCK23*

RESET*

EDC1
EDC2

NC

DQ28

A10/A0

CKE*

BA0/A2

DQ3
DQ4
DQ5
DQ6

DQ8

DQ9
DQ10
DQ11

BA3/A3

BA2/A4

WE*

DBI2*

A9/A1

A8/A7

CK*

DQ30

ABI*

CK

CS*

DBI1*

DBI3*

DQ0

DQ1

DQ2

DQ7

DQ12

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ25
DQ26

EDC0

EDC3

RAS*

DQ13

DQ15

DQ27

DBI0*

DQ14

DQ31

DQ24

WCK01

ZQ

A12/RFU/NC

NC

(1 OF 2)

(MF=0)

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

NC

NC

BI
BI
BI
BI

IN
IN
IN
IN

IN

IN

IN

IN

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN
IN
IN

IN

IN

BI
BI
BI
BI

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI
BI

BI

BI

IN

IN

IN
IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN

IN
IN

IN

NC

NC

A11/A6

SEN

WCK01*

WCK01

EDC3

EDC0

A10/A0

DQ0

DQ13

DQ12

DQ24

CK

A9/A1

BA1/A5
BA2/A4

CAS*

CK*

CKE*

CS*

DQ9

DQ11

DQ14

DQ16

DQ19

DQ23

DQ25
DQ26
DQ27

DQ31

EDC1
EDC2

MF

RAS*

WCK23
WCK23*

WE*

ZQ

BA0/A2

DQ28
DQ29

DQ22

DQ21

DQ17

DQ15

DQ10

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DBI3*

DBI0*

DBI2*

DBI1*

BA3/A3

A8/A7

ABI*

RESET*

DQ18

DQ20

NC

A12/RFU/NC

DQ30

NC

(MF=1)

(1 OF 2)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

This memory device is in Mirrored Mode.

(NONE)

Page Notes

(NONE)

CK TERMINATION - B0

- =PP1V5R1V35_S0_FB_VDD

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

PLACE CLOSE TO U8500

PLACE CLOSE TO U8550

CK TERMINATION - B1

73 99

73 99

FBB

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

6.3V

4.7UF

X5R
402

20%

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

4.7UF

X5R
402

20%

6.3V

FBB

120

MF

201

1%

1/20W

FBB

120

MF

201

1%

1/20W

FBB

120

MF

201

1%

1/20W

FBB

1/20W

MF

1%

201

120

FBB

FBB

40.2

MF
201

1%

1/20W

PLACE_NEAR=U8500.J11:8.4MM

FBB

PLACE_NEAR=U8500.J11:8.4MM

0.01UF

X5R
201

10V

10%

FBB

FBB

PLACE_NEAR=U8500.J12:8.4MM

40.2

MF

201

1%

1/20W

FBB

1/20W

MF

40.2

201

1%

PLACE_NEAR=U8550.J11:8.4MM

FBB

X5R

10%
10V

PLACE_NEAR=U8550.J11:8.4MM

201

0.01UF

FBB

FBB

40.2

MF

201

1/20W

1%

PLACE_NEAR=U8550.J12:8.4MM

FBB

PLACE_NEAR=U8500.J14:8.4MM

MF
201

1%
1/20W

1.33K

73 75 76

FBB

PLACE_NEAR=U8500.J14:8.4MM

MF
201

1%
1/20W

931

FBB

PLACE_NEAR=U8500.J14:8.4MM

MF

549

201

1%
1/20W

FBB

FBB

PLACE_NEAR=U8500.J14:8.4MM

820PF

CERM
402

10%
50V

FBB

PLACE_NEAR=U8500.U10:8.4MM

1.33K

MF
201

1%
1/20W

FBB

PLACE_NEAR=U8500.U10:8.4MM

931

MF
201

1%
1/20W

FBB

PLACE_NEAR=U8500.U10:8.4MM

549

MF
201

1%
1/20W

73 75 76

FBB

FBB

PLACE_NEAR=U8500.A10:8.4MM

0.01UF

X5R
201

10%
10V

FBB

PLACE_NEAR=U8500.U10:8.4MM

820PF

CERM
402

10%
50V

FBB

PLACE_NEAR=U8550.J14:8.4MM

549

MF
201

1%
1/20W

73 75 76

FBB

FBB

931

1%

PLACE_NEAR=U8550.J14:8.4MM

MF
201

1/20W

FBB

PLACE_NEAR=U8550.J14:8.4MM

1/20W
201

1.33K

MF

1%

FBB

50V
CERM

PLACE_NEAR=U8550.J14:8.4MM

820PF

402

10%

FBB

FBB

PLACE_NEAR=U8550.U10:8.4MM

820PF

CERM
402

10%
50V

73 75 76

FBB

FBB

PLACE_NEAR=U8550.U10:8.4MM

931

MF
201

1%
1/20W

FBB

201

PLACE_NEAR=U8550.U10:8.4MM

549

MF

1%
1/20W

FBB

1.33K

PLACE_NEAR=U8550.U10:8.4MM

MF
201

1%
1/20W

FBB

FBB

PLACE_NEAR=U8550.A10:8.4MM

10%

0.01UF

X5R
201

10V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB
1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB
1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

6.3V

1UF

X5R
0201

20%

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

20%

6.3V

1UF

X5R
0201

FBB

1UF

X5R
0201

20%

6.3V

FBB

1UF

X5R
0201

20%

6.3V

FBB

1/20W

201

MF

1K

5%

BGA

OMIT_TABLE

K4G10325FG-HC03

32MX32-1.5GHZ-MFL

OMIT_TABLE

BGA

32MX32-1.5GHZ-MFL

K4G10325FG-HC03

FBB

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 76 99

73 76 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

FBB

FBB

120

MF

201

1%

1/20W

73 99

73 99

73 99

73 99

73 99

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 76 99

73 76 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

OMIT_TABLE

BGA

K4G10325FG-HC03

32MX32-1.5GHZ-MFH

FBB

201

0.1UF

X5R

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

X5R
201

10%

6.3V

0.1UF

FBB

0.1UF

X5R
201

10%

6.3V

FBB

0.1UF

X5R
201

10%

6.3V

FBB

6.3V

0.1UF

X5R
201

10%

FBB

0.1UF

X5R
201

10%

6.3V

FBB

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

73 99

BGA

32MX32-1.5GHZ-MFH

K4G10325FG-HC03

OMIT_TABLE

GDDR5 Frame Buffer B

SYNC_DATE=12/13/2011

SYNC_MASTER=D7_TONY

FB_B1_VREFC

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B1_VREFD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B0_VREFC

FB_B0_VREFD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

=PP1V35_GPU_FBVDDQ

FB_B1_WCLK_N<1>

FB_B1_MF

FB_B0_SEN

FB_B0_ZQ

FBB0_CK_MID

FB_SW_LEG

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

FB_B1_SEN

FB_B1_ZQ

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

FB_SW_LEG

=PP1V35_GPU_FBVDDQ

=PP1V35_GPU_FBVDDQ

FB_B0_CLK_N

FB_B0_MF

FB_B0_CLK_P

FB_B1_CLK_N

=PP1V35_GPU_FBVDDQ

FBB1_CK_MIDFB_B1_CLK_P

FB_B0_WE_L

FB_B0_DQ<31>

FB_B0_A<8>

FB_B0_RESET_L

FB_B1_DBI_L<2>

FB_B1_DQ<8>

FB_B0_DQ<10>

FB_B1_A<8>

FB_B0_VREFD

FB_B0_VREFC

FB_B0_DQ<19>

FB_B0_DQ<21>

FB_B0_DQ<23>

FB_B0_DQ<5>

FB_B0_DQ<7>

FB_B1_VREFD

FB_B1_VREFC

FB_B1_A<6>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<0>

FB_B1_EDC<3>

FB_B1_EDC<0>

FB_B1_A<0>

FB_B1_DQ<0>

FB_B1_DQ<13>

FB_B1_DQ<12>

FB_B1_DQ<24>

FB_B1_CLK_P

FB_B1_A<1>

FB_B1_A<5>
FB_B1_A<4>

FB_B1_CAS_L

FB_B1_CKE_L

FB_B1_DQ<9>

FB_B1_DQ<14>

FB_B1_DQ<16>

FB_B1_DQ<19>

FB_B1_DQ<23>

FB_B1_DQ<25>
FB_B1_DQ<26>
FB_B1_DQ<27>

FB_B1_DQ<31>

FB_B1_EDC<1>
FB_B1_EDC<2>

FB_B1_RAS_L

FB_B1_WCLK_P<1>

FB_B1_WE_L

FB_B1_DQ<28>
FB_B1_DQ<29>

FB_B1_DQ<22>

FB_B1_DQ<21>

FB_B1_DQ<17>

FB_B1_DQ<15>

FB_B1_DQ<10>

FB_B1_DQ<7>

FB_B1_DQ<6>

FB_B1_DQ<5>

FB_B1_DQ<4>

FB_B1_DQ<3>

FB_B1_DQ<1>

FB_B1_DBI_L<3>

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B1_A<3>

FB_B1_A<7>

FB_B1_ABI_L

FB_B1_RESET_L

FB_B1_DQ<18>

FB_B1_DQ<20>

FB_B1_DQ<30>

FB_B1_DQ<2>

FB_B1_CLK_N

FB_B1_CS_L

FB_B0_WCLK_P<0>

FB_B0_DQ<24>

FB_B0_DBI_L<0>

FB_B0_DQ<27>

FB_B0_DQ<15>

FB_B0_DQ<13>

FB_B0_RAS_L

FB_B0_EDC<3>

FB_B0_EDC<0>

FB_B0_DQ<26>

FB_B0_DQ<25>

FB_B0_DQ<20>

FB_B0_DQ<18>

FB_B0_DQ<16>

FB_B0_DQ<2>

FB_B0_DQ<1>

FB_B0_DQ<0>

FB_B0_DBI_L<3>

FB_B0_DBI_L<1>

FB_B0_CLK_P

FB_B0_ABI_L

FB_B0_DQ<30>

FB_B0_CLK_N

FB_B0_A<7>
FB_B0_A<1>

FB_B0_DBI_L<2>

FB_B0_A<4>
FB_B0_A<3>

FB_B0_DQ<9>

FB_B0_DQ<8>

FB_B0_DQ<6>

FB_B0_DQ<4>

FB_B0_DQ<3>

FB_B0_CKE_L

FB_B0_A<0>

FB_B0_DQ<28>

FB_B0_EDC<2>

FB_B0_WCLK_N<1>

FB_B0_WCLK_P<1>

FB_B0_WCLK_N<0>

FB_B0_A<5>

FB_B0_A<6>

FB_B0_CAS_L

FB_B0_A<2>

FB_B0_DQ<12>

FB_B0_DQ<11>

FB_B0_EDC<1>

FB_B0_DQ<29>

FB_B0_CS_L

FB_B1_A<2>

FB_B1_DQ<11>

FB_B0_DQ<22>

FB_B0_DQ<14>

FB_B0_DQ<17>

U8500

H4
K5

J5

K4
H5

J4

H11
K10
K11
H10

L3

J12
J11

J3

G12

D2
D13
P13
P2

A4
A2

B11
B13
E11
E13
F11
F13
U11
U13
T11
T13

B4

N11
N13
M11
M13
U4
U2
T4
T2
N4
N2

B2

M4
M2

E4
E2
F4
F2
A11
A13

C2
C13
R13

R2

J1

A5

U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

R8500

1

2

C8516

1

2

C8517

1

2

C8518

1

2

C8519

1

2

C8520

1

2

C8521

1

2

C8522

1

2

C8523

1

2

C8524

1

2

C8525

1

2

U8550

C5

L11

G11
G14

L1
L4

L14
P11

R5
R10
C10
D11

G1

G4

B1
E10

K3

B3
K12

L2
L13

M1

M3
M12
M14

N5

F1

N10

P1
B12

P3
P12
P14

T1

T3
T12
T14

F3

B14

D1

D3
D12
D14

E5

F12
F14

G2
G13

H3
H12

J14
A10
U10

B5
L5

H1
H14
K1
K14

L10
P10
T5
T10
B10
D10
G5
G10

A1
C14

K2
A3
K13
M5
M10
N1
N3
N12
N14
R1

E1

R3
R4
A12
R11
R12
R14
U1
U3
U12
U14

E3

A14
C1
C3
C4
C11
C12

E12
E14
F5
F10
H2
H13

C8567

1

2

C8566

1

2

C8571

1

2

C8575

1

2

C8570

1

2

C8574

1

2

C8569

1

2

C8573

1

2

C8568

1

2

C8572

1

2

U8550

K4
H5

J5

H4
K5

J4

K11
H10
H11
K10

G3

J12
J11

J3

L12

P2

P13
D13

D2

U4
U2

T11
T13
N11
N13
M11
M13
A11
A13
B11
B13

T4

E11
E13
F11
F13
A4
A2
B4
B2
E4
E2

T2

F4
F2

N4
N2
M4
M2
U11
U13

R2
R13
C13

C2

J1

A5

U5

L3

J2

J10

P4

P5

D4

D5

G12

J13

C8500

1

2

C8501

1

2

C8502

1

2

C8505

1

2

C8504

1

2

C8503

1

2

C8550

1

2

C8551

1

2

C8552

1

2

C8553

1

2

C8554

1

2

C8555

1

2

R8504

1

2

R8503

1

2

R8553

1

2

R8550

1

2

R8502

1 2

C8590

1

2

R8501

1 2

R8552

1 2

C8591

1

2

R8551

1 2

R8531

1

2

R8534

1

2

R8530

1

2

C8531

1

2

R8533

1

2

R8535

1

2

R8532

1

2

C8532

1

2

C8533

1

2

R8580

1

2

R8584

1

2

R8581

1

2

C8581

1

2

C8583

1

2

R8585

1

2

R8582

1

2

R8583

1

2

C8582

1

2

C8506

1

2

C8507

1

2

C8508

1

2

C8509

1

2

C8510

1

2

C8511

1

2

C8512

1

2

C8513

1

2

C8514

1

2

C8515

1

2

C8556

1

2

C8557

1

2

C8558

1

2

C8559

1

2

C8560

1

2

C8561

1

2

C8562

1

2

C8563

1

2

C8564

1

2

C8565

1

2

R8554

1

2

U8500

C5

C10

L14
P11

R5

R10

D11

G1

G4
G11
G14

L1

L4
L11

B1

B3

F1

F3
F12
F14

G2
G13

H3
H12

K3
K12

B12

L2
L13

M1

M3
M12
M14

N5
N10

P1

P3

B14

P12
P14

T1

T3
T12
T14

D1

D3
D12
D14

E5
E10

J14
A10
U10

B5
B10

L10
P10
T5
T10

D10
G5
G10
H1
H14
K1
K14
L5

A1
A3

E1
E3
E12
E14
F5
F10
H2
H13
K2
K13

A12

M5
M10
N1
N3
N12
N14
R1
R3
R4
R11

A14

R12
R14
U1
U3
U12
U14

C1
C3
C4
C11
C12
C14

051-9509

4.2.0

85 OF 113
76 OF 100

76

76

76

76

6

72 75 76

6

72 75 76

6

72 75 76

6

72 75 76

6

72 75 76

6

72 75 76

73 76 99 73 76

99

73
76

99

6

72

75 76

73
76

99

76

76

76

76

BI
BI
BI
BI
BI
BI

IN

OUT

IN
OUT

IN

OUT

IN
IN
IN
IN
IN

NC

NC
NC

NC

NC

NC
NC
NC

NC

NC

NC

NC

NC

NC

NC

NC
NC
NC
NC

NC
NC

OUT

BI

OUT
BI

BI

OUT

OUT

OUT

NC

NC

NC

NC
NC
NC

NC

NC

NC
NC

NC

BI
BI

IFPEF_PLLVDD
IFPEF_RSET

IFPD_RSET

IFPD_PLLVDD

I2CA_SDA

IFPF_IOVDD

IFPAB_PLLVDD
IFPAB_RSET

IFPC_PLLVDD
IFPC_RSET

IFPC_L1

IFPC_L0*

IFPC_L0

IFPC_AUX_I2CW_SCL

IFPB_TXD7*

IFPA_TXD3*

IFPB_TXC

DACA_VREF
DACA_RSET

IFPE_IOVDD

I2CA_SCL

IFPC_L3*

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

IFPF_AUX_I2CZ_SDA*

IFPF_AUX_I2CZ_SCL

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX_I2CY_SDA*

IFPE_AUX_I2CY_SCL

IFPD_L3*

IFPD_L3

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

IFPD_IOVDD

IFPC_L3

IFPC_L1*

IFPC_IOVDD

IFPC_AUX_I2CW_SDA*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD6

IFPB_TXD5*

IFPB_TXD5

IFPB_TXD4*

IFPB_TXD4

IFPB_TXC*

IFPB_IOVDD

IFPA_TXD3

IFPA_TXD2*

IFPA_TXD2

IFPA_TXD1*

IFPA_TXD1

IFPA_TXD0*

IFPA_TXD0

IFPA_TXC

IFPA_IOVDD

I2CS_SDA

I2CS_SCL

I2CC_SDA

I2CC_SCL

I2CB_SDA

I2CB_SCL

DACA_VSYNC

DACA_VDD DACA_RED

DACA_HSYNC

DACA_GREEN

DACA_BLUE

CEC

IFPA_TXC*

IFPD_L2*

IFPC_L2

IFPC_L2*

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA*

(5 OF 10)

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

NC

BI
BI

BI
BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

NC
NC

NC
NC

NC

NC

NC

THERMDP
THERMDN

JTAG_TRST*

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

STRAP3
STRAP4

STRAP2

STRAP1

STRAP0

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

VID_PLLVDD

PLLVDD

SP_PLLVDD

TESTMODE

MULTI_STRAP_REF0_GND

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS*

VDD33

GPIO20

GPIO16

GPIO0
GPIO1
GPIO2

GPIO5
GPIO6
GPIO7
GPIO8
GPIO9

GPIO10

GPIO13
GPIO14
GPIO15

GPIO17
GPIO18
GPIO19

GPIO21

GPIO11
GPIO12

GPIO4

GPIO3

(6 OF 10)

IN
IN

IN

IN

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PD FOR AUX CHANNELS (FOR NVIDIA)

GPU 3V3 VDD

ESR = 0.05OHM

IFP EF IOVDD

ESR = 0.05OHM

IFP CD IOVDD

IFPX PLLVDD

DISABLE PHYs A, B & C FOR K70

- =PP1V8_GPU_DPLL

Power aliases required by this page:

- =PP1V05_GPU_DPLL

- =PP1V05_GPU_IFPEF_IOVDD

PD FOR RSET

- =PP1V05_GPU_IFPCD_IOVDD

- =PP1V8_GPU_IFPA_IOVDD

- =PP3V3_GPU_IFPX_PLLVDD

Signal aliases required by this page:

- =PP3V3_GPU_VDD33

BOM options provided by this page:

Page Notes

- =PP3V3_GPU_IFPB_IOVDD

- J31:YES

- J5:YES

(NONE)

Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other

GPU PLL VDD

ESR = 0.05OHM

I2CC -> Not used
(was ext SSC cntl)

DDC MAPPING

--------------------­I2CA -> IFPE DDC

I2CB -> IFPF DDC

78

78

78

78

78

78

8

8

78

78

78

78

0201

MF

0.1%
1/20W

40.2K

PLACE_NEAR=U8000.J1:5MM

10%

402

X7R-CERM

16V

0.1UF

10%
16V
X7R-CERM
402

0.1UF

X5R

10%
25V

1UF

402

16V

10%

X7R-CERM
402

0.1UF

10%

402

X7R-CERM

0.1UF

16V

402

20%

4.7UF

X5R-CERM1

6.3V

X7R-CERM
402

0.1UF

10%
16V

78

78

78

78

78

83

83

MF

100K

201

1%
1/20W

201

MF

1%

100K

1/20W

MF
201

1%

100K

1/20W

201

1%
1/20W
MF

100K

100K

201

MF

1/20W

1%

100K

1/20W

1%

MF
201

PLACE_NEAR=U8000.AN2:5MM

1%
1/20W
MF
201

1K 1K

PLACE_NEAR=U8000.AD6:5MM

MF

1/20W

1%

201

83

83

78 99

78 99

20%

X5R

4V

0402

22UF

CRITICAL

0603

FERR-220-OHM-2A

FERR-220-OHM-2A

CRITICAL

0603

0603

FERR-220-OHM-2A

CRITICAL

X5R-CERM

4.7UF

10%

603

6.3V

4.7UF

20%

6.3V
X5R-CERM1
402

201

1%
1/20W

4.7K

MFMF

201

1/20W

4.7K

1%

X7R-CERM

16V

10%

0.1UF

402

16V

10%

0.1UF

402

X7R-CERM

X5R

20%

1UF

0201

6.3V

78

78

10K

201

MF

1/20W

1%

201

MF

1/20W

1%

10K

201

1/20W

5%

MF

10K

X5R-CERM1

4.7UF

6.3V

20%

402

10%

0.1UF

402

16V
X7R-CERM

0.1UF

10%
16V

402

X7R-CERMX7R-CERM

402

16V

10%

0.1UF

10%

0.1UF

16V

402

X7R-CERM

10%
16V

0.1UF

402

X7R-CERM

10K

1/20W
MF

5%

201201

1/20W
MF

5%

10K

201

MF

1/20W

5%

100K

NOSTUFF

5%

201

MF

1/20W

NOSTUFF

100K

100K

201

1/20W
MF

NOSTUFF

5%
1/20W
MF
201

100K

NOSTUFF

5%

77 82 98

77 82 98

NV-GK107

BGA

OMIT_TABLE

CRITICAL

82

82

82

82

82 98

82 98

82 98

82 98

71 77

71 77

71 77

71 77

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

34 98

MF

1/20W

201

1%

10K

201

MF

1/20W

10K

1% 1%

1/20W
MF
201

10K

201

1%
1/20W
MF

10K

CRITICAL

0603

330-OHM-1.2A

1UF

25V

10%

X5R
402

0.1UF

16V

10%

402

X7R-CERM

402

16V

0.1UF

X7R-CERM

10%

1UF

20%

X5R
0201

6.3V

1UF

20%

X5R
0201

6.3V

4.7UF

20%

402

X5R-CERM1

6.3V

NV-GK107

OMIT_TABLE

BGA

1/20W

10K

MF

1%

201

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

KEPLER EDP/DP/GPIO

SYNC_DATE=12/13/2011

SYNC_MASTER=D7_TONY

VOLTAGE=3.3V

PP3V3_GPU_IFPX_PLLVDD

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM

PP1V05_GPU_IFPD_IOVDD

MAKE_BASE=TRUE

PP1V05_GPU_SP_PLLVDD

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.41MM

PP1V05_GPU_PLLVDD

MIN_NECK_WIDTH=0.2mm

VOLTAGE=1.05V

PP1V05_GPU_IFPEF_IOVDD

MIN_LINE_WIDTH=0.5MM

GPU_SSC_SMB_CLK

GPU_SSC_SMB_DAT

DP_TBTSNK0_DDC_CLK

=PP3V3_GPU_VDD33

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_EG_AUXCH_N

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK0_EG_AUXCH_N

GPU_IFPC_IOVDD

=PP3V3_GPU_MISC

DP_TBTSNK1_DDC_CLK

DP_TBTSNK1_DDC_DATA

=PP3V3_GPU_VDD33

GPU_SMB_CLK

DP_TBTSNK0_EG_AUXCH_P

PP3V3_GPU_IFPX_PLLVDD

PP1V05_GPU_PLLVDD

PP1V05_GPU_VID_PLLVDD

GPU_OSC_27M_XTALIN

GPU_MLS_STRAP1

GPU_XTAL_SSIN

GPU_XTAL_OUTBUFF

GPU_OSC_27M_XTALOUT

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<2>

GPU_MLS_STRAP4

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_N<2>

DP_TBTSNK1_ML_C_N<2>

=PP3V3_GPU_VDD33

GPU_JTAG_TRST_L

DP_INT_EG_ML_P<0>

=PP3V3_GPU_MISC

DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK1_ML_C_N<0>

DP_INT_EG_AUX_N

DP_INT_EG_AUX_P

DP_TBTSNK1_EG_AUXCH_N

GPU_ROM_CS_L

GPU_ROM_SI

GPU_ROM_SCLK

GPU_GPIO_19

DP_INT_EG_AUX_N

GPU_TDIODE_P

GPU_JTAG_TDO

GPU_GPIO_0

GPU_GPIO_1
GPU_GPIO_2

GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_GPIO_4

GPU_GPIO_6

PP1V05_GPU_VID_PLLVDD

GPU_GPIO_12

GPU_GPIO_21

GPU_GPIO_7
GPU_GPIO_8

GPU_GPIO_9

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK1_ML_C_P<1>

GPU_GPIO_5

GPU_ROM_SO

GPU_SMB_DAT

GPU_IFPB_IOVDD GPU_IFPC_IOVDD

DP_INT_EG_ML_N<0>

GPU_GPIO_10

GPU_GPIO_3

IFPEF_RSET

GPU_GPIO_18

GPU_JTAG_TCK

GPU_JTAG_TMS

GPU_JTAG_TDI

GPU_TDIODE_N

DP_TBTSNK0_ML_C_P<2>

GPU_IFPA_IOVDD
GPU_IFPB_IOVDD

IFPD_RSET

GPU_IFPX_PLLVDD

GPU_IFPX_PLLVDD

GPU_IFPAB_PLLVDD

DP_TBTSNK1_ML_C_P<0>

GPU_TESTMODE

DP_INT_EG_ML_P<1>

GPU_IFPAB_PLLVDD

GPU_GPIO_17

GPU_GPIO_16

GPU_GPIO_11

GPU_IFPA_IOVDD

GPU_TESTMODE

PP1V05_GPU_SP_PLLVDD

GPU_GPIO_20

MULTI_STRAP_REF

=PP3V3_GPU_VDD33

PP1V05_GPU_IFPD_IOVDD

DAC_AVDD

PP1V05_GPU_IFPEF_IOVDD

PP1V05_GPU_IFPEF_IOVDD

=PP3V3_GPU_IFPX_PLLVDD

=PP1V05_GPU_IFPCD_IOVDD

=PP1V05_GPU_IFPEF_IOVDD

PP3V3_GPU_IFPX_PLLVDD

IFPD_RSET

IFPEF_RSET

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_P<1>

=PP1V05_GPU_PEX_PLLVDD

DP_TBTSNK1_ML_C_P<3>

DP_INT_EG_AUX_P

DP_TBTSNK0_EG_AUXCH_P

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

DP_INT_EG_ML_P<2>

DP_INT_EG_ML_N<1>

GPU_MLS_STRAP0

GPU_MLS_STRAP3

GPU_MLS_STRAP2

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_N<1>

U8000

L3

AL9

AL10

AM9

AK9

AP8

AG10

AP9

AN9

R4

R5

R7
R6

R2

R3

T4

T3

AG8 AM6

AN6

AP3
AN3

AN5

AM5
AL6

AK6

AJ6
AH6

AH8

AJ8

AG9

AJ9

AH9

AP6
AP5

AM7

AL7
AN8

AM8

AK8
AL8

AG3

AG2

AF6

AK1
AJ1

AJ3

AJ2
AH3

AH4

AG5
AG4

AF7
AF8

AK3

AK2

AG6

AM1
AM2

AM3

AM4
AL3

AL4

AK4
AK5

AG7

AN2

AB3

AB4

AC7

AD2
AD3

AD1

AC1
AC2

AC3

AC4
AC5

AB8

AD6

AF3

AF2

AC8

AE3
AE4

AF4

AF5
AD4

AD5

AG1
AF1

R8600

1

2

R8601

1

2

R8602

1

2

R8604

1

2

L8604

1 2

C8615

1

2

C8617

1

2

C8618

1

2

C8636

1

2

C8635

1

2

C8634

1

2

U8000

P6

M3

L1
M5

N3

M4
N4

P2

R8
M6

R1
P3

L6

P4

P1

P5

P7

L7
M7

N8
M1

M2

AM10

AM11
AP12

AP11

AN11

J1

AD8

H6
H4

H5
H7

AE8

J2
J7

J6
J5

J3

AK11

K4

K3

J8

K8

L8
M8

AD7

H3

H2

J4

H1

R8608

1

2

R8609

1 2

C8644

1

2

C8643

1

2

C8642

1

2

C8650

1

2

C8649

1

2

C8646

1

2

C8654

1

2

R8613

1

2

R8614

1

2

R8615

1

2

R8616

1

2

R8617

1

2

R8618

1

2

R8606

1

2

R8607

1

2

C8651

1

2

L8606

1 2

L8605

1 2

L8607

1 2

C8619

1

2

C8633

1

2

R8623

1

2

R8624

1

2

C8658

1

2

C8657

1

2

C8656

1

2

R8603

1

2

R8619

1

2

R8610

1

2

C8625

1

2

C8612

1

2

C8632

1

2

C8631

1

2

C8638

1

2

C8637

1

2

R8622

1

2

R8620

1

2

R8626

1

2

R8625

1

2

R8628

1

2

R8627

1

2

051-9509

4.2.0

86 OF 113
77 OF 100

77

77

77 79

77

77

6

71 77 78 79

71 77

71 77

71 77

77

6

77 80

6

71 77 78 79

71 77

77

77

77

6

71 77 78 79

6

77 80

77 82 98

77 82 98

77

77 77

77

77

77 77 77

77

77

77

77

77

77

77 79

6

71 77 78 79

77

77

77

6

6

6

77

77

77

6

79

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

IN

OUT

BI

D

G S

08

VCC

GND

THRM

SCLK

CS*

SO

SI

HOLD*

WP*

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

GP

GPU overtemp masking

Native Func

GP

GPIOs

Quad AND gate from .csa70

GPU VBIOS ROM

GP

GP

GP

GP

GPIOs

GP

GP

Unused signals

GP

GP

GP

Native Func

GP

GP

GP

GP

GP

GP

GP

CONFIG STRAPS - MLPS

GP

GP

GP

GP

ISOLATION R’s for GPU Int Temp Sense

GPU XTAL 27 MHZ

NO STUFF

201

1/20W

MF5%

0

201

1/20W

5%

0

MF

44 45 78

10K

MF

201

1/20W

5%

1/20W

5%

10K

201

MF

8

78

78

74 78

77

77

1/20W

201

MF

33

5%

GPU_ROM:YES

201

X5R

6.3V

10%

0.1UF

GPU_ROM:YES

0

201

1/20W

5%

MF

0

5%

MF

1/20W

201

201

1%

NOSTUFF

MF

5.62K

1/20W

77

77

NOSTUFF

1/20W

201

MF

1%

3.24K

77

NOSTUFF

1%

201

5.62K

MF

1/20W

77

77

201

MF

1/20W

1%

3.24K

NOSTUFF

77 78

1%
1/20W
MF

OMIT_TABLE

3.24K

201

77 78

77 78

1%

201

MF

1/20W

45.3K

1%

201

1/20W
MF

34.8K

1%

MF

25.5K

1/20W

201

OMIT_TABLE

45.3K

201

1%

MF

1/20W

OMIT_TABLE

NO STUFF

201

1/20W

0

5%

MF

0

5%

GPU_ROM:YES

MF

1/20W

201

MF 5%

1/20W

201

33

GPU_ROM:YES

NP0-C0G

25V

201

18PF

5%

NP0-C0G
201

18PF

25V

5%

10K

MF
201

1%
1/20W

1%
1/20W

201

MF

45.3K

35.7K

201

MF

1/20W

OMIT_TABLE

1%

1/20W

15K

1%

MF
201

OMIT_TABLE

33

1/20W

5% MF

201

GPU_ROM:YES

5%

10K

201

1/20W

MF

201

10K

MF

1/20W

5%

201

MF

1/20W

5%

10K

NO STUFF

201

MF

1/20W

10K

5%

1/20W

NOSTUFF

201

MF

1%

10K

1%
1/20W

10K

MF
201

OMIT_TABLE

201

MF

1/20W

1%

10K

26
71

44
45

78

10K

5%

1/20W

MF

201

44

201

MF

5%

10K

1/20W

NOSTUFF

VESM

SSM3K15AMFVAPE

TSSOP-HF

74LVC08

PLACE_SIDE=BOTTOM

CRITICAL

SM-2.5X2.0MM

27MHZ-15PPM-18PF

USON

1MBIT

MX25V1005C

OMIT_TABLE

CRITICAL

10K

1/20W

MF

GPU_ROM:YES

5%

201

GPU_ROM:YES

MF

201

5%

1/20W

33

1

RES,MF,NOSTUFF,1,1/20W,0201

R8704

GPU:107GTX

CRITICAL998-3824

RES,MF,4.99k ,1,1/20W,0201

GS

1 R8704

CRITICAL118S0409

RES,MF,NOSTUFF,1,1/20W,0201

CRITICAL

R8710

FB:BOTH_HYNIX

1

998-3824

SYNC_MASTER=D7_TONY

SYNC_DATE=01/10/2012

KEPLER GPIOS,CLK & STRAPS

RES,MF,NOSTUFF,1,1/20W,0201

CRITICAL

FB:BOTH_SAMSUNG

R8710

998-3824

1

RES,MF,NOSTUFF,1,1/20W,0201

GS

CRITICAL

1 R8705

998-3824

RES,MF,4.99k ,1,1/20W,0201

R8705

CRITICAL

1

118S0409

GPU:107EGE

RES,MF,30.1k ,1,1/20W,0201

1

GPU:107GTX

R8705

CRITICAL118S0280

1

RES,MF,NOSTUFF,1,1/20W,0201

GPU:107EGE

R8704

CRITICAL998-3824

CRITICAL

RES,MF,15.0k ,1,1/20W,0201

118S0105

R8711

FB:BOTH_HYNIX

1

CRITICAL

RES,MF,20.0k ,1,1/20W,0201

1

118S0175

R8711 FB:BOTH_SAMSUNG

FB:CH1_SAMSUNG

R87101

998-3824 CRITICAL

RES,MF,NOSTUFF,1,1/20W,0201

FB:CH2_SAMSUNG

RES,MF,NOSTUFF,1,1/20W,0201

CRITICAL998-3824

1 R8710

FB:CH1_HYNIX

CRITICAL

R8710

RES,MF,NOSTUFF,1,1/20W,0201

998-3824

1

FB:CH2_HYNIX1

998-3824

RES,MF,NOSTUFF,1,1/20W,0201

R8710

CRITICAL

FB:CH1_SAMSUNG

1

RES,MF,10.0k ,1,1/20W,0201

R8711

118S0013 CRITICAL

FB:CH2_SAMSUNG

CRITICAL118S0013

R8711

RES,MF,10.0k ,1,1/20W,0201

1

FB:CH1_HYNIX

RES,MF,24.9k ,1,1/20W,0201

118S0230

1 R8711

CRITICAL

FB:CH2_HYNIX

CRITICAL

R87111

118S0230

RES,MF,24.9k ,1,1/20W,0201

GPU:107GTX

118S0409

1 R8714

RES,MF,4.99k ,1,1/20W,0201

CRITICAL

1

118S0409

R8714

GS

RES,MF,4.99k ,1,1/20W,0201

CRITICAL

GPU:107EGE

998-3824 CRITICAL

R87141

RES,MF,NOSTUFF,1,1/20W,0201

GPU:107GTX

RES,MF,NOSTUFF,1,1/20W,0201

998-3824 CRITICAL

1 R8715

RES,MF,NOSTUFF,1,1/20W,0201

998-3824 CRITICAL

1 R8715

GS

118S0105

GPU:107EGE

CRITICAL

RES,MF,15.0k ,1,1/20W,0201

1 R8715

NC_HDMI_EG_HPD

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_21_RSVD

TP_GPU_JTAG_TRST_L

MAKE_BASE=TRUE

GPU_ALT_VREF

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

NC_DP_EXTA_CA_DET_EG

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_DP_EXTB_CA_DET_EG

DP_TBTSNK1_HPD

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

NC_GPU_GPIO_20_RSVD

NO_TEST=TRUE

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

TP_GPU_JTAG_TCK

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TMS

GPU_VCORE_VID4

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_VCORE_VID5

MAKE_BASE=TRUE

EG_BKLT_EN

DP_INT_EG_HPD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_LCD_BKLT_PWM

MAKE_BASE=TRUE

FB_CLAMP_TOGGLE_REQ_L

FBVDD_ALTVO

MAKE_BASE=TRUE

GPU_OSC_27M_XTALIN

=PP3V3_S5_PWRCTL

SMC_GFX_OVERTEMP

GPU_MLS_STRAP0

=PP3V3_GPU_VDD33

GPU_GPIO_19

GPU_GPIO_2

GPU_GPIO_1

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_R_L

EG_LCD_PWR_EN

EG_BKLT_EN

FBVDD_ALTVO

GPU_GPIO_4

GPU_GPIO_10

GPU_JTAG_TRST_L

GPU_JTAG_TMS

GPU_GPIO_13

=PP3V3_GPU_VDD33

GPU_JTAG_TCK

GPU_SMB_CLK_R

=PP3V3_GPU_VDD33

GPU_SMB_CLK

GPU_SMB_DAT_R

SMC_GFX_THROTTLE_L

SMC_GFX_OVERTEMP

GPU_JTAG_TDO

GPU_JTAG_TDI

GPU_SMB_DAT

=PP3V3_GPU_VDD33

=PP3V3_GPU_VDD33

GPU_GPIO_11

=PP3V3_GPU_VDD33

GPU_GPIO_14

GPU_GPIO_21

GPU_GPIO_18

GPU_GPIO_15

GPU_GPIO_20

GPU_GPIO_16

=PP3V3_GPU_VDD33

GPU_ROM_SO

GPU_ROM_SCLK

GPU_GPIO_9

GPU_MLS_STRAP4

=PP3V3_GPU_VDD33

GPU_MLS_STRAP1

=PP3V3_GPU_VDD33

GPU_MLS_STRAP2

GPU_MLS_STRAP3

GPU_ROM_SI

SMC_GFX_OVERTEMP_R_L

GPU_RESET_L

GPU_GPIO_12

GPU_OSC_27M_XTALOUT

GPU_GPIO_17

GPU_GPIO_5

GPU_GPIO_3

GPU_GPIO_0

SMC_GFX_OVERTEMP_Q

GPU_ROM_SO

GPU_ROM_SCLK

GPU_ROM_SI

=PP3V3_GPU_VDD33

GPU_GPIO_8

GPU_GPIO_6

GPU_ROM_WP_L

GPU_ROM_CS_L

GPU_ROM_SO_R

GPU_ROM_SI_R

GPU_ROM_SCLK_R

GPU_ROM_CS_L_R

=PP3V3_GPU_VDD33

GPU_GPIO_7

R8798

1 2

R8799

1 2

R8797

1

2

R8796

1

2

R8723

1 2

C8721

1

2

R8781

1 2

R8780

1 2

R8701

1

2

R8702

1

2

R8707

1

2

R8708

1

2

R8710

1

2

R8700

1

2

R8703

1

2

R8711

1

2

R8715

1

2

R8722

1

2

R8721

1

2

R8724

12

C8700

1

2

C8701

1

2

R8706

1

2

R8709

1

2

R8714

1

2

R8705

1

2

R8726

1 2

R8792

1

2

R8793

1

2

R8794

1

2

R8790

1

2

R8713

1

2

R8712

1

2

R8704

1

2

R8752

1

2

R8791

1

2

Q8701

3

1

2

U7000

7

10

9

8

14

Y8700

2 4

1 3

U8701

1

4

7

6

5
2

9

8

3

R8720

1

2

R8725

12

051-9509

4.2.0

87 OF 113
78 OF 100

80

8

78

73

78

80

80

34

34

80

78

80

80

78

82

82 74 78

6

60 61 70

6

71 77 78 79

77

77

77

78

78

77

77

77

77

77

6

71 77

78 79

77

47 99

6

71 77 78 79

77 99

47 99

77

77

77 99

6

71 77

78 79

6

71 77

78 79

77

6

71 77 78 79

77

77

77

77

77

77

6

71 77

78 79

77

6

71 77 78 79

6

71 77 78 79

78

77

77

77

77

77

77
78

77
78

77
78

6

71 77 78 79

77

77

77

6

71 77 78 79

77

NC

NC

OUT

OUT

OUT

OUT

GND

(9 OF 10)

GND

(8 OF 10)

GND_SENSE

NC

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDDQ

PEX_PLLVDD

NC

NC

NC

NC

NC

NC

NC

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDD

PEX_IOVDD

NC

PEX_IOVDDQ
NC
NC
NC

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

BUFRST*

NC

NC

PEX_PLL_HVDD

VDD_SENSE

GND_OPT

GND_OPT

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

PEX_IOVDDQ

(2 OF 10)

NC
NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ESR = 0.05OHM

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

(NONE)

(NONE)

Power aliases required by this page:

- =PP3V3_GPU_VDD33

- =PP1V05_GPU_PEX_PLLVDD

- =PP1V05_GPU_PEX_IOVDD

PLACE XW8800 & XW8804 CLOSE TO C8803

EDP = 2000 MA

PEX IOVDD & PEX IOVDDQ

GPU SP PLLVDD

EDP = 1100MA

4V
X5R

22UF

402

20%

6.3V
X5R-CERM1
402

4.7UF

20%

6.3V

4.7UF

20%

402

X5R-CERM1

20%

4.7UF

6.3V
X5R-CERM1
402

16V
X7R-CERM
402

10%

0.1UF

X5R

1UF

6.3V

20%

0201

MF

10K

1/20W

1%

201

80 97

80 97

6.3V
X5R-CERM1
402

4.7UF

20%

X5R

4V

402

20%

22UF

X7R-CERM
402

16V

10%

0.1UF

X7R-CERM
402

0.1UF

16V

10%

0603

CRITICAL

FERR-220-OHM-2A

6.3V
X5R-CERM1
402

4.7UF

20%

0.1UF

10%

6.3V
X5R
201

4V
X5R

22UF

402

20%

20%

402

22UF

4V
X5R

20%

402

4V

22UF

X5R

4.7UF

X5R-CERM1

20%

402

6.3V

SM

SM

SM

SIGNAL_MODEL=EMPTY

SM

PLACE_NEAR=C8803.1:2MM

74 97

SIGNAL_MODEL=EMPTY

SM

PLACE_NEAR=C8803.2:2MM

74 97

5%

NOSTUFF

1/20W

201

100

MF

NOSTUFF

1/20W
MF
201

5%

100

20%

402

4V
X5R

10UF

25V
X7R
0603

10%

1UF

20%

402

10UF

X5R

4V

25V
X7R
0603

1UF

10%

25V
X7R
0603

10%

1UF

402

20%

X5R

4V

10UF

1UF

10%

0603

X7R

25V

X5R

4V

10UF

402

20%

OMIT_TABLE

NV-GK107

BGA

OMIT_TABLE

BGA

NV-GK107

OMIT_TABLE

BGA

NV-GK107

KEPLER PEX PWR/GNDS

SYNC_DATE=01/10/2012

SYNC_MASTER=D7_TONY

=PP1V05_GPU_PEX_IOVDD

GPU_BUFRSTN

PP1V05_GPU_SP_PLLVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

GND_GPU_SP_PLLVDD

VOLTAGE=0V

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

GND_GPU_PEX_PLLVDD

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

GND_GPU_PEX_PLL_HVDD

VOLTAGE=0V

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_GPU_PEX_IOVDD

=PP1V05_GPU_PEX_IOVDD

SNS_GPU_PEX_IOVDD_N

SNS_GPU_PEX_IOVDD_P

=PPVCORE_GPU

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_PEX_IOVDD

=PP1V05_GPU_PEX_PLLVDD

=PP3V3_GPU_VDD33

SNS_GPU_CORE_N

SNS_GPU_CORE_P

U8000

C7
D2

D31
D33

E10

E22
E25

E5

E7

F28

F7

G10
G13

G16
G19

G2

G22
G25

G28

G3
G30

G32

G33

G5

G7

K2

K28

K30
K32

K33

K5

K7

M13

M15
M17

M18
M20

M22

N12
N14

N16

N19

N2

N21

N23
N28

N30
N32

N33

N5

N7
P13

P15
P17

P18

P20
P22

R12

R14
R16

R19

R21
R23

T13
T15

T17

T18
T2

T20

T22
T28

T32

T5
T7

U12
U14

U16

U19
U21

U23

V12
V14

V16

V19
V21

V23
W13

W15

W17
W18

W20

W22
W28

Y12

Y14
Y16

Y19
Y21

Y23

AH11

U8000

AG11

AB12

C28

AB14

AB16
AB19

AB2

AB21
AB23

AB28

AB30
AB32

A2

AB5

AB7
AC13

AC15
AC17

AC18

AC20
AC22

AE2

AE28

A33

AE30

AE32

AE33

AE5

AE7
AH10

AH13

AH16
AH19

AH2

AA13

AH22
AH24

AH28

AH29
AH30

AH32
AH33

AH5

AH7

AJ7

AA15

AK10

AK7
AL12

AL14

AL15
AL17

AL18

AL2
AL20

AL21

AA17

AL23
AL24

AL26
AL28

AL30

AL32
AL33

AL5

AM13
AM16

AA18

AM19

AM22
AM25

AN1
AN10

AN13

AN16
AN19

AN22

AN25

AA20

AN30

AN34

AN4
AN7

AP2
AP33

B1

B10
B22

B25

AA22

B28
B31

B34

B4
B7

C10
C13

C19

C22
C25

U8000

L2

C16

W32

L5

P8

D23

D26

H31

T8

V32

AC6

AJ28

AJ4

AJ5

AL11

C15

D19

D20

AG19
AG21

AG22
AG24

AH21

AH25

AG13
AG15

AK27

AL27
AM28

AN28

AG16

AG18
AG25

AH15
AH18

AH26

AH27
AJ27

AH12

AG26

L4

C8801

1

2

C8802

1

2

C8822

1

2

C8827

1

2

C8829

1

2

C8828

1

2

R8800

1

2

C8831

1

2

C8830

1

2

C8837

1

2

C8836

1

2

L8804

1 2

C8823

1

2

C8825

1

2

C8800

1

2

C8804

1

2

C8803

1

2

C8805

1

2

XW8801

1 2

XW8802

1 2

XW8803

1 2

XW8804

1 2

XW8800

1 2

R8810

1

2

R8811

1

2

C8812

1

2

C8807

1

2

C8806

1

2

C8813

1

2

C8810

1

2

C8809

1

2

C8816

1

2

C8815

1

2

051-9509

4.2.0

88 OF 113
79 OF 100

6

73 79

77

6

73 79

6

73 79

6

72

6
77
79

6

73 79

6

77 79

6

71 77 78

PVCC

VCC

OCSET

PGOOD

ENLL

IREF

ICOMP

ISUM

RGND

VDIFF

VID4
VID3
VID2
VID1
VID0
VID12.5

REF
FB

VSEN

COMP

OFS

UGATE1

BOOT1

PHASE1
LGATE1

FS

BOOT2

UGATE2
PHASE2

LGATE2

ISEN1
ISEN2

THRM_PAD

S

D

G

D

S

G

S

D

G

D

S

G

IN

IN

OUT

IN

IN

NCNC

NCNC

IN

IN

IN

IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Core sense from GPU

(comp out)

? A (nom)/? A (min)

(isum in)

(icomp out)

290 kHz

(vdiff out)

(straps)

? A (design)/? A (budget)
? A (design)/? A (budget)

(iref in)

GPU Core Phases

(vsense in)

GPU Core current sense

Straps & VID inputs

Power goods

Switching freq:

GPU Core Output Decoupling

(straps)

Max avg current:
Max peak current:
OC trip point:

GPU Core S0 Regulator

(straps)

(straps)

(straps)

(straps)

(fb in)

To Core feedback

To Core voltage sense

GPU Core voltage sense input

GPU Core compensation and feedback

5%
CERM

50V
402

27PF

QFN

ISL6568

CRITICAL

SDP110808MR36MF-TH

0.36UH-28A-0.66MOHM

CRITICAL

270UF

8X9-TH1

20%
ELEC

16V

CERM

50V

10%

402

0.001UF

MF-LF

1/8W
805

1.02

1%

CRITICAL

IRF6802SDTRPBF

DIRECTFET-SA

IRF6892STR1PBF

CRITICAL

DIRECTFET_S3C

10%

0.22UF

603

16V
X7R

0

5%
1/10W
MF-LF

603

603

1.0K

1/10W
MF-LF

1%

CRITICAL

270UF

8X9-TH1

20%
16V
ELEC

CERM

50V
402

0.001UF

10%

1/8W
MF-LF
805

1.02

1%

CRITICAL

DIRECTFET-SA

IRF6802SDTRPBF

10%

603

16V

0.22UF

X7R

603

0

1/10W

5%
MF-LF

1%
MF-LF

1/10W

1.0K

603

DIRECTFET_S3C

CRITICAL

IRF6892STR1PBF

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

20%
POLY

CRITICAL

CASE-D2-SM

330UF-0.006OHM

2V

20%
2V
POLY
CASE-D2-SM

330UF-0.006OHM

CRITICAL

CASE-D2-SM

20%
2V
POLY

330UF-0.006OHM

CRITICAL

11K

1/16W
MF-LF

1%

402

402

MF-LF

NOSTUFF

28K

1/16W

1%

402

CERM

50V

NOSTUFF

5%

100PF

NP0-C0G
402

25V

5%

NOSTUFF

1000PF

1/16W

10

5%

402

MF-LF

SIGNAL_MODEL=EMPTY

10

5%
1/16W
MF-LF

402

SIGNAL_MODEL=EMPTY

402

CERM

50V

5%

100PF

NOSTUFF

79 97

79 97

402

10%
16V
CERM-X5R

0.022UF

MF-LF
402

1%
1/16W

4.99K

1.0K

1/10W

1%

603

MF-LF

0

1/16W
MF-LF

5%

402

0.012UF

25V
X7R

10%

402

42.2K

MF-LF

1%

603

1/10W

402

1.5K

1%

MF-LF

1/16W

200K

MF-LF

1/10W

603

1%

200K

1%

1/10W

603

MF-LF

25V

5%

402

NP0-C0G

1000PF

NOSTUFF

1000PF

402

5%

NP0-C0G

25V

NOSTUFF

5%

100PF

CERM

50V
402

10

NOSTUFF

1%
1/16W
MF-LF

402

4.99

402

1%

MF-LF

1/16W

10%

0.01UF

X7R

25V
402

80.6

402

1%

MF-LF

1/16W

50V

10%

402

CERM-X7R

0.0015UF

100

402

1/16W

1%
MF-LF

16V

10%

0.022UF

CERM-X5R
402

1/8W

5%

4.7

805

MF-LF

X7R

1UF

25V

10%

805

X7R

1UF

25V

10%

805

60

60

1%

1K

1/20W
MF
201

NOSTUFF

MF-LF

1/16W
402

1%

64.9K

1/8W

4.7

5%

805

MF-LF

CRITICAL

0.36UH-28A-0.66MOHM

SDP110808MR36MF-TH

1K

1/20W

1%
MF

201

1/20W
201

NOSTUFF

1%

1K

MF

201

NOSTUFF

1%

1K

1/20WMF1/20W

NOSTUFF

1%

1K

201

MF

201

1K

1/20W

1%
MF

1/20W
MF
201

NOSTUFF

1K

1%

1/20W
201

1%

1K

MF

1/20W

1K

MF
201

1% 1%

201

1/20W

1K

MF

1K

201

MF

1%

NOSTUFF

1/20W

MF
201

1K

1%
1/20W

Q8910.5:3MM

402

X5R

25V

10%

1UF

EMC

X5R

25V

10%

1UF

Q8910.6:3MM

EMC

402

402

X5R

25V

10%

Q8910.7:3MM

1UF

EMC

1UF

EMC
Q8910.8:3MM

402

X5R

25V

10%

1/20W
MF
201

5%

10K

MF

201

0

5%

1/20W

78

1/20W

0

5% MF

201

0

5%

1/20WMF201

1/20W

5%0MF

201

0

MF

201

5%

1/20W

0

5%

1/20WMF201

78

78

78

78

78

MF

5%

10K

201

1/20W

SOT723

MMBT2222AM3T5G

1/20W
MF

1%

1K

201

201

100PF

5%
25V
CERM

VReg GPU Core

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_NICK

REG_PHASE_GPUCORE_1

REG_SNUBBER_GPUCORE_1

=PP3V3_GPU_MISC

REG_GPUCORE_RGND

REG_GPUCORE_OFS

REG_GPUCORE_VID3

REG_GPUCORE_MODE_PU

REG_GPUCORE_COMP

REG_GPUCORE_FB

GPUCORE_COMP_RC

REG_GPUCORE_ISUM

REG_GPUCORE_OCSET

REG_GPUCORE_VDIFF

REG_ISEN_GPUCORE_1

REG_GPUCORE_REF

REG_GPUCORE_MODE_B

REG_GPUCORE_MODE

=PP1V8_S0_GPUVID

REG_GPUCORE_MODE

=PP12V_S0_REG_GPUCORE_S0

REG_VCC_U8900

REG_GPUCORE_ICOMP

REG_GPUCORE_VID3

REG_ISEN_GPUCORE_1

=PP12V_S0_REG_GPUCORE_S0

REG_GPUCORE_VID2

REG_GPUCORE_VID0

REG_GPUCORE_VID1

GPUCORE_VDIFF_R

PPGPUCORE_S0_REG

PPGPUCORE_S0_REG

REG_PHASE_GPUCORE_2

REG_SNUBBER_GPUCORE_2

=PP12V_S0_REG_GPUCORE_S0

REG_ISEN_GPUCORE_2

REG_BOOT_GPUCORE_2_RC

REG_BOOT_GPUCORE_1

REG_BOOT_GPUCORE_1_RC

PPGPUCORE_S0_REG

REG_GPUCORE_PGOOD

=PP3V3_S0_PWRCTL

REG_GPUCORE_VSEN

REG_GPUCORE_COMP

REG_GPUCORE_VSEN

REG_GPUCORE_IREF

GPU_VCORE_VID0

GPU_VCORE_VID1

GPU_VCORE_VID3

GPU_VCORE_VID4

REG_PVCC_U8900

PM_EN_REG_GPUCORE_S0

REG_BOOT_GPUCORE_1

REG_GPUCORE_VID2

REG_GPUCORE_VID4

REG_GPUCORE_RGND

REG_GPUCORE_IREF

REG_GPUCORE_ISUM

=PP5V_S0_REG_GPUCORE_S0

REG_GPUCORE_OCSETREG_GPUCORE_ICOMP

GPUCORE_ICOMP_R

REG_PHASE_GPUCORE_1

REG_GPUCORE_FS

REG_PHASE_GPUCORE_1
REG_LGATE_GPUCORE_1

REG_UGATE_GPUCORE_1

REG_UGATE_GPUCORE_2

REG_GPUCORE_VDIFF

REG_ISEN_GPUCORE_2

REG_BOOT_GPUCORE_2

REG_LGATE_GPUCORE_2

REG_PHASE_GPUCORE_2

REG_GPUCORE_PGOOD

REG_GPUCORE_VID1

REG_GPUCORE_FB

PPGPUCORE_S0_REG

GPU_VCORE_VID2

GPUCORE_VDIFF_RC

REG_PHASE_GPUCORE_2

REG_GPUCORE_VID0

REG_GPUCORE_VID4

REG_VCC_U8900

REG_BOOT_GPUCORE_2

GPU_VCORE_VID5

SNS_GPU_CORE_N

SNS_GPU_CORE_P

REG_LGATE_GPUCORE_2

MIN_LINE_WIDTH=0.4mm

MIN_NECK_WIDTH=0.2mm

MIN_NECK_WIDTH=0.2mm
MIN_LINE_WIDTH=0.4mm

REG_UGATE_GPUCORE_2

MIN_NECK_WIDTH=0.2mm

REG_UGATE_GPUCORE_1

MIN_LINE_WIDTH=0.4mm

REG_LGATE_GPUCORE_1

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.4mm

PM_PGOOD_REG_GPUCORE_S0
MAKE_BASE=TRUE

U8900

24

18

5

20

6

29

11

13

26
16

12

27

14

10

3

28

23

19

15

2

8

33

25

17

4

7

32

31

1

30

21

22

9

L8910

1 2

C8910

1

2

C8917

1

2

R8917

1

2

Q8910

7

8

2

3

Q8911

128

7

4

356

C8916

1

2

R8916

1

2

R8915

1

2

C8930

1

2

C8937

1

2

R8937

1

2

Q8910

5

6

1

4

C8936

1

2

R8936

1

2

R8935

1

2

Q8931

128

7

4

3

5

6

C8923

1

2

C8922

1

2

C8921

1

2

C8920

1

2

R8995

1

2

R8996

1

2

C8976

1

2

C8978

1

2

R8971

1 2

R8976

1 2

C8971

1

2

C8980

1

2

R8980

1

2

R8986

1

2

R8985

1 2

C8941

1

2

R8941

1

2

R8942

1

2

R8946

1 2

R8945

1 2

C8946

1

2

C8945

1

2

C8948

1

2

R8948

1 2

R8947

1 2

C8947

1

2

R8940

1 2

C8983

1

2

R8983

1

2

C8990

1

2

R8900

1

2

C8900

1

2

C8901

1

2

R8960

1

2

R8997

1

2

R8901

1

2

L8930

1 2

R8962

1

2

R8964

1

2

R8966

1

2

R8968

1

2

R8961

1

2

R8963

1

2

R8965

1

2

R8967

1

2

R8969

1

2

R8992

1

2

R8993

1

2

C8918

1

2

C8919

1

2

C8938

1

2

C8939

1

2

R8910

1

2

R8955

1 2

R8950

1 2

R8951

1 2

R8953

1 2

R8952

1 2

R8954

1 2

R8994

1

2

Q8990

1

32

R8998

1

2

C8991

1

2

C8981

1

2

051-9509

4.2.0

89 OF 113
80 OF 100

80 97

97

6

77

80 97

97

80 97

80 97

80 97

97

80 97

80 97

80 97

80 97

97

80 97

6

80 97

6

80

80 97

80 97

80 97

80 97

6

80

80 97

80 97

80 97

97

6

80

6

80

80 97

97

6

80

80 97

97

80 97

97

6

80

80

6

70

80 97

80 97

80 97

80 97

97

80 97

80 97

80 97

80 97

80 97

80 97

6

80 97 80 97

97

80 97

97

80 97

80 97

80 97

80 97

80 97

80 97

80 97

80 97

80 97

80

80 97

80 97

6

80

97

80 97

80 97

80 97

80 97

80 97

80 97

80 97

80 97

80 97

OUT

IN

OUT

NC

OUT

BI

IN
IN

IN

BI

OUT
OUT

BI
BI

IN

IN

OUT
OUT

GND

Y1
Y2

A

NC

VCC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U9000 output Y2 is a non-inverted, delayed version of input A

Y1 is simply an inverted version of A, with no delay

Internal DP Connector

To BLC

To Diag LED

Backlight Control

Display TCon Slave

Display TCon Master

The delay applies only on a L->H transition on A. This guarantees video is valid before the backlight is enabled.

518S0829

On a H->L transition of A, Y2 follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video

402

10V

20%
CERM

0.1UF

86

81

5

0.001UF

402

CERM

20%
50V

0805

X5R-CERM

16V

10%

10UF

FERR-250-OHM

SM

47 94

47 94

82 98

82 98

47

47

52 98

82

82 98

82 98

82 98

82 98

81

86

SC70

CRITICAL

SN1105002

CRITICAL

20525-130E-01

F-RT-SM

SYNC_DATE=11/30/2011SYNC_MASTER=K70_MLB

Internal DP Support

VOLTAGE=12V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm

PP12V_LCD

VIDEO_ON

BKLT_EN

DP_INTPNL_AUX_N

DP_INT_SPDIF_AUDIO
DP_INTPNL_HPD

SMB_DP_TCON_SLA_SCL

SMB_DP_TCON_SCL

SMB_DP_TCON_SDA

DP_INTPNL_AUX_P

DP_INTPNL_ML_P<0>

BKLT_VSYNC

VIDEO_ON

DP_INTPNL_ML_N<1>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_N<0>

SMB_DP_TCON_SLA_SDA

=PP12V_S0_LCD

=PP3V3_S0_DP

VIDEO_ON_L

C9106

1

2

C9101

1

2

C9120

1

2

L9100

1 2

U9100

3

2

1

5
4

J9100

1

10
11
12
13
14
15
16
17
18
19

2

20
21
22
23
24
25
26
27
28
29

3

30

31

32

33
34
35
36
37
38
39

4

40
41

5
6
7
8
9

051-9509

4.2.0

91 OF 113
81 OF 100

6

6

6

47 83

S

GND

OUTPUT

MUX

SELECTOR

I1
I0

Y

VCC

IN
IN

IN

OUT

OUT

IN
IN

IN
IN

OUT
OUT

OUT
OUT

BI

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

IN

IN

BI

BI

AUX-

AUX+

D1+
D1-

HPD_SEL

GND

THMPAD

SEL

HPD_B

AUX-B

AUX+B

D1-B

D1+B

D0-B

HPD_A

AUX-A

AUX+A

D1-A

D0-

D0+A
D0-A

D1+A

HPD

D0+

D0+B

VDD

AUX_SEL

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PD is on the CR page

TP to DP aliases

NC aliases

74LVC1G157

SOT487

BKLT_PWM

45

78

21 58 82

MF-LF

BKLT_PWM

47

402

5%

1/16W

BKLT_PWM

FERR-220-OHM

0402

82 86

0.1UF

10%

6.3V
X5R
201

X5R

6.3V

10%

0.1UF

201

78 82

X5R

10%

6.3V

201

0.1UF

201
X5R

10%

6.3V

0.1UF

201

0.1UF

6.3V

10%

X5R

201
X5R

10%

6.3V

0.1UF

77 98

77 98

77 98

77 98

81 98

81 98

81 98

81 98

201

0.1UF

6.3V

10%

X5R

201

0.1UF

6.3V

10%

X5R

81 98

77 98

77 98

10%

6.3V

0.1UF

201
X5R

X5R

10%

6.3V

0.1UF

201

82 98

82 98

100K

5%
1/20W
MF
201

34

201

1/20W

5%

10K

MF

21 58 82

81 98

81

201

100K

5%
1/20W
MF

201

MF

1/20W

5%

100K

34

34

34

34

34

34

PI3VEDP212

TQFN

CRITICAL

77

77

77

77

34

34

34

34

82 98

82 98

82 98

82 98

201

5%
1/20W
MF

2.7K

X5R

10%

6.3V

201

0.1UF

X5R

10%

6.3V

0.1UF

201

X5R

10%

6.3V

0.1UF

201

X5R

10%

6.3V

0.1UF

201

201

5%
1/20W
MF

2.7K

201

5%
1/20W
MF

2.7K 2.7K

MF

1/20W

5%

201

BKLT_PWM

0.1uF

16V

10%

402

X5R

SYNC_DATE=12/14/2011

Internal DP MUXing

SYNC_MASTER=D7_NICK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_EG_ML_P<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_P<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_EG_ML_N<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_EG_ML_P<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_INT_EG_ML_N<2>

NO_TEST=TRUE

NC_DP_TBTSRC_ML_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_TBTSRC_ML_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_N<2>

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_N

DP_TBTSRC_ML_N<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_P

DP_TBTSRC_ML_P<1>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_C_N<1>

DP_TBTSRC_ML_C_P<1>

DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_ML_C_P<0>

DP_TBTSRC_ML_N<1>

DP_TBTSRC_ML_P<1>

DP_TBTSRC_ML_N<0>

DP_TBTSRC_ML_P<0>

DP_INT_EG_ML_P<0>

DP_TBTSRC_ML_C_P<0>
DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_ML_C_P<1>
DP_TBTSRC_ML_C_N<1>

DP_INT_EG_ML_N<0>

DP_INT_EG_ML_P<1>
DP_INT_EG_ML_N<1>

GPU_LCD_BKLT_PWM

BDV_BKL_PWM

DP_GPU_TBT_SEL

LCD_BKLT_PWM

LCD_BKLT_FILT

LCD_BKLT_PWM

=PP3V3_S0_INTDPMUX

TP_DP_TBTSRC_AUXCH_CP

=PP3V3_S0_INTDPMUX

TP_DP_TBTSRC_ML_CP<2>

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_N<2>

DP_INT_EG_ML_P<2>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<3>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CP<0>

DP_INTPNL_ML_P<0>

DP_INTPNL_ML_N<1>

DP_INTPNL_ML_N<0>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_C_P<0>
DP_INTPNL_ML_C_N<0>

DP_INTPNL_ML_C_N<1>

=PP3V3_S0_INTDPMUX

DP_INTPNL_AUX_P

DP_INTPNL_HPD

DP_INT_EG_AUX_C_N

DP_INT_EG_AUX_P

DP_INT_EG_AUX_N

DP_TBTSRC_AUX_C_P
DP_TBTSRC_AUX_C_N

DP_TBTSRC_AUXCH_P

DP_TBTSRC_AUXCH_N

DP_TBTSRC_HPD

DP_INT_EG_HPD

DP_INTPNL_AUX_N

DP_INTPNL_ML_C_P<1>

DP_GPU_TBT_SEL

DP_INT_EG_AUX_C_P

DP_INT_EG_HPD

C9270

1

2

U9220

2

3

1

6

5

4

R9222

12

L9201

1 2

C9268

1

2

C9269

1

2

C9200

1 2

C9201

1 2

C9202

1 2

C9203

1 2

C9208

1 2

C9209

1 2

C9211

1 2

C9210

1 2

R9200

1

2

R9201

1

2

R9202

1

2

R9203

1

2

U9200

7

6

32

18

19

14

15

2

1

30

31

24

25

5

4

26

27

22

23

21

28

8

17

13

11

10

33

39121620

29

R9212

1

2

C9212

1 2

C9213

1 2

C9214

1 2

C9215

1 2

R9213

1

2

R9214

1

2

R9215

1

2

051-9509

4.2.0

92 OF 113
82 OF 100

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82 98

82

86

6

82

6

82

98

98

98

6

82

98

98

98

98

98

78 82

IN

OUT

IN

BI

BI

IN

BI

VCC

OUTA1+
OUTA1-

OUTA0+
OUTA0-

SAO

OUTB1+
OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

ENB

SAI

INB-

INB+

SBI

GND

THRM

PAD

OUT
BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Dual-Port Host DDC Crossbar

77

85

34

85

77

77

77

20%

CERM

10V

0.1UF

402

TS3DS10224

QFN

84

84

TBT DDC Crossbar

SYNC_DATE=12/15/2011

SYNC_MASTER=D7_DOUG

TBT_DDC_XBAR_EN_L

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_DATA

DP_TBTSNK1_DDC_CLK

DP_TBTPA_DDC_CLK

DP_TBTPB_DDC_CLK
DP_TBTPB_DDC_DATA

DP_TBTPA_DDC_DATA

=PP3V3_S0_DP

C9300

1

2

U9300

16

10

5

2

1

4

3

17

18

19

20

9

8

7

6

14

15

12 11

21

13

051-9509

4.2.0

93 OF 113
83 OF 100

6

47 81

IN
IN

OUT

IN
IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

IN

IN

DPMLO+
DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIO­AUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX
LSRX

HPDOUT

HPD

OUT

BI
IN

IN

IN

IN

IN

OUT

OUT
OUT

OUT

OUT

IN
IN

BI
BI

IN
IN

OUT

ML_LANE1N

CONFIG1

SHLD

GND4

DP_PWR

CONFIG2

AUX_CHN

HPD

AUX_CHP

GND2

ML_LANE3N

GND1

ML_LANE3P

ML_LANE0N

ML_LANE1P

GND3

GND0

ML_LANE0P

SHLD

RETURN

ML_LANE2N

ML_LANE2P

PORT A

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: Polarity Swapped for layout!

NOTE: Polarity Swapped for layout!

NOTE: Polarity Swapped for layout!

For 12V systems:

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

Nominal Min Max

for single-fault protection(S0,S3 only)

Two Rs in series required by CD3210

Nominal Min Max

(Both D’s)

Thunderbolt Connector A

TBT: Terminated

18.9V Max

470k R’s for ESD protection
on AC-coupled signals.

(0-18.9V)

TBT: TX_1

TBT: RX_1 Bias Sink

(Both C’s)

Low: 0 - 0.8V

High: 2.0 - 5.0V

(Both C’s)

to 100K (DPv1.1a).

Sink HPD range:

greater than or equal

DP Source must pull

(Both C’s)

DP Dir

TBT: LSX_R2P/P2R (P/N)

TBT: LSX_A_R2P/P2R (P/N)

(Both C’s)

DP Dir

(0-18.9V)

down HPD input with

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

IV3P3 1100mA 1030mA 1200mA

3.3V/HV Power MUX

wake from Thunderbolt devices.

V3P3 must be S4 to support

12V: See
below

TBT: TX_0

TBT Dir

TBT Dir

514-0824

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

0.01UF

X7R
402

50V

10%

34 98

34 98

25V

0201

X5R-CERM

0.01UF

10%

5%

201

1/20W

MF

12

50V
X7R
402

10%

0.01UF

1/20W

201

MF

1K

5%

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

201

1/20W
MF

5%

1K

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

30PF

50V

CERM

402

5%

50V

30PF

5%

CERM
402

201

1/20W
MF

100K

5%

SIGNAL_MODEL=EMPTY

CRITICAL

650NH-5%-0.430MA-0.52OHM

GND_VOID=TRUE

0603

0603

CRITICAL

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

650NH-5%-0.430MA-0.52OHM

10V

0.1UF

20%

CERM
402

22UF

20%

X5R-CERM-1

6.3V

603

CRITICAL

100UF

POLY-TANT

CRITICAL

6.3V

20%

CASE-B2-SM

201

1/20W

MF

5%

1M

201

1/20W
MF

1M

5%

201

X7R

16V

10%

330PF

201

X7R

16V

330PF

10%

201

1/20W

MF

5%

GND_VOID=TRUE

2.2K

201

1/20W
MF

GND_VOID=TRUE

5%

2.2K

FERR-120-OHM-3A

0603

34

603-1

10%
50V
X7R

0.1UF

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

CRITICAL

TSLP-2-7

BAR90-02LRH

5%

GND_VOID=TRUE

201

MF

470K

1/20W

5%

470K

GND_VOID=TRUE

MF

1/20W

201

0.22UF

20%

6.3V

X5R

GND_VOID=TRUE

0201

X5R

20%

0.22UF

6.3V

GND_VOID=TRUE

0201

34 98

34 98

GND_VOID=TRUE

6.3V

X5R

20%

0.22UF

0201

0.22UF

GND_VOID=TRUE

6.3V

X5R

20%

0201

470K

5%

GND_VOID=TRUE

MF

1/20W

201

5%

MF

1/20W

201

GND_VOID=TRUE

470K

25V

0.01UF

0201

10%

X5R-CERM

25V

0201

10%

X5R-CERM

0.01UF

CD3210A0RGP

CRITICAL

QFN

34

45

60 85

TBTHV:P15V

1/16W
MF-LF

22.6K

1%

402

1%

402

1/16W

TBTHV:P15V

MF-LF

22.6K

1/16W

1%
MF-LF

402

36.5K

X7R

10%

603-1

50V

0.1UF

HVQFN

CBTL05023

CRITICAL

201

1/20W

MF

100K

5%

201

1/20W
MF

100K

5%

201

X5R

6.3V

10%

0.1UF

201

X5R

6.3V

10%

0.1UF

34

83

83

15 85

34

34

34

201

5%

1M

MF

1/20W

10K

5%
MF

1/20W
201

201

X5R

6.3V

0.1UF

10%

34

GND_VOID=TRUE

X5R

0.22UF

20%

6.3V
0201

0.22UF

X5R

GND_VOID=TRUE

6.3V

20%

0201

34 98

34 98

6.3V

20%

0.22UF

GND_VOID=TRUE

0201

X5R

6.3V

GND_VOID=TRUE

20%

0.22UF

X5R

0201

34 98

34 98

0.22UF

20%

0201

X5R

6.3V

0.22UF

6.3V

20%
X5R

0201

34 98

34 98

201X5R

6.3V

0.1UF

10%

201X5R

6.3V

10%

0.1UF

34 98

34 98

0.22UF

6.3V

20%
X5R

0201

6.3V

20%

0.22UF

0201

X5R

34 98

34 98

1/20W

MF

5%

470K

201

201

1/20W

MF

5%

470K

10%

4.7UF

X5R-CERM

25V

0603

22.6K

1/16W
MF-LF

402

1%

TBTHV:P15V

1%
1/16W

402

MF-LF

22.6K

TBTHV:P15V

SOT891

74AUP1T97

34

0.1UF

10%

0201

X5R-CERM

16V

F-ANG-TH

CRITICAL

DUAL-MDP-K70

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

114S0338

R9411,R9414

2

TBTHV:P12V

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

2

TBTHV:P12V

114S0338

R9410,R9413

SYNC_DATE=12/15/2011

SYNC_MASTER=D7_DOUG

Thunderbolt Connector A

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

VOLTAGE=3.3V

TBT_A_BIAS

TBTACONN_20_RC

VOLTAGE=18V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

TBTACONN_1_C

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_SW_TBTAPWR

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM

DP_A_LSX_ML_N<1>

TBT_A_D2R1_AUXDDC_N

TBT_A_HPD

TBT_A_D2R1_AUXDDC_P

TBT_A_R2D_N<0>

DP_A_LSX_ML_P<1>

TBT_A_R2D_P<0>

TBT_A_R2D_N<1>

TBT_A_R2D_P<1>

DP_A_AUXCH_DDC_N

TBT_A_D2R_C_N<1>

DP_TBTPA_ML_N<1>

=PP3V3_S4_TBT

TBT_A_CIO_SEL

TBT_A_CONFIG2_RC

DP_A_AUXCH_DDC_N

DP_TBTPA_ML_C_P<1>

TBT_A_D2R_N<0>

DP_A_AUXCH_DDC_P

TBT_A_R2D_C_P<0>
TBT_A_R2D_C_N<0>

TBT_A_CONFIG1_BUF

DP_TBTPA_DDC_DATA

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

DP_TBTPA_ML_P<1>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<1>

TBT_A_BIAS

TBT_A_HPD

DP_TBTPA_DDC_CLK

TBT_A_CONFIG1_RC

DP_A_AUXCH_DDC_P

DP_AUXIO_EN

TBT_A_LSTX

=PPHV_SW_TBTAPWRSW

TBTAPWRSW_ISET_S0_R

TBT_A_DP_PWRDN

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_N
DP_TBTPA_AUXCH_P

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<1>

TBT_A_LSRX

=PP3V3_S4_TBT

TBT_A_LSRX_UNBUF

TBT_A_D2R_C_P<1>

DP_TBTPA_ML_P<3>

TBT_A_D2R_C_P<0>

=TBTAPWRSW_EN

=PP3V3_S4_TBTAPWRSW

TBT_A_HV_EN

=TBT_S0_EN

TBTAPWRSW_ISET_S3_R

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_V3P3

TBT_A_D2R_N<1>
TBT_A_D2R_P<1>

TBT_A_CONFIG1_RC

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_C_N<3>

TBT_A_D2R_P<0>

DP_TBTPA_ML_C_P<3>

TBT_A_D2R_C_N<0>

L9400

1 2

C9400

1

2

C9402

1

2

R9401

1 2

C9401

1

2

R9494

1

2

R9495

1

2

C9498

1

2

C9499

1

2

R9441

1

2

L9498

12

L9499

12

C9481

1

2

C9480

1

2

C9487

1

2

R9452

1

2

R9451

1

2

C9494

1

2

C9495

1

2

R9498

1

2

R9499

1

2

C9410

1

2

D9499

A K

D9498

A K

R9470

1

2

R9471

1

2

C9471

1 2

C9470

1 2

C9472

1 2

C9473

1 2

R9473

1

2

R9472

1

2

C9405

1 2

C9406

1 2

U9410

5

123

4

13

11 10

9

8

12

14

1516

17

21

19

20

18

6
7

R9410

1

2

R9411

1

2

R9412

1

2

C9411

1

2

U9420

7

8

2

23

22

1

24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3

15

R9429

1

2

R9428

1

2

C9420

1

2

C9421

1

2

R9426

1

2

R9427

1

2

C9425

1

2

C9477

1 2

C9476

1 2

C9475

1 2

C9474

1 2

C9432

1 2

C9433

1 2

C9430

1 2

C9431

1 2

C9478

1 2

C9479

1 2

R9479

1 2

R9478

1 2

C9415

1

2

R9413

1

2

R9414

1

2

U9460

2

3

1

6

5

4

C9460

1

2

J9400

18

16

4
6

20

1

78

1314

2

5

3

11

9

17

15

12

10

19

41

5051524265

434445

46

47

48

49

051-9509

4.2.0

94 OF 113
84 OF 100

84

84 98

98

84

98

98

84 98

98

98

98

84 98

98

98

6

34 35 36 84 85

84 98

84 98

84 98

84 98

98

84

84

84

84 98

6

98

98

6

34 35 36 84 85

98

98

98

6

45

84

98

98

IN
IN

OUT

IN
IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

IN

IN

DPMLO+
DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIO­AUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX
LSRX

HPDOUT

HPD

OUT

BI
IN

IN

IN

IN

IN

OUT

OUT
OUT

OUT

OUT

IN
IN

BI
BI

IN
IN

OUT

GND1

ML_LANE0N

ML_LANE1P

AUX_CHN

AUX_CHP

CONFIG1
CONFIG2

DP_PWR

GND2

HPD

ML_LANE3N

ML_LANE3P

SHLD

SHLD

GND4

ML_LANE0P

GND0

RETURN

ML_LANE2N

ML_LANE2P

GND3

ML_LANE1N

PORT B

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: Polarity Swapped for Layout!

NOTE: Polarity Swapped for Layout!

NOTE: Polarity Swapped for Layout!

For 12V systems:

Thunderbolt Connector B

Nominal Min Max

(Both C’s)

for single-fault protection(S0,S3 only)

12V: See

18.9V Max

below

Nominal Min Max

wake from Thunderbolt devices.

V3P3 must be S4 to support

IV3P3 1100mA 1030mA 1200mA

down HPD input with

DP Source must pull

DP Dir

TBT: TX_0

TBT: Terminated

(Both C’s) (Both D’s)

to 100K (DPv1.1a).

Sink HPD range:

greater than or equal

DP Dir

TBT: TX_1

TBT: LSX_A_R2P/P2R (P/N)

(Both C’s)

TBT Dir

(0-18.9V)

(0-18.9V)

TBT: RX_1 Bias Sink

(Both C’s)

on AC-coupled signals.

470k R’s for ESD protection

Low: 0 - 0.8V

High: 2.0 - 5.0V

Two Rs in series required by CD3210

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT: LSX_R2P/P2R (P/N)

514-0824

TBT Dir

3.3V/HV Power MUX

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

50V

0.01UF

X7R
402

10%

34 98

34 98

25V

0.01UF

10%

X5R-CERM

0201

12

5%

MF

1/20W

201

0.01UF

10%

402

X7R

50V

1K

5%

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

MF

1/20W

201

5%

1K

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

MF

1/20W

201

30PF

50V

CERM

402

5%

30PF

5%

CERM

50V

402

201

1/20W
MF

5%

100K

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

0603

CRITICAL

650NH-5%-0.430MA-0.52OHM

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.52OHM

0603

CRITICAL

GND_VOID=TRUE

20%
10V
CERM
402

0.1UF

CRITICAL

20%

603

22UF

X5R-CERM-1

6.3V

CRITICAL

6.3V

20%

POLY-TANT

CASE-B2-SM

100UF

5%

1M

MF

1/20W

201

1M

5%
MF

1/20W

201

201

X7R

16V

330PF

10%

201

X7R

16V

10%

330PF

5%

GND_VOID=TRUE

2.2K

MF

1/20W

201

GND_VOID=TRUE

5%

2.2K

MF

1/20W

201

FERR-120-OHM-3A

0603

34

10%
50V
X7R
603-1

0.1UF

GND_VOID=TRUE

CRITICAL

TSLP-2-7

BAR90-02LRH

GND_VOID=TRUE

CRITICAL

BAR90-02LRH

TSLP-2-7

201

1/20W
MF

470K

5%

GND_VOID=TRUE GND_VOID=TRUE

201

1/20W
MF

5%

470K

0201

GND_VOID=TRUE

X5R

6.3V

20%

0.22UF

0.22UF

0201

GND_VOID=TRUE

6.3V

20%
X5R

34 98

34 98

0201

0.22UF

20%
X5R

6.3V

GND_VOID=TRUE

0201

0.22UF

20%
X5R

6.3V

GND_VOID=TRUE

1/20W

201

MF

470K

5%

GND_VOID=TRUEGND_VOID=TRUE

201

1/20W
MF

5%

470K

25V

10%

X5R-CERM

0.01UF

0201

25V

10%

X5R-CERM

0.01UF

0201

QFN

CRITICAL

CD3210A0RGP

34

45

60 84

22.6K

TBTHV:P15V

1/16W
MF-LF

402

1%

22.6K

1%

MF-LF
402

1/16W

TBTHV:P15V

402

1%

MF-LF

36.5K

1/16W

603-1

50V

0.1UF

X7R

10%

HVQFN

CBTL05023

CRITICAL

100K

5%
MF

1/20W

201

100K

5%

MF

1/20W

201

6.3V

0.1UF

X5R
201

10%

0.1UF

6.3V
X5R
201

10%

34

83

83

15 84

34

34

34

5%

1M

MF

1/20W

201

5%

10K

MF

1/20W
201

0.1UF

6.3V
X5R
201

10%

34

0201

6.3V

20%

0.22UF

X5R

GND_VOID=TRUE

0201

6.3V

GND_VOID=TRUE

20%
X5R

0.22UF

34 98

34 98

0201

X5R

GND_VOID=TRUE

0.22UF

20%

6.3V

6.3V
0201

X5R

20%

GND_VOID=TRUE

0.22UF

34 98

34 98

0201

0.22UF

6.3V

20%
X5R

0201

0.22UF

6.3V

20%
X5R

34 98

34 98

0.1UF

6.3V

X5R 201

10%

0.1UF

6.3V

X5R 201

10%

34 98

34 98

0201

X5R

20%

6.3V

0.22UF

0201

0.22UF

20%

6.3V

X5R

34 98

34 98

5%

470K

MF

1/20W

201

5%

470K

MF

1/20W

201

22.6K

1%

402

MF-LF

1/16W

TBTHV:P15V

22.6K

1/16W
402

MF-LF

1%

TBTHV:P15V

10%
25V

X5R-CERM

4.7UF

0603

74AUP1T97

SOT891

16V
X5R-CERM
0201

10%

0.1UF

34

F-ANG-TH

CRITICAL

DUAL-MDP-K70

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

2

TBTHV:P12V

R9611,R9614

114S0338

SYNC_DATE=12/15/2011

SYNC_MASTER=D7_DOUG

Thunderbolt Connector B

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

114S0338

TBTHV:P12V

2

R9610,R9613

PPHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

VOLTAGE=3.3V

TBT_B_BIAS

VOLTAGE=18V

TBTBCONN_20_RC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

MIN_LINE_WIDTH=0.38 MM

TBTBCONN_1_C

TBTBCONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

PP3V3RHV_SW_TBTBPWR

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM

TBTBPWRSW_ISET_V3P3

TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>

DP_TBTPB_ML_P<3>

TBT_B_HPD

TBT_B_R2D_N<0>

DP_B_LSX_ML_P<1>

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R1_AUXDDC_P

DP_TBTPB_ML_N<3>

TBT_B_R2D_P<0>

TBT_B_R2D_N<1>

TBT_B_R2D_P<1>

DP_B_LSX_ML_N<1>

TBT_B_BIAS

TBT_B_CIO_SEL

TBT_B_CONFIG2_RC

TBT_B_D2R_P<0>

TBT_B_CONFIG1_RC

DP_TBTPB_HPD

TBT_B_DP_PWRDN

TBT_B_HPD

TBT_B_CONFIG1_BUF

DP_TBTPB_DDC_DATA
DP_TBTPB_DDC_CLK

DP_B_LSX_ML_N<1>

DP_B_LSX_ML_P<1>

DP_B_AUXCH_DDC_P

DP_B_AUXCH_DDC_N

DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_C_P

TBT_B_R2D_C_N<1>

TBT_B_CONFIG1_RC

TBT_B_D2R_N<0>

DP_TBTPB_ML_C_P<3>
DP_TBTPB_ML_C_N<3>

DP_B_AUXCH_DDC_P

TBT_B_D2R_P<1>

TBT_B_D2R_C_N<1>

DP_TBTPB_AUXCH_N

TBT_B_LSTX

DP_TBTPB_ML_P<1>

DP_TBTPB_ML_C_P<1>
DP_TBTPB_ML_C_N<1>

DP_B_AUXCH_DDC_N

TBT_B_R2D_C_N<0>

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_P<1>

TBT_B_D2R_C_P<1>

=TBTBPWRSW_EN

TBTBPWRSW_ISET_S3

TBTBPWRSW_ISET_S0

TBT_B_HV_EN

TBTBPWRSW_ISET_S3_R

=TBT_S0_EN

=PPHV_SW_TBTBPWRSW

=PP3V3_S4_TBTBPWRSW

TBTBPWRSW_ISET_S0_R

=PP3V3_S4_TBT

TBT_B_LSRX

DP_AUXIO_EN

DP_TBTPB_ML_N<1>

DP_TBTPB_AUXCH_P

=PP3V3_S4_TBT

TBT_B_LSRX_UNBUF

TBT_B_D2R_N<1>

L9600

1 2

C9600

1

2

C9602

1

2

R9601

1 2

C9601

1

2

R9694

1

2

R9695

1

2

C9698

1

2

C9699

1

2

R9641

1

2

L9698

12

L9699

12

C9681

1

2

C9680

1

2

C9687

1

2

R9652

1

2

R9651

1

2

C9694

1

2

C9695

1

2

R9698

1

2

R9699

1

2

C9610

1

2

D9699

A K

D9698

A K

R9670

1

2

R9671

1

2

C9671

1 2

C9670

1 2

C9672

1 2

C9673

1 2

R9673

1

2

R9672

1

2

C9605

1 2

C9606

1 2

U9610

5

123

4

13

11 10

9

8

12
14

1516

17

21

19
20

18

6

7

R9610

1

2

R9611

1

2

R9612

1

2

C9611

1

2

U9620

7

8

2

23

22

1

24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3

15

R9629

1

2

R9628

1

2

C9620

1

2

C9621

1

2

R9626

1

2

R9627

1

2

C9625

1

2

C9677

1 2

C9676

1 2

C9675

1 2

C9674

1 2

C9632

1 2

C9633

1 2

C9630

1 2

C9631

1 2

C9678

1 2

C9679

1 2

R9679

1 2

R9678

1 2

R9613

1

2

R9614

1

2

C9615

1

2

U9660

2

3

1

6

5

4

C9660

1

2

J9400

38

36

24
26

40

21

2728

3334

22

25

23

31

29

37

35

32

30

39

53

5455565758

59

6061626364

65

051-9509

4.2.0

96 OF 113
85 OF 100

85

98

98

98

85

98

85 98

98

98

98

98

98

98

85 98

85

85

85

85 98

85 98

85 98

85 98

85

85 98

98

98

98

85 98

98

6

6

45

6

34 35 36 84 85

98

98

6

34 35 36 84 85

S

G

D

ISENSE_GND

GD

VLDO

VDDIO

VIN

SD

VSYNC

SCLK

SDA

PWM

EN

OUT1

OUT2

OUT4

OUT3

OUT5

OUT6

ISENSE

FB

GND_S

GND_S

GND_L

THRM

FILTER

ISET

PAD

IN

IN

IN

IN

S

D

G

D

G S

IN

IN

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CRITICAL

IRF6645PBF

DIRECTFET-SJ

10%
50V

0.001UF

402

CERM

603-1

X5R

25V

10%

1UF

25V

1UF

X5R

10%

603-1

5%

603

CERM

50V

4700PF

CERM

402

16V

10%

0.01UF

0.01UF

10%
16V

CERM

402

0.1UF

402

10%
16V
X5R

402

16V

10%

0.1UF

X5R

402

MF-LF

1%
1/16W

1M

MF-LF

5%

330K

1/16W
402

1%

12.4K

1/16W
MF-LF
402

301K

MF-LF

1/16W

1%

402

NOSTUFF

1%

MF-LF

1/16W

147K

402

1206

FERR-600-OHM-3A

SM-1

400-OHM-EMI

400-OHM-EMI

SM-1

SM-1

400-OHM-EMI

SM-1

400-OHM-EMI

SM-1

400-OHM-EMI

400-OHM-EMI

SM-1

SM-1

400-OHM-EMI

400-OHM-EMI

SM-1

100V

100PF

5%

0603-1

C0G-CERM

NOSTUFF

5%

MF-LF

1/10W

603

0

C0G-CERM

1000PF

603

5%
50V

NOSTUFF

C0G-CERM

5%
100V

100PF

0603

0603

100PF

5%
C0G-CERM

100V

5%
C0G-CERM

100V

100PF

0603

10%
CERM

402

330PF

50V

5%

270K

402

MF-LF

1/16W

CERM

50V

5%

33PF

402

NOSTUFF

0

402

NOSTUFF

5%

MF-LF1/16W

100PF

5%

0603

100V
C0G-CERM

0603

C0G-CERM

5%
100V

100PF

C0G-CERM

100V

5%

100PF

0603

1UF

X7R

10%

805

25V 25V

10%
X7R

805

1UF 1UF

805

25V

10%
X7R

805

X7R

1UF

25V

10%

402

MF-LF

5%
1/16W

0

SM

MF-LF

1/16W
402

10K

1%

OMIT_TABLE

CRITICAL

LLP

LP8561

1/8W

0

5%

805

MF-LF

SM

402

MF-LF

1/16W

5%

1

402

1

5%
1/16W
MF-LF

MF-LF

5%

1/16W

0

402

5%01/16W MF-LF

402

1/16W

402

5%

MF-LF

0

NOSTUFF

1/16W

NOSTUFF

402

5%

MF-LF

0

47

47

47

47

5AMP-32V

0603

402

10%
25V
X5R

0.1UF

NOSTUFF

1/10W
MF-LF
603

0

5%

SM

SM

SM

0.100

1/16W

402

MF1%

2512

1%
MF-LF

0.05

1W

1/10W

1%

603

MF-LF

100K

5%

1206

MF-LF

4.7

1/4W

NOSTUFF

DEVELOPMENT

M-ST-SM

50293-00471-H01

0

5%

MF-LF

402

1/16W

402

NOSTUFF

MF-LF

1/16W

5%

0

0

5%

1/16W

402

MF-LF

FDMS6681Z

POWER56

CRITICAL

CRITICAL

33UH-20%-10A-0.0351OHM

IHLP6767GZ-IHLP4040DZ11-SM

VESM

SSM3K15AMFVAPE

81 86

81 86

0603

10%
100V

CRITICAL

1000PF

X7R-CERM

1000PF

100V
0603

X7R-CERM

CRITICAL

10%

CRITICAL

10%

1000PF

0603

100V
X7R-CERM

0603

1000PF

10%
100V
X7R-CERM

CRITICAL CRITICAL

0603

1000PF

10%
100V
X7R-CERM X7R-CERM

100V

10%

0603

1000PF

CRITICAL

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

2.2UF

100V
X7R-CERM
1206

CRITICAL

10%

1206

100V

10%

2.2UF

CRITICAL

X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM X7R-CERM

100V

10%

2.2UF

CRITICAL

1206

CRITICAL

SI3440DVT1GE3

TSOP TSOP

CRITICAL

SI3440DVT1GE3

TSOP

CRITICAL

SI3440DVT1GE3

TSOP

CRITICAL

SI3440DVT1GE3

TSOP

CRITICAL

SI3440DVT1GE3 SI3440DVT1GE3

CRITICAL

TSOP

0603

33PF

5%
100V
C0G-CERM

504050-1091

CRITICAL

F-RT-SM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

X7R-CERM

100V

10%

2.2UF

CRITICAL

1206 1206

CRITICAL

2.2UF

10%
100V
X7R-CERM

805

10%
25V
X5R

10UF

10%

805

10UF

25V
X5R

25V
805

10%
X5R

10UF

805

10%
25V
X5R

10UF

X5R
402

25V

0.1UF

10%

402

25V

10%

0.1UF

X5R

NOSTUFF

0.1UF

10%
25V
X5R
402

0.1UF

X5R

25V

10%

402

NOSTUFF

CRITICAL

PDS5100H

POWERDI5-TO277A

SYNC_DATE=01/03/2012

SYNC_MASTER=D7_NICK

LCD Backlight Driver (LP8545)

BLC_CAP

138S0743138S0745

BLC Ouput Cap

353S3665

IC,LP8561,LED BKLT CTRLR,LLP24,B0

U9700

1

CRITICAL

ALL

Short Protection FET

376S1071 376S1073

152S1592

BLC Switch Inductor

152S1591

L9700

376S1022

Q9700

BLC Switch FET

376S1054

371S0648 371S0694

D9700

BLC Switch Diode

Q9702

376S1067376S0845

BLC Inrush FET

BKLT_BOOST

PGND_BKLT

BKLT_BOOST

PGND_BKLT

PP12V_S0_BKLT_PWR

BKLT_BOOST

PGND_BKLT

PGND_BKLTBKLT_SW_N

BKLT_FB

PP5V_S0_BKLT_R

PGND_BKLT

LGND_BKLT

BKLT_ISEN2

DGND_BKLT

BKLT_ISEN1_R

PGND_BKLT

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

BKLT_BOOST_1
BKLT_BOOST_2

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

BKLT_ISEN2_R

BKLT_ISEN2 BKLT_ISEN4

PP12V_S0_BKLT_FUSED

BKLT_GATE_R

BKLT_GATE

BKLT_ISEN4

BKLT_FB_R

=PP12V_S0_BKLT

PP12V_S0_BKLT_PWR

PGND_BKLT

BKLT_SNUBBER

BKLT_PHASE

BKLT_FLT

DGND_BKLT

BKLT_ISET

BKLT_SHUTDOWN

DGND_BKLT

DGND_BKLT

BKLT_ISEN3

BKLT_ISEN4

BKLT_ISEN6

BKLT_FLT_RC

BKLT_ISEN6

BKLT_ISEN5

BKLT_ISEN3

BKLT_SCL
BKLT_SDA

PP5V_S0_BKLT_R

PP3V3_S0_BKLT_VDDIO_R

=I2C_BKLT_SDA

=SMB_DP_BLC_SCL

PP12V_S0_BKLT_PWR_R

BKLT_BOOST

PGND_BKLT PGND_BKLT

DGND_BKLT

PGND_BKLT

BKLT_SCL

BKLT_EN

=PP3V3_S0_BKLT_VDDIO

=PP5V_S0_BKLT

LCD_BKLT_PWM_R

LCD_BKLT_PWM

=PP12V_S0_BKLT

BKLT_FB_XW

BKLT_SDA

PP12V_S0_BKLT_PWR

LVDS_BKLT_PWM_RC

PP12V_S0_BKLT_PWR

BKLT_ISEN2_R

LCD_BKLT_PWM

=I2C_BKLT_SCL

BKLT_SW_N

PGND_BKLT

=PP3V3_S0_BKLT_VDDIO

BKLT_ISEN5_R

BKLT_ISEN4_R

BKLT_ISEN3_R

BKLT_ISEN1_R

LGND_BKLT

BKLT_SHUTDOWN

BKLT_ISEN1

DGND_BKLT

BKLT_VSYNC_R

PP3V3_S0_BKLT_VDDIO_R

PP12V_S0_BKLT_PWR_R

BKLT_VSYNC

BKLT_VSYNC_R

PP12V_S0_BKLT_FILT

=SMB_DP_BLC_SDA

BKLT_EN_DIV

BKLT_ISEN6_R

BKLT_SW_R

BKLT_EN_L

BKLT_ISEN2

BKLT_EN

BKLT_EN

PP12V_S0_BKLT_PWR

BKLT_BOOST

BKLT_ISEN1

BKLT_ISEN5

BKLT_SW_P

BKLT_ISEN1 BKLT_ISEN3

BKLT_ISEN3_R BKLT_ISEN4_R

BKLT_ISEN5

BKLT_ISEN5_R

BKLT_ISEN6

BKLT_ISEN6_R

C9700

1

2

C9701

1

2

C9702

1

2

C9703

1

2

C9704

1

2

C9705

1

2

C9706

1

2

C9707

1

2

D9700

1

2

3

Q9700

1 2 6 7

5

3 4

C9737

1

2

C9731

1

2

C9734

1

2

C9729

1

2

C9732

1

2

C9735

1

2

C9733

1

2

C9736

1

2

R9710

1

2

R9711

1

2

R9705

1

2

R9721

1

2

R9720

1 2

FB9708

1 2

FB9700

1 2

FB9701

1 2

FB9702

1 2

FB9703

1 2

FB9704

1 2

FB9705

1 2

FB9706

1 2

FB9707

1 2

C9727

1

2

R9707

1 2

C9726

1

2

C9720

1

2

C9721

1

2

C9722

1

2

C9730

1

2

R9703

1

2

C9728

1

2

R9702

1 2

C9723

1

2

C9724

1

2

C9725

1

2

C9751

1

2

C9752

1

2

C9753

1

2

C9754

1

2

R9722

1

2

XW9702

12

R9723

1

2

U9700

4

21

20

6

15

5

9

24

1

3

12

13

14

16

17

18

2

10

7

11

25

82322

19

R9706

1

2

XW9701

12

R9730

1 2

R9731

1 2

R9701

1 2

R9700

1 2

R9740

1 2

R9741

1 2

F9700

1 2

C9771

1

2

R9724

1

2

XW9703

12

XW9704

12

XW9705

12

R9704

1 2

R9708

1

2

R9750

1

2

R9709

1

2

J9710

1
2
3
4

R9760

1 2

R9761

1

2

R9752

1 2

Q9702

5

4

1

2

3

L9700

1 2

Q9701

3

1

2

C9740

1

2

C9741

1

2

C9742

1

2

C9743

1

2

C9744

1

2

C9745

1

2

C9708

1

2

C9709

1

2

C9710

1

2

C9711

1

2

C9712

1

2

C9713

1

2

C9714

1

2

C9715

1

2

C9716

1

2

C9717

1

2

C9718

1

2

C9719

1

2

C9793

1

2

C9794

1

2

C9795

1

2

C9796

1

2

Q9705

1
2
5
63

4

Q9706

1
2
5
63

4

Q9707

1
2
5
63

4

Q9708

1
2
5
63

4

Q9709

1
2
5
63

4

Q9710

1
2
5
63

4

C9760

1

2

J9700

11

12

1

10

2
3
4
5
6
7
8
9

C9797

1

2

C9790

1

2

C9791

1

2

C9792

1

2

051-9509

4.2.0

97 OF 113
86 OF 100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

100

100

100

100

100

100

100

100

86

100

86

100

86

100

100

100

100

86

100

100

6

86

86

100

86

100

100

100

100

86

100

100

86

86

100

86

100

86

100

86

100

86

100

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

6

86

6

82 86

6

86

100

86

100

86

100

86

100

86

100

82
86

86

100

86

100

6

86

86

100

86

100

86

100

86

100

86

100

86

86

100

86

100

86

86

100

86

100

81 86

86

100

100

86

100

81 86

86

100

86

100

86

100

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

86

100

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

General Physical Rule Definitions

0.5 oz (Cu plated)

General Spacing Definitions

Btm

Signal

6

2

3

4

5

Core

Signal

Signal

Plane

Plane

Plane

2

Top

Signal

Plane

Finished board thickness: 1.58 mm

Board Stack-up

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

Prepreg

0.071 mm

0.5 oz

0.076 mm

1 oz

0.071 mm

0.435 mm
1 oz

0.5 oz (Cu plated)

1 oz

0.076 mm

0.5 oz

1 oz

0.435 mm

0.127 mm

K70 Board Specific Physical and Spacing Constraints

BGA

BGA Area Constraints

Fixed and Dielectric

Power and Common

Default

NO_TYPE,BGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM

16.2

MM

0.1 MM

=50_OHM_SE

Y*

DEFAULT

10 MM

0 MM 0 MM

10 MM

=DEFAULT =DEFAULT

=DEFAULT

* Y

STANDARD

=DEFAULT

=STANDARD =STANDARD* Y

0.085 MM

=STANDARD34_OHM_SE

0.215 MM

=STANDARD

=STANDARD

* Y =STANDARD

0.085 MM

39_OHM_SE

0.170 MM

0.145 MM

42_OHM_SE

=STANDARD =STANDARD* Y

0.085 MM

=STANDARD

?

=STANDARD

GND

*

GND_P2MM

1000

=2:1_SPACING

*

PWR_P2MM

*

=2:1_SPACING

1100

STANDARD

*

?

=DEFAULT

1X_DIELECTRIC?TOP,BOTTOM

0.071 MM

K70 Rule Definitions

SYNC_DATE=12/12/2011

SYNC_MASTER=D7_DAVE

TOP,BOTTOM

0.190 MM

Y

85_OHM_DIFF

=STANDARD

0.085 MM0.125 MM

0.1 MM

0.1 MM

0.085 MM

Y*

=STANDARD

68_OHM_DIFF

0.180 MM

0.140 MM

0.085 MM

0.1 MM

=STANDARD

Y

TOP,BOTTOM

68_OHM_DIFF

0.180 MM

0.140 MM

=STANDARD

=STANDARD

0.085 MM

Y

0.110 MM

TOP,BOTTOM

50_OHM_SE

=STANDARD

0.085 MM

=STANDARD

50_OHM_SE

Y*

0.110 MM

=STANDARD

=STANDARD

=STANDARD

TOP,BOTTOM

=STANDARDY

0.085 MM

=STANDARD

45_OHM_SE

0.138 MM

=STANDARD

0.085 MM

Y* =STANDARD=STANDARD

45_OHM_SE

0.138 MM

0.145 MM

42_OHM_SE

=STANDARD

0.085 MM

Y =STANDARD

TOP,BOTTOM

=STANDARD

=STANDARD

TOP,BOTTOM

Y =STANDARD

=STANDARD39_OHM_SE

0.170 MM 0.085 MM

DEFAULT

?

0.1 MM

*

BGA

* *

BGA_P1MM

1X_DIELECTRIC

?

*

0.076 MM

1:1_SPACING

0.1 MM

*

?

BGA_P1MM

=STANDARD

?

*

=STANDARD=STANDARD

0.085 MM

Y

TOP,BOTTOM

=STANDARD34_OHM_SE

0.215 MM

0.085 MM 0.085 MM

=STANDARD =STANDARD

=STANDARD

Y

TOP,BOTTOM

55_OHM_SE

=STANDARDY

0.085 MM 0.085 MM

=STANDARD

*

55_OHM_SE

=STANDARD

TOP,BOTTOM

0.111 MM 0.085 MM

=STANDARD

0.200 MM

90_OHM_DIFF

0.1 MMY

0.111 MM

0.200 MM

=STANDARD

* Y

90_OHM_DIFF

0.085 MM

0.1 MM

100_OHM_DIFF

0.220 MM

=STANDARD

0.085 MM

Y

0.089 MM

TOP,BOTTOM

0.1 MM

100_OHM_DIFF

0.089 MM

* 0.1 MM

0.220 MM

0.085 MM

=STANDARD

Y

TOP,BOTTOM

0.135 MM

Y

80_OHM_DIFF

=STANDARD

0.1 MM

0.085 MM

0.160 MM

*

=STANDARD

0.135 MM

Y

80_OHM_DIFF

0.085 MM

0.1 MM

0.160 MM

0.190 MM

* Y

85_OHM_DIFF

=STANDARD

0.085 MM

0.1 MM

0.125 MM

051-9509

4.2.0

100 OF 113

87 OF 100

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

DDR3-specific Spacing Definitions

Clocks: CK[3:0], CK#[3:0]

Constraints

Command: MA[15:0], RAS#, CAS#, WE# BS[2:0]

Control: CS#[3:0], CKE[3:0], ODT[3:0]

Note (3):

Note (2):

Note (1):

20 mA per trace with edge rates in the 100s of ps. The main

one rule per channel is needed by trading off a little space.

complexity to contraints, even though it can be less. Only

Deliberately set DQ to DQS spacing to 3:1 to avoid adding

coupling mechanism is capacitive. A 0.65 mm spacing is used
for power nets, which draw far more current (inductive
coupling however). These rules are far too conservative.

In order for the constraints DDR_*_DQ_BYTE* to =SAME to win
out over DDR_{A,B}_DQ_BYTE* to DDR_{A,B}_DQ_BYTE* so that

To meet these rules, the spacing must be applied to the net.

DDR_DQ2DQ must have a weight greater than DDR_BL2BL.

the small intra-bytelane spacing is used, the spacing rule

and via to pad to two different channels. DDR3 draws about

Intel suggests 25 mil (0.65 mm) spacing for via to channel,

-

3-5

3-4

Table
3-2

3-3

12

10

12

25

126

8.5

7.87

7.87

9.84

Trace

15

12

(diff)

Design

4

8

Iso

Data: DQS[7:0], DQS#[7:0], DQ[63:0]

25.59

13.78

19.69

Design

25.59

11.81

13.78

Comments

11.81

11.81

DQ or DQS to other signals not in the same bytelane (but not ch)

DQ to DQS in the same bytelane of the same channel

DDR3 to any other signal not DDR3

CLK trace spacing controlled by =68_OHM_DIFF

DQ to DQ in the same bytelane of the same channel

DQ or DQS in different channels

DQ or DQS in different bytelanes of the same channel

See Note (1)

See Note (3)

See Note (2)

See Note (3)

See Note (1)

Channel B

DDR3

Spacing

Channel A

Physical

DDR3-specific Physical Rules

DDR3

Table 3-5, Intel Doc# 473718

Minimum diff spacing is 4 mil

Electrical Contraint Set

Reset

Main Segment Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

DDR3 Power-specific Spacing Definitions

Physical Net Type to Rule Map

I178

I179

I180

I181

I182

I183

I184

I185
I186

I187

I188

I189

I190

I191

I192
I193

I194
I195

I196

I197

I198
I199

I200

I201

I202

I203

I204

I205

I206
I207

I208

I209
I210

I211

I212
I213

I214
I215

I216

I217
I218

I219

I220
I221

I222

I223

I224

I225

I226

I227
I228

I229

I230
I231

I232

I233
I234

I235

I236

I237

I238
I239

I240

I241
I242

I243

I244
I245

I246

I247

I248

I249

I250
I251

I252

I253

I254

I255
I256

SYNC_MASTER=D7_DAVE

SYNC_DATE=12/12/2011

DDR3 Constraints

?

*

DDR_CTRL_ISO

=3.5:1_SPACING

900

DDR_DQ2DQ

*

=2:1_SPACING

=5:1_SPACING

?

*

DDR_CLK_ISO

=3:1_SPACING

*

DDR_BL2BL

?

DDR_DATA_ISO

**

DDR_B_DQ_BYTE*

DDR_DATA_ISO

**

DDR_B_DQS*

DDR_DQ2DQS

*

DDR_A_DQS*

DDR_A_DQ_BYTE*

DDR_B_DQ_BYTE*

*

DDR_DQ2DQSDDR_B_DQS*

=34_OHM_SE =34_OHM_SE

=STANDARD

=34_OHM_SE=34_OHM_SE

* =STANDARD

DDR_34S

=39_OHM_SE =39_OHM_SE=39_OHM_SE =39_OHM_SE

=STANDARD* =STANDARD

DDR_39S

=42_OHM_SE =42_OHM_SE=42_OHM_SE

*

DDR_42S

=42_OHM_SE

=STANDARD=STANDARD

=42_OHM_SE =42_OHM_SE=42_OHM_SE

*

=42_OHM_SE

0.1016 MM 0.1016 MM

DDR_42S_D

=50_OHM_SE =50_OHM_SE

*

=50_OHM_SE

DDR_50S

=50_OHM_SE

=STANDARD =STANDARD

=68_OHM_DIFF=68_OHM_DIFF=68_OHM_DIFF

* =68_OHM_DIFF

DDR_68D

=68_OHM_DIFF

=68_OHM_DIFF

*

DDR_CMD2CMD

DDR_CMD DDR_CMD

**

DDR_CMD_ISO

DDR_CMD

DDR_CTRL2CTRL

*

DDR_CTRL DDR_CTRL

**

DDR_CTRL_ISO

DDR_CTRL

DDR_CLK_ISO

* *

DDR_CLK

*

?

DDR_CH2CH

=6.5:1_SPACING

?

=3.5:1_SPACING

*

DDR_CMD_ISO

=2.5:1_SPACING

*

DDR_CTRL2CTRL

?

DDR_CH2CH

DDR_B_*DDR_A_*

*

*

DDR_B_DQ_BYTE*DDR_B_DQ_BYTE*

DDR_BL2BL

*

DDR_BL2BL

DDR_A_DQ_BYTE*DDR_A_DQ_BYTE*

DDR_DQ2DQ

*

DDR_*_DQ_BYTE*

=SAME

DDR_DATA_ISO

*

DDR_A_DQS*

*

DDR_DATA_ISO

**

DDR_A_DQ_BYTE*

DDR_DQS_PHY

DDR_42S_D

*

POWER_DDR

?

=2:1_SPACING

*

POWER_DDR_P4MM

POWER_DDR

*

DDR_68D

*

DDR_CLK_PHY

DDR_39S

*

DDR_CTRL_PHY

DDR_34S

*

DDR_CMD_PHY

=3:1_SPACING

?

*

DDR_DATA_ISO

=3:1_SPACING

?

*

DDR_DQ2DQS

=2:1_SPACING

?

*

DDR_CMD2CMD

DDR_42S

*

DDR_DQ_PHY

0.100 MM

POWER_DDR_P4MM

0.400 MM

3.0 MM

=STANDARDY =STANDARD*

DDR_A_DQS6

MEM_A_DQS_N<6>

DDR_A_DQS6

DDR_DQS_PHY

DDR_CMD

MEM_A_A<15..0>

DDR_A_CMD

DDR_CMD_PHY

DDR_CMD

MEM_A_BA<2..0>

DDR_A_CMD

DDR_CMD_PHY

DDR_CMD

MEM_A_RAS_L

DDR_A_CMD

DDR_CMD_PHY

MEM_A_CKE<1..0>

DDR_CTRL

DDR_A_CTRL0

DDR_CTRL_PHY

MEM_A_ODT<1..0>

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL0

MEM_A_DQ<47..40>

DDR_A_DQ_BYTE5DDR_A_DQ_BYTE5

DDR_DQ_PHY

DDR_A_DQ_BYTE6

MEM_A_DQ<55..48>

DDR_A_DQ_BYTE6

DDR_DQ_PHY

DDR_A_DQ_BYTE7DDR_A_DQ_BYTE7

MEM_A_DQ<63..56>

DDR_DQ_PHY

MEM_A_CS_L<1..0>

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL0

DDR_A_DQ_BYTE1

MEM_A_DQ<15..8>

DDR_A_DQ_BYTE1

DDR_DQ_PHY

DDR_A_DQS0

MEM_A_DQS_N<0>

DDR_A_DQS0

DDR_DQS_PHY

MEM_B_CLK_N<3..2>

DDR_B_CLK1

DDR_CLK

DDR_CLK_PHY

DDR_CTRL

DDR_B_CTRL0

MEM_B_CKE<1..0>

DDR_CTRL_PHY

DDR_CTRL

DDR_B_CTRL0

MEM_B_CS_L<1..0>

DDR_CTRL_PHY

MEM_A_DQS_P<7>

DDR_A_DQS7DDR_A_DQS7

DDR_DQS_PHY

DDR_A_DQS6 DDR_A_DQS6

MEM_A_DQS_P<6>

DDR_DQS_PHY

DDR_A_DQS3 DDR_A_DQS3

MEM_A_DQS_P<3>

DDR_DQS_PHY

DDR_A_DQS1

MEM_A_DQS_P<1>

DDR_A_DQS1

DDR_DQS_PHY

DDR_CLK

MEM_A_CLK_P<3..2>

DDR_A_CLK1

DDR_CLK_PHY

DDR_CLK

MEM_A_CLK_N<3..2>

DDR_A_CLK1

DDR_CLK_PHY

DDR_CLK

MEM_A_CLK_N<1..0>

DDR_A_CLK0

DDR_CLK_PHY

DDR_CLK

MEM_A_CLK_P<1..0>

DDR_A_CLK0

DDR_CLK_PHY

MEM_A_CKE<3..2>

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL1

MEM_A_ODT<3..2>

DDR_CTRL

DDR_A_CTRL1

DDR_CTRL_PHY

MEM_A_CS_L<3..2>

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL1

DDR_CMD

MEM_A_WE_L

DDR_A_CMD

DDR_CMD_PHY

DDR_CMD

MEM_A_CAS_L

DDR_A_CMD

DDR_CMD_PHY

DDR_A_DQ_BYTE0

MEM_A_DQ<7..0>

DDR_A_DQ_BYTE0

DDR_DQ_PHY

DDR_A_DQ_BYTE3

MEM_A_DQ<31..24>

DDR_A_DQ_BYTE3

DDR_DQ_PHY

DDR_A_DQ_BYTE2 DDR_A_DQ_BYTE2

MEM_A_DQ<23..16>

DDR_DQ_PHY

MEM_A_DQ<39..32>

DDR_A_DQ_BYTE4DDR_A_DQ_BYTE4

DDR_DQ_PHY

DDR_A_DQS0 DDR_A_DQS0

MEM_A_DQS_P<0>

DDR_DQS_PHY

MEM_A_DQS_N<1>

DDR_A_DQS1DDR_A_DQS1

DDR_DQS_PHY

DDR_A_DQS2

MEM_A_DQS_N<2>

DDR_A_DQS2

DDR_DQS_PHY

DDR_A_DQS4

MEM_A_DQS_P<4>

DDR_A_DQS4

DDR_DQS_PHY

DDR_A_DQS3 DDR_A_DQS3

MEM_A_DQS_N<3>

DDR_DQS_PHY

DDR_A_DQS5

MEM_A_DQS_P<5>

DDR_A_DQS5

DDR_DQS_PHY

DDR_A_DQS4 DDR_A_DQS4

MEM_A_DQS_N<4>

DDR_DQS_PHY

DDR_A_DQS5

MEM_A_DQS_N<5>

DDR_A_DQS5

DDR_DQS_PHY

DDR_A_DQS7

MEM_A_DQS_N<7>

DDR_A_DQS7

DDR_DQS_PHY

DDR_B_CLK0

DDR_CLK

DDR_CLK_PHY

MEM_B_CLK_P<1..0>

MEM_B_CLK_P<3..2>

DDR_B_CLK1

DDR_CLK

DDR_CLK_PHY

MEM_B_CLK_N<1..0>

DDR_B_CLK0

DDR_CLK

DDR_CLK_PHY

DDR_CTRL

MEM_B_CKE<3..2>

DDR_B_CTRL1

DDR_CTRL_PHY

DDR_CTRL

DDR_B_CTRL0

MEM_B_ODT<1..0>

DDR_CTRL_PHY

DDR_CTRL

MEM_B_CS_L<3..2>

DDR_B_CTRL1

DDR_CTRL_PHY

DDR_CTRL

MEM_B_ODT<3..2>

DDR_B_CTRL1

DDR_CTRL_PHY

DDR_CMD

MEM_B_A<15..0>

DDR_B_CMD

DDR_CMD_PHY

DDR_CMD

MEM_B_RAS_L

DDR_B_CMD

DDR_CMD_PHY

DDR_CMD

MEM_B_BA<2..0>

DDR_B_CMD

DDR_CMD_PHY

MEM_B_WE_L

DDR_B_CMD

DDR_CMD

DDR_CMD_PHY

DDR_CMD

MEM_B_CAS_L

DDR_B_CMD

DDR_CMD_PHY

MEM_B_DQ<15..8>

DDR_B_DQ_BYTE1DDR_B_DQ_BYTE1

DDR_DQ_PHY

DDR_B_DQ_BYTE0

MEM_B_DQ<7..0>

DDR_B_DQ_BYTE0

DDR_DQ_PHY

DDR_B_DQ_BYTE2

MEM_B_DQ<23..16>

DDR_B_DQ_BYTE2

DDR_DQ_PHY

DDR_B_DQ_BYTE4

MEM_B_DQ<39..32>

DDR_B_DQ_BYTE4

DDR_DQ_PHY

DDR_B_DQ_BYTE3

MEM_B_DQ<31..24>

DDR_B_DQ_BYTE3

DDR_DQ_PHY

MEM_B_DQ<55..48>

DDR_B_DQ_BYTE6DDR_B_DQ_BYTE6

DDR_DQ_PHY

DDR_B_DQ_BYTE5

MEM_B_DQ<47..40>

DDR_B_DQ_BYTE5

DDR_DQ_PHY

DDR_B_DQ_BYTE7DDR_B_DQ_BYTE7

MEM_B_DQ<63..56>

DDR_DQ_PHY

MEM_B_DQS_P<0>

DDR_B_DQS0 DDR_B_DQS0

DDR_DQS_PHY

MEM_B_DQS_N<0>

DDR_B_DQS0 DDR_B_DQS0

DDR_DQS_PHY

DDR_B_DQS1

MEM_B_DQS_N<1>

DDR_B_DQS1

DDR_DQS_PHY

MEM_B_DQS_P<1>

DDR_B_DQS1 DDR_B_DQS1

DDR_DQS_PHY

DDR_B_DQS2

MEM_B_DQS_P<2>

DDR_B_DQS2

DDR_DQS_PHY

DDR_B_DQS4

MEM_B_DQS_P<4>

DDR_B_DQS4

DDR_DQS_PHY

DDR_B_DQS4

MEM_B_DQS_N<4>

DDR_B_DQS4

DDR_DQS_PHY

DDR_B_DQS5

MEM_B_DQS_N<5>

DDR_B_DQS5

DDR_DQS_PHY

DDR_B_DQS5

MEM_B_DQS_P<5>

DDR_B_DQS5

DDR_DQS_PHY

DDR_B_DQS6

MEM_B_DQS_N<6>

DDR_B_DQS6

DDR_DQS_PHY

DDR_B_DQS6

MEM_B_DQS_P<6>

DDR_B_DQS6

DDR_DQS_PHY

DDR_B_DQS7

MEM_B_DQS_P<7>

DDR_B_DQS7

DDR_DQS_PHY

DDR_B_DQS7

MEM_B_DQS_N<7>

DDR_B_DQS7

DDR_DQS_PHY

MEM_RESET_L

DDR_50S

DDR_A_DQS2

MEM_A_DQS_P<2>

DDR_A_DQS2

DDR_DQS_PHY

MEM_B_DQS_N<3>

DDR_B_DQS3 DDR_B_DQS3

DDR_DQS_PHY

DDR_B_DQS3DDR_B_DQS3

MEM_B_DQS_P<3>

DDR_DQS_PHY

DDR_B_DQS2

MEM_B_DQS_N<2>

DDR_B_DQS2

DDR_DQS_PHY

051-9509

4.2.0

101 OF 113

88 OF 100

12 31

12 29

12 29

12 29

12 29

12 29

12 31

12 31

12 31

12 29

12 31

12 31

8

12

12 30

12 30

12 31

12 31

12 31

12 31

8

12

8

12

12 29

12 29

8

12

8

12

8

12

12 29

12 29

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 30

8

12

12 30

8

12

12 30

8

12

8

12

12 30

12 30

12 30

12 30

12 30

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

12 31

28 29 30

12 31

12 31

12 31

12 31

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCIe Gen3. Allow looser spacing for same direction on stripline per Anil

PEG Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

Section

4.2.1

Imp
80 80

Design

16

Design

15.75

Iso

Comments

Spacing Constraints

Design
50

Imp
50
50

15.75

Iso
15

15.75

8

Comments

DMI. Numbers based on Intel stack-up.

PCIe. Impedance inferred from Table 4-7.

PCI Express/DMI

CPU PCIe Compensation

CPU PCIe Clocks

PCIe (CPU)

Electrical Contraint Set

Spacing

Physical

Electrical Contraint Set

Physical

Spacing

PCIe (CPU)

x16 Graphicsx16 Graphics

Design

50

PCIe-specific Spacing Definitions

Table

4-7

4-5

Physical Net Type to Rule Map

PCIe-specific Physical Rules

PCIe and DMI Compensation Rules (mils)

I440

I441

I442
I443

I444

I445
I446

I447

I448

I449

I450

I451

I452

I453

I454

I455

I456

I457

I458

I459

I460

I461

I462

I463

I464
I465

I466

I467

I468

I469

I470

I471

I472

I473

I474

I475

I476

I477

I478

I479

I480

I481

I482

I483

I484

I485

I486

I487

I488

I489

I490

I491

I492

I493

I494

I495

I496

I497

I498
I499

I500

I501

I502

I503

I504

I505

I506

I507

I508

I509

I510

I511

I512

I513

I514

I515

I516

I517

I518

I519

I520

I521

I522
I523

I524
I525

I526

I527

I528
I529

I530

I531
I532

I533

I534
I535

I536

I537

I538

I539

I540

I541

I542

I543

I544

I545

I546

I547

I548

I549

I550

I551

I552

I553

I554

I555

I556

I557

I558

I559

I560

I561

I562

I563

I564

I565

I566

I567

I568
I569

I570

=4:1_SPACING

PEG_ISO

*

?

=7X_DIELECTRIC

*

PEG_ALT_DIR

?

=3.5X_DIELECTRIC

PEG_SAME_DIR

*

?

?

=5X_DIELECTRIC

TOP,BOTTOM

PEG_SAME_DIR

?

=4:1_SPACING

*

COMP_PCIE_ISO

PCIE_80D

*

PCIE3_PHY

PEG_SAME_DIR

PEG_R2DPEG_R2D

*

PEG_ALT_DIR

PEG_D2R

*

PEG_R2D

CLK_PCIE_ISO

?

*

=5:1_SPACING

* *

COMP_PCIE

COMP_PCIE_ISO

PEG_R2D PEG_ISO

* *

PEG_ISO

*

PEG_D2R

*

PEG_D2RPEG_D2R

PEG_SAME_DIR

*

CLK_PCIE_ISO

CLK_PCIE

**

PCIE_COMP

COMP_PCIE_PHY

*

PCIE_90D

CLK_PCIE_PHY

*

=80_OHM_DIFF

* =80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

PCIE_80D

PCIE_90D

=90_OHM_DIFF

=90_OHM_DIFF*

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF*

PCIE_85D

=85_OHM_DIFF

=STANDARD

=50_OHM_SE

* =STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE

PCIE_50S

=STANDARD=STANDARD

=STANDARD

0.105 MM0.305 MM

Y

PCIE_COMP

*

CPU PCIe Constraints

SYNC_DATE=12/12/2011

SYNC_MASTER=D7_DAVE

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_P<15>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_N<15>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<15>

PCIE3_PHY

PCIE_GEN3_D2R

PEG_D2R_P<6>

PCIE3_PHY

PEG_D2R

PEG_R2D

PEG_R2D_C_P<5>

PCIE3_PHY

PEG_R2D_C_N<5>

PCIE3_PHY

PEG_R2D

PEG_R2D

PEG_R2D_N<5>

PCIE3_PHY

PCIE_GEN3_R2D_RVSD

PEG_D2R_C_N<6>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_P<6>

PCIE3_PHY

PEG_D2R

PEG_R2D

PEG_R2D_C_P<15>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_N<15>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_N<14>

PCIE3_PHY

PEG_D2R_C_N<14>

PEG_D2R

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<13>

PCIE3_PHY

PEG_D2R_N<13>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<12>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_P<12>

PCIE3_PHY

PEG_D2R

PCIE3_PHY

PEG_D2R_C_P<15>

PCIE_GEN3_D2R

PEG_D2R_N<15>

PCIE3_PHY

PEG_D2R

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<15>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_P<13>

PCIE3_PHY

PCIE_GEN3_D2R_RVSD

PCIE3_PHY

PEG_D2R_N<0>

PEG_D2R

PEG_R2D

PEG_R2D_C_P<8>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<2>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_P<2>

PCIE3_PHY

PEG_R2D

PEG_R2D_N<2>

PCIE_GEN3_R2D

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<12>

PCIE3_PHY

PEG_D2R_C_N<1>

PCIE3_PHY

PEG_D2R

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<1>

PCIE3_PHY

PCIE_GEN3_D2R

PEG_D2R_N<4>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<4>

PCIE3_PHY

PEG_D2R

PEG_R2D_C_N<4>

PCIE3_PHY

PEG_R2D

PEG_D2R_C_N<4>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_R2D

PEG_R2D_N<4>

PCIE3_PHY

PEG_R2D

PEG_D2R_C_N<3>

PCIE3_PHY

PEG_D2R

PEG_R2D_C_N<3>

PCIE3_PHY

PEG_R2D

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_N<2>

PCIE3_PHY

PEG_R2D_C_P<4>

PCIE3_PHY

PEG_R2D

PEG_D2R_P<9>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R_RVSD

PEG_R2D_P<5>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D_RVSD

PEG_D2R_C_N<5>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_N<6>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<3>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_P<3>

PCIE3_PHY

PEG_D2R

PEG_R2D

PEG_R2D_C_P<1>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_N<10>

PCIE3_PHY

PCIE_GEN3_D2R_RVSD

PEG_D2R_P<8>

PCIE3_PHY

PEG_D2R

COMP_PCIE_PHY

COMP_PCIE

CPU_PEG_COMP

CLK_PCIE_PHY

PEG_CLK100M_N

CLK_PCIE

PEG_REF_CLK

PEG_R2D

PEG_R2D_C_P<12>

PCIE3_PHY

PCIE_GEN3_D2R

PEG_D2R_N<3>

PCIE3_PHY

PEG_D2R

PEG_D2R

PEG_D2R_C_P<2>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_N<1>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<2>

PCIE3_PHY

PEG_R2D_N<3>

PCIE_GEN3_R2D

PCIE3_PHY

PEG_R2D

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_P<3>

PCIE3_PHY

PEG_D2R_C_P<13>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<10>

PCIE3_PHY

PEG_D2R

PEG_R2D

PCIE_GEN3_R2D_RVSD

PEG_R2D_N<13>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D_RVSD

PEG_R2D_P<13>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_N<1>

PCIE3_PHY

CLK_PCIE_PHY

CLK_PCIE

PEG_CLK100M_P

PEG_REF_CLK

PEG_D2R_P<11>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R_RVSD

PCIE_GEN3_D2R

PEG_D2R_N<12>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_P<8>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_R2D

PEG_R2D_N<6>

PCIE3_PHY

PEG_R2D

PEG_D2R

PEG_D2R_C_P<1>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_N<10>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<1>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_N<2>

PCIE3_PHY

PEG_R2D_C_P<3>

PCIE3_PHY

PEG_R2D

PEG_D2R_C_P<4>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_R2D

PEG_R2D_P<4>

PCIE3_PHY

PEG_R2D

PEG_D2R_C_P<5>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R_RVSD

PEG_D2R_N<5>

PCIE3_PHY

PEG_D2R

PEG_D2R_P<5>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R_RVSD

PEG_D2R_C_P<7>

PCIE3_PHY

PEG_D2R

PEG_D2R_P<7>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R_RVSD

PEG_R2D_C_N<7>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_P<6>

PCIE3_PHY

PEG_R2D

PEG_D2R_C_N<7>

PCIE3_PHY

PEG_D2R

PEG_D2R_N<7>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R_RVSD

PEG_R2D_C_P<7>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_N<7>

PCIE3_PHY

PEG_R2D

PEG_R2D

PEG_R2D_P<7>

PCIE3_PHY

PCIE_GEN3_R2D

PCIE_GEN3_D2R_RVSD

PCIE3_PHY

PEG_D2R_P<0>

PEG_D2R

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_P<1>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D

PEG_R2D_P<10>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<11>

PCIE3_PHY

PEG_R2D

PEG_R2D_N<11>

PCIE_GEN3_R2D

PCIE3_PHY

PCIE_GEN3_R2D

PEG_R2D_N<12>

PCIE3_PHY

PEG_R2D

PEG_D2R_C_N<13>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_R2D

PEG_R2D

PCIE3_PHY

PEG_R2D_P<14>

PEG_D2R_C_N<8>

PCIE3_PHY

PEG_D2R

PEG_R2D_C_N<8>

PCIE3_PHY

PEG_R2D

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D_RVSD

PEG_R2D_N<8>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_R2D_RVSD

PEG_R2D_N<9>

PCIE_GEN3_R2D

PEG_R2D

PEG_R2D_N<10>

PCIE3_PHY

PEG_D2R_P<13>

PCIE3_PHY

PEG_D2R

PCIE_GEN3_D2R

PEG_R2D

PEG_R2D_C_P<6>

PCIE3_PHY

PEG_R2D_C_N<6>

PCIE3_PHY

PEG_R2D

PEG_D2R

PCIE_GEN3_D2R

PEG_D2R_P<14>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<14>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_P<14>

PCIE3_PHY

PEG_R2D

PEG_R2D_N<14>

PCIE3_PHY

PCIE_GEN3_R2D

PEG_R2D

PEG_R2D_C_N<10>

PCIE3_PHY

PEG_R2D

PCIE3_PHY

PEG_R2D_C_P<10>

PEG_D2R_C_P<11>

PEG_D2R

PCIE3_PHY

PEG_D2R_N<11>

PEG_D2R

PCIE3_PHY

PCIE_GEN3_D2R_RVSD

PEG_R2D

PEG_R2D_P<11>

PCIE3_PHY

PCIE_GEN3_R2D

PEG_D2R_C_N<12>

PCIE3_PHY

PEG_D2R

PEG_R2D

PCIE_GEN3_R2D_RVSD

PEG_R2D_P<8>

PCIE3_PHY

PEG_D2R_C_N<9>

PCIE3_PHY

PEG_D2R

PEG_R2D_C_N<9>

PEG_R2D

PCIE3_PHY

PEG_R2D

PEG_R2D_C_P<9>

PCIE3_PHY

PEG_D2R_C_P<10>

PCIE3_PHY

PEG_D2R

PCIE3_PHY

PEG_D2R_C_N<0>

PEG_D2R

PCIE3_PHY

PEG_D2R

PEG_D2R_C_P<0>

PEG_D2R_C_P<14>

PEG_D2R

PCIE3_PHY

PCIE_GEN3_R2D_RVSD

PEG_R2D

PEG_R2D_N<0>

PCIE3_PHY

PCIE_GEN3_R2D_RVSD

PEG_R2D

PEG_R2D_P<0>

PCIE3_PHY

PEG_R2D_C_P<0>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_N<0>

PCIE3_PHY

PEG_R2D

PCIE_GEN3_D2R_RVSD

PEG_D2R_N<8>

PCIE3_PHY

PEG_D2R

PEG_D2R

PEG_D2R_C_P<9>

PCIE3_PHY

PEG_D2R

PCIE3_PHY

PEG_D2R_N<9>

PCIE_GEN3_D2R_RVSD

PEG_D2R

PEG_D2R_C_P<12>

PCIE3_PHY

PEG_R2D

PEG_R2D_C_P<11>

PCIE3_PHY

PEG_D2R

PEG_D2R_C_N<11>

PCIE3_PHY

PEG_R2D

PEG_R2D_P<9>

PCIE3_PHY

PCIE_GEN3_R2D_RVSD

PCIE_GEN3_R2D

PEG_R2D_P<2>

PCIE3_PHY

PEG_R2D

051-9509

4.2.0

102 OF 113

89 OF 100

71

71

9

71

9

71

9

71

9

71

71

71

71

9

71

71

9

71

71

9

71

9

71

9

71

71

71

9

71

9

71

9

71

9

71

9

71

9

71

9

71

71

9

71

71

9

71

9

71

9

71

9

71

71

71

71

9

71

9

71

9

71

9

71

71

71

9

71

9

71

71

9

71

71

9

71

10

18 71

9

71

9

71

71

71

9

71

71

71

71

9

71

71

71

9

71

18 71

9

71

9

71

71

71

71

9

71

9

71

71

9

71

71

71

71

9

71

9

71

71

9

71

9

71

71

71

9

71

9

71

71

71

9

71

71

71

9

71

71

71

71

71

71

9

71

71

71

71

9

71

9

71

9

71

9

71

9

71

9

71

71

9

71

9

71

71

9

71

71

71

71

71

9

71

9

71

71

71

71

71

71

71

9

71

9

71

9

71

71

9

71

71

9

71

71

71

71

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DMI Compensation

PCIe (PCH)

Electrical Contraint Set

TBT x4 PCIE Spacing Constraints

DMI x4 PCIE Spacing Constraints

DMI-specific Spacing Definitions

SSD x2 PCIE Spacing Constraints

PCH x1 PCIE Constraints

DMI

Electrical Contraint Set

DMI

x1 Caesar IV

x2 SSD

Physical

x1 AirPort

Spacing

Physical

Spacing

x4 Thunderbolt

PCIe-specific Spacing Definitions

Physical Net Type to Rule Map

I132

I133

I134
I135

I136

I137
I138

I139

I140

I141

I142
I143

I144

I145

I146

I147

I148

I149

I150

I151

I152

I153

I154

I155

I156
I157

I158

I159

I165

I166

I167
I168

I169

I170

I171

I174

I175

I176
I177

I178

I179
I180

I181

I182

I183

I184

I185

I186
I187

I188

I189
I190

I191

I192
I193

PCIE_ISO

PCIE_TBT_D2R

* *

PCIE_ISO

PCIE_TBT_R2D

* *

=4X_DIELECTRICDMI_ISO

?

*

DMI_SAME_DIR

DMI_N2SDMI_N2S

*

DMI_SAME_DIR

DMI_S2NDMI_S2N

*

DMI_ALT_DIR

DMI_S2NDMI_N2S

*

DMI_ISODMI_N2S

**

DMI_ISODMI_S2N

**

=5X_DIELECTRIC

DMI_ALT_DIR

?

*

=4X_DIELECTRIC

DMI_SAME_DIR

?

*

DMI_SAME_DIR

TOP,BOTTOM

=5X_DIELECTRIC

?

=5X_DIELECTRIC

TOP,BOTTOM

?

PCIE_SAME_DIR
PCIE_SAME_DIR

=3.5X_DIELECTRIC

*

?

=7X_DIELECTRIC

*

?

PCIE_ALT_DIR

PCIE_SAME_DIR

PCIE_TBT_R2DPCIE_TBT_R2D

*

PCIE_SAME_DIR

PCIE_TBT_D2RPCIE_TBT_D2R

*

PCIE_ALT_DIRPCIE_TBT_R2DPCIE_TBT_D2R

*

PCIE_SAME_DIR

*

PCIE_SSD_R2DPCIE_SSD_R2D

PCIE_SAME_DIR

*

PCIE_SSD_D2RPCIE_SSD_D2R

PCIE_ALT_DIR

*

PCIE_SSD_R2DPCIE_SSD_D2R

PCIE_ISO

**

PCIE_SSD_D2R

PCIE_ISO

**

PCIE_SSD_R2D

*

PCIE_ISO

PCIE

*

=4:1_SPACING

*

?

PCIE_ISO

SYNC_MASTER=D7_DAVE

SYNC_DATE=12/12/2011

PCH PCIe/DMI Constaints

PCIE_85DPCIE_PHY

*

50_OHM_SE

COMP_DMI_PHY

*

PCIE

PCIE_PHY

PCIE_ENET_D2R_N

PCIE_GEN2_D2R

PCIE_PHY

PCIE

PCIE_GEN2_D2R

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_N

PCIE

PCIE_PHY

PCIE_TBT_D2R_N<3..0>

PCIE_TBT_D2R

PCIE_PHY

PCIE_GEN2_D2R

PCIE_SSD_D2R_C_N<0>

PCIE_SSD_D2R

PCIE_PHY

PCIE_PHY

PCIE

PCIE_AP_R2D_C_P

PCIE

PCIE_AP_R2D_C_N

PCIE_PHY

PCIE_PHY

PCIE

PCIE_AP_R2D_N

PCIE_GEN2_R2D_CONN_AP

DMI_N2SDMI_N2S

DMI_N2S_N<3..0>

PCIE_PHY

DMI_S2N

DMI_S2N_P<3..0>

PCIE_PHY

DMI_S2N
DMI_S2N DMI_S2N

DMI_S2N_N<3..0>

PCIE_PHY

PCIE_PHY

PCIE

PCIE_AP_R2D_P

PCIE_GEN2_R2D_CONN_AP

CLK_PCIE_PHY

PCIE_REF_CLK_CONN

PCIE_CLK100M_SSD_N

CLK_PCIE

PCIE_AP_D2R_P

PCIE

PCIE_PHY

PCIE_GEN2_D2R_CONN_AP

PCIE_PHY

PCIE

PCIE_AP_D2R_C_P

PCIE

PCIE_PHY

PCIE_AP_D2R_C_N

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK_CONN

PCIE_CLK100M_AP_P

PCIE_SSD_R2D

PCIE_SSD_R2D_P<0>

PCIE_PHY

PCIE_GEN2_R2D_MUX_SSD

PCIE_PHY

PCIE_AP_D2R_N

PCIE

PCIE_GEN2_D2R_CONN_AP

PCIE_CLK100M_ENET_N

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_CLK100M_ENET_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_PHY

PCIE

PCIE_ENET_D2R_C_N

PCIE

PCIE_PHY

PCIE_ENET_D2R_C_P

PCIE_PHY

PCIE_ENET_R2D_C_P

PCIE

PCIE_PHY

PCIE

PCIE_ENET_R2D_P

PCIE_GEN2_R2D

PCIE_PHY

PCIE_ENET_R2D_N

PCIE

PCIE_GEN2_R2D

CLK_PCIE_PHY

CLK_PCIE

PCIE_CLK100M_AP_N

PCIE_REF_CLK_CONN

CLK_PCIE_PHY

PCIE_CLK100M_SSD_P

CLK_PCIE

PCIE_REF_CLK_CONN

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_R2D

PCIE_PHY

PCIE_REF_CLK

CLK_PCIE

DMI_CLK100M_CPU_P

CLK_PCIE_PHY

DMI_N2S

DMI_N2S_P<3..0>

DMI_N2S

PCIE_PHY

PCIE_SSD_D2R_C_P<0>

PCIE_SSD_D2R

PCIE_PHY

PCIE_SSD_D2R

PCIE_PHY

PCIE_GEN2_D2R_MUX_SSD

PCIE_SSD_D2R_N<0>

PCIE_GEN2_D2R_MUX_SSD

PCIE_SSD_D2R

PCIE_PHY

PCIE_SSD_D2R_P<0>

PCIE_TBT_R2D

PCIE_TBT_R2D_C_N<3..0>

PCIE_PHY

PCIE_TBT_R2D_C_P<3..0>

PCIE_TBT_R2D

PCIE_PHY

PCIE_TBT_R2D

PCIE_GEN2_R2D

PCIE_PHY

PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D

PCIE_GEN2_R2D

PCIE_PHY

PCIE_REF_CLK

CLK_PCIE

DMI_CLK100M_CPU_N

CLK_PCIE_PHY

PCIE_SSD_R2D_C_P<1>

PCIE_SSD_R2D

PCIE_PHY

PCIE_PHY

PCIE_GEN2_R2D_CONN_SSD

PCIE_SSD_R2D

PCIE_SSD_R2D_N<1>

PCIE_SSD_D2R_C_P<1>

PCIE_PHY

PCIE_SSD_D2R

PCIE_SSD_D2R

PCIE_PHY

PCIE_SSD_D2R_N<1>

PCIE_GEN2_D2R_CONN_SSD

PCIE_SSD_R2D_P<1>

PCIE_PHY

PCIE_SSD_R2D

PCIE_GEN2_R2D_CONN_SSD

PCIE_SSD_D2R_C_N<1>

PCIE_SSD_D2R

PCIE_PHY

PCIE_SSD_R2D

PCIE_GEN2_R2D_MUX_SSD

PCIE_PHY

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D

PCIE_PHY

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_P<1>

PCIE_PHY

PCIE_SSD_D2R

PCIE_GEN2_D2R_CONN_SSD

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_R2D

PCIE_PHY

PCIE_CLK100M_TBT_N

CLK_PCIE

PCIE_REF_CLK CLK_PCIE_PHY

COMP_DMI_PHY

PCH_DMI_COMP

COMP_PCIE

PCIE_TBT_D2R_C_P<3..0>

PCIE_TBT_D2R

PCIE_PHY

PCIE_TBT_D2R_C_N<3..0>

PCIE_TBT_D2R

PCIE_PHY

PCIE_CLK100M_TBT_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_GEN2_D2R

PCIE_TBT_D2R

PCIE_PHY

PCIE_TBT_D2R_P<3..0>

051-9509

4.2.0

103 OF 113

90 OF 100

18 37

18 37

18 37

18 34

41

18 33

18 33

33

10 19

10 19

10 19

33

18 41

18 33

18 33

41

18 33

18 37

18 37

37

37

18 37

37

37

18 33

18 41

18 41

11 18

10 19

41

18 41

18 41

18 34

18 34

34

34

11 18

18 41

41

41

18 41

41

41

41

18 41

18 41

18 41

18 34

19

34

34

18 34

18 34

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FDI Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

PCH SATA Port 1 (SSD)

XDP-specific Spacing Definitions

PCH XDP

PCH SATA Port 0 (HDD)

SSD PCIe/SATA Mux Output

PCH SATA Compensation

All signals default are 50 Ohm SE.

FDI

FDI Compensation

Electrical Contraint Set

Comments
SATA Gen2, SATA Gen3

SATA Gen2, SATA Gen3

SATA Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

Spacing

FDI

SATA-specific Spacing Definitions

50

Constraints

1.5

Section

45-65

55

Design

Imp

-

Iso

Desktop Debug Design Guide (Intel Doc# 430883)

Design

15.75

Comments
Isolation is for JTAG clocks.

Physical Net Type to Rule Map

Physical Net Type to Rule Map

Electrical Contraint Set

CPU XDP

Physical

Comments
FDI main length

Design

SATA Compensation Rules (mils)

XDP

XDP-specific Physical Rules

FDI-specific Physical Rules

FDI

Constraints

Table

Table

10

Design

Trace

11.81

8585

Design

12

-

FDI Compensation Rules (mils)

Iso

Iso

Comments

15.75

11.81

Design

Comments

Physical Net Type to Rule Map

15-3

50 15

15.75

Table

Section

15.2.1

9590

Design

Imp

Imp

Design

Iso
20

Iso

23.62

Design

Design

SATA-specific Physical Rules

Spacing

SATA

Spacing

Physical

Electrical Contraint Set

XDP

SATA

Physical

6-4

Imp

Using PCIe guidelines

FDI-specific Spacing Definitions

6-1/6-2

Constraints

I100
I101

I102

I103

I104

I105

I106

I109

I110

I111

I112

I113

I114

I115

I116
I117

I118

I37

I38

I39

I40
I41

I42

I43

I44

I45

I46
I47

I48

I49

I50
I51

I52

I88
I89

I90

I91

I92

I93

I94

I95

I96

I97

I98

I99

=STANDARD

=50_OHM_SE =50_OHM_SE

*

=50_OHM_SE=50_OHM_SE

=STANDARD

FDI_50S

=55_OHM_SE

=STANDARD=STANDARD*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

XDP_55S

*

COMP_SATA_PHY

SATA_50S

**

XDP

XDP_ISO

=4:1_SPACING

?

*

CLK_JTAG_ISO

XDP_ISO

?

*

=2:1_SPACING

*

XDP_55SXDP_PHY

*

FDI_50S

FDI_SE_PHY

*

SATA_90DSATA_PHY

CLK_JTAG_ISO

CLK_JTAG

**

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF*=90_OHM_DIFF

SATA_90D

=90_OHM_DIFF

=90_OHM_DIFF

=STANDARD

=50_OHM_SE

*

=50_OHM_SE =50_OHM_SE

=STANDARD

SATA_50S

=50_OHM_SE

=STANDARD =STANDARD* Y

3 MM

0.25 MM

COMP_FDI

0.25 MM

*

COMP_FDI

COMP_FDI_PHY

COMP_FDI_ISO

*

?

=4:1_SPACING

*

FDI

FDI_ISO

*
**

COMP_FDI

COMP_FDI_ISO

*

FDI_85D

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

COMP_SATA

*

COMP_SATA_ISO

*

?

*

SATA_ISO

=6:1_SPACING

FDI_85D

*

FDI_DIFF_PHY

=3:1_SPACING

FDI_ISO

*

?

SATA_ISO

SATA

**

COMP_SATA_ISO

?

*

=4:1_SPACING

SYNC_MASTER=D7_DAVE

SATA/FDI/XDP Constraints

SYNC_DATE=12/12/2011

XDP_PHY

XDP

XDP_PCH_TDO

XDP_PHY

XDP

XDP_PCH_TDI

XDP_PHY

XDP

XDP_PCH_TMS

XDP_PHY

CLK_JTAG

XDP_PCH_TCK

XDP_PHY

XDP

XDP_CPU_TDO

XDP_PHY

XDP

XDP_CPU_TDI

XDP_PHY

XDP

XDP_CPU_TMS

XDP_PHY

CLK_JTAG

XDP_CPU_TCK

CLK_PCIE_PHY

XDP_CPU_CLK100M_N

CLK_PCIE

ITPXDP_CLK100M_N

CLK_PCIE

CLK_PCIE_PHY
CLK_PCIE_PHY

XDP_CPU_CLK100M_P

CLK_PCIE

CLK_PCIE_PHY

CLK_PCIE

ITPXDP_CLK100M_P

ITP_CLK_CONN

ITPCPU_CLK100M_P

CLK_PCIE

CLK_PCIE_PHY

ITP_CLK_CONN CLK_PCIE_PHY

CLK_PCIE

ITPCPU_CLK100M_N

CPU_CFG<17..0>

XDP

XDP_PHY

SATA

SATA_HDD_R2D_N

SATA_PHYSATA_R2D

SATA_D2R

SATA

SATA_HDD_D2R_N

SATA_PHY

SATA_SSD_R2D_N

SATA

SATA_PHY

SATA_R2D_MUX_SSD

SATA

SATA_HDD_R2D_P

SATA_PHYSATA_R2D

SATA_HDD_R2D_C_P

SATA

SATA_PHY

SATA_SSD_R2D_C_P

SATA

SATA_PHY

SATA_SSD_D2R_P

SATA_PHY

SATA

SATA_D2R_MUX_SSD

SATA_SSD_D2R_C_N

SATA

SATA_PHY

PCIE_SATA_SSD_D2R_P

SATA

SATA_PHY

PCIE_SATA_D2R_MUX_CONN

COMP_SATA_PHY

COMP_SATA

PCH_SATAICOMP

PCIE_SATA_SSD_R2D_N

SATA

SATA_PHY

PCIE_SATA_R2D_MUX_CONN

SATA

PCIE_SATA_SSD_R2D_P

SATA_PHY

PCIE_SATA_R2D_MUX_CONN

SATA

SATA_PHY

PCIE_SATA_SSD_D2R_N

PCIE_SATA_D2R_MUX_CONN

CPU_FDI_INT

FDI_SE_PHY

FDI

CPU_FDI_COMPIO

COMP_FDI

COMP_FDI_PHY

XDP_BPM_L<7..0>

XDP

XDP_PHY

FDI_SE_PHY

FDI

CPU_FDI_LSYNC<1..0>

FDI_SE_PHY

FDI

CPU_FDI_FSYNC<1..0>

FDI_DIFF_PHY

FDIFDI_TX

CPU_FDI_TX_P<7..0>

SATA_HDD_D2R_C_P

SATA

SATA_PHY

SATA_D2R

SATA_HDD_D2R_P

SATA

SATA_PHY

SATA_HDD_R2D_C_N

SATA

SATA_PHY

SATA_SSD_R2D_P

SATA

SATA_PHY

SATA_R2D_MUX_SSD

COMP_SATA

COMP_SATA_PHY

PCH_SATA3RBIAS

COMP_SATA

COMP_SATA_PHY

PCH_SATA3COMP

SATA_SSD_D2R_C_P

SATA

SATA_PHY

SATA_PHY

SATA_SSD_D2R_N

SATA

SATA_D2R_MUX_SSD

SATA_SSD_R2D_C_N

SATA

SATA_PHY

SATA_HDD_D2R_C_N

SATA

SATA_PHY

FDI_DIFF_PHY

FDI

CPU_FDI_TX_N<7..0>

FDI_TX

051-9509

4.2.0

104 OF 113

91 OF 100

18 25

18 25

18 25

18 25

11 25

11 25

11 25

11 25

25

15 18 25

25

15 18 25

11 15

11 15

8

10 15 25 41

18 41

41

41

18 41

18 41

18 41

41

41

18

41

41

41

8

10

10

11 25

8

10

8

10

8

10

41

18 41

18 41

41

18

18

41

18 41

18 41

41

8

10

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Spacing

Electrical Contraint Set

PCI-specific Spacing Definitions

PCI-specific Physical Rules

PCH RTC 32K

LPC-specific Spacing Definitions

Electrical Contraint Set

LPC

LPC

Crystal-specific Spacing Definitions

PCI

HDA

PCI Clock

PCH-specific Spacing Definitions

SMC 32K

Spacing

SPDIF

Physical

PCH Clocks

PCH-specific Physical Rules

Electrical Contraint Set

LPC Clocks

25M Reference Clocks

Physical

Physical

Spacing

LPC

Physical

Spacing

PCI

Electrical Contraint Set

PCH

HDA

SpacingSpacing

Physical

PCH Ref Clock Comp

PCH Reference Clock

25M Reference Crystal

Electrical Contraint Set

Crystal-specific Physical Rules

SPI ROM

Physical

HDA-specific Physical Rules

HDA

HDA-specific Spacing Definitions

LPC-specific Physical Rules

Electrical Contraint Set

SPI Bootrom

25 MHz Reference Clocks

Crystal

SPI-specific Spacing Definitions

SPI-specific Physical Rules

SPI

I333

I334

I335

I336

I337

I338

I339
I340

I341

I342

I346

I347
I348

I349

I350

I352

I353

I361

I362

I363

I364

I365

I366

I367

I368

I369

I370

I371

I379

I380

I381

I384

I385

I386

I387

I388

I391
I392

I393

I394

I395
I396

I397

I399
I400

I401

I403

I404

I405

I406

I407

I408

I409

I410
I411

I412

I413

SYNC_MASTER=D7_DAVE

PCH and BR Constraints

SYNC_DATE=12/12/2011

=2:1_SPACING

?

*

CLK_PCI

=2:1_SPACING

*

?

COMP_PCH

=1.5:1_SPACING

*

?

LPC

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

*

=55_OHM_SE

CLK_PCI_55S

=55_OHM_SE

=55_OHM_SE=55_OHM_SE

CLK_LPC_55S

=55_OHM_SE =55_OHM_SE

* =STANDARD =STANDARD

*

=4:1_SPACING

?

CLK_PCH

=2:1_SPACING

*

?

CLK_LPC

=STANDARD*

=55_OHM_SE

PCH_55S

=55_OHM_SE=55_OHM_SE

=STANDARD

=55_OHM_SE

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD*

CLK_PCH_55S

=55_OHM_SE

?

*

XTAL

=4X_DIELECTRIC

=2x_DIELECTRIC

?

*

HDA

=STANDARD

HDA_55S

=55_OHM_SE=55_OHM_SE =55_OHM_SE

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

LPC_55S

=55_OHM_SE

=STANDARD*

=55_OHM_SE

=STANDARD

=55_OHM_SE

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

*

CLK_XTAL

=100_OHM_DIFF

=2:1_SPACING

SPI

*

?

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

SPI_55S

=STANDARD* =STANDARD

SPI_50S

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

SYSCLK_CLK25M_ENET

CLK_PCH

CLK_PCH_55S

CLK_PCH

CLK_PCH_55S

SYSCLK_CLK25M_TBT_R

CLK_PCH

CLK_PCH_55S

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_X2_R

XTAL

CLK_XTAL

SPIROM_USE_MLB

SPI

SPI_50S

SPI

SPI_MLB_MISO

SPI_50S

SPI

SPI_SMC_MISO

SPI_50S

SPI

SPI_ALT_MOSI

SPI_50S

SPI_MOSI

SPI

SPI_50S

SPI

SPI_MLB_CS_L

SPI_50S

HDA

HDA_55S

HDA_SDIN0
AUD_SDI_R

HDA

HDA_55S

CLK_LPC_55S

LPC_CLK33M_SMC_R

CLK_LPC

CLK_LPC_55S

CLK_LPC

LPC_CLK33M_LPCPLUS_R

LPC_55S

LPC

LPC_FRAME_L

LPC_CLK33M_LPCPLUS

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_SMC

CLK_LPC_55S

CLK_LPC

LPC_55S

LPC

LFRAME_L

HDA

HDA_55S

HDA_SDOUT_R

HDA

HDA_BIT_CLK

HDA_55S

HDA

HDA_55S

HDA_SYNC

SYSCLK_CLK25M_X1

CLK_XTAL

XTAL

HDA_BIT_CLK_R

HDA

HDA_55S

SYSCLK_CLK25M_X2

XTAL

CLK_XTAL

SYSCLK_CLK25M_ENET_R

CLK_PCH

CLK_PCH_55S

CLK_PCI_55S

CLK_PCI

PCH_CLK33M_PCIOUT

CLK_PCI_55S

CLK_PCI

PCH_CLK33M_PCIIN

LPC_AD<3..0>

LPC_55S

LPC
LPC

LPC_55S

LPC_R_AD<3..0>

PCH_CLK32K_RTCX2_R

XTAL

CLK_XTAL

CLK_PCH

CLK_PCH_55S

SYSCLK_CLK25M_SB

PCH_CLK32K_RTCX1

XTAL

CLK_XTAL

HDA_55S

HDA

HDA_SYNC_R

SPI_ALT_CLK

SPI

SPI_50S

SPI_CLK

SPI

SPI_50S

CLK_PCH_55S

CLK_PCH

PM_CLK32K_SUSCLK_R

SPI

SPI_SMC_CS_L

SPI_50S

SPI

SPI_CS0_R_L

SPI_50S

SPI_SMC_CLK

SPI

SPI_50S

SPI_CLK_R

SPI

SPI_50S

SPI_ALT_MISO

SPI

SPI_50S

SPI_MISO

SPI

SPI_50S

SPI

SPI_MLB_MOSI

SPI_50S

SPI_50S

SPI_SMC_MOSI

SPI

SPI

SPI_MOSI_R

SPI_50S

SPI_50S

SPI_ALT_CS_L

SPI

PCH_CLK25M_XTALIN

CLK_PCH_55S

CLK_PCH

PCH_XCLK_RCOMP

COMP_PCH

PCH_55S

SMC_CLK32K

CLK_PCH

CLK_PCH_55S

PCH_CLK32K_RTCX2

CLK_XTAL

XTAL

SPI_50S

SPI

SPI_CS0_L

SPI

SPI_MLB_CLK

SPI_50S

AUD_SPDIF_CHIP

HDA
HDA

AUD_SPDIF_OUT

HDA_55S

HDA

HDA_SDOUT

HDA_RST_R_L

HDA

HDA_55S

HDA_RST_L

HDA

HDA_55S

051-9509

4.2.0

105 OF 113

92 OF 100

26 37

34

26 34

26

21 46

45 46

44 45

46

46

45 46

18 52

52

20 26

20 26

18 44 46

26 46

26 44

18

15 18

18 52

15 18 52

26

18

26

26

20 26

18 26

18 44 46

18

26

26

18 26

18

46

46

19 45

44 45

18 46

44 45

18 46

46

18 46

45 46

44 45

18 46

46

18 26

18

44 45

18 26

46

45 46

52

52 56

18 52

18

18 52

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Camera Processor-Camera Sensor I/F

Physical

Electrical Contraint Set

Spacing

CIV SPI

SD

Ethernet

Electrical Contraint Set

Et tu Brute?

Physical

Spacing

External Port A (J4600)

Camera (J3510)

CIV-specific Spacing Definitions
Ethernet Ethernet

Constraints

2 kV isolation

Physical Net Type to Rule Map

USB-specific Spacing Definitions

USB 3.0 and USB 2.0 Trixies Muxing

Physical Net Type to Rule Map

Camera Processor’s SMIA Interface Spacing Definitions

CIV-specific Physical Rules

Caesar IV (Ethernet/SD)

USB 2.0 Hub Crystal

USB 2.0 Hub Compensation

USB 2.0 Hub

Spacing

USB

Comments

USB 3.0

USB 2.0

21.65

11.81

Design

20

Iso
12

Design
90

Imp
90

85

13.3.1

85

12.2.1

Physical

External Port B (J4610)

External Port D (J4710)

Section

Physical

Spacing

Electrical Contraint Set

RMH Love

PCH USB Compensation

Constraints

External Port C (J4700)

SD

Camera Processor’s SMIA Interface Physical Rules

Camera Processor-to-Camera Sensor I/F (SMIA/MIPI)

SD

Electrical Contraint Set

USB Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

USB-specific Physical Rules

I320

I321

I324

I326

I376
I378

I384

I391
I392

I393

I394

I401

I402

I409

I410
I413

I414

I415
I416

I417

I418

I419
I420

I421
I422

I423
I424

I425

I426

I427

I428

I429
I430

I431

I432

I433

I434

I435

I436

I437

I438

I439

I440

I441
I442

I443

I444

I445

I446

I450

I452

I453

I454

I455

I456

I457
I458

I459

I460

I461

I462

I463

I464
I465

I466

I467

I468

I469

I470

I471

I472

I473

I474

I475

I476

I477

I478

I479

I480

I481

I482

I483

I484

I485

I486

I487

I488

I489

I490

I491

I492

I493

I494

I495

I496

I497

I498

I499

I500

I501

I502

I503

I504

I505

I506

I507

I508

I509

I510

I511

I512

I513

I514

I515

I516

I517

I518

I519

I520

I521

I522

I523

I524

I525

I526

I527

SYNC_MASTER=D7_DAVE

USB/Ethernet/SD Constraints

SYNC_DATE=12/12/2011

ENET_DIFF

**

ENET_DIFF_ISO

?

ENET_TRANS_ISO

*

1.27 MM

ENET_DIFF_ISO

*

?

=6:1_SPACING

*

ENET_DIFF2DIFF

?

=3:1_SPACING

?

COMP_ENET_ISO

*

=4:1_SPACING

ENET_DIFF2DIFF

ENET_TRANSENET_TRANS

*

COMP_ENET_ISO

**

COMP_ENET

ENET_TRANS_ISO

*

ENET_TRANS

*

ENET_DIFF2DIFF

ENET_DIFF

*

ENET_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF*

=90_OHM_DIFF

USB_90D

=90_OHM_DIFF

=90_OHM_DIFF

*

USB_85D

USB3_PHY

ENET_50S

=50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE =50_OHM_SE=50_OHM_SE

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE

*

SD_50S

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF

ENET_100D

*

ENET_100D

ENET_DIFF_PHY

*

SD_PHY SD_50S

SMIA_100D

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

SMIA_100D

*

SMIA_DIFF_PHY

*

SMIA_DIFF_ISO

?

=6:1_SPACING

SMIA_DIFF2DIFF

*

?

=3:1_SPACING

SMIA_DIFF_ISO

*

SMIA_DIFF

*

*

CIV_SPI SPI_55S

**

USB3

USB3_ISO

USB2

**

USB2_ISO

USB2_ISO

?

*

=3:1_SPACING

TOP,BOTTOM

USB3_ISO

?

=5.5:1_SPACING

ENET_50S

*

ENET_COMP_PHY

USB3_ISO

?

=5.5:1_SPACING

*

USB2_ISO

TOP,BOTTOM?=3:1_SPACING

*

USB2_PHY

USB_90D

=85_OHM_DIFF

=85_OHM_DIFF*

=85_OHM_DIFF=85_OHM_DIFF

USB_85D

=85_OHM_DIFF

=85_OHM_DIFF

SD_ISO

* *SD

SMIA_DIFFSMIA_DIFF

SMIA_DIFF2DIFF

*

SD_ISO

?

*

=3:1_SPACING

USB3

USB3_EXTA_RX_F_P

USB3_PHY

USB3_EXTA_RX_P

USB3

USB3_PHY

USB3_RX_CONN

USB3_PHY

USB3

USB3_EXTC_TX_F_P

USB2_PHY

USB_BT_P

USB2

USB2_HUB_CONN

XTAL

CLK_XTAL

USB_HUB_XTAL2

USB2

USB2_PHY

USB_HUB_2_N

USB2_PHY

USB_HUB_2_P

USB2

USB2_PHY

USB2_HUB_CONN

USB2

USB_BT_MUX_N

USB3

USB3_EXTA_RX_F_N

USB3_PHY

USB_SMC_P

USB2

USB2_PHY

USB2_HUB_RES

USB3_TX_CONN

USB3_PHY

USB3

USB3_EXTA_TX_N

USB3_EXTA_RX_N

USB3

USB3_PHY

USB3_RX_CONN

USB3_PHY

USB3_TX_CONN

USB3_EXTC_TX_N

USB3

USB2

USB2_PHY

USB_PCH_7_N

USB2_HUB

USB3_EXTA_TX_C_P

USB3_PHY

USB3

USB3

USB3_EXTA_TX_F_N

USB3_PHY

USB3_PHY

USB3_EXTA_TX_P

USB3

USB3_TX_CONN

USB2

USB2_MUXED_MOJO_CONN

USB2_PHY

USB_PCH_0_P

USB2_PHY

USB2

USB_PCH_3_P

USB2_MUXED_CONN

USB2_PHY

USB2

USB_PCH_7_P

USB2_HUB

USB2_PHY

USB_BT_N

USB2_HUB_CONN

USB2

USB2_PHY

USB2

USB2_HUB_CONN

USB_BT_MUX_P

USB2_PHY

USB_SMC_N

USB2

USB2_HUB_RES

USB_HUB_RBIAS

COMP_PCH

PCH_55S

USB_HUB_XTAL1

XTAL

CLK_XTAL

USB2_PHY

USB2

USB2_EXTC_N

USB2

USB2_PHY

USB2_CONN

USB_PCH_2_P

USB3_EXTC_TX_F_N

USB3_PHY

USB3

USB2_PHY

USB2

USB2_CONN

USB_PCH_2_N

USB3_PHY

USB3

USB3_EXTB_RX_F_N

USB3

USB3_PHY

USB3_EXTC_TX_C_N

USB2_EXTC_P

USB2

USB2_PHY

USB3_EXTD_RX_P

USB3_PHY

USB3

USB3_RX_CONN

USB3

USB3_PHY

USB3_EXTA_TX_C_N

USB2_PHY

USB2

USB2_MUXED_MOJO_CONN

USB_PCH_0_N

USB2_PHY

USB2

USB2_EXTA_N

PCH_55S

COMP_PCH

PCH_USB_RBIAS

USB2_PHY

USB2

USB2_EXTD_MUXED_N

USB2_PHY

USB2

USB_PCH_10_P

USB2_PHY

USB2

USB2_EXTA_MUXED_P

USB2_PHY

USB2

USB2_EXTA_MUXED_N

USB2

USB2_PHY

USB2_EXTA_P

USB2

USB2_MUXED_CONN

USB2_PHY

USB_PCH_1_P

USB2

USB2_PHY

USB_PCH_9_P

USB2

USB2_PHY

USB_PCH_9_N

USB2

USB2_PHY

USB2_EXTB_MUXED_P

USB3_PHY

USB3

USB3_EXTB_TX_C_N

USB3_RX_CONN

USB3

USB3_PHY

USB3_EXTB_RX_N

USB3_PHY

USB3_EXTB_TX_F_N

USB3

USB3_PHY

USB3_TX_CONN

USB3_EXTC_TX_P

USB3

USB3_EXTB_TX_N

USB3_TX_CONN

USB3

USB3_PHY

USB3_TX_CONN

USB3

USB3_PHY

USB3_EXTB_TX_P

USB3_RX_CONN

USB3_PHY

USB3

USB3_EXTB_RX_P

USB3_PHY

USB3

USB3_EXTB_RX_F_P

USB2_PHY

USB2

USB2_EXTB_MUXED_N

USB2_PHY

USB2

USB2_EXTB_P

USB2_PHY

USB2_EXTB_N

USB2

USB3_RX_CONN

USB3_PHY

USB3_EXTC_RX_P

USB3

USB3_PHY

USB3_RX_CONN

USB3

USB3_EXTC_RX_N

USB3_EXTC_RX_F_N

USB3

USB3_PHY

USB3

USB3_PHY

USB3_EXTB_TX_F_P

USB2_EXTD_P

USB2_PHY

USB2

USB2_EXTD_MUXED_P

USB2_PHY

USB2

USB_PCH_10_N

USB2_PHY

USB2

USB3_EXTC_TX_C_P

USB3

USB3_PHY

USB3_PHY

USB3

USB3_EXTC_RX_F_P

USB3_PHY

USB3

USB3_EXTB_TX_C_P

USB2

USB2_MUXED_CONN

USB2_PHY

USB_PCH_1_N

USB3_EXTA_TX_F_P

USB3

USB3_PHY

ENET_DIFF

ENETCONN_MDI_P<3..0>

ENET_DIFF_PHY

ENET_MDI

ENET_DIFF_PHY

ENET_DIFF

ENETCONN_MDI_N<3..0>

ENET_MDI

ENETCONN_MDI_T_P<3..0>

ENET_TRANS

ENET_DIFF_PHY

ENETCONN_MDI_T_N<3..0>

ENET_TRANS

ENET_DIFF_PHY

ENET_TRANS

ENETCONN_MCT0
ENETCONN_MCT1

ENET_TRANS

ENETCONN_MCT2

ENET_TRANS
ENET_TRANS

ENETCONN_MCT3

ENET_TRANS

ENETCONN_MCT_BS

ENET_RDAC

COMP_ENET

ENET_COMP_PHY

SD_PHY

SDCONN_DATA<7..0>

SD

SD_PHY

SD

ENET_CR_DATA<7..0>

SD_DATA

SD_PHY

SDCONN_DATA_R_<7..0>

SD

SD_CMD SD_PHY

SD

ENET_SD_CMD

SD

SDCONN_CMD

SD_PHY

SD

SD_PHY

SDCONN_CMD_R

SD

ENET_SD_CLK

SD_PHYSD_CLK

SDCONN_CLK_R

SD

SD_PHY

SD

SDCONN_CLK

SD_PHY

SD

ENET_SD_DETECT_L

SD_PHY

SD

ENET_MEDIA_SENSE

SD_PHY

SD

SD_PHY

SDCONN_WP

USB3_EXTD_RX_N

USB3

USB3_RX_CONN

USB3_PHY

SPI_50S

SPI

CAM_SF_CLK_R

SPI_50S

SPI

CAM_SF_DIN_R
CAM_SF_CS_L

SPI_50S

SPI

SMIA_DIFF

SMIA_CLK_F_N

SMIA_DP

SMIA_DIFF_PHY

USB3_EXTD_RX_F_N

USB3

USB3_PHY

USB2_MUXED_CONN

USB2

USB_PCH_3_N

USB2_PHY

SPI_50S

SPI

CAM_SF_DIN

CAM_SF_CLK

SPI_50S

SPI

CIV_SPI

SPI

ENET_CS_L

CIV_SPI

SPI

ENET_MOSI

CIV_SPI

SPI

ENET_MISO

CIV_SPI

SPI

ENET_SCLK

SMIA_DIFF_PHY

SMIA_DP

SMIA_DATA_N

SMIA_DIFF

SMIA_DIFF_PHY

SMIA_DP

SMIA_DIFF

SMIA_DATA_P

SMIA_DATA_F_P

SMIA_DIFF

SMIA_DP

SMIA_DIFF_PHY

SMIA_DATA_F_N

SMIA_DIFF

SMIA_DP

SMIA_DIFF_PHY

SMIA_CLK_P

SMIA_DIFF_PHY

SMIA_DP

SMIA_DIFF

SMIA_CLK_N

SMIA_DIFF

SMIA_DIFF_PHY

SMIA_DP

SMIA_CLK_F_P

SMIA_DIFF_PHY

SMIA_DP

SMIA_DIFF

I2C_CAMSENSOR_SCL

SMB

SMB_PHY

I2C_CAMSENSOR_SDA

SMB_PHY

SMB

SPI_50S

CAM_SF_DOUT_R

SPI

CAM_SF_WP_L

SPI_50S

SPI

SPI_50S

CAM_SF_DOUT

SPI

USB2_PHY

USB2

USB2_EXTD_N

USB_CAMERA_N

USB2_CONN_INT

USB2_PHY

USB2

USB_CAMERA_P

USB2_PHY

USB2

USB2_CONN_INT

USB3

USB3_PHY

USB3_EXTD_TX_C_N

USB3_EXTD_TX_C_P

USB3

USB3_PHY

USB3_PHY

USB3

USB3_EXTD_TX_F_N

USB3_EXTD_TX_F_P

USB3_PHY

USB3

USB3

USB3_PHY

USB3_EXTD_TX_N

USB3_TX_CONN

USB3_EXTD_TX_P

USB3_PHY

USB3

USB3_TX_CONN

USB3_EXTD_RX_F_P

USB3

USB3_PHY

051-9509

4.2.0

106 OF 113

93 OF 100

20 42

42

43

27 33

27

27

27

33

20 42

27 44

20 42

42

20 43

20 27

42

42

20 42

20 42

20 43

20 27

27 33

33

27 44

27

27

43

20 43

43

20 43

20 42

43

43

43

42

20 42

42

20

43

20 43

42

42

42

20 42

20 42

20 42

42

42

42

42

20 43

20 42

20 42

42

20 42

42

42

42

43

43

20 43

42

43

43

20 43

43

20 43

42

20 42

42

37 38

37 38

38

38

38

38

38

38

38

37

37 39

37

39

37

37 39

39

37

39

37 39

37 39

15 18 37

37 39

43

40

40

40

40

20 43

20 43

40

40

37

37

37

37

40

40

40

40

40

40

40

40

40

40

40

40

43

40

40

43

43

43

43

20 43

20 43

20 43

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VDDQ S0 (GPU Uncore)

VDDQ S3 (DDR)

Electrical Contraint Set

12V S0 (GPU Core)

Current/Voltage Sense

Electrical Contraint Set

12V S5 (System Total)

SSD

HDD

CPU AXG

CPU Core

PCH

SMBus-specific Spacing Definitions

Physical Net Type to Rule Map

EMC1414-1 (Production)

Spacing

Physical

Spacing

Electrical Contraint Set

SMC

SMC

Common

Physical

SMC

Constraints

SMBus-specific Physical Rules

SMBus

Physical Net Type to Rule Map

Sensor-specific Physical Rules

Sensor

Sensor-specific Spacing Definitions

Constraints

Physical

HDD Out-of-Band

SSD Out-of-Band

Temperature Sense

Electrical Contraint Set

Spacing

Physical

TMP423 (Development)

Display TCon

Spacing

SMBus

I1

I10

I11

I12

I13
I14

I15

I16

I19

I2

I20

I21

I22

I23

I24

I25

I26

I3

I32

I33

I34

I35

I36

I37

I38

I39

I4

I40

I41

I42

I43

I44

I45

I46

I47

I48

I49

I5

I50

I51

I52

I53
I54

I55

I56

I57

I58

I59

I6

I60

I61

I62

I65
I66

I67

I68

I69

I7

I70

I71
I72

I73

I74
I75

I76

I77

I78
I79

I8

I80

I81

I82

I83

I84

I85

I86

I87

I88

I89

I9

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

SMB_55S

=55_OHM_SE

=STANDARD

*

SMB_PHY SMB_55S

SMB_ISO

*

=2x_DIELECTRIC

?

1:1_DIFFPAIR

*

SNS_DIFF_PHY

SENSE_ISO

?

*

=4:1_SPACING

SMB

**

SMB_ISO

=STANDARD

Y

=STANDARD

*

=STANDARD

0.1 MM

0.085 MM

1:1_DIFFPAIR

SENSE_ISO

SENSE

* *

SENSE

*

POWER

PWR_P2MM

GND

*

GND_P2MM

SENSE

SYNC_MASTER=D7_DOUG

SYNC_DATE=01/03/2012

SMBus/Sensor Constraints

VSNS_P12VS0_GPUUNCORE

SENSE

ISNS_P12VS0_GPUUNCORE

SENSE

SENSE

ISNS_P12VS0_GPUUC_R

SENSE

ISNS_VDDQS3_DDR_R

SENSE

VSNS_VDDQS3_DDR

SNS_CURRENT

SENSE

SNS_DIFF_PHY

SNS_P12VS0_GPUUC_P

SNS_CURRENT

SENSE

SNS_DIFF_PHY

SNS_P12VS0_GPUUC_N

SENSE

ISNS_CPUCORE_FB
ISNS_CPUCORE

SENSE

VSNS_CPUCORE

SENSE

SNS_CURRENT

SENSE

SNS_DIFF_PHY

ISNS_CPUAXG_P

SENSE

ISNS_CPUAXG_FB

SENSE

SNS_VDDQS3_DDR_P

SNS_DIFF_PHY

SNS_CURRENT

SENSE

VSNS_SSDS0

SENSE

SNS_CURRENT

SNS_P12VS0_GPUCORE_N

SNS_DIFF_PHY

SENSE

VSNS_P12VG3H

ISNS_P12VG3H_R

SENSE

SENSE

SNS_CURRENT

SNS_P12VG3H_N

SNS_DIFF_PHY

ISNS_SSDS0_R

SENSE

SNS_P12VS0_GPUCORE_P

SENSE

SNS_CURRENT

SNS_DIFF_PHY

SNS_T2_2_N

SENSE

SNS_DIFF_PHY

SNS_TEMP

SENSE

SNS_DIFF_PHY

SNS_TEMP

SNS_SKIN_P

SENSE

SNS_DIFF_PHY

SNS_TEMP

SNS_SKIN_N

SNS_DIFF_PHY

SENSE

SNS_TEMP

SNS_T2_3_P

SNS_DIFF_PHY

SENSE

SNS_TEMP

SNS_T2_3_N

SENSE

SMC_HDD_OOB_TEMP

SNS_TEMP

SNS_T2_2_P

SENSE

SNS_DIFF_PHY

SNS_T2_1_N

SENSE

SNS_DIFF_PHY

SNS_TEMP

TBT_I2C

TBT_I2C_55S

SMBUS_PCH_DATA

SMC_EXTAL

CLK_XTAL

XTAL

SNS_P12VG3H_P

SNS_CURRENT

SENSE

SNS_DIFF_PHY

SNS_SSD_P

SENSE

SNS_CURRENT

SNS_DIFF_PHY

SNS_SSD_N

SENSE

SNS_CURRENT

SNS_DIFF_PHY

SENSE

ISNS_SSDS0

SMB_PHY

SMB

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

SMB_PHY

SMB

SNS_T1_2_N

SENSE

SNS_DIFF_PHY

SNS_TEMP

SNS_DIFF_PHY

SENSE

SNS_ACDC_N

SNS_TEMP

SENSE

SNS_VDDQS3_DDR_N

SNS_DIFF_PHY

SNS_CURRENT

SENSE

ISNS_VDDQS3_DDR

SNS_CURRENT

SENSE

ISNS_CPUCORE_P

SNS_DIFF_PHY

SNS_CURRENT

SENSE

ISNS_CPUCORE_N

SNS_DIFF_PHY

SENSE

VSNS_CPUAXG

SENSE

ISNS_CPUAXG

SNS_CURRENT

SENSE

SNS_DIFF_PHY

ISNS_CPUAXG_N

SMB_PHY

SMB

SMBUS_SMC_1_S0_SCL

SMB_DP_TCON_SCL

SMB

SMB_PHY

TBT_I2C_55S

TBT_I2C

SMBUS_PCH_CLK

SMB_PHY

SMB

SMBUS_SMC_5_G3H_SDA

SNS_DIFF_PHY

SENSE

SNS_TEMP

SNS_T1_1_P

SENSE

SSD_OOB_TEMP

SENSE

SMC_SSD_OOB_TEMP

SENSE

SMC_SSD_TEMP_CTL

SENSE

HDD_OOB_TEMP_R

HDD_OOB_TEMP_FILT

SENSE

SENSE

HDD_OOB_TEMP_CONN

SNS_DIFF_PHY

SENSE

SNS_TEMP

SNS_T1_2_P

SNS_T2_1_P

SNS_TEMP

SENSE

SNS_DIFF_PHY

SNS_DIFF_PHY

SENSE

SNS_ACDC_P

SNS_TEMP

SMC_XTAL

CLK_XTAL

XTAL

SMB

SMB_PHY

SML_PCH_0_DATA

SENSE

ISNS_P12VS0_GPUCORE_R

SNS_DIFF_PHY

SENSE

SNS_T1_1_N

SNS_TEMP

SENSE

VSNS_HDDS0

SENSE

ISNS_HDDS0

SENSE

ISNS_HDDS0_R

SNS_DIFF_PHY

SNS_CURRENT

SENSE

SNS_HDD_N

SENSE

SNS_CURRENT

SNS_HDD_P

SNS_DIFF_PHY

SENSE

VSNS_P12VS0_GPUCORE

SENSE

ISNS_P12VS0_GPUCORE

SENSE

ISNS_P12VG3H

GND_SMC_AVSS

SENSE

SMB_DP_TCON_SDA

SMB

SMB_PHY

SML_PCH_0_CLK

SMB

SMB_PHY

SMB

SMB_PHY

SMBUS_SMC_5_G3H_SCL

SMBUS_SMC_3_SDA

SMB_PHY

SMB

SMBUS_SMC_3_SCL

SMB

SMB_PHY

SMB_PHY

SMB

SMBUS_SMC_1_S0_SDA

SMB_PHY

SMB

SMBUS_SMC_2_S4_SDA

SMB

SMB_PHY

SMBUS_SMC_2_S4_SCL

051-9509

4.2.0

107 OF 113

94 OF 100

45 48

45 48

48

49

45 49

48

48

48

45 48

45 48

48

48

49

45 49

48

45 48

48

48

49

48

50

50

50

50

50

50

50

18 47

44 45

48

49

49

45 49

44 47

44 47

50

6

50

49

45 49

48

48

45 48

45 48

48

44 47

47 81

18 47

44 45

50

50

50

6

50

44 45

18 47

48

50

45 48

45 48

48

48

48

45 48

45 48

45 48

44 45 48 49

47 81

18 47

44 45

44 47

44 47

44 47

44 47

44 47

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

Power-specific Spacing Definitions

Power and Common

Constraints

Physical Net Type to Rule Map

DC-DC Baddies

DC-DC Control

DC-DC Baddies

DC-DC Control

Power and Common

Physical

Power-specific Physical Rules

FET Switched

Sensed

Output Bus

Local Ground

Input Bus

DIDT

Voltage

Output Bus

VCCIO

Input Bus

Electrical Contraint Set

Local Ground

Spacing NO_TEST

DIDT

Voltage

CPU VccIO/ PCH 1.05V S0

Physical

VDDQ S3 (1.5V)/VTT S0

NO_TEST

Output Bus

DC-DC

NO_TEST

DIDT

VoltageSpacing

Electrical Contraint Set

Local Ground

Input Bus

1.05V S0

FET Switched

Spacing

VDDQ S3

Physical

CPU VccSA

I1

I10

I11

I12

I13

I14

I15
I16

I17

I18

I19

I2

I20

I21

I22

I23

I24

I25

I26

I27
I28

I29

I3

I30

I31

I32

I33

I34

I35

I36

I37

I38

I39

I4

I40

I41

I42

I43

I44

I45

I46

I47

I48

I49

I5

I50

I51

I52

I53

I54

I55
I56

I57

I58

I59

I6

I60
I61

I62

I63

I64

I66

I7

I8

I9

VReg Constraints

SYNC_DATE=12/12/2011

SYNC_MASTER=D7_DAVE

*

POWER_P3MM

=STANDARDY

0.150 MM0.300 MM

=STANDARD

3.0 MM

BGA

VR_DIDT_PHY

STANDARD

*

VR_DIDT_PHY

POWER_P6MM

Y =STANDARD*

GND_P3MM

=STANDARD

0.150 MM0.300 MM

3.0 MM

3.0 MM

Y

GND_P5MM

* =STANDARD

0.150 MM0.500 MM

=STANDARD

GND_P5MM

GND

*

BGAGND

GND_P3MM

GND_ISO

*

GND

*

Y =STANDARD

0.600 MM

POWER_P6MM

* =STANDARD

0.150 MM

3.0 MM

=STANDARD

=50_OHM_SE

=STANDARD

=50_OHM_SE

POWER_50S

=50_OHM_SE

*

=50_OHM_SE

POWER_ISO

*

POWER

*

VR_SWITCH

* *

SWNODE_ISO

*

VR_SWITCH VR_SWITCH

SWNODE_SW2SW

VR_SWITCH

*

BGA

BGA_P1MM

*

POWER POWER_P6MM

VR_CTL_PHY

*

POWER_P3MM

*

POWER_50S

VR_VID_PHY

POWER_ISO

?

*

=STANDARD

GND_ISO

?

*

=STANDARD

?

*

SWNODE_SW2SW =1:1_SPACING

POWER_P3MM

BGA

POWER

POWER

*

VR_SWITCH

SWNODE_SW2PWR

**

VR_VID

VR_VID_ISO

VR_SWITCH

*

GND

SWNODE_SW2GND

BGA

STANDARD

VR_CTL_PHY

*

SWNODE_ISO

1000

=8:1_SPACING

SWNODE_SW2PWR

?

*

=2:1_SPACING

?

*

=2:1_SPACING

SWNODE_SW2GND

**

VR_CTL

VR_CTL_ISO

*

?

=4X_DIELECTRIC

VR_VID_ISO

*

=3:1_SPACING

?

VR_CTL_ISO

5V

POWER POWER

REG_PVCC_U7500

POWER

5V

REG_VCC_U7500

POWER

PPVDDQ_S3_DDR

POWER

1.5V

POWER

PP1V5_S0

POWER POWER

1.5V

REG_V5IN_U7700

5V

POWER POWER

VR_DIDT_PHY

12V

TRUE

REG_LGATE_VDDQS3

VR_SWITCH

REG_LGATE_VCCSAS0

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_UGATE_VCCSAS0

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

12V

REG_BOOT_VCCSAS0_RC

TRUE

VR_SWITCH

TRUE

VR_DIDT_PHY

1.5V

PPVDDQ_S3

POWERPOWER

SNS_P1V05S0_XW_N

SENSE

SNS_DIFF_PHY

POWER POWER 1.05V

PP1V05_TBTCIO

0.925V

POWER POWER

PPVCCSA_S0

VR_CTL_PHY

VR_CTL

REG_VCCSAS0_FSEL

VR_CTL_PHY

VR_CTL

REG_VCCSAS0_SREF

REG_VCCSAS0_RTN

SENSE

SENSE

REG_VCCSAS0_FB

VSNS_CPU_VCCSA

SENSE

SNS_DIFF_PHY

SNS_VCCSAS0_XW_N

SNS_VCCSAS0_XW_P

VSNS_CPU_VCCSA

SNS_DIFF_PHY

SENSE

SENSE

SNS_CPU_VCCSA

VR_CTL_PHY

VR_CTL

REG_VCCSAS0_VO

REG_VCCSAS0_OCSET

VR_CTL_PHY

VR_CTL

REG_SNUBBER_VCCSAS0

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

12V

REG_BOOT_VCCSAS0

TRUE

VR_SWITCH

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

REG_PHASE_VCCSAS0

VR_DIDT_PHY

AGND_VCCSAS0

GND

0V

GND

PP1V05_S0

1.05VPOWERPOWER

VR_CTL

VR_CTL_PHY

REG_P1V05S0_SREF

REG_PHASE_P1V05S0_L

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

SNS_P1V05S0_XW_P

SENSE

SNS_DIFF_PHY

REG_P1V05S0_FB

SENSE

REG_VCC_U7400

5V

POWERPOWER

REG_P1V05S0_OCSET

VR_CTL

VR_CTL_PHY

SNS_CPU_VCCIO_N

SENSE

SNS_DIFF_PHY

VSNS_CPU_VCCIO

TRUE

VR_SWITCH 12V

REG_LGATE_P1V05S0

VR_DIDT_PHY

REG_BOOT_P1V05S0

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

REG_PHASE_P1V05S0

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

AGND_P1V05S0

0V

GNDGND

REG_PVCC_U7400

5V

POWERPOWER

REG_SNUBBER_P1V05S0

TRUE

VR_SWITCH 12V

VR_DIDT_PHY

1.5V

POWER POWER

PPVDDQ_S3_SENSE

12V

TRUE

VR_SWITCH

REG_BOOT_VDDQS3_RC

VR_DIDT_PHY

TRUE

AGND_VDDQS3

GND

0V

GND

VR_DIDT_PHY

12V

REG_UGATE_VDDQS3

VR_SWITCH

TRUE

12V

TRUE

VR_SWITCH

REG_UGATE_VDDQS3_R

VR_DIDT_PHY

TRUE

REG_BOOT_P1V05S0_RC

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

REG_UGATE_P1V05S0

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

TRUE

12VVR_SWITCH

REG_UGATE_P1V05S0_R

VR_DIDT_PHY

REG_P1V05S0_VO

VR_CTL

VR_CTL_PHY

SNS_CPU_VCCIO_P

SENSE

SNS_DIFF_PHY

VSNS_CPU_VCCIO

REG_P1V05S0_RTN

SENSE

REG_P1V05S0_FSEL

VR_CTL

VR_CTL_PHY

POWER POWER 1.05V

PP1V05_TBTLC

LDO_DDRVTTS0_SNS

VR_CTL

VR_CTL_PHY

REG_PHASE_VDDQS3

12VVR_SWITCH

TRUE

VR_DIDT_PHY

POWER_DDR

0.75V

POWER_DDR

PPDDRVTT_S0

VR_DIDT_PHY

VR_SWITCH 12V

TRUE

REG_SNUBBER_VDDQS3

PPDDRVTT_S3

POWER_DDR

0.75V

POWER_DDR

VR_CTL_PHY

VR_CTL

REG_VDDQS3_MODE

VR_CTL

REG_VDDQS3_VREF

VR_CTL_PHY

VR_DIDT_PHY

VR_SWITCH 12V

REG_BOOT_VDDQS3

TRUE

VR_DIDT_PHY

VR_SWITCH 12V

REG_PHASE_VDDQS3_L

TRUE

VR_CTL_PHY

VR_CTL

REG_VDDQS3_TRIP

REG_VDDQS3_REFIN

VR_CTL

VR_CTL_PHY

VR_CTL

REG_VDDQS3_VDDQSNS

VR_CTL_PHY

051-9509

4.2.0

108 OF 113

95 OF 100

66

66

6

6

68

68

66

66

66

6

65

6

6

66

66

66

66

66

66

13 66

66

66

66

66

66

66

6

65

65

65

65

65

65

13 65

65

65

65

65

65

65

68

68

68

68

65

65

65

65

13 65

65

65

6

68

68

6

68

6

68

68

68

68

68

68

68

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Electrical Contraint Set

CPU Core Phases

Electrical Contraint Set

NO_TEST

DIDT

VoltageSpacing

Phase 2

Phase 3

Physical

Phase 1

Local Ground

Input Bus

NO_TEST

DIDT

VoltageSpacing

Physical

CPU AXG Phase and Core Controller

AXG

Output Bus

ISL6364

I1011

I1012

I1013

I1015
I1016

I1017

I1018

I1019

I1020

I1021

I1022

I1023

I1024

I1025

I1026

I1027

I1028
I1029

I1030

I1031

I1032

I1033

I1034

I1035

I1036

I1037

I1038

I1039
I1040

I1041

I1042

I1043

I1044

I1045

I1046

I1047

I1048
I1049

I1050

I1051

I1052
I1053

I1054

I1055

I1056

I1057

I1059
I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1068

I1069

I1136

I1138

I1140
I1141

I1142

I1143

I1144

I1145

I1146

I1147

I1148

I1149

I1150

I1151

I1152

I1155

I1156

I1157

I1158

I1159
I1160

I1161
I1162

I1163

I1164

I1165

I1166

I1183

I1185

I1186

I1187
I1188

I1189

I1190
I1191

I1192

I1193

I1194
I1195

I1196

I1197

I1198

I1264

I836

I883

I884
I885

I887

I888

I889

I890

I891
I892

I893

I894

I895
I896

CPU VReg Constraints

SYNC_MASTER=D7_DAVE

SYNC_DATE=12/12/2011

REG_CPUCORE_FDVID

VR_CTL

VR_CTL_PHY

REG_CPUCORE_IAUTO

VR_CTL

VR_CTL_PHY

REG_CPUCORE_SW_FREQ

VR_CTL

VR_CTL_PHY

REG_CPUCORE_RAMPADJ

VR_CTL

VR_CTL_PHY

REG_CPUCORE_RSET

VR_CTL

VR_CTL_PHY

VSNS_CPU_CORE

SENSE

SNS_DIFF_PHY

SNS_CPU_VAXG_N

1.1V

SENSE

SNS_DIFF_PHY

SNS_VAXG_XW_P

SENSE

SNS_DIFF_PHY

SNS_VAXG_R_N

0V

SNS_DIFF_PHY

SENSE

SNS_VAXG_XW_N
REG_CPUAXG_VSEN

SENSE

REG_CPUAXG_RGND

SENSE

REG_CPUAXG_IMON

VR_CTL_PHY

VR_CTL

SENSE

SNS_DIFF_PHY

SNS_VAXG_R_P

VSNS_CPU_CORE

SENSE

SNS_DIFF_PHY

SNS_CPU_VAXG_P

REG_CPUAXG_HFCOMP

VR_CTL

VR_CTL_PHY

CPUAXG_FB_RC

VR_CTL_PHY

VR_CTL

REG_CPUCORE_HFCOMP

VR_CTL

VR_CTL_PHY

VR_DIDT_PHY

REG_BOOT_CPUCORE_1_RC

VR_SWITCH 12V

TRUE TRUE

REG_UGATE_CPUCORE_1

VR_SWITCH

TRUE

VR_DIDT_PHY

12V

VR_DIDT_PHY

REG_LGATE_CPUCORE_1

TRUE

VR_SWITCH 12V

VR_DIDT_PHY

REG_SNUBBER_CPUCORE_1

12V

TRUE

VR_SWITCH

REG_PWM_CPUCORE_2_R

VR_CTL

VR_CTL_PHY

12V

REG_LVCC_U7230

POWERPOWER

VR_DIDT_PHY

VR_SWITCH 12V

TRUE

REG_UGATE_CPUCORE_2

REG_ISENAXG_P

SENSE

SNS_DIFF_PHYISNS_CPU_AXG

0V

SENSE

SNS_DIFF_PHY

SNS_VCORE_XW_N

REG_CPUCORE_RGND

SENSE

REG_CPUCORE_TM

VR_CTL

VR_CTL_PHY

CPUAXG_FB_R_1

VR_CTL

VR_CTL_PHY

CPUAXG_FB_R_2

VR_CTL

VR_CTL_PHY

REG_CPUAXG_TCOMP

VR_CTL

VR_CTL_PHY

CPU_VIDSOUT

VR_VID_PHY

VR_VID

CPU_VIDSOUT_R

VR_VID_PHY

VR_VID

PPVCORE_S0_CPU

1.1V

POWERPOWER

CPUCORE_PSICOMP_RC

VR_CTL

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

CPUCORE_FB_R_1

CPUCORE_FB_RC

VR_CTL

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

REG_CPUCORE_FB

VR_CTL

VR_CTL_PHY

CPUCORE_COMP_RC

VR_CTL

REG_CPUCORE_COMP

VR_CTL_PHY

VR_DIDT_PHY

REG_PHASE_CPUCORE_2

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_PHASE_CPUCORE_3

VR_SWITCH 12V

TRUE

SENSE

REG_ISENCORE_3_NR

ISNS_CPU_CORE

REG_ISENCORE_3_N

SENSE

SNS_DIFF_PHY

ISNS_CPU_CORE

REG_ISENCORE_3_P

SENSE

SNS_DIFF_PHY

PPCPUCORE_S0_SENSE_3

POWER

1.1V

POWER

VR_DIDT_PHY

REG_BOOT_CPUCORE_3_RC

VR_SWITCH 12V

TRUE TRUE

REG_PWM_CPUAXG

VR_CTL

VR_CTL_PHY

VR_DIDT_PHY

REG_LGATE_CPUAXG

TRUE

12VVR_SWITCH

VR_CTL_PHY

VR_CTL

CPUCORE_FB_R_2

SENSE

SNS_DIFF_PHY

SNS_VCORE_R_P

SENSE

SNS_DIFF_PHY

SNS_VCORE_R_N

1.1V

SENSE

SNS_DIFF_PHY

SNS_VCORE_XW_P

REG_CPUCORE_IMON

VR_CTL

VR_CTL_PHY

CPUCORE_IMON_R

VR_CTL

VR_CTL_PHY

REG_CPUCORE_SUTH

VR_CTL

VR_CTL_PHY

REG_CPUCORE_NPSI

VR_CTL

VR_CTL_PHY

CPUCORE_EN_PWR_R

VR_CTL_PHY

VR_CTL

REG_CPUAXG_FB

VR_CTL

VR_CTL_PHY

CPU_VIDALERT_R_L

VR_VID_PHY

VR_VID

PPVAXG_S0

1.1V

POWERPOWER

CPUAXG_COMP_RC

VR_CTL_PHY

VR_CTL

REG_CPUAXG_COMP

VR_CTL_PHY

VR_CTL

REG_PWM_CPUAXG_R

VR_CTL

VR_CTL_PHY

SENSE

REG_ISENCORE_2_NR

VR_DIDT_PHY

VR_SWITCH

REG_LGATE_CPUCORE_2

12V

TRUE

AGND_CPU

GND

0V

GND

5V

POWER

REG_VCC_U7100

POWER

POWER

PP12V_S0_CPUCORE_FLT

12V

POWER

CPUAXG_IMON_R

VR_CTL

VR_CTL_PHY

REG_CPUAXG_TM

VR_CTL

VR_CTL_PHY

REG_CPUAXG_SW_FREQ

VR_CTL

VR_CTL_PHY

CPU_VIDSCLK

VR_VID

VR_VID_PHY

CPU_VIDSCLK_R

VR_VID

VR_VID_PHY

CPU_VIDALERT_L

VR_VID_PHY

VR_VID

REG_CPUCORE_EN_PWR

VR_CTL

VR_CTL_PHY

REG_CPUCORE_VSEN

SENSE

VSNS_CPU_CORE

SENSE

SNS_DIFF_PHY

SNS_CPU_VCORE_N

VR_CTL_PHY

REG_SNUBBER_CPUCORE_3

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_LGATE_CPUCORE_3

12V

TRUE

VR_SWITCH

12V

TRUE

REG_UGATE_CPUCORE_3

VR_SWITCH

VR_DIDT_PHY

VR_DIDT_PHY

REG_BOOT_CPUCORE_3

12V

TRUE

VR_SWITCH

REG_ISENCORE_2_P

SENSE

SNS_DIFF_PHY

ISNS_CPU_CORE

VR_DIDT_PHY

REG_SNUBBER_CPUCORE_2

VR_SWITCH 12V

TRUE

SENSE

REG_ISENCORE_1_NR

ISNS_CPU_CORE

REG_ISENCORE_1_N

SENSE

SNS_DIFF_PHY

ISNS_CPU_CORE

SENSE

SNS_DIFF_PHY

REG_ISENCORE_1_P

VR_DIDT_PHY

REG_BOOT_CPUCORE_1

VR_SWITCH 12V

TRUE

VR_CTL

VR_CTL_PHY

REG_PWM_CPUCORE_1_R

VR_DIDT_PHY

VR_SWITCH

REG_BOOT_CPUCORE_2_RC

TRUE

12V

TRUE

VR_DIDT_PHY

VR_SWITCH

REG_BOOT_CPUCORE_2

12V

TRUE

VR_CTL_PHY

REG_PWM_CPUCORE_2

VR_CTL

POWERPOWER

PPCPUCORE_S0_SENSE_1

1.1V

VR_DIDT_PHY

VR_SWITCH 12V

TRUE

REG_PHASE_CPUCORE_1

REG_PWM_CPUCORE_1

VR_CTL_PHY

VR_CTL

REG_LVCC_U7210

12V

POWER POWER

REG_PWM_CPUCORE_3_R

VR_CTL

VR_CTL_PHY

REG_PWM_CPUCORE_3

VR_CTL

VR_CTL_PHY

PPCPUCORE_S0_SENSE_2

POWER

1.1V

POWER

REG_LVCC_U7250

POWER

12V

POWER

ISNS_CPU_CORE

REG_ISENCORE_2_N

SENSE

SNS_DIFF_PHY

VSNS_CPU_CORE

SENSE

SNS_DIFF_PHY

SNS_CPU_VCORE_P

VR_CTL

VR_CTL_PHY

REG_CPUCORE_PSICOMP

SENSE

REG_ISENAXG_NR

SENSE

REG_ISENAXG_PR

REG_ISENAXG_N

SNS_DIFF_PHY

SENSE

ISNS_CPU_AXG

PPCPUAXG_S0_SENSE

1.1V

POWERPOWER

12V

VR_DIDT_PHY

REG_UGATE_CPUAXG

TRUE

VR_SWITCH

VR_SWITCH

VR_DIDT_PHY

REG_BOOT_CPUAXG_RC

TRUETRUE

12V

VR_DIDT_PHY

REG_PHASE_CPUAXG

12V

TRUE

VR_SWITCH
VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_BOOT_CPUAXG

VR_DIDT_PHY

REG_SNUBBER_CPUAXG

12V

TRUE

VR_SWITCH

REG_LVCC_U7330

12V

POWERPOWER

051-9509

4.2.0

109 OF 113

96 OF 100

62

62

62

62

62

13 62

62

62

62

62

62

48 62

62

13 62

62

62

62

63

63

63

63

62

63

63

64

62

62

62

62

62

62

13 62

13

6

62

62

62

62

62

62

63

63

62 63

63

62 63

63

63

62 64

64

62

62

62

62

48 62

62

62

62

62

62

13

6

62

62

62

62 63

63

62 63 64

62

62 63 64

62

62

62

13 62

13

13 62

62

62

13 62

63

63

63

63

62 63

63

62 63

63

62 63

63

62

63

63

62 63

63

63

62 63

63

62

62 63

63

63

63

13 62

62

62 64

62 64

64

64

64

64

64

64

64

64

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Common

Physical

Ground/Common

Spacing Voltage

DIDT

NO_TEST

Input Bus

Sensed

12V

HDD S0

Physical

HDD S0

Physical

1.8V S0

1.8V S0

Physical

3.42V G3H

Output Bus

Physical

Spacing

Voltage

DIDT

DIDT

Spacing

Spacing

Voltage

Voltage

DIDT

DIDT

3.42V G3H

NO_TEST

NO_TEST

NO_TEST

NO_TEST

VoltageSpacing

DIDT

5V S3

Sensed

3.3V S5

Output Bus

FET Switched

Spacing Voltage

DIDT

NO_TEST

Output Bus

DIDT

VoltageSpacing

Electrical Contraint Set

Input Bus

Phase 1

Phase 2

ISL6568

Output Bus

Voltage

DIDT

Spacing

Physical

Output Bus

Electrical Contraint Set

Local Ground

Input Bus

GPU 1.05V S0

1.05V S0

DIDT

NO_TESTVoltageSpacing

Physical

NO_TEST

NO_TEST

DDR3 Vref

Memory Vref

Physical

GPU Core Phases and Controller

Local Ground

GPU VDDQ

NO_TEST

Physical

3.3V S5/5V S4

Output Bus

Spacing

Voltage

FET Switched

Physical

GPU VDDQ

Input Bus

Electrical Contraint Set

Input Bus

I1071

I1072

I1077

I1078

I1082

I1136

I1137
I1138

I1139

I1140
I1141

I1142

I1143

I1144

I1145

I1146

I1147

I1148

I1149

I1151

I1153

I1155

I1165

I1166

I1185

I1218

I1219

I1233

I1236

I1254
I1255

I1268
I1269

I1271

I1272

I1273

I1274

I1275

I1276

I1277

I1278
I1279

I1280
I1282

I1290

I1292

I1293
I1294

I1297

I1298
I1299

I1300

I1301

I1302

I1303

I1304

I1305

I1308

I1311

I1312

I1313

I1314
I1315

I1316
I1317

I1318
I1319

I1320

I1321

I1322
I1323

I1324

I1351

I1352

I1353

I1354

I1355

I1356

I1382

I1389

I1390

I1392

I1393

I1395

I1396

I1397

I1398
I1399

I1400
I1401

I1402

I1404

I1405

I1406
I1407

I1410

I1411

I1412

I1413

I1414

I1415

I1416

I1417

I1418

I1419

I1421
I1422

I1423

I1425
I1428

I1429

I1432
I1433

I1434

I1435
I1436

I1437

I1438

I1439

I1440
I1441

I1442

I1443

I1444

I1445

I1446

I1447

I1448

I1449

I1450

I1451

I1452

I1453

I1454

I1456

I1458

I1459

I843

I847

I848

I849

I850

I851

I852

SYNC_DATE=12/12/2011

Platform VReg Constraints

SYNC_MASTER=D7_DAVE

REG_VCC_U8300

5V

POWERPOWER

GND

P1V05_GPU_AGND

GND

0V

AGND_GPUVDDQ

0V

GNDGND

TRUE

REG_PHASE_GPUVDDQ

VR_SWITCH 12V

VR_DIDT_PHY
VR_DIDT_PHY

REG_BOOT_GPUVDDQ

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

TRUE TRUE

REG_BOOT_GPUVDDQ_RC

VR_SWITCH 12V

SNS_DIFF_PHY

VSNS_GPU_VDDQ

SNS_GPUVDDQ_P

SENSE

SNS_DIFF_PHY

VSNS_GPU_VDDQ

SNS_GPUVDDQ_N

SENSE

SENSE

REG_GPUVDDQ_RTN

VR_CTL

VR_CTL_PHY

REG_GPUVDDQ_SREF

VR_CTL_PHY

VR_CTL

REG_GPUVDDQ_FSEL

VR_CTL

REG_GPUVDDQ_SET0

VR_CTL_PHY

VR_CTL

REG_GPUVDDQ_SET1

VR_CTL_PHY

VR_CTL

REG_GPUVDDQ_SET1_R

VR_CTL_PHY

1.5V

POWERPOWER

PPVDDQ_S0_GPU

REG_GPUCORE_VSEN

SENSE

REG_GPUCORE_RGND

SENSE

VR_VID_PHY

REG_GPUCORE_VID3

VR_VID

VR_VID_PHY

REG_GPUCORE_VID2

VR_VID

REG_LGATE_GPUVDDQ

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_GPUVDDQ_VO

VR_CTL

VR_CTL_PHY

POWERPOWER

REG_VCC_U8350

5V

POWER

REG_PVCC_U8350

5V

POWER

POWER

12V

POWER

REG_PVCC_U8900

POWER

5V

POWER

REG_VCC_U8900

VR_SWITCH

REG_BOOT_GPUCORE_1

12V

TRUE

VR_DIDT_PHY

VR_CTL_PHY

VR_CTL

REG_GPUCORE_COMP

REG_GPUCORE_MODE

VR_CTL

VR_CTL_PHY

POWER POWER

5V

PP5V_S4

REG_BOOT_P5VS4

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_BOOT_P5VS4_RC

TRUE

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_PHASE_P5VS4

12V

TRUE

VR_SWITCH

VR_DIDT_PHY

POWER

PP12V_S5

POWER

12V

PP12V_ACDC

POWERPOWER

12V

POWER

1.8V

PP1V8_S0

POWER

VR_SWITCH 12V

TRUE

REG_ISEN_GPUCORE_1

VR_DIDT_PHY

SENSE

REG_GPUVDDQ_FB

REG_LGATE_GPUCORE_2

TRUE

VR_SWITCH 12V

VR_DIDT_PHY

TRUE

VR_SWITCH 12V

VR_DIDT_PHY

REG_SNUBBER_GPUCORE_2

VR_CTL_PHY

REG_P1V8S0_SYNCH

VR_CTL

VR_SWITCH 12V

TRUE

REG_PHASE_GPUCORE_1

VR_DIDT_PHY

REG_GPU_P1V05S0_VO

VR_CTL_PHY

VR_CTL

REG_GPU_P1V05S0_OCSET

VR_CTL_PHY

VR_CTL

REG_GPU_P1V05S0_VO_R

VR_CTL_PHY

VR_CTL

REG_GPU_P1V05S0_OCSET_R

VR_CTL_PHY

VR_CTL

REG_UGATE_GPU_P1V05S0

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

REG_PHASE_GPU_P1V05S0_L

REG_GPUCORE_REF

VR_CTL

VR_CTL_PHY

PP3V3_TBTLC

POWER

3.3V

POWER

POWERPOWER

PP5V_S0

5V

PP12V_S0_GPUUNCORE

12V

POWERPOWER

REG_UGATE_P5VS4

TRUE

12VVR_SWITCH

VR_DIDT_PHY

REG_SNUBBER_P5VS4

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

VR_CTL

VR_CTL_PHY

REG_P5VS4_ISEN

0V

GND

GND

GND

REG_P5VS4_FB

VR_CTL_PHY

VR_CTL

VSNS_GPU_CORE

SNS_GPU_CORE_N

SENSE

SNS_DIFF_PHY

POWER POWER

12V

REG_VIN_U7600

POWER POWER

5V

REG_VCC2_U7600

TRUE

VR_SWITCH

REG_PHASE_P3V3S5

12V

VR_DIDT_PHY

12V

TRUE

REG_UGATE_P3V3S5

VR_SWITCH

VR_DIDT_PHY

TRUE

VR_SWITCH

REG_LGATE_P3V3S5

12V

VR_DIDT_PHY

12V

TRUE

REG_SNUBBER_P3V3S5

VR_SWITCH

VR_DIDT_PHY

REG_GPUCORE_FS

VR_CTL

VR_CTL_PHY

REG_UGATE_GPU_P1V05S0_R

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_GPU_P1V05S0_SREF

VR_CTL_PHY

VR_CTL

12V

POWERPOWER

PP12V_S0_GPUCORE

POWER

12V

POWER

PP12V_G3H

PP12V_S0

POWER POWER

12V

PPHDD_S0

POWER POWER

5V

REG_P1V8S0_VFB

VR_CTL_PHY

VR_CTL

REG_PHASE_P1V8S0

5V

VR_SWITCH

POWER

3.425V

POWERPOWER

PP3V42_G3H

P3V42G3H_FB

VR_CTL

VR_CTL_PHY

P3V42G3H_SHDN_L

VR_CTL

VR_CTL_PHY

VR_SWITCH

POWER

12V

P3V42G3H_BOOST
P3V42G3H_SW

12V

POWER

VR_SWITCH

POWER_DDR

CPU_DDR_VREF

0.75V

POWER_DDR

POWER

PP3V3_S4_VREFMRGN_CTRL

3.3V

POWER

PPDDRVREF_DQ_MEM_B_S3

0.75V

POWER_DDR POWER_DDR

PPDDRVREF_CA_MEM_A_S3

0.75V

POWER_DDR POWER_DDR

CPU_DIMM_VREF_DAC_B

POWER_DDRPOWER_DDR

0.75V

CPU_DIMM_VREF_DAC_A

POWER_DDR

0.75V

POWER_DDR

PPDDRVREF_CA_MEM_B_S3

0.75V

POWER_DDRPOWER_DDR

POWER_DDR

0.75V

PPDDRVREF_DQ_MEM_A_S3

POWER_DDR

PP3V3_S4_VREFMRGN_DAC

POWER POWER

3.3V

VR_SWITCH

TRUE

12V

REG_PHASE_GPU_P1V05S0

VR_DIDT_PHY

REG_GPU_P1V05S0_FSEL

VR_CTL_PHY

VR_CTL

TRUE

REG_BOOT_GPU_P1V05S0_RC

VR_SWITCH

TRUE

12V

VR_DIDT_PHY

POWER POWER 1.05V

PP1V05_S0_GPU

REG_GPU_P1V05S0_RTN

SENSE

SNS_DIFF_PHY

SNS_GPU_PEX_IOVDD_P

VSNS_GPU_P1V05

SENSE

PP3V3_S0_SSD

3.3V

POWERPOWER

PP3V3_S0

3.3V

POWERPOWER

POWER

PP3V3_S4

3.3V

POWER

PP3V3_S5

3.3V

POWERPOWER

PP5V_S5

POWER

5V

POWER

VR_CTL

REG_P5VS4_VOUT_R

VR_CTL_PHY

VR_CTL

VR_CTL_PHY

REG_P5VS4_FSET

VR_SWITCH

REG_LGATE_P5VS4

TRUE

12V

VR_DIDT_PHY

REG_P3V3S5_FB

VR_CTL_PHY

VR_CTL

VR_CTL

VR_CTL_PHY

REG_P3V3S5_OCSET

VR_CTL_PHY

VR_CTL

REG_P3V3S5_FSET

VR_CTL_PHY

REG_P3V3S5_VOUT_R

VR_CTL

VR_CTL

REG_P3V3S5_ISEN

VR_CTL_PHY

REG_GPUCORE_VID4

VR_VID_PHY

VR_VID

GPUCORE_VDIFF_R

VR_CTL

VR_CTL_PHY

VR_CTL_PHY

REG_GPUCORE_OCSET

VR_CTL

REG_UGATE_GPUVDDQ

TRUE

12V

VR_DIDT_PHY

VR_SWITCH

REG_GPUVDDQ_OCSET

VR_CTL

VR_CTL_PHY

VR_SWITCH

TRUE

12V

REG_BOOT_GPU_P1V05S0

VR_DIDT_PHY

REG_LGATE_GPU_P1V05S0

12VVR_SWITCH

TRUE

VR_DIDT_PHY

REG_GPUCORE_VID0

VR_VID

VR_VID_PHY

VR_VID_PHY

REG_GPUCORE_VID1

VR_VID

VR_CTL

VR_CTL_PHY

GPUCORE_VDIFF_RC

REG_GPU_P1V05S0_FB

SENSE

SNS_DIFF_PHY

SNS_GPU_PEX_IOVDD_N

VSNS_GPU_P1V05

SENSE

VSNS_GPU_CORE

SNS_GPU_CORE_P

SENSE

SNS_DIFF_PHY

REG_GPUCORE_IREF

VR_CTL

VR_CTL_PHY

TRUE TRUE

VR_SWITCH 12V

REG_BOOT_GPUCORE_2_RC

VR_DIDT_PHY

REG_GPUCORE_OFS

VR_CTL

VR_CTL_PHY

PPVCORE_S0_GPU

POWER

1.0V

POWER

12V

TRUE TRUE

REG_BOOT_GPUCORE_1_RC

VR_DIDT_PHY

VR_SWITCH

VR_CTL

VR_CTL_PHY

REG_GPUCORE_FB

REG_P5VS4_VOUT

VR_CTL

VR_CTL_PHY

VR_CTL_PHY

VR_CTL

REG_P5VS4_OCSET

PP3V3_ENET

POWER POWER

3.3V

POWER POWER

3.3V

PPSSD_S0

GPUCORE_COMP_RC

VR_CTL

VR_CTL_PHY

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

REG_SNUBBER_GPUCORE_1

VR_SWITCH 12V

TRUE

REG_BOOT_GPUCORE_2

VR_DIDT_PHY

REG_UGATE_GPUCORE_1

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

VR_CTL

REG_GPUCORE_ICOMP

VR_CTL_PHY

REG_LGATE_GPUCORE_1

TRUE

VR_SWITCH 12V

VR_DIDT_PHY

VR_SWITCH 12V

TRUE

REG_UGATE_GPUCORE_2

VR_DIDT_PHY

REG_PHASE_GPUCORE_2

VR_SWITCH 12V

TRUE

VR_DIDT_PHY

12V

TRUE

VR_SWITCH

REG_BOOT_P3V3S5

VR_DIDT_PHY

VR_SWITCH

TRUE

12V

REG_BOOT_P3V3S5_RC

TRUE

VR_DIDT_PHY

POWER

5V

POWER

REG_VCC1_U7600

REG_P3V3S5_VOUT

VR_CTL_PHY

VR_CTL

REG_GPUCORE_VDIFF

VR_CTL

VR_CTL_PHY

REG_GPUCORE_ISUM

VR_CTL

VR_CTL_PHY

GPUCORE_ICOMP_R

VR_CTL

VR_CTL_PHY

TRUE

VR_SWITCH 12V

REG_ISEN_GPUCORE_2

VR_DIDT_PHY

051-9509

4.2.0

110 OF 113

97 OF 100

74

74

74

74

74

74

73 74

73 74

74

74

74

74

74

74

6

80

80

80

80

74

74

74

74

80

80

80

80

80

6

67

67

67

6

6

6

80

74

80

80

68

80

74

74

74

74

74

74

80

6

6

6

67

67

67

67

79 80

67

67

67

67

67

67

80

74

74

6

6

6

6

68

68

6

69

69

69

69

11

32

6

6

11
32

11
32

6

6

32

74

74

74

6

74

74 79

6

6

6

6

6

67

67

67

67

67

67

67

67

80

80

80

74

74

74

74

80

80

80

74

74 79

79 80

80

80

80

6

80

80

67

67

6

6

80

80

80

80

80

80

80

80

67

67

67

67

80

80

80

80

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TBT IC Net Properties

Electrical Contraint Set

Port A

Electrical Contraint Set

DisplayPort

Electrical Contraint Set

Physical

TBT/DP Net Properties

Port B

Graphics Source

Spacing

Internal Panel

Internal DP SPDIF

Physical

Spacing

Thunderbolt

Spacing

DisplayPort AUX channel intra-pair matching should be 5 ps. No relationship to other signals.

Physical

Thunderbolt-specific Spacing Definitions

DP-specific Spacing Definitions

Max length of DisplayPort traces: 12 inches

Thunderbolt-specific Physical Rules

DP-specific Physical Rules

DisplayPort

SOURCE: Bill Cornelius’s T29 Routing Notes

Pairs should be within 100 mils of clock length.

DisplayPort intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

*: Only used on hosts supporting T29 video-in

*

I511

I512

I513

I514

I515

I516

I517

I518

I519

I520

I521

I522

I523

I524

I525

I526

I529
I530

I531
I532

I533
I534

I535

I538

I541

I542

I543

I544

I545

I546

I547

I548

I549
I550

I563

I564

I565
I566

I595

I596

I599
I600

I601
I602

I603

I604

I605

I606
I607

I608

I609
I610

I611

I642

I643
I644

I645

I646
I647

I648

I649
I650

I651

I652
I653

I654

I655

I656

I657

I658

I659

I660

I661

I662

I663

I664

I665

I666
I667

I668

I669

I670

I671

I672

I673

I674

I675

I676
I677

I678
I679

I680

I681

I682

I683

I684

I685

I686

I687

SYNC_MASTER=D7_NICK

SYNC_DATE=12/13/2011

TBT/DP Constraints

=55_OHM_SE

TBT_I2C_55S

=STANDARD*

=55_OHM_SE=55_OHM_SE

=STANDARD

=55_OHM_SE

TBT_SPI_55S

=STANDARD

=55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE*=55_OHM_SE

TBT_SPI

*

=2x_DIELECTRIC

?

TBTDP

=5x_DIELECTRIC

?

*

=90_OHM_DIFF

TBTDP_90D

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

*

=90_OHM_DIFF

TBT_I2C

?

=2x_DIELECTRIC

*

TBTDP

=7x_DIELECTRIC

?

TOP,BOTTOM

?

=3:1_SPACING

*

DISPLAYPORT

=85_OHM_DIFF

=85_OHM_DIFF

DP_85D

=85_OHM_DIFF

*

0.08MM

=85_OHM_DIFF

=85_OHM_DIFF

DP_TBTSNK0_AUXCH_P

DISPLAYPORT

DP_85D

DP_TBTSNK0_AUX

DP_TBTSNK1_ML_C_N<3..0>

DISPLAYPORT

DP_85D

TBT_SPI_55S

TBT_SPI

TBT_SPI_CLK

TBT_SPI_CLK

TBT_SPI_55S

TBT_SPI

TBT_SPI_MOSI

TBT_SPI_MOSI

TBT_SPI_CS_L

TBT_SPI_55S

TBT_SPI_CS_L

TBT_SPI

DP_85D

DISPLAYPORT

DP_TBTSRC_AUX_C_N

DP_TBTSNK1_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML

DP_INTPNL_TBT_AUX_MUX

DISPLAYPORT

DP_TBTSRC_AUXCH_N

DP_85D

TBT_I2C_55S

TBT_I2C

=I2C_TBTRTR_SDA

DP_INTPNL_TBT_ML_MUX

DISPLAYPORT

DP_85D

DP_TBTSRC_ML_C_P<3..0>

DP_INTPNL_TBT_ML_MUX

DP_85D

DISPLAYPORT

DP_TBTSRC_ML_C_N<3..0>

DP_INTPNL_TBT_ML_MUX

DISPLAYPORT

DP_TBTSRC_ML_N<3..0>

DP_85D

DP_INTPNL_TBT_ML_MUX

DP_TBTSRC_ML_P<3..0>

DP_85D

DISPLAYPORT

TBT_SPI_MISO

TBT_SPI_55S

TBT_SPI_MISO

TBT_SPI

TBT_I2C

TBT_I2C_55S

=I2C_TBTRTR_SCL

DISPLAYPORT

DP_TBTSRC_AUX_C_P

DP_85D

DP_INTPNL_TBT_AUX_MUX

DP_TBTSRC_AUXCH_P

DP_85D

DISPLAYPORT

TBTDP_90D

TBTDP

TBT_B_R2D_N<1..0>

TBTDP

TBTDP_90D

TBT_B_R2D_C_P<1..0>

TBT_B_R2D

TBTDP_90D

TBT_A_D2R_N<1>

TBTDP

TBT_A_D2R1

TBTDP_90D

TBT_A_D2R1

TBT_A_D2R_P<1>

TBTDP

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_P

DP_85D

DP_A_AUXCH_DDC_N

DISPLAYPORT

DP_A_AUXCH_DDC

DP_85D

DP_TBTSNK1_AUXCH_C_N

DISPLAYPORT

DISPLAYPORT

DP_85D

DP_TBTSNK1_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_TBTSNK1_AUX

DP_TBTSNK1_AUXCH_P

DISPLAYPORT

DP_85D

DP_TBTSNK1_AUX

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK1_ML

DISPLAYPORT

DP_85D

DP_INT_EG_AUX_N

DP_INTPNL_EG_AUX_MUX

DISPLAYPORT

DP_85D

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML3

DP_85D

DISPLAYPORT

DP_TBTPB_ML_N<3>
DP_B_LSX_ML_P<1>

DP_85D

DISPLAYPORT

DP_B_LSX

DP_B_LSX_ML_N<1>

DISPLAYPORT

DP_85D

DP_B_LSX

TBTDP_90D

TBTDP

TBT_B_D2R_C_P<1..0>

TBTDP_90D

TBTDP

TBT_B_D2R_C_N<1..0>

TBT_B_D2R1

TBT_B_D2R_P<1>

TBTDP

TBTDP_90D

TBT_B_D2R0

TBT_B_D2R_P<0>

TBTDP_90D

TBTDP

TBT_B_D2R0

TBT_B_D2R_N<0>

TBTDP_90D

TBTDP

TBT_B_AUXCH

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_C_P

TBT_B_AUXCH

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_C_N

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_N

DP_85D

DISPLAYPORT

DP_B_AUXCH_DDC_N

DP_B_AUXCH_DDC

TBTDP

TBTDP_90DTBT_B_R2D

TBT_B_R2D_C_N<1..0>

DP_85D

DISPLAYPORT

DP_TBTPB_ML1

DP_TBTPB_ML_C_P<1>

TBTDP

TBTDP_90D

TBT_B_R2D_P<1..0>

TBT_B_D2R1

TBT_B_D2R_N<1>

TBTDP

TBTDP_90D

DP_INTPNL_ML_C_P<3..0>

DISPLAYPORT

DP_85D

TBTDP

TBT_B_D2R1_AUXDDC_N

TBTDP_90D

TBTDP

TBT_B_D2R1_AUXDDC_P

TBTDP_90D

DP_85D

DISPLAYPORT

DP_B_AUXCH_DDC_P

DP_B_AUXCH_DDC

DP_85D

DISPLAYPORT

DP_TBTPB_ML_P<1>

TBT_A_D2R1_AUXDDC_N

TBTDP

TBTDP_90D

TBTDP_90D

TBT_A_D2R1_AUXDDC_P

TBTDP

DISPLAYPORT

DP_85D

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML3

DP_85D

DP_TBTPA_ML_N<1>

DISPLAYPORT

DP_TBTSNK1_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_85D

DP_INTPNL_AUX_N

DP_INTPNL_AUX_CONN

DISPLAYPORT

DP_85D

DP_INTPNL_AUX_P

DISPLAYPORT

DP_INTPNL_AUX_CONN

DP_INTPNL_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DISPLAYPORT

DP_INTPNL_ML_N<3..0>

DP_INTPNL_ML_CONN

DP_85D

DP_INTPNL_ML_P<3..0>

DP_INTPNL_ML_CONN

DISPLAYPORT

DP_85D

DP_85D

DISPLAYPORT

DP_TBTPB_AUXCH_P

DP_85D

DISPLAYPORT

DP_A_AUXCH_DDC_P

DP_A_AUXCH_DDC

DISPLAYPORT

DP_85D

TBT_A_AUXCH

DP_TBTPA_AUXCH_C_N

DP_85D

DP_A_LSX_ML_N<1>

DISPLAYPORT

DP_A_LSX

TBT_A_R2D_N<1..0>

TBTDP_90D

TBTDP

TBT_A_R2D_P<1..0>

TBTDP_90D

TBTDP

TBT_A_R2D

TBT_A_R2D_C_N<1..0>

TBTDP_90D

TBTDP

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML_C_P<3..0>

DP_TBTSNK0_AUXCH_N

DISPLAYPORT

DP_85D

DP_TBTSNK0_AUX

DP_TBTSNK0_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML

DP_TBTSNK0_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_TBTSNK0_ML

DP_TBTSNK0_AUXCH_C_N

DP_85D

DISPLAYPORT

DP_TBTSNK0_AUXCH_C_P

DP_85D

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML1

DISPLAYPORT

DP_85D

DP_TBTPB_ML_N<1>

DISPLAYPORT

DP_85D

DP_TBTPB_ML_P<3>

DP_INTPNL_EG_ML_MUX

DISPLAYPORT

DP_85D

DP_INT_EG_ML_P<1..0>

DP_85D

DISPLAYPORT

DP_TBTPA_AUXCH_N

DP_TBTPA_AUXCH_C_P

DISPLAYPORT

DP_85D

TBT_A_AUXCH

TBTDP_90D

TBT_A_D2R_N<0>

TBTDP

TBT_A_D2R0

TBTDP_90D

TBT_A_D2R_P<0>

TBTDP

TBT_A_D2R0

TBTDP_90D

TBT_A_D2R_C_P<1..0>

TBTDP

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML3

DP_85D

DISPLAYPORT

DP_85D

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML3

DISPLAYPORT

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML1

DP_85D

DISPLAYPORT

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML1

DISPLAYPORT

DP_85D

DP_85D

DP_TBTPA_ML_P<3>

DISPLAYPORT

DP_85D

DP_TBTPA_ML_N<3>

DISPLAYPORT

DP_85D

DP_TBTPA_ML_P<1>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_A_LSX_ML_P<1>

DP_A_LSX

TBT_A_R2D_C_P<1..0>

TBT_A_R2D TBTDP_90D

TBTDP

TBTDP_90D

TBT_A_D2R_C_N<1..0>

TBTDP

DP_INTPNL_EG_ML_MUX

DP_85D

DISPLAYPORT

DP_INT_EG_ML_N<1..0>

DISPLAYPORT

DP_INT_EG_AUX_P

DP_85D

DP_INTPNL_EG_AUX_MUX

HDA

DP_INT_SPDIF_AUDIO

DP_85D

DISPLAYPORT

DP_INT_EG_AUX_C_N

DISPLAYPORT

DP_INT_EG_AUX_C_P

DP_85D

DP_85D

DISPLAYPORT

DP_TBTSNK0_ML_C_N<3..0>

051-9509

4.2.0

111 OF 113

98 OF 100

34

34 77

34

34

34

82

34

82

34 47

82

82

82

82

34

34 47

82

82

85

34 85

34 84

34 84

84

84

34 71

34 71

34

34

34

77 82

34 85

85

85

85

85

85

34 85

34 85

34 85

34 85

34 85

85

85

34 85

34 85

85

34 85

82

85

85

85

85

84

84

34 85

84

34 77

81 82

81 82

82

81 82

81 82

85

84

34 84

84

84

84

34 84

34 77

34

34

34

34 71

34 71

34 85

85

85

77 82

84

34 84

34 84

34 84

84

34 84

34 84

34 84

34 84

84

84

84

84

34 84

84

77 82

77 82

52 81

82

82

34 77

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Address Dynamic Bus Inversion: ADBIxy

Clock: CKxy

Electrical Contraint Set

GPU Misc.

SMB

Physical

Micro

5:1

Memory address (MA). Implented 4.5 Gbps or less rules for K70.

Memory Address: MAxy[8:0]

Control

Physical Net Type to Rule Map

GDDR5 Frame Buffer B

Physical

Data Dynamic Bus Inv

Forwarded Clock

3:1

Constraints (x in {A, B}, y in {0, 1})

Strip

5:1

5:12:1

2:1

Design

5:1

5:1

Design

2:1

5:1

3:1

7:1

5-6/5-7
5-6/5-7

5-6/5-7

Table

5-6/5-7
5-6/5-7
5-6/5-7
5-6/5-7

3:1

3:1

5:1

2:1
2:1

2:1
2:1
2:1

7:1

2:1

3:1 3:1

5:1
3:1

7:1

5:1

5:1
5:1
5:1

5:1

Strip

5:1

5:1

5:1

5:1

5:1
5:1

Forwarded Clock

Data

Clock

Error Detection

Control

Electrical Contraint Set

Physical

Spacing

GDDR5

Data

Clock

Data Dynamic Bus Inversion: DDBIxy[3:0]

2:1

Micro

Design

Trace-to-Trace

5:1

5:1

7:1

5:1

5:1

Design

Isolation

Comments

5:1
5:1
5:1

Clock (CLK)
Data (DQ)

7:1

5:1

5:15:15:1

5-6/5-7

Error Detection

5:1

7:1 7:1 7:1

5:1

GDDR5-specific Spacing Definitions

2:1

2:1

3:1
5:1

Control (CTRL)

5:15:1

5:1

Address Dynamic Bus Inv Address Dynamic Bus Inv

Spacing

GDDR5 Frame Buffer A

Memory Address

Address dynamic bus inversion (ADBI)

Data Dynamic Bus Inv

Memory Address

Electrical Contraint Set

Frame Buffer Reset

Physical

Spacing

Electrical Contraint Set

Reset

Main Segment Min Spacing Rules for 4.5 Gbps or Less (AMD Doc# 49919)

GDDR5-specific Physical Rules

Error detection pins (EDC). Using larger isolation rules,
Data dynamic bus inversion (DBI)
Forwarded clock (WCK)

Error Detection: EDCxy[3:0]

Control: Reset, CKExy, CSxy, WExy, RASxy, CASxy

Data: DQxy[31:0]

Forwarded Clock: WCKxy[1:0]

Spacing

I563

I564

I642

I643

I644

I645

I647
I648

I649
I650

I651

I652

I653

I654

I655

I656

I657
I658

I659

I660

I661

I662

I663

I664

I665

I666

I667
I668

I669

I670

I671
I672

I673

I674

I675

I676

I677

I678

I679

I680

I681

I682

I683

I684

I685

I686

I687

I688

I689
I690

I691

I692

I693

I694

I695

I696

I697

I698

I700

I701

I702

I703

I704

I705

I706

I707

I708

I709

I710

I711

I712

I713

I714

I715

I716

I717

I718

I719

I720

I721

I722

I723

I724

I725

I726

I727

I728

I729

I730

I731

I732

I733

I734

I735

I736

I737

I738

I739

I740

I741

I742

I743

I744

I745

I746

I753

I754

I755

SYNC_MASTER=D7_DAVE

SYNC_DATE=12/12/2011

GDDR5/GPU Constraints

GDDR_*_*_ADBI

*

GDDR_ISO

*

* *

GDDR_ISO

GDDR_*_*_CLK

*

=SAME

GDDR_CLK2CLKGDDR_*_*_CLK

*

?

GDDR_ADBI2ADBI =2x_DIELECTRIC

*

?

=5x_DIELECTRIC

GDDR_WCK2WCK

=STANDARD

12 MM

* =STANDARD

=50_OHM_SE =50_OHM_SE

GDDR_50S

=50_OHM_SE

* =STANDARD

=45_OHM_SE =45_OHM_SE=45_OHM_SE

GDDR_45S

=STANDARD

=45_OHM_SE

GDDR_DQ_PHY

GDDR_45S

*

GDDR_CLK_PHY

GDDR_80D

*

GDDR_CTRL_PHY

*

GDDR_45S

GDDR_ADBI_PHY

GDDR_45S

*

=SAME

GDDR_*_*_MA

*

GDDR_MA2MA

GDDR_ISO

GDDR_*_*_DQ

* *

=SAME GDDR_DQ2DQ

GDDR_*_*_DQ

*

GDDR_ADBI2ADBI

=SAME

*

GDDR_*_*_ADBI

GDDR_DBI_PHY

*

GDDR_45S

GDDR_WCK_PHY

*

GDDR_80D

?

*

=2x_DIELECTRICGDDR_CTRL2CTRL

*

GDDR_ISO

?

=5x_DIELECTRIC

TOP,BOTTOM

?

GDDR_MA2MA

=2x_DIELECTRIC

GDDR_CLK2CLK

=5x_DIELECTRIC

TOP,BOTTOM

?

?

*

GDDR_CLK2CLK

=5x_DIELECTRIC

GDDR_DQ2DQ

?

*

=3x_DIELECTRIC

=7x_DIELECTRIC

GDDR_EDC_ISO

?

*

TOP,BOTTOM

?

GDDR_ADBI2ADBI =2x_DIELECTRIC

?

TOP,BOTTOM

=5x_DIELECTRIC

GDDR_ISO

GDDR_EDC_PHY

*

GDDR_45S

GDDR_MA_PHY

*

GDDR_45S

=80_OHM_DIFF

GDDR_80D

=80_OHM_DIFF*

=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF

GDDR_MA2MA

*

?

=2x_DIELECTRIC

?

GDDR_CTRL2CTRL =2x_DIELECTRIC

TOP,BOTTOM

*

=SAME

GDDR_CTRL2CTRL

GDDR_*_*_CTRL

GDDR_DBI2DBI

=3x_DIELECTRIC

*

?

TOP,BOTTOM

=3x_DIELECTRIC

?

GDDR_DQ2DQ

GDDR_EDC_ISO

=7x_DIELECTRIC

?

TOP,BOTTOM

TOP,BOTTOM

=7x_DIELECTRIC

GDDR_EDC2EDC

?

TOP,BOTTOM?=5x_DIELECTRIC

GDDR_WCK2WCK

GDDR_*_*_EDC

**

GDDR_EDC_ISO

GDDR_ISO

**

GDDR_*_*_DBI

* *

GDDR_*_*_CTRL

GDDR_ISO

* *

GDDR_ISO

GDDR_CTRL

GDDR_ISO

GDDR_*_*_MA

**

TOP,BOTTOM

GDDR_DBI2DBI

=3x_DIELECTRIC

?

*

=7x_DIELECTRIC

?

GDDR_EDC2EDC

=SAME

*

GDDR_*_*_EDC GDDR_EDC2EDC

GDDR_*_*_DBI

*

=SAME

GDDR_DBI2DBI

GDDR_*_*_WCK

*

GDDR_WCK2WCK

=SAME

GDDR_ISO

**

GDDR_*_*_WCK

GDDR_B_1_CLK

FB_B1_CLK_N

GDDR_CLK_PHY

GDDR_B1_CLK

GDDR_DBI_PHY GDDR_A_0_DBI

FB_A0_DBI_L<3>

GDDR_A0_DBI3

FB_A0_DBI_L<2>

GDDR_A_0_DBIGDDR_DBI_PHYGDDR_A0_DBI2

GDDR_DBI_PHY GDDR_A_1_DBI

FB_A1_DBI_L<3>

GDDR_A1_DBI3

GDDR_DBI_PHYGDDR_A1_DBI1 GDDR_A_1_DBI

FB_A1_DBI_L<1>

GDDR_DBI_PHYGDDR_A1_DBI0 GDDR_A_1_DBI

FB_A1_DBI_L<0>

GDDR_B_1_DQ

GDDR_B1_DQ_BYTE3

FB_B1_DQ<31..24>

GDDR_DQ_PHY

GDDR_ADBI_PHY

GDDR_B1_ADBI

FB_B1_ABI_L

GDDR_B_1_ADBI

GDDR_ADBI_PHY

FB_B0_ABI_L

GDDR_B_0_ADBI

GDDR_B0_ADBI

GDDR_B0_CKE

GDDR_CTRL_PHY

FB_B0_CKE_L

GDDR_B_0_CTRL

GDDR_CTRL_PHY

FB_B0_WE_L

GDDR_B0_CTRL

GDDR_B_0_CTRL

GDDR_CTRL_PHY

FB_B0_CS_L

GDDR_B0_CTRL

GDDR_B_0_CTRL

GDDR_CTRL_PHY GDDR_B_0_CTRL

GDDR_B0_CTRL

FB_B0_CAS_L

GDDR_B_0_CTRL

FB_B0_RAS_L

GDDR_B0_CTRL

GDDR_CTRL_PHY

GDDR_B1_CKE

GDDR_B_1_CTRL

FB_B1_CKE_L

GDDR_CTRL_PHY

GDDR_B_1_CTRL

GDDR_B1_CTRL

FB_B1_CS_L

GDDR_CTRL_PHY

GDDR_B0_CLK

GDDR_B_0_CLK

FB_B0_CLK_P

GDDR_CLK_PHY

GDDR_B1_EDC0 GDDR_B_1_EDC

FB_B1_EDC<0>

GDDR_EDC_PHY

GDDR_B0_DBI2 GDDR_B_0_DBI

FB_B0_DBI_L<2>

GDDR_DBI_PHY

GDDR_B1_DBI0 GDDR_B_1_DBI

FB_B1_DBI_L<0>

GDDR_DBI_PHY

GDDR_B1_DBI1 GDDR_B_1_DBI

FB_B1_DBI_L<1>

GDDR_DBI_PHY

GDDR_B_0_WCKGDDR_WCK_PHY

FB_B0_WCLK_P<0>

GDDR_B0_WCK0
GDDR_B0_WCK0 GDDR_WCK_PHY GDDR_B_0_WCK

FB_B0_WCLK_N<0>

FB_B1_WCLK_P<1>

GDDR_WCK_PHYGDDR_B1_WCK1 GDDR_B_1_WCK

GDDR_A1_DBI2 GDDR_DBI_PHY GDDR_A_1_DBI

FB_A1_DBI_L<2>

GDDR_WCK_PHYGDDR_A0_WCK0

FB_A0_WCLK_P<0>

GDDR_A_0_WCK

GDDR_A1_EDC3 GDDR_EDC_PHY

FB_A1_EDC<3>

GDDR_A_1_EDC

FB_A1_WCLK_P<0>

GDDR_WCK_PHYGDDR_A1_WCK0 GDDR_A_1_WCK

GDDR_B_1_CTRL

GDDR_B1_CTRL

FB_B1_WE_L

GDDR_CTRL_PHY

GDDR_B1_CTRL

GDDR_B_1_CTRL

FB_B1_RAS_L

GDDR_CTRL_PHY

GDDR_B0_CLK

GDDR_B_0_CLK

FB_B0_CLK_N

GDDR_CLK_PHY

GDDR_B1_CLK

GDDR_B_1_CLK

FB_B1_CLK_P

GDDR_CLK_PHY

GDDR_B0_DQ_BYTE0

GDDR_B_0_DQ

FB_B0_DQ<7..0>

GDDR_DQ_PHY

GDDR_B0_DQ_BYTE2

GDDR_B_0_DQ

FB_B0_DQ<23..16>

GDDR_DQ_PHY

GDDR_DBI_PHYGDDR_B0_DBI0 GDDR_B_0_DBI

FB_B0_DBI_L<0>

GDDR_B1_DBI2 GDDR_B_1_DBI

FB_B1_DBI_L<2>

GDDR_DBI_PHY

GDDR_EDC_PHYGDDR_B1_EDC1 GDDR_B_1_EDC

FB_B1_EDC<1>

GDDR_B0_EDC3 GDDR_B_0_EDC

FB_B0_EDC<3>

GDDR_EDC_PHY

GDDR_B0_EDC2

FB_B0_EDC<2>

GDDR_EDC_PHY GDDR_B_0_EDC

GDDR_B0_EDC0 GDDR_B_0_EDC

FB_B0_EDC<0>

GDDR_EDC_PHY

GDDR_B1_DQ_BYTE1

GDDR_B_1_DQ

FB_B1_DQ<15..8>

GDDR_DQ_PHY

GDDR_B0_DQ_BYTE3

GDDR_B_0_DQ

FB_B0_DQ<31..24>

GDDR_DQ_PHY

GDDR_B_0_DQ

FB_B0_DQ<15..8>

GDDR_DQ_PHY

GDDR_B0_DQ_BYTE1

FB_A1_DQ<31..24>

GDDR_A_1_DQ

GDDR_A1_DQ_BYTE3

GDDR_DQ_PHY

FB_B1_CAS_L

GDDR_B_1_CTRLGDDR_CTRL_PHY

GDDR_B1_CTRL

GDDR_B0_DBI3

FB_B0_DBI_L<3>

GDDR_DBI_PHY GDDR_B_0_DBI

GDDR_B1_EDC2 GDDR_B_1_EDC

FB_B1_EDC<2>

GDDR_EDC_PHY

GDDR_B0_EDC1 GDDR_B_0_EDC

FB_B0_EDC<1>

GDDR_EDC_PHY

GDDR_B1_DQ_BYTE0

GDDR_B_1_DQ

FB_B1_DQ<7..0>

GDDR_DQ_PHY

GDDR_DQ_PHY

GDDR_B1_DQ_BYTE2

GDDR_B_1_DQ

FB_B1_DQ<23..16>

GDDR_B0_DBI1 GDDR_B_0_DBI

FB_B0_DBI_L<1>

GDDR_DBI_PHY

GDDR_B1_MA

GDDR_B_1_MAGDDR_MA_PHY

FB_B1_A<8..0>

GDDR_B_0_MAGDDR_MA_PHY

FB_B0_A<8..0>

GDDR_B0_MA

FB_A1_DQ<23..16>

GDDR_A_1_DQGDDR_DQ_PHY

GDDR_A1_DQ_BYTE2

GDDR_A1_EDC2 GDDR_EDC_PHY

FB_A1_EDC<2>

GDDR_A_1_EDC

GDDR_WCK_PHYGDDR_A0_WCK1 GDDR_A_0_WCK

FB_A0_WCLK_P<1>
FB_A0_WCLK_N<1>

GDDR_A_0_WCKGDDR_WCK_PHYGDDR_A0_WCK1

FB_A0_WCLK_N<0>

GDDR_WCK_PHY GDDR_A_0_WCKGDDR_A0_WCK0

GDDR_WCK_PHY GDDR_B_1_WCK

FB_B1_WCLK_N<0>

GDDR_B1_WCK0

GDDR_A0_CKE

GDDR_CTRL_PHY GDDR_A_0_CTRL

FB_A0_CKE_L

GDDR_CTRL_PHY

GDDR_A0_CTRL

FB_A0_WE_L

GDDR_A_0_CTRL

GDDR_CLK_PHY

FB_A0_CLK_P

GDDR_A0_CLK

GDDR_A_0_CLK

FB_A0_DQ<15..8>

GDDR_A0_DQ_BYTE1

GDDR_DQ_PHY GDDR_A_0_DQ

GDDR_A_0_DQ

FB_A0_DQ<23..16>

GDDR_A0_DQ_BYTE2

GDDR_DQ_PHY

GDDR_A_0_DQ

FB_A0_DQ<7..0>

GDDR_A0_DQ_BYTE0

GDDR_DQ_PHY

FB_A1_CLK_P

GDDR_CLK_PHY GDDR_A_1_CLK

GDDR_A1_CLK

FB_A0_CS_L

GDDR_CTRL_PHY

GDDR_A0_CTRL

GDDR_A_0_CTRL

GDDR_A_0_ADBIGDDR_ADBI_PHY

GDDR_A0_ADBI

FB_A0_ABI_L

GDDR_A_0_MA

FB_A0_A<8..0>

GDDR_A0_MA

GDDR_MA_PHY

GDDR_CTRL_PHY

FB_A1_WE_L

GDDR_A_1_CTRL

GDDR_A1_CTRL

GDDR_A0_DBI0 GDDR_DBI_PHY GDDR_A_0_DBI

FB_A0_DBI_L<0>

GDDR_DBI_PHYGDDR_A0_DBI1 GDDR_A_0_DBI

FB_A0_DBI_L<1>

GDDR_A1_EDC0 GDDR_EDC_PHY

FB_A1_EDC<0>

GDDR_A_1_EDC

GDDR_EDC_PHY

FB_A0_EDC<3>

GDDR_A_0_EDCGDDR_A0_EDC3

FB_A0_EDC<1>

GDDR_EDC_PHY GDDR_A_0_EDCGDDR_A0_EDC1

GDDR_A_0_EDCGDDR_EDC_PHYGDDR_A0_EDC0

FB_A0_EDC<0>

FB_A1_DQ<15..8>

GDDR_DQ_PHY

GDDR_A1_DQ_BYTE1

GDDR_A_1_DQ

FB_A1_DQ<7..0>

GDDR_A1_DQ_BYTE0

GDDR_DQ_PHY GDDR_A_1_DQ

FB_A0_DQ<31..24>

GDDR_DQ_PHY GDDR_A_0_DQ

GDDR_A0_DQ_BYTE3

FB_A1_CLK_N

GDDR_CLK_PHY GDDR_A_1_CLK

GDDR_A1_CLK

FB_A0_CAS_L

GDDR_CTRL_PHY

GDDR_A0_CTRL

GDDR_A_0_CTRL

GDDR_ADBI_PHY

FB_A1_ABI_L

GDDR_A1_ADBI

GDDR_A_1_ADBI

GDDR_A_1_MA

FB_A1_A<8..0>

GDDR_A1_MA

GDDR_MA_PHY

GDDR_A_0_CTRL

FB_A0_RAS_L

GDDR_CTRL_PHY

GDDR_A0_CTRL

FB_A1_CS_L

GDDR_A1_CTRL

GDDR_CTRL_PHY GDDR_A_1_CTRL

FB_A1_CAS_L

GDDR_A_1_CTRLGDDR_CTRL_PHY

GDDR_A1_CTRL

GDDR_CTRL_PHY GDDR_A_1_CTRL

GDDR_A1_CTRL

FB_A1_RAS_L

FB_A0_EDC<2>

GDDR_EDC_PHY GDDR_A_0_EDCGDDR_A0_EDC2

GDDR_A1_EDC1

FB_A1_EDC<1>

GDDR_EDC_PHY GDDR_A_1_EDC

GDDR_B_1_DBIGDDR_B1_DBI3

FB_B1_DBI_L<3>

GDDR_DBI_PHY

GDDR_B_0_WCKGDDR_WCK_PHY

FB_B0_WCLK_P<1>

GDDR_B0_WCK1

GDDR_WCK_PHY GDDR_B_1_WCK

FB_B1_WCLK_P<0>

GDDR_B1_WCK0

FB_B0_WCLK_N<1>

GDDR_WCK_PHY GDDR_B_0_WCKGDDR_B0_WCK1

GDDR_A0_RESET

FB_A0_RESET_L

GDDR_50S

GDDR_CTRL

GDDR_WCK_PHYGDDR_B1_WCK1

FB_B1_WCLK_N<1>

GDDR_B_1_WCK

GDDR_B0_RESET

FB_B0_RESET_L

GDDR_CTRL

GDDR_50S

GDDR_B1_RESET

FB_B1_RESET_L

GDDR_CTRL

GDDR_50S

GDDR_A1_RESET

GDDR_CTRL

FB_A1_RESET_L

GDDR_50S

FB_A1_CKE_L

GDDR_A1_CKE

GDDR_A_1_CTRLGDDR_CTRL_PHY

FB_A0_CLK_N

GDDR_A_0_CLKGDDR_CLK_PHY

GDDR_A0_CLK

FB_A1_WCLK_N<0>

GDDR_A1_WCK0 GDDR_A_1_WCKGDDR_WCK_PHY

GDDR_WCK_PHY

FB_A1_WCLK_P<1>

GDDR_A_1_WCKGDDR_A1_WCK1

GDDR_A1_WCK1

FB_A1_WCLK_N<1>

GDDR_WCK_PHY GDDR_A_1_WCK

GPU_SMB_CLK

SMB_PHY

SMB
SMB

GPU_SMB_DAT

SMB_PHY

GPU_SMB_CLK_R

SMB

SMB_PHY

GDDR_B1_EDC3 GDDR_B_1_EDC

FB_B1_EDC<3>

GDDR_EDC_PHY

GPU_SMB_DAT_R

SMB

SMB_PHY

051-9509

4.2.0

112 OF 113

99 OF 100

73 76

73 75

73 75

73 75

73 75

73 75

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 75

73 75

73 75

73 75

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 75

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 75

73 75

73 75

73 75

73 75

73 76

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 76

73 76

73 76

73 76

73 75

73 76

73 76

73 76

73 75

73 75

73 75

73 75

73 75

73 75

77 78

77 78

47 78

73 76

47 78

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

NO_TEST

BLC High Voltage Output

Physical

Input Bus

Voltage

DIDT

Spacing

Local Ground

BLC-specific Spacing Definitions

Physical Net Type to Rule Map

Is it chel’oh or sel’oh?

Backlight

Output Bus

Physical

Spacing

Cello Miscellaneous

Electrical Contraint Set

SPI

BLC-specific Physical Rules

Backlight Controller

BLC Control

BLC BaddiesBLC Baddies

BLC Control

Constraints
BLC High Voltage Output

I563

I564

I749

I750

I751

I752

I753
I754

I755
I757

I759

I762

I763

I764

I765

I770

I772

I773
I774

I775

I776

I777

I778

I779

I780

I782

I783

I784

I785

I786
I787

I788

I789

I790

I791
I792

I793

I794

I795

I796

I797

I798

I799

I800

I801

* =STANDARD=STANDARD

BLC_P3MM 0.300 MM

3.0 MM

Y

0.100 MM

BLC_P6MM

*

3.0 MM

Y =STANDARD=STANDARD

0.100 MM0.600 MM

SYNC_MASTER=D7_DAVE

SYNC_DATE=12/12/2011

BLC Constraints

*

BLC_HV_ISO

0.45mm

1000

BLC_P3MM

BLC_CTL_PHY

*

BLC_P3MM

POWER_BLC_RET

*

BLC_P6MM

POWER_BLC

*

**

BLC_PHASE PHASE_ISO

PHASE_SW2PWR

POWER

BLC_PHASE

*

BLC_PHASE

GND

*

PHASE_SW2GND

PHASE_SW2SW

BLC_PHASEBLC_PHASE

*

**

BLC_CTL_ISO

BLC_CTL

=8:1_SPACING

*

2000

PHASE_ISO

PHASE_SW2SW

*

?

=1:1_SPACING

PHASE_SW2GND =2:1_SPACING

*

?

PHASE_SW2PWR =2:1_SPACING

*

?

*

=3:1_SPACING

?

BLC_CTL_ISO

*

BLC_HV

BLC_HV_ISO

*

*

BLC_HV

BLC_CTL_ISO

BLC_HV

*

BLC_HV

BLC_CTL

BLC_CTL_ISO

BKLT_SW_P

SNS_DIFF_PHY

SENSE

SNS_DIFF_PHY

SENSE

BKLT_SW_N

SENSE

BKLT_FB

BLC_HV

BKLT_FB_XW

67V

POWER_BLC_RET

BLC_CTL

BKLT_ISEN1

POWER_BLC_RET

BLC_CTL

BKLT_ISEN2

POWER_BLC_RET

BLC_CTL

BKLT_ISEN3

POWER_BLC_RET

BLC_CTL

BKLT_ISEN4

BLC_HV

BKLT_FB_R

67V

BLC_CTL

BLC_CTL_PHY

BKLT_FLT

BLC_CTL

BLC_CTL_PHY

BKLT_FLT_RC

0V

BLC_CTL_PHY

BLC_PHASE

LGND_BKLT

80V

TRUE

BKLT_PHASE

POWER_BLC BLC_PHASE

BKLT_ISEN6

POWER_BLC_RET

BLC_CTL

POWER_BLC_RET

BLC_CTL

BKLT_ISEN5

BKLT_ISEN1_R

POWER_BLC_RET

BLC_HV

BKLT_ISEN2_R

POWER_BLC_RET

BLC_HV

POWER_BLC_RET

BKLT_ISEN3_R

BLC_HV

0V

BLC_CTL_PHY

BLC_PHASE

PGND_BKLT

PP12V_S0_BKLT_PWR

POWER POWER

12V

PP12V_S0_BKLT_PWR_R

12V

POWER POWER

SMB

SMB_PHY

BKLT_SDA

BKLT_SCL

SMB

SMB_PHY

POWER_BLC

BKLT_BOOST_2

67VBLC_HV

POWER_BLC

BKLT_BOOST

BLC_HV 67V

POWER_BLC

BKLT_BOOST_1

67VBLC_HV

LED_RETURN_6

POWER_BLC_RET

BLC_HV

POWER_BLC_RET

LED_RETURN_5

BLC_HV

LED_RETURN_3

POWER_BLC_RET

BLC_HV

LED_RETURN_4

POWER_BLC_RET

BLC_HV

LED_RETURN_2

POWER_BLC_RET

BLC_HV

POWER_BLC_RET

LED_RETURN_1

BLC_HV

POWER_BLC_RET

BKLT_ISEN5_R

BLC_HV

BKLT_ISEN6_R

POWER_BLC_RET

BLC_HV

BKLT_ISEN4_R

POWER_BLC_RET

BLC_HV

BLC_CTL

BLC_CTL_PHY

BKLT_ISET

80VBLC_PHASE

BLC_CTL_PHY

TRUETRUE

BKLT_SNUBBER

12V

TRUE

BLC_PHASE

BLC_CTL_PHY

BKLT_SW_R

80V

BLC_CTL_PHY

TRUE

BLC_PHASE

BKLT_GATE_R

BKLT_GATE

TRUE

BLC_PHASE 80V

BLC_CTL_PHY

12V

PP12V_S0_BKLT_FUSED

POWER POWER

0V

BLC_CTL_PHY

BLC_PHASE

DGND_BKLT

3.3V

PP3V3_S0_BKLT_VDDIO_R

POWER POWER

POWER

12V

PP12V_S0_BKLT_FILT

POWER

5V

PP5V_S0_BKLT_R

POWER POWER

051-9509

4.2.0

113 OF 113
100 OF 100

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86

86