MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7630 group is a single chip 8-bit microcomputer designed with CMOS silicon gate technology.
Being equipped with a CAN (Controller Area Network) module circuit, the microcomputer is suited to drive automotive equipments. The CAN module complies with CAN specification version 2.0, part B and allows priority-based message management.
In addition to the microcomputers simple instruction set, the ROM, RAM and I/O addresses are placed in the same memory map to enable easy programming.
The built-in ROM is available as mask ROM or One Time PROM. For development purposes, emulatorand EPROM-type microcomputers are available as well.
FEATURES
z Basic machine-language instructions . . . . . . . . . . . . . . . . . . 71
zMinimum instruction execution time
(at 10 MHz oscillation frequency) . . . . . . . . . . . . . . . . . . 0.2 μs
zMemory size
ROM . . . . . . . . . . . . . . . . .16252 bytes (M37630M4T-XXXFP) RAM . . . . . . . . . . . . . . . . . . .512 bytes (M37630M4T-XXXFP)
zI/O ports
Programmable I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
z Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 24 sources, 24 vectors
zTimers
16-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels 8-bit Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels
zSerial I/Os
Clock synchronous. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 channel
zCAN module
(CAN specification version 2.0, part B) . . . . . . . . . . . 1 channel z A-D converter . . . . . . . . . . . . . . . . . . . . . . . . 8-bits x 8 channels z Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 z Clock Generating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Built-in with internal feedback resistor
zPower source voltage
(at 10 MHz oscillation frequency). . . . . . . . . . . . . . . 4.0 to 5.5 V
zPower dissipation
In high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 mW (at 8 MHz oscillation frequency, at 5 V power source voltage)
z Operating temperature range. . . . . . . . . . . . . . . . . –40 to 85 °C z Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44QFP (44P6N-A)
APPLICATION
Automotive controls
PIN CONFIGURATION (TOP VIEW)
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/PWM |
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0 |
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/TX |
/INT |
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/INT |
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/AN |
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/AN |
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/AN |
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/AN |
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/AN |
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/CNTR |
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/CNTR |
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P1 |
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P1 |
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P1 |
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P1 |
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P1 |
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P0 |
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P0 |
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P0 |
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P0 |
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P0 |
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33 |
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P17 |
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P02/AN2 |
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34 |
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22 |
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P20/SIN |
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P01/AN1 |
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21 |
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P21/SOUT |
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P00/AN0 |
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36 |
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20 |
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P22/SCLK |
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VREF |
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M37630M4T-XXXFP |
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AVSS |
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P23/SRDY |
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VSS |
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VCC |
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M37630E4T-XXXFP |
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17 |
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XOUT |
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P24/URXD |
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40 |
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16 |
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P25/UTXD |
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XIN |
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15 |
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P26 |
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VSS |
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/URTS |
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42 |
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14 |
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P27/UCTS |
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43 |
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13 |
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RESET |
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P30 |
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P47/KW7 |
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44 |
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12 |
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/CTX |
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/CRX |
3 |
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0 |
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P3 |
P3 |
/KW |
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/KW |
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/KW |
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/KW |
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/KW |
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/KW |
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/KW |
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1 |
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0 |
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P3 |
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P3 |
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P4 |
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P4 |
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P4 |
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P4 |
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P4 |
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P4 |
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P4 |
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Package type: 44P6N-A 44-pin plastic molded QFP
Fig. 1 Pin configuration of M37630M4T–XXXFP
MITSUBISHI |
1 |
ELECTRIC |
2 |
Fig |
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2 . |
M37630MXT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE: 44P6N-A) |
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blockFunctional |
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Clock |
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Clock |
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Reset |
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output |
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input |
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input |
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VCC |
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VSS |
AVSS |
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XOUT |
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XIN |
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RESET |
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16 |
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15 |
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13 |
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17 |
14 |
39 |
18 |
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diagram |
Clock generating circuit |
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CPU |
A (8) |
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ROM |
RAM |
WDT |
Timer X (16) |
Timer 1 (8) |
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X (8) |
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2 |
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Y (8) |
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Timer Y (16) |
Timer 2 (8) |
PWM |
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S (8) |
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Timer 3 (8) |
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PCH (8) |
PCL (8) |
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PS (8) |
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MITSUBISHI ELECTRIC |
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key on |
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CAN |
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UART |
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Serial I/O |
A-D Converter |
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wake up |
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2 |
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4 |
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4 |
INT0, INT1 |
8 |
MICROCOMPUTERCMOSBIT-8CHIP-SINGLE |
Group7630 |
MICROCOMPUTERSMITSUBISHI |
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2 |
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P4 (8) |
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P3 (5) |
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P2 (8) |
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P1 (7) |
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P0 (8) |
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12 11 10 |
9 |
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2 |
1 |
44 |
43 42 41 40 38 37 36 35 |
34 33 32 31 30 29 28 |
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27 26 25 24 23 22 21 20 |
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VREF input |
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I/O port P4 |
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I/O port P3 |
I/O port P2 |
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I/O port P1 |
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I/O port P0 |
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MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1: Pin description
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Pin |
Name |
Input/Output |
Description |
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VCC, VSS |
Power source |
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Power supply pins; apply 4.0 to 5.5 V to VCC and 0 V to VSS |
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voltage |
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AVSS |
Analog power |
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Ground pin for A-D converter. Connect to VSS |
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source voltage |
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Reset pin. This pin must be kept at “L” level for more than 2 μs, to enter the reset |
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Reset input |
Input |
state. If the crystal or ceramic resonator requires more time to stabilize, extend the |
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RESET |
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“L” level period. |
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XIN |
Clock input |
Input |
Input and output pins of the internal clock generating circuit. Connect a ceramic or |
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quartz–crystal resonator between the XIN and XOUT pins. When an external clock |
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XOUT |
Clock output |
Output |
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source is used, connect it to XIN and leave XOUT open. |
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VREF |
Reference volt- |
Input |
Reference voltage input pin for A-D converter |
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age input |
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P00/AN0— |
I/O port P0 |
I/O |
CMOS I/O ports or analog input ports |
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P07/AN7 |
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CMOS input port or external interrupt input port. The active edge (rising or falling) of |
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P11/INT0 |
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Input |
external interrupts can be selected. This pin will be used as VPP pin during PROM |
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programming of One Time PROM Versions. |
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P12/INT1 |
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CMOS I/O port or external interrupt input port. The active edge (rising or falling) of |
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external interrupts can be selected. |
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P13/TX0 |
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CMOS I/O port or input pin used in the bi-phase counter mode |
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P14/CNTR0 |
I/O port P1 |
I/O |
CMOS I/O port or timer X input pin used for the event counter, pulse width measure- |
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ment and bi-phase counter mode |
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P15/CNTR1 |
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CMOS I/O port or timer Y input pin used for the event counter, pulse width and pulse |
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period measurement mode |
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P16/PWM |
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CMOS I/O port or PWM output pin used in the PWM mode of timers 2 and 3 |
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P17 |
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CMOS I/O port |
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P20/SIN |
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P21/SOUT |
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CMOS I/O ports or clock synchronous serial I/O pins |
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P22/SCLK |
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P23/SRDY |
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I/O |
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I/O port P2 |
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P24/URXD |
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P25/UTXD |
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CMOS I/O ports or asynchronous serial I/O pins |
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P26/URTS |
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P27/UCTS |
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P30 |
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CMOS I/O port |
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P31/CTX |
I/O port P3 |
I/O |
CMOS I/O port or CAN transmit data pin |
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P32/CRX |
CMOS I/O port or CAN receive data pin |
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P33—P3 4 |
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CMOS I/O port |
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P40/KW0— |
I/O port P4 |
I/O |
CMOS I/O ports. These ports can be used for key-on wake-up when configured as |
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P47/KW7 |
inputs. |
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MITSUBISHI |
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ELECTRIC |
3 |
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product |
M37630 M 4 T– XXX FP |
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Package type
FP: 44P6N-A package
FS: 80D0 package
ROM number
Omitted in One Time PROM version (blank) and EPROM version
T: Automotive use
ROM/PROM size 4: 16384 bytes
The first 128 bytes and the last 4 bytes of ROM are reserved areas.
They cannot be used.
Memory type
M: Mask ROM version
E: EPROM or One Time PROM version
Fig. 3 Part numbering
4 |
MITSUBISHI |
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ELECTRIC |
||
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MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7630 group as follows: |
Memory Size |
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ROM/PROM size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes |
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Memory Type |
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RAM size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 bytes |
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Package |
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Support mask ROM, One Time PROM and EPROM versions. |
44P6N-A |
. . . . . . . . . . . . . . . . .0.8mm-pitch plastic molded QFP |
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80D0 . . . . . . . . . . .0.8mm-pitch ceramic LCC (EPROM version) |
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ROM |
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External |
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60K |
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48K |
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32K |
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28K |
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24K |
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20K |
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Under development |
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M37630M4T |
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16K |
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M37630E4T |
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12K |
Mass product |
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8K |
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384 |
512 |
640 |
768 |
896 |
1024 |
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RAM size (bytes) |
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Fig. 4 Memory expansion plan
Currently supported products are listed below:
Table 2: List of supported products |
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As of March 1998 |
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Product |
(P)ROM size (bytes) |
RAM size (bytes) |
Package |
Remarks |
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ROM size for User ( ) |
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M37630M4T-XXXFP |
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Mask ROM version |
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M37630E4T-XXXFP |
16384 |
512 |
44P6N-A |
One Time PROM version |
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M37630E4FP |
(16252) |
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One Time PROM version (blank) |
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M37630E4FS |
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80D0 |
EPROM version |
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MITSUBISHI |
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ELECTRIC |
5 |
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The core of 7630 group microcomputers is the 7600 series CPU. This core is based on the standard instruction set of 740 series; however the performance is improved by allowing to execute the same instructions as that of the 740 series in less cycles. Refer to the 7600 Series Software Manual for details of the instruction set.
CPU Mode Register CPUM
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated to address 000016.
7 |
0 |
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CPU mode register (address 000016) |
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CPUM |
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Processor mode bits (set these bits to “00”) |
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b1 b0 |
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0 |
0: |
Single–chip mode |
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0 |
1: |
Not used |
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1 |
0: |
Not used |
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1 |
1: |
Not used |
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Stack page selection bit |
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0 |
: |
0 page |
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1 |
: |
1 page |
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Not used (“0” when read, do not write “1”) |
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Internal system clock selection bit |
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0 |
: |
φ=f(XIN) divided by 2 (high–speed mode) |
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1 |
: |
φ=f(XIN) divided by 8 (middle–speed mode) |
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Not used (“0” when read, do not write “1”) |
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Fig. 5 |
Structure of CPU mode register |
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6 |
MITSUBISHI |
|
ELECTRIC |
||
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MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area |
Interrupt Vector Area |
The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers.
The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Zero Page
This area can be accessed most efficiently by means of the zero page addressing mode.
ROM
ROM is used for storing user’s program code as well as the interrupt vector area.
Special Page
This area can be accessed most efficiently by means of the special page addressing mode.
RAM area |
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RAM size |
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Address |
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000016 |
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(byte) |
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XXXX16 |
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192 |
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011F16 |
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004016 |
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256 |
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015F16 |
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384 |
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01DF16 |
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006016 |
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00FF16 |
512 |
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025F16 |
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640 |
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02DF16 |
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User RAM |
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768 |
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035F16 |
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896 |
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03DF16 |
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XXXX16 |
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1024 |
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045F16 |
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1536 |
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06DF16 |
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086016 |
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2048 |
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085F16 |
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ROM area |
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ROM size |
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Address |
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Address |
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(byte) |
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YYYY16 |
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ZZZZ16 |
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4096 |
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F00016 |
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F08016 |
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YYYY16 |
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8192 |
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E00016 |
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E08016 |
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ZZZZ16 |
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12288 |
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D00016 |
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D08016 |
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16384 |
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C00016 |
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C08016 |
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20480 |
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B00016 |
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B08016 |
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24576 |
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A00016 |
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A08016 |
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ROM |
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28672 |
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900016 |
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908016 |
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FF0016 |
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32768 |
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800016 |
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808016 |
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36864 |
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700016 |
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708016 |
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FFCA16 |
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40960 |
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600016 |
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608016 |
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FFFB16 |
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45056 |
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500016 |
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508016 |
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FFFC16 |
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FFFF16 |
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49152 |
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400016 |
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408016 |
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53248 |
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300016 |
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308016 |
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57344 |
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200016 |
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208016 |
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61440 |
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100016 |
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108016 |
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SFR area
Not used
Reserved ROM area
Interrupt vector area
Reserved ROM area
CAN |
Zero page |
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SFRs |
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Special page
Fig. 6 Memory map diagram
MITSUBISHI |
|
ELECTRIC |
7 |
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SPECIAL FUNCTION REGISTERS (SFR)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
CPU mode register |
CPUM |
003016 |
Not used |
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003116 |
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003216 |
Interrupt request register A |
IREQA |
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003316 |
Interrupt request register B |
IREQB |
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003416 |
Interrupt request register C |
IREQC |
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Interrupt control register A |
ICONA |
003516 |
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003616 |
Interrupt control register B |
ICONB |
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003716 |
Interrupt control register C |
ICONC |
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003816 |
Port P0 register |
P0 |
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003916 |
Port P0 direction register |
P0D |
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003A16 |
Port P1 register |
P1 |
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003B16 |
Port P1 direction register |
P1D |
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Port P2 register |
P2 |
003C16 |
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003D16 |
Port P2 direction register |
P2D |
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003E16 |
Port P3 register |
P3 |
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003F16 |
Port P3 direction register |
P3D |
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004016 |
Port P4 register |
P4 |
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004116 |
Port P4 direction register |
P4D |
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004216 |
Serial I/O shift register |
SIO |
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004316 |
Serial I/O control register |
SIOCON |
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A-D conversion register |
AD |
004416 |
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004516 |
A-D control register |
ADCON |
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004616 |
Timer 1 |
T1 |
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004716 |
Timer 2 |
T2 |
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004816 |
Timer 3 |
T3 |
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004916 |
Timer 123 mode register |
T123M |
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004A16 |
Timer XL |
TXL |
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Timer XH |
TXH |
004B16 |
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004C16 |
Timer YL |
TYL |
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004D16 |
Timer YH |
TYH |
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004E16 |
Timer X mode register |
TXM |
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004F16 |
Timer Y mode register |
TYM |
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005016 |
UART mode register |
UMOD |
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005116 |
UART baud rate generator |
UBRG |
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005216 |
UART control register |
UCON |
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UART status register |
USTS |
005316 |
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005416 |
UART transmit buffer register 1 |
UTBR1 |
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005516 |
UART transmit buffer register 2 |
UTBR2 |
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005616 |
UART receive buffer register 1 |
URBR1 |
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005716 |
UART receive buffer register 2 |
URBR2 |
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005816 |
Port P0 pull-up control register |
PUP0 |
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005916 |
Port P1 pull-up control register |
PUP1 |
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Port P2 pull-up control register |
PUP2 |
005A16 |
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005B16 |
Port P3 pull-up control register |
PUP3 |
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005C16 |
Port P4 pull-up/down control register |
PUP4 |
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005D16 |
Interrupt polarity selection register |
IPOL |
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005E16 |
Watchdog timer register |
WDT |
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005F16 |
Polarity control register |
PCON |
CAN transmit control register |
CTRM |
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CAN bus timing control register 1 |
CBTCON1 |
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CAN bus timing control register 2 |
CBTCON2 |
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CAN acceptance code register 0 |
CAC0 |
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CAN acceptance code register 1 |
CAC1 |
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CAN acceptance code register 2 |
CAC2 |
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CAN acceptance code register 3 |
CAC3 |
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CAN acceptance code register 4 |
CAC4 |
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CAN acceptance mask register 0 |
CAM0 |
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CAN acceptance mask register 1 |
CAM1 |
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CAN acceptance mask register 2 |
CAM2 |
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CAN acceptance mask register 3 |
CAM3 |
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CAN acceptance mask register 4 |
CAM4 |
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CAN receive control register |
CREC |
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CAN transmit abort register |
CABORT |
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Reserved |
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CAN transmit buffer register 0 |
CTB0 |
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CAN transmit buffer register 1 |
CTB1 |
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CAN transmit buffer register 2 |
CTB2 |
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CAN transmit buffer register 3 |
CTB3 |
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CAN transmit buffer register 4 |
CTB4 |
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CAN transmit buffer register 5 |
CTB5 |
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CAN transmit buffer register 6 |
CTB6 |
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CAN transmit buffer register 7 |
CTB7 |
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CAN transmit buffer register 8 |
CTB8 |
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CAN transmit buffer register 9 |
CTB9 |
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CAN transmit buffer register A |
CTBA |
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CAN transmit buffer register B |
CTBB |
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CAN transmit buffer register C |
CTBC |
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CAN transmit buffer register D |
CTBD |
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Reserved |
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Reserved |
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CAN receive buffer register 0 |
CRB0 |
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CAN receive buffer register 1 |
CRB1 |
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CAN receive buffer register 2 |
CRB2 |
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CAN receive buffer register 3 |
CRB3 |
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CAN receive buffer register 4 |
CRB4 |
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CAN receive buffer register 5 |
CRB5 |
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CAN receive buffer register 6 |
CRB6 |
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CAN receive buffer register 7 |
CRB7 |
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CAN receive buffer register 8 |
CRB8 |
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CAN receive buffer register 9 |
CRB9 |
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CAN receive buffer register A |
CRBA |
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CAN receive buffer register B |
CRBB |
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CAN receive buffer register C |
CRBC |
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CAN receive buffer register D |
CRBD |
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Reserved |
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Reserved |
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Fig. 7 Memory map of special register (SFR)
8 |
MITSUBISHI |
|
ELECTRIC |
||
|
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The 7630 group has 35 programmable I/O pins and one input pin arranged in five I/O ports (ports P0 to P4). The I/O ports are controlled by the corresponding port registers and port direction registers; each I/O pin can be controlled separately.
When data is read from a port configured as an output port, the port latch’s contents are read instead of the port level. A port configured
as an input port becomes floating and its level can be read. Data written to this port will affect the port latch only; the port remains floating.
Refer to Structure of portand port direction registers, Structure of port I/Os (1) and Structure of port I/Os (2).
7 |
0 |
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Port Pi register (i = 0 to 4) (address 000816 + 2 · i) |
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Pi |
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Port Pij control bit (j = 0 to 7) |
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0 : |
“L” level |
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1 : |
“H” level |
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Note : The control bits corresponding to P10, P35, P36 and P37 are not used |
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(“0” when read, do not write “1”). |
7 |
0 |
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Port Pi direction register (i = 0 to 4) (address 000916 + 2 · i) |
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PiD |
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Port Pij direction control bit (j = 0 to 7) |
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0 : Port configured as input |
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1 : Port configured as output |
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Note : The direction control bits corresponding to P10, P11, P35, P36 and |
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P37 are not used (“0” when read, do not write “1”). Port direction re- |
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gisters are undefined when read (write only). |
Fig. 8 Structure of portand port direction registers
MITSUBISHI |
|
ELECTRIC |
9 |
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P00/AN0 to P07/AN7 |
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(4) Port P13/TX0 |
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Analog input selection |
Pull-up control bit |
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Pull-up control bit |
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Direction |
direction |
register |
register |
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Data bus |
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Port latch |
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Data bus |
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Port latch |
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ADC input |
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Timer bi-phase mode input |
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Analog input selection |
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(5) Ports P14/CNTR0, P15/CNTR1 |
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Pull-up control bit |
(2) Port P11/INT0 |
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Direction |
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register |
Interrupt input |
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Data bus |
Data bus |
Port latch |
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(3) Port P12/INT1 |
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Pull-up control bit |
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Direction |
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register |
Data bus |
Port latch |
Interrupt input
Timer bi-phase mode input
(6) Port P16/PWM
Pull-up control bit
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PWM output enable |
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Direction |
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register |
Data bus |
Port latch |
PWM output
Fig. 9 Structure of port I/Os (1)
10 |
MITSUBISHI |
|
ELECTRIC |
||
|
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7) Ports P17, P30, P33, P34 |
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Pull-up control bit |
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Direction |
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register |
Data bus |
Port latch |
(8) Port P20/SIN |
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Pull-up control bit |
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SIO Port Select |
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Direction |
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register |
Data bus |
Port latch |
SIO1 input |
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(9) Port P21/SOUT
Pull-up control bit
SIO port selection bit |
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Transmit complete signal |
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Direction |
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register |
Data bus |
Port latch |
SIO output
(10) Port P22/SCLK
Pull-up control bit
Clock selection bit |
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Port selection bit |
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direction |
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register |
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Data bus |
Port latch |
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SIO clock output |
External clock input |
(11) Port P23/SRDY
Pull-up control bit
SRDY output selection bit |
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Direction |
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register |
Data bus |
Port latch |
SRDY output
(12) Ports P24/URXD, P27/UCTS |
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Transmission or reception* in |
Pull-up control bit |
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progress |
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Transmit or receive* enable bit |
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Direction |
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register |
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Data bus |
Port latch |
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URXD or UCTS input |
(13) Ports P25/UTXD, P26/URTS
Transmission or reception** in |
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Pull-up control bit |
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progress |
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Transmit or receive** enable bit |
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Direction |
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register |
Data bus |
Port latch |
UTXD or URTS output |
(*) for UCTS
(**)for URTS
(14)Port P31/CTX
Pull-up control bit
CAN port selection bit |
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Direction |
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register |
Data bus |
Port latch |
CTX output
(15) Port P32/CRX |
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CAN dominant level control bit |
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Pull-up/down control bit |
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Direction |
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register |
Data bus |
Port latch |
CAN interrupt |
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CRX input |
(16) Ports P40/KW0 to P47/KW7 |
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Key-on wake-up control bit |
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Pull-up/down control bit |
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Direction |
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register |
Data bus |
Port latch |
Key-on wake-up interrupt |
Fig. 10 Structure of port I/Os (2)
MITSUBISHI |
|
ELECTRIC |
11 |
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port Pull-up/pull-down Function
Each pin of ports P0 to P4 except P11 is equipped with a programmable pull-up transistor. P32/CRX and P40/KW0 to P47/KW7 are equipped with programmable pull-down transistors as well. The pull-up function of P0 to P3 can be controlled by the corresponding
port pull-up control registers (see Structure of port pull-up/down control registers). The pull-up/down function of ports P32 and P4 can be controlled by the corresponding port pull-up/pull-down registers together with the polarity control register (see Structure of polarity control register).
7 |
0 |
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Port Pi pull-up control register (address 002816 + i) (i = 0, 2) |
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PUP0, PUP2 |
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Pij pull-up transistor control bit (j = 0 to 7) |
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0 : Pull-up transistor disabled |
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1 : Pull-up transistor enabled |
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7 |
0 |
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Port P1 pull-up control register (address 002916) |
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PUP1 |
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Not used (“0” when read, do not write “1”) |
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P1j pull-up transistor control bit (j = 2 to 7) |
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7 |
0 |
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Port P3 pull-up control register (address 002B16) |
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PUP3 |
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P3j pull-up transistor control bit (j = 0, 1) |
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P32 pull-up/down transistor control bit |
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P3j pull-up transistor control bit (j = 3, 4) |
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Not used (“0” when read, do not write “1”) |
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7 |
0 |
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Port P4 pull-up/down control register (address 002C16) |
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PUP4 |
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P4j pull-up/down transistor control bit (j = 0 to 7) |
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0 : |
Pull-up/down transistor disabled |
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Pull-up/down transistor enabled |
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Fig. 11 Structure of port pull-up/down control registers |
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Polarity control register (address 002F16)
PCON
Key-on wake-up polarity control bit 0 : Low level active
1 : High level active
CAN module dominant level control bit 0 : Low level dominant
1 : High level dominant
Not used (undefined when read)
Fig. 12 Structure of polarity control register
12 |
MITSUBISHI |
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ELECTRIC |
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MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port Overvoltage Application
When configured as input ports, P1 to P4 may be subjected to overvoltage (VI > VCC) if the input current to the applicable port is limited to the specified values (see “Table 8:”). Use a serial resistor of appropriate size to limit the input current. To estimate the resistor value, assume the port voltage to be VCC at overvoltage condition.
Notes:
•Subjecting ports to overvoltage may effect the supply voltage. Assure to keep VCC and VSS within the target limits.
•Avoid to subject ports to overvoltage causing VCC to rise above
5.5V.
•The overvoltage condition causing input current flowing through the internal port protection circuits has a negative effect on the ports noise immunity. Therefore, careful and intense testing of the target system’s noise immunity is required. Refer to the “countermeasures against noise” of the corresponding users manual.
•Port P0 must not be subjected to overvoltage conditions.
MITSUBISHI |
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ELECTRIC |
13 |
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
There are 24 interrupts: 6 external, 17 internal, and 1 software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs when the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be cleared or set by software. Interrupt request bits can be cleared by software but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupt requests occur at the same time, the interrupt with the highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt, the following operations are automatically performed.
1.The processing being executed is stopped.
2.The contents of the program counter and processor status register are automatically pushed onto the stack.
3.Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program counter.
4.The interrupt disable flag is set and the corresponding interrupt request bit is cleared.
Notes on use
When the active edge of an external interrupt (INT0, INT1, CNTR0, CNTR1, CWKU or KOI) is changed, the corresponding interrupt request bit may also be set. Therefore, take the following sequence.
(1)Disable the external interrupt which is selected.
(2)Change the active edge in interrupt edge selection register.
(in the case of CNTR0: Timer X mode register; in the case of CNTR1: Timer Y mode register)
(3)Clear the interrupt request bit to “0”.
(4)Enable the external interrupt which is selected.
14 |
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ELECTRIC |
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MITSUBISHI MICROCOMPUTERS |
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7630 Group |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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Table 3: Interrupt vector addresses and priority |
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Vector Address (Note 1) |
Interrupt Request Generating |
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Interrupt source |
Priority |
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Remarks |
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High |
Low |
Conditions |
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Reset (Note 2) |
1 |
FFFB16 |
FFFA16 |
At Reset |
Non-maskable |
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Watchdog timer |
2 |
FFF916 |
FFF816 |
At Watchdog timer underflow |
Non-maskable |
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INT0 |
3 |
FFF716 |
FFF616 |
At detection of either rising or falling |
External Interrupt |
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edge of INT0 interrupt |
(active edge selectable) |
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INT1 |
4 |
FFF516 |
FFF416 |
At detection of either rising or falling |
External Interrupt |
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edge of INT1 interrupt |
(active edge selectable) |
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CAN successful |
5 |
FFF316 |
FFF216 |
At CAN module successful |
Valid when CAN module is |
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transmit |
transmission of message |
activated and request transmit |
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CAN successful |
6 |
FFF116 |
FFF016 |
At CAN module successful reception |
Valid when CAN module is |
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receive |
of message |
activated |
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CAN overrun |
7 |
FFEF16 |
FFEE16 |
If CAN module receives message |
Valid when CAN module is |
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when receive buffers are full. |
activated |
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CAN error |
8 |
FFED16 |
FFEC16 |
When CAN module enters into error |
Valid when CAN module is |
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passive |
passive state |
active |
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CAN error bus off |
9 |
FFEB16 |
FFEA16 |
When CAN module enters into bus |
Valid when CAN module is |
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off state |
active |
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CAN wake up |
10 |
FFE916 |
FFE816 |
When CAN module wakes up via |
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Timer X |
11 |
FFE716 |
FFE616 |
At Timer X underflow or overflow |
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Timer Y |
12 |
FFE516 |
FFE416 |
At Timer Y underflow |
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Timer 1 |
13 |
FFE316 |
FFE216 |
At Timer 1 underflow |
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Timer 2 |
14 |
FFE116 |
FFE016 |
At Timer 2 underflow |
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Timer 3 |
15 |
FFDF16 |
FFDE16 |
At Timer 3 underflow |
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CNTR0 |
16 |
FFDD16 |
FFDC16 |
At detection of either rising or falling |
External Interrupt |
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edge in CNTR0 input |
(active edge selectable) |
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CNTR1 |
17 |
FFDB16 |
FFDA16 |
At detection of either rising or falling |
External Interrupt |
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edge in CNTR1 input |
(active edge selectable) |
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UART receive |
18 |
FFD916 |
FFD816 |
At completion of UART receive |
Valid when UART is selected |
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UART transmit |
19 |
FFD716 |
FFD616 |
At completion of UART transmit |
Valid when UART is selected |
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UART transmit |
20 |
FFD516 |
FFD416 |
At UART transmit buffer empty |
Valid when UART is selected |
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UART receive |
21 |
FFD316 |
FFD216 |
When UART reception error occurs. |
Valid when UART is selected |
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error |
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Serial I/O |
22 |
FFD116 |
FFD016 |
At completion of serial I/O data |
Valid when serial I/O is |
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selected |
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A-D conversion |
23 |
FFCF16 |
FFCE16 |
At completion of A-D conversion |
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Key-on wake-up |
24 |
FFCD16 |
FFCC16 |
At detection of either rising or falling |
External Interrupt |
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edge of P4 input |
(active edge selectable) |
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BRK instruction |
25 |
FFCB16 |
FFCA16 |
At BRK instruction execution |
Non-maskable |
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Notes 1: Vector addresses contain interrupt jump destination address |
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2: Reset function in the same way as an interrupt with the highest priority |
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MITSUBISHI |
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ELECTRIC |
15 |