Intel mcs-48 User Manual

MCS-48™ FAMILY OF SINGLE CHIP MICROCOMPUTERS USER'SMANUAL

September 1980

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel'ssoftware license, or as defined in ASPR 7·104.9(a) (9). Intel Cor· poration assumes no responsibility for the use of any circuitry other than circuitry embodied. in an Intel product. No other circuit patent licenses are implied.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation.

The following are trademarks of Intel Corporation and may only be used to identify Intel products:

BXP	Intelevision	MULTIBUS*
CREDIT	Intellec	MULTIMODULE
i	iSBC	PROMPT
ICE	iSBX	Promware
ICS	Library Manager	RMX
im	MCS	UPI
Insite	Megachassis	flScope
Intel	Micromap

and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix.

MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk Data Sciences Corporation.

*MULTIBUS is a patented Intel bus.

Additional copies of this manual or other Intel literature may be obtained from:

Literature Department

Intel Corporation

3065 Bowers Avenue

Santa Clara, CA 95051

© INTEL CORPORATION, 1980

AFN·01300A-1

	Table of Contents
CHAPTER 1
Introduction
1.0 Introduction to MCS-48™ ...................................................................			1-1
1.1 The Functions of a Computer	...............................................................		1-5
1.2 Programming a Microcomputer ............................................................			1-10
1.3 Developing an MCS-48™ Based Product ....................................................			1-13
CHAPTER 2
The Single Component MCS-48™	System
8048/8748/8035 and 8049/8039
2.0 Summary ....................................................	'............................		2-1
2.1 Architecture .............................................................................			2-1
2.2 Pin Description .........................................................................			2-14
2.3 Programming, Verifying and Erasing EPROM ..............................................			2-16
2.4 Test and Debug .........................................................................			2-18
8021
2.5 Program Memory. . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ..	2-20
2.6 Data Memory ...........................................................................			2-20
2.7 Oscillator and Clock .....................................................................			2-21
2.8 Timer/Event Counter ....................................................................			2-21
2.9 Input/Output Capabilities ................................................................			2-22
2.10 CPU ...................................................................................			2-24
2.11 Reset. . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ..	2-24
8022
2.12 Program Memory ......................................................................			2-25
2.13 Data Memory ..........................................................................			2-25
2.14 Oscillator and Clock ....................................................................			2-26
2.15 Timer/Event Counter ...................................................................			2-26
2.16 Input/Output ...........................................................................			2-26
2.17 Test and Interrupt Inputs ................................................................			2-27
2.18 Analog to Digital Converter	.................................................	; ...........	2-28
2.19 CPU ...................................................................................			2-29
2.208022 Testing ..............................................	'.............................		2-29
CHAPTER 3
The Expanded MCS-48™ System
3.0 Summary ..................................................................................			3-1
3.1 Expansion of Program Memory ..............................................................			3-1
3.2 Expansion of Data Memory. . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . ..	3-4
3.3 Expansion of Input/Output ..................................................................			3-5
3.4 Multi-Chip MCS-48™ Systems ...............................................................			3-9
3.5 Bank Switching ...........................................................................			3-10
3.6 Control Signal Summary ...................................................................			3-11
3.7 Port Characteristics .......................................................................			3-11
CHAPTER 4
Instruction Set
4.0 Introduction ...............................................................................			4-1
4.1 Instruction Set Description .......................	." ..........................................		4-4
CHAPTER 5
Application Examples
5.0 Introduction ...............................................................................			5-1
5.1 Hardware Examples ........................................................................			5-1
5.2 Software Examples ................................................	'.............	: . . . . . . . . ..	5-22

iii

CHAPTER 6

MCS-48™ Component Specifications
8048H/8048H-1/8035HU8035HL-1 HMOS Single Component 8-Bit Microcomputer ..................	6-1
8048L Special Low Power Comsumption Single Component 8-Bit Microcomputer ..................	6-8
8048/8035U8748/8748-6/8035 Single Component 8-Bit Microcomputer .............................	6-9
108048/8748/8035L Industrial Temperature Range Single Component 8-Bit Microcomputer .........	6-18
M8048/M8748/M8035L Single Component 8-Bit Microcomputer ..................................	6-27
New High Performance 8049/8039/8039-6 Single Component 8-Bit Microcomputer ................	6-36
New High Performance 18049/8039 Single Component 8-Bit Microcomputer ......................	6-41
8021 Single Component 8-Bit Microcomputer ...................................................	6-48
8022 Single Component 8-Bit Microcomputer With On-Chip NO Converter .......................	6-51
8243 MCS-48™ Input/Output Expander .........................................................	6-57
108243 MCS-48™ Input/Output Expander .......................................................	6-63
8355/8355-2 16,384-Bit ROM With I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..	6-69
8755A 16,384-Bit EPROM With I/O .............................................................	6-74
8155/8156/8155-2/8156-22048 Bit Static MOS RAM With I/O Ports and Time .......................	6-82
8185/8185-21024 x 8-Bit Static RAM for MCS-85™ ..............................................	6-96

CHAPTER 7

MCS-S1TM Component Specification
8051/8751/8031 Microcomputer .................................	" ..............................	7-1

CHAPTERS

Compatible MCS-48™ Components
2114A 1024 x 4-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..	8-1
2316E 16K (2K x 8) ROM ........................................................	" ..............	8-5
2708 8K (1 K x 8) UV Erasable PROM .............................................................		8-8
2716 16K (2K x 8) UV Erasable PROM ..........................................................		8-12
2732A 32K (4K x 8) UV Erasable PROM .........................................................		8-17
8205 High Speed 1 out of 8 Binary Decoder .....................................................		8-18
8212 8-Bit Input/Output Port ....................................	'" ............................	8-24
8214/3214 Priority Interrupt Control Unit ........................................................		8-34
8216/8266 4-Bit Parallel Bidirectional Bus Driver .................................	" .............	8-38
8282/8283 Octal Latch ........................................................................		8-43
8286/8287 Octal Bus Transeiver ................................................................		8-48

CHAPTER 9

Peripherals
8251A/S2657 Programmable Communication Interface ...........................................				9-1
8253/8253-5 Programmable Interval Timer .......................................................				9-6
8255A/8255A-5 Programmable Peripheral Interface		..............................................		9-17
8259A Programmable Interrupt Controller ......................................................				9-38
8272	Single/Double Density Floppy Disk Controller	..............................................		9-51
8273,8273-4,8273-8 Programmable HDLC/SDLC Protocal Controller .............................				9-67
8279/8279-5 Programmable Keyboard/Display Interface ..........................................				9-70
8291 GPIB Talker/Listener .....................................................................				9-82
8292	GPIB Controller ..........................................................		'"	........... 9-106
8293	GPIB Transceiver .................................................................			, ..... 9-108
8294	Data Encryption Unit .......................	'" ............................	" .........	•.. 9-121
8041 N8641N8741 A Universal Peripheral Interface 8-Bit Microcomputer .........................				9-123

iv

CHAPTER 10

Support Products

Model 22SIntellec Series II ....................................................................		10-1
Intellec Prompt 48 MCS-48™ Microcomputer Design Aid .........................................		10-6
ICE-49 MCS-48™ In-Circuit Emulator ..........................................................		10-12
EM1	8021 Emulation Board ..................................................................	10-16
EM2	8022 emulation Board ...................................................................	10-19
UPP-103 Universal PROM Programmer ........................................................		10-22
SP-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..		10-24
Insite User'sLibrary .........................................................................		10-26

APPENDICES

Packing Information ..........................................................................	A1-1
Ordering Information .........................................................................	A2-1

v

INTRODUCTION

1.0 Introduction to MCS-48™

Recent advances in NMOS technology have allowed Intel for the first time to place enough .capability on a single silicon die to create a true single-chip microcomputer containing all the functions required in a digital processing system. A set of such microcomputers on single chips, their variations, and optional peripherals are collectively called the MCS-48 microcomputer family. These products are fully described in this manual.

The head of the family is the 8048 microcomputer which contains the following functions in a single 40 pin package:

8-Bit CPU

1K x 8 ROM Program Memory

64 x 8 RAM Data Memory

27 I/O Lines

8-Bit Timer/Event Counter

A 2.5 or 5.0 microsecond cycle time and a repertoire of over 90 instructions, each consisting of either one or two cycles, makes the single chip 8048 the equal in performance of most presently available multi-chip NMOS microprocessors. The 8048 is, however, a true "low-cost"

microcomputer. A single 5V supply requirement for all MCS-48 components assures that "low cost" also applies to the power supply in your system.

New Family Members

The MCS-48 family of microcomputers which began with the 8048 and 8748 has now been expanded with new members which provide either more capability or lower cost than the original family members. While broadening the applications possible with a single chip microcomputer, these new microcomputers share both the instruction set and development support of the 8048.

The 8049 is a single-chip microcomputer which is completely interchangeable with the 8048, but contains twice the program memory and twice the data memory of the 8048.

The 8022 is an 8021-based microcomputer with additional memory, 1/0, and an AID converter.

The 8021 is a new very low cost MCS-48 family member which contains a subset of

8049	8048	8021	8022	FEATURES
~	~	~	~	8·BITCPU
2Kx8	1Kx8	1Kx 8	2Kx8	PROGRAM MEMORY
128x 8	64x8	64x8	64x 8	DATA RAM
27	27	21	28	1/0 LINES
~	~	~	~	TIMER COUNTER
~	~	~	~	OSCILLATOR AND CLOCK
~	~	~	~	RESET CIRCUIT
~	~		~	INTERRUPT

ON CHIP FEATURES

1-1

INTRODUCTION

the 8048'sinstruction set and incorporates several new features critical in low cost applications.

Even with low component costs, however, a project may be jeopardized by high development and rework costs resulting from an inflexible production design. Intel has solved this problem by creating two pin-compatible versions of the 8048 microcomputer: the 8048 with mask Programmable ROM program memory for low cost production and the 8748 with user programmable and erasable EPROM program memory for prototype development. The 8748 is essentially a single chip microcomputer "breadboard" which can be modified over and over again during development and pre-produc- tion then replaced by the low cost 8021 *, 8048, or 8049 ROM for volume production. The 8748 provides a very easy transition from development to production and also provides an easy vehicle for temporary field updates while new ROMs are being made.

SPECIAL FEATURES

•SINGLE 5V SUPPLY

•40 PIN DIP OR 28 PIN DIP

•PIN COMPATIBLE ROM AND EPROM

•2.5,5.0 AND 10.0 J,Lsec CYCLE VERSIONS

•ALL INSTRUCTIONS 1 OR 2 CYCLES

•SINGLE STEP

•8 LEVEL STACK

•2 WORKING REGISTER BANKS

•LC, XTAL, OR EXTERNAL FREQUENCY SOURCE

•OPTIONAL CLOCK OUTPUT

•POWER DOWN STANDBY MODE

To allow the MCS-48 to solve a wide range of problems and to provide for future expansion, all 8048 and 8049 functions have been made externally expandable using either special expanders or standard memories and peripherals. An efficient low cost means of I/O expansion is provided by either the 8243 I/O Expander or standard TTL or CMOS circuits. The 8243 provides 16 1/0 lines in a 24 pin package. For systems with large 1/0 requirements, multiple 8243s can be used.

For such applications as Keyboards, Displays, Serial communication lin~s, etc. standard MCS-80/85 peripheral circuits may be added. Program and data memory may be expanded using standard memories or the 8355 and 8155 memories that also include programmable I/O lines and timing functions.

For applications which require a more custom tailored interface, the 8041 or 8741 Universal Peripheral Interface (UPI-41) devices can be used. The UPI-41 devices are available in both ROM and EPROM versions and are essentially slave versions of the 8048/8748 which are designed to interface directly with expandable MCS-48 processors and provide flexible intelligent I/O capability. The 8041/8741 share the instruction set of the MCS-48 family of processors.

The 8035 and 8039 are an 8048 or 8049 respectively without internal program memory that allows the user to match his program memory requirements exactly by using a wide variety of external memories. The 8035 and 8039 allow the user to select a minimum cost system no matter what his program memory reo quirements. The 8035L is an 8035 with the powerdown mode of the 8048.

The MCS-48 processors are designed to be efficient control processors as well as arithmetic processors. They provide an instruction set which allows the user to directly set and reset individual lines within its 1/0 ports as well as test individual bits within the accumulator. A large variety of branch and table look-up instructions l11ake these processors very efficient in implementing standard logic functions. Also, special attention has been given to code efficiency. Over 70% of the instructions are a single byte long and all others are only two bytes long. This means many functions requiring 1.5K to 2.0K bytes in other computers may very well be compressed into the 1K words resident in the 8048 or up to 3K to 4K equivalent bytes may be compressed into the 8049.

*The 8021 is code compatible but not pin compatible with the 8748.

1·2

INTRODUCTION

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	FUNCTION	PART
		NUMBER
	Microcomputers	8021
		8022
		8048
		8035
		8035L
		8049
		8039
		8748-8
		8035-8
		8748-6
	Memory and I/O	8355
	Expanders	8755A
		8155/56
		8185
	I/O Expander	8243
	Standard ROMs	2308
		2316E
		2332
	Standard EPROMs	2708
		2716
		2732
	Standard RAMs	2111A-4
		2101A-4
	Standard I/O	8212
		8255A
		8251A

DESCRIPTION

COMMENTS

~~ :g~ :~~~~:~ ~:~~~with AID } 10		I'secCycle
1K ROM Program Memory	f
No Program Memory 64 x 8 RAM	2.5	I'secCycle
8035 with Power Down Mode
2K ROM Program Memory	} 1.36 I'secCycle
No Program Memory 128 x 8 RAM

1K EPROM Program Memory

No Program Memory	} 5.0 I'secCycle
1K EPROM 0°C-55°C, 6 MHz

2K x 8 ROM with 16 I/O Lines

2K x 8 EPROM with 16 110 Lines

256 x 8 RAM with 22 I/O Lines and Timer 1Kx 8HAM

16 Line I/O Expander

1Kx8 450 ns 2Kx8 450 ns 4Kx8 450 ns

1Kx8 450 ns Light Erasable 2Kx8 450 ns Light Erasable 4Kx8 450 ns Light Erasable

256x4 450 ns Common I/O

256x4 450 ns Separate I/O

8-B it I/O Port

Programmable Peripheral Interface

Programmable Communication Interface

Compatible versions of the single chip microcomputers pro· vide mask programmed, light erasable, or no internal program memory.

Compatible devices allow direct expansion of MCS-48 functions with no additional external com· ponents.

Low cost I/O expander.

Allows low cost external expan· sion of Program Memory. Each ROM is interchangeable with an EPROM.

User programmable and eras· able.

Data memory can be easily ex· panded using standard NMOS RAMs.

Serves as Address Latch or I/O port.

Three 8-bit programmable 110 ports.

Serial Communications Receiv· er/Transmitters.

8273	Programmable HDLC/SDLC Controller
Standard Peripherals 8205	1·of-8Binary Decoder	MCS-80 peripheral devices are
8214	Priority Interrupt Controller	compatible with the MCS-48, al·
8216	Bidirectional Bus Driver	lowing easy addition of such
8226	Bidirectional Bus Driver (Inverting)	specialized interfaces as the
8253	Programmable Interval Timer	8279 Keyboard/Display Interface.
8279/78	Programmable Keyboard/Display Interface	Future MCS-80/85 devices will
8291	(64 Keys/128 Keys)	also be compatible.
	GPIB Talker/Listener
8294	Data Encryption Unit
8295	Dot Matrix Printer Controller

·Universal Peripheral	8041A	ROM Program Memory	User programmable to perform
Interface	8741A	EPROM Program Memory	any custom I/O and control func·
			tions.

MCS·48™ MICROCOMPUTER COMPONENTS

1-3

INTRODUCTION

384

8049	8049
8155	8155
	835&

320

8048	8048
8155	8355
	8155

(38)	(38)	(53)	(S3)
128
	8049		8049
			8355
64
8048		8048
		8355
(24)	(24)	(28)	(28)
1K	2K	3K	4K
	PROGRAM MEMORY (ROM)

( ) NUMBER OF AVAILABLE 1/0 LINES

THE EXPANDED MCS-48™ SYSTEM

The chart above shows the expansion possibilities using the 8048 and 8049 in various combinations with the Intel® 8355/ 8755 Program Memory and I/O Expander and the 8155 Data Memory and I/O Expander. Data Memory can be expanded beyond the resident words in blocks of 256

by adding 8155's.Program Memory can be expanded beyond the resident 1K or 2K in blocks of 2K by using the 8355/8755 in combination with the 8048 or 8049. If all external memory is desired, the 8035 or 8039 can be substituted for the 8048 and 8049.

1-4

INTRODUCTION

1.1 The Function of a Computer

This chapter introduces certain basic computer concepts. It provides background information and definitions which will be useful in later chapters of this manual. Those already familiar with computers may skip this material, at their option.

printer, to a peripheral storage device, such as a floppy disk·unit, or the output may constitute process control signals that direct the operations of another system, such as an automated assembly line. Like input ports, output ports are addressable. The input and output ports together permit the processor to communicate with the outside world.

1.1.1 A Typical Computer System

A typical digital computer consists of:

A central processor unit (CPU)

Program Memory

Data Memory

Input/output (I/O) ports

The processor memory serves as a place to store Instructions, the coded pieces of information that direct the activities of the CPU, while Memory stores the Data, the coded pieces of information that are processed by the CPU. A group of logically related instructions stored in memory is referred to as a Program. The CPU "reads" each instruction from memory in a logically determined sequence, and uses it to initiate processing actions. If the program sequence is coherent and logical, processing the program will produce intelligible and useful results. The program must be organized such that the CPU does not read a non-instruction word when it expects to see an instruction.

The CPU can rapidly access any data stored in memory; but often the memory is not large enough to store the entire data bank required for a particular application. The problem can be resolved by providing the computer with one or more Input Ports. The CPU can address these ports and input the data contained there. The addition of input ports enables the computer to receive information from external equipment (such as a paper tape reader or floppy disk) at high rates of speed and in large volumes.

A computer also requires one or more Output Ports that permit the CPU to communicate the result of its processing to the outside world. The output may go to a display, for use by a human operator, to a peripheral device that produces "hard-copy", such as a line-

The CPU unifies the system. It controls the functions performed by the other components. The CPU must be able to fetch instructions from memory, decode their binary contents and execute them. It must also be able to reference memory and I/O ports as necessary in the execution of instructions. In addition, the CPU should be able to recognize and respond to certain external control signals, such as INTERRUPT requests. The functional units within a CPU that enabl~ it to perform these functions are described below.

1.1.2 The Architecture of a CPU

A typical central processor unit (CPU) consists of the following interconnected functional units:

Registers

Arithmetic/Logic Unit (ALU)

Control Circuitry

Registers are temporary storage units within the CPU. Some registers, such as the program counter and instruction register, have dedicated uses. Other registers, such as the accumulator, are for more general purpose use.

Accumulator

The accumulator usually stores one of the operands to be manipulated by the ALU. A typical instruction might direct the ALU to add the contents ofsome other reg ister to the contents of the accumulator and store the result in. the accumulator itself. In general, the accumulator is both a source (operand) and a destination (result) register. Often a CPU will include a number of additional general purpose registers that can be used to store operands or intermediate data. The availability of general purpose registers

1·5

INTRODUCTION

eliminates the need to "shuffle" intermediate results back and forth between memory and the accumulator, thus improving processing speed and efficiency.

Program Counter (Jumps, Subroutines and

the Stack):

The instructions that make up a program are stored in the system'smemory. The central processor references the contents of memory in order to determine what action is appropriate. This means that the processor must know which location contains the next instruction.

Each of the locations in memory is numbered, to distinguish it from all other locations in memory. The number which identifies a memory location is called its Address. The processor maintains a counter which contains the address of the next program instruction. This register is called the Program Counter. The processor updates the program counter by adding "1" to the counter each time it fetches an instruction, so that the program counter is always current (pointing to the next instruction).

The programmer therefore stores his instructions in numerically adjacent addresses, so that the lower addresses contain the first instructions to be executed and the higher addresses contain later instructions. The only time the progrl:immer may violate this sequential rule is when an instruction in one section of memory is a Jump instruction to another section of memory.

A jump instruction contains the address of the instruction which is to follow it. The next instruction may be stored in any memory location, as long as the programmed jump specifies the correct address. During the execution of a jump instruction, the processor replaces the contents of its program counter with the address embodied in the Jump. Thus, the logical continuity of the program is maintained.

A special kind of program jump occurs when the stored program "Calls" a subroutine. In

this kind of jump, the pJOcessor is required to "remember" the contents of the program counter at the time that the jump occurs. This enables the processor to resume execution of the main program when it is finished with the last instruction of the subroutine.

A Subroutine is a program within a program. Usually it is a general-purpose set of instructions that must be executed repeatedly in the course of a main program. Routines which calculate the square, the sine, or the logarithm of a program variable are good examples of functions often written as subroutines. Other examples might be programs designed for inputting data to a particular peripheral device.

The processor has a special way of handling subroutines, in order to insure an orderly return to the main program. When the processor receives a Call instruction, it increments the Program Counter and stores the counter'scontents in a reserved memory area known as the Stack. The Stack thus saves the address of the instruction to be executed after the subroutine is completed. Then the processor loads the address specified in the Call into its Program Counter. The next instruction fetched will therefore be the first step of the subroutine.

The last instruction in any subroutine is a Return. Such an instruction need specify no address. When the processor fetches a Return instruction, it simply replaces the current contents of the Program Counter with the address on the top of the stack. This causes the processor to resume execution of the calling program at the point immediately following the original Call instruction.

Subroutines are often Nested; that is, one subroutine will sometimes call a second subroutine. The second may call a third, and so on. This is perfectly acceptable, as long as the processor has enough capacity to store the necessary return addresses, and the logical provision for doing so. In other words, the maximum depth of nesting is determined by the depth of the stack itself. If the stack has space for storing three return addresses, then

1·6

INTRODUCTION

three levels of subroutines may be accommodated.

Instruction Register and Decoder

Every computer has a Word Length that is characteristic of that machine. A computer's word length is usually determined by the size of its internal storage elements and interconnecting paths (referred to as Buses); for example, a computer whose registers and buses can store and transfer 8-bits of information has a characteristic word length of 8-bits and is referreq to as an 8-bit parallel processor. An 8-bit parallel processor generally finds it most efficient to deal with 8-bit binary fields, and the memory associated with such a processor is therefore organized to store 8-bits in each addressable memory location. Data and instructions are stored in memory as 8-bit binary numbers, or as numbers that are integral multiples of 8-bits: 16-bits, 24-bits, and so on. This characteristic 8-bit field is often referred to as a Byte. If however, efficient handling of 4 or even 1-bit data is necessary special processor instructions can provide this capability.

signals that can then be used to initiate specific actions. This translation of code into action is performed by the Instruction Decoder and by the associated control circuitry.

An 8-bit instruction code is often sufficient to specify a particular processing action. There are times, however, when execution of the instruction requires more information than 8- bits can convey.

One example of this is when the instruction references a memory location. The basic instruction code identifies the operation to be performed, but cannot specify the object address as well. In a case like this, a two byte instruction must be used. Successive instruction bytes are stored in sequentially adjacent memory locations, and the processor performs two fetches in succession to obtain the full instruction. The first byte retrieved from memory is placed in the prbcessor'sinstruction register, and subseq!Jent byte is placed in temporary storage; t~e processor then proceeds with the executiol1 phase.

Address Register(s)

Each operation that the processor can perform is identified by a unique byte of data known as an Instruction Code or Operation Code. An 8-bit word used as an instruction code can distinguish between 256 alternative actions, more than'adequate for most processors.

The processor fetches an instruction in two distinct operations. First, the processor transmits the address in its Program Counter to the program memory. Then the program memory returns the addressed byte to the processor. The CPU stores this instruction byte in a register known as the Instruction Register, and uses it to direct activities during the remainder of the instruction execution.

The 8-bits stored in the instruction register can be decoded and used to selectively activate one of a number of output lines. Each line represents a set of activities associated with execution of a particular instruction code. The enabled line can be combined with selected timing pulses, to develop 'el'ectrical

A CPU may use a register to hold the address of a memory location that is to be accessed for data. If the address register is Programmable, (Le., if there are instructions that allow the programmer to alter the contents of the register) the program can "build" an address in the address register prior to executing a Memory Reference instruction (Le., an instruction that reads data from memory, writes data to memory or operates on data stored in memory).

Arithmetic/Logic Unit (ALU)

All processors contain an arithmetic/logic unit, which is often referred to simply as the ALU. The ALU, as its name implies, is that portion of the CPU hardware which performs the arithmetic and logical operations on the binary data.

The ALU must contain an Adder which is capable of combining the contents of two registers in accordance with the logic of binary arithmetic. This provision permits the

1·7

INTRODUCTION

processor to perform arithmetic manipulations on the data it obtains from memory and from its other inputs.

Using only the basic adder a capable programmer can write routines which will subtract, multiply and divide, giving. the machine complete arithmetic capabilities. In practice, however, most ALUs provide other built-in functions, including boolean logic operations, and shift capabilities.

The ALU contains Flag Bits which specify certain conditions that arise in the course of arithmetic and logical manipulations. It is possible to program jumps which are conditionally dependent on the status of one or more flags. Thus, for example, the program may be designed to jump to a special routine if the carry bit is set following an addition instruction.

Control Circuitry

The control circuitry is the primary functional unit within a CPU. Using clock inputs, the control circuitry maintains the proper sequence of events required for any processing task. After an instruction is fetched and decoded, the control circuitry issues the appropriate signals (to units both internal and external to the CPU) for initiating the proper processing action. Often the control circuitry will be capable of responding to external signals, such as an interrupt. An Interrupt request will cause the control circuitry to temporarily interrupt main program execution, jump to a special routine to service the interrupting device, then automatically return to the main program.

1.1.3 Computer Operations

There are certain operations that are basic to almost any computer. A sound understanding of these basic operations is a necessary prerequisite to examining the specific operations of a particular computer.

Timing

The activities of the central processor are cyclical. The processor fetches an instruction, performs the operations required,

fetches the next instruction, and so on. This orderly sequence of events requires precise timing, and the CPU therefore requires a free running oscillator clock which furnishes the reference for all processor actions. The combined fetch and execution of a single instruction is referred to as an Instruction Cycle. The portion of a cycle identified with a clearly defined activity is called a State. And the interval between pulses of the timing oscillator is referred to as a Clock Period. As a general rule, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle.

Instruction Fetch

The first state(s) of any instruction cycle will be dedicated to fetching the next instruction. The CPU issues a read signal and the contents of the program counter are sent to program memory, which responds by returning the next instruction word. The first byte of the instruction is placed in the instruction register. If the instruction consists of more than one byte, additional states are required to fetch the second byte of the instruction. When the entire instruction is present in the CPU, the program counter is incremented (in preparation for the next instruction fetch) and the instruction is decoded. The operation specified in the instruction will be executed ih the remaining states of the instruction cycle. The instruction may call for a data memory read or write, an input or output and/or an internal CPU operation, such as a register-to-register transfer or an add operation.

Memory Read

An instruction fetch is merely a special program memory read operation that brings the instruction to the CPU's instruction register. The instruction fetched may then call for data to be read from data memory into the CPU. The CPU again issues a read signal and sends the proper memory address; memory responds by returning the requested word. The data received is placed in the accumulator or one of the other geheral purpose registers (not the instruction register).

1-8

INTRODUCTION

Memory Write

A memory write operation is similar to a read except for the direction of data flow. The CPU issues a write signal, sends the proper memory address, then sends the data word to be written into the addressed data memory location.

Input/Output

Input and Output operations are similar to memory read and write operations with the exception that an I/O port is addressed instead of a memory location. The CPU issues the appropriate input or output control signal, sends the proper address and either receives the data being input or sends the data to be output.

Data can be input/output in either parallel or serial form. All data within a digital computer is represented in binary coded form. A binary data word consists of a group of bits; each bit is either a one or Ii zero. Parallel I/O consists of transferring all bits in the word at the same time, one bit per line. Serial I/O consists of transferring one bit at a time on a single line. Naturally serial I/O is much slower, but it requires considerable less hardware than does parallel I/O.

Interrupts

Interrupt provisions are included on many central processors, asa means of improving

the processor'sefficiency. Consider the case of a computer that is processing a large volume of data, portions of which are to be output to a printer. The CPU can output a byte of data within asingle machine cycle but it may take the printer the equivalent of many machine cycles to actually print the character specified by the data byte. The CPU could then remain idle waiting until the printer can accept the next data byte. If an interrupt capability is implemented on the computer, the CPU can output a data byte then return to data processing. When the printer is ready to accept the next data byte, it can request an interrupt. When the CPU acknowledges the interrupt, it suspends main program execution and automatically branches to a routine that will output the next data byte. After the byte is output, the CPU continues with main program execution. Note that this is, in principle, quitesimilarto a subroutine call, except that the jump is initiated externally rather than by the program.

More complex interrupt structures are possible, in which several interrupting devices share the same processor but have different priority levels. Interruptive processing is an important feature that enables maximum utilization of a processor'scapacity for high system throughput.

1·9

INTRODUCTION

	1.2 Programming a Microcomputer	counts the number of words to be stored.
	1.2.1 Machine Language Programming	When finished the processor continues on
		to the next instructions.

A microprocessor is instructed what to do by programming it with a series of instructions stored in Program Memory. The processor fetches these instructions one at a time and performs the operation indicated. These instructions must be stored in a form that the processor can understand. This format is referred to as Machine Language. For most microprocessors this instruction is a group of a binary bits (1'sand O's)called a word (also called a byte if the word is a-bits). Some instructions require more than one location in Program Memory. To execute a multi-byte instruction, the processor must execute multiple fetches of program memory before performing the instruction. Because mUltibyte instructions take more Program Memory and take longer to execute than single byte instructions their use is usually kept to a minimum.

A processor may be programmed by writing a sequence of instructions in the binary code (ones and zeros) which the machine can interpret directly. This is machine language programming and it is very useful where the program to be written is small and the application requires that the designer have an intimate knowledge of the microprocessor. Machine language programming allows the user, because of his detailed knowledge, to use many programming "tricks" to produce the most compact and efficient code possible.

The following is an example of a machine language program: This program reads 5 sequential 8-bit words in from an I/O port and stores them sequentially in data memory. The program starts by initializing two registers, one which determines where the data is to be stored and another which

Step	Machine
Number	Code	Explanation
0	1011 1000	Load	decimal 32	in
1	00100000	register RO
2	1011 1010 Load decimal 5 in
3	00000101	register R2
4	00001001	Load Port 1 to accu-
		mulator
5	10100000	Transfer contents of
		accumulator to reg-
		ister	addressed	by
		register 0
6	0001 1000	Increment RO by		1

711101010 Decrement register 2

80000 0100 by 1, if result is zero

continue to step 9, if not go to step 4

9

10

As you can see, writing machine instructions in ones and zeros can be very laborious and subject to error. It is almost always more efficient to represent each a-bits of machine language code in a shorthand format called Hexadecimal. The term hexadecimal results from the character set used in hexadecimal notation. Hexadecimal is merely an extension of the normal decimal numbers by the addition of the first six letters of the alphabet. This gives a total of 16 different characters. Each hexadecimal "digit" can represent 16 values or the equivalent of four binary bits; therefore, each a-bit machine language word can be represented by 2 hexadecimal (hex for short) digits. The correspondence among the decimal, binary, and hex number systems is given below:

1-10

INTRODUCTION

Decimal	Hex	Binary
0	0	0000
1	1	0001
2	2	0010
3	3	0011
4	4	0100
5	5	0101
6	6	0110
7	7	0111
8	8	1000
9	9	1001
10	A	1010
11	B	1011
12	C	1100
13	0	1101
14	E	1110
15	F	1111

step 8 would have to be changed to refer to the new address of step 4.

1.2.2 Assembly Language Programming Assembly language overcomes the disadvantages of machine language by allowing the use of alphanumeric symbols to represent machine operation codes, branch addresses, and other operands. For example, the instruction to increment the contents of register 0 becomes INC RO instead of the hex 18, giving the user at a glance the meaning of the instruction. Our example program can be written in assembly language as follows:

Step No. Hex Code		Assembly Code
o	88	MOV RO, #32

Our machine language program then becomes:

Step	Hex Code
o	B8

120

2BA

305

409

5FO

618

7EA

804

This coding is now quite efficient to write and read and coding errors are much easier to detect. Hex coding is usually very efficient for small programs (a few hundred lines of code). However, it does have two major limitations in larger programs:

1.Hex coding is not self-documenting, that is, the code itself does not give any indication in human terms of the operation to be performed. The user must learn each code or constantly use a Program Reference Card to convert.

2.Hex coding is absolute, that is, the program will work only when stored in a specific location in program memory. This is because the branch or jump instructions in the program reference specific addresses elsewhere in the program. In the example above steps 7 and 8 reference step (or address) 4. If the program were to be moved,

1	20
2	8A		MOV R2, #05
3	05
4	09	INP:	IN A, P1
5	AO		MOV @RO, A
6	18		INC RO
7	EA		DJNZ R2, INP
8	04

The first statement can be verbalized as follows: Move to Register 0 the decimal number 32. Move instructions are always structured such that the destination is first and the source is second. The pound sign "#" indicates that the source is "immediate" data (data contained in the following byte of program memory). In this case data was specified as a decimal 32, however, this could have been written as a hex 20H or a binary 0010 00008 since the assembler will accept either form. Notice also that in this instance two lines of hex code are represented by one line of assemlJly code.

The input instruction IN A, P1 has the same form as a MOV instruction indicating that the contents of Port 1 are to be transferred to the accumulator. In front of the input instruction is an address label which is delineated by a colon. This label allows the program to be written in a form independent of its final location in program memory since the branch instruction at the end of the program can refer to this label rather than a specific address. This is a very important advantage of assembly language programs since it

1·11

INTRODUCTION

allows instructions to be added or deleted throughout the program during debugging without requiring that any jump addresses be changed.

The next instruction MOV @RO, A can be verbalized as, Move to the data memory location addressed by RO, the contents of the accumulator. The @ sign indicates an indirect operation whereby the contents of either register 0 or register 1 acts as a pointer to the data memory location to be operated on.

The last instruction is a Decrement and Jump if Not Zero instruction which acts in combination with the specified register as a loop counter. In this case register 2 is loaded with 5 initially and then decremented by one each time the loop is executed. If the result of the decrement is not zero, the program jumps to INP and executes another input operation. The fifth time thru the loop the result is zero and execution falls through to whatever routine follows the DJNZ instruction.

In addition to the normal features provided by assemblel'3,more advanced assemblers such as that for the MCS-48 offer such things as evaluation of expressions at assembly time, conditional assembly, and macro capability.

1. Evaluation of Expressions - Certain assemblers allow the use of arithmetic expressions and multiple symbols in the operand portion of instructions. For instance the MCS-48 assembler accepts instructions such as:

ADD A, # ALFA*BETA/2

ALFA and BETA are two previously defined symbols. At assembly time the expression ALFA*BETA/2 will be evaluated and the resulting number (which is the average of ALFA and BETA) will be treated as immediate data and .designated as the second byte of the ADD immediate instruction. This expression has allowed the immediate data of this instruction to be defined in a single statement and eliminated the need for a third symbol .equal to ALFA*BETA/2.

2. Conditional Assembly - Conditional assembly allows the programmer to select only certain portions of his assembly language (source) program for conversion to machine (object) code at assembly time. This allows for instance, the inclusion of various "debug" routines to be included in the program during development. Using conditional assembly, they can then be left out when the final assembly is done.

Conditional assembly also allows several versions of one basic program to be generated by selecting various portions of a larger program at assembly time.

3. Macro's- A macro instruction is essentially a symbol which is recognized by the assembler to represent a specific sequence of several standard instructions. A macro is a shorthand way of generating the same sequence of instructions at several locations in a program without having to rewrite the sequence each time it is used. For example, a typical macro instruction might beonewhich performs a subtract operation. The 8048 does not have a subtract instruction as such but the operation can be performed easily with three instructions:

CPLA

ADD A, REG

CPLA

This routine subtracts a register from the accumulator and leaves the result in the accumulator. This sequence can be defined as a macro with the name SUB and an operand which can be RO to R7. To subtract R7 from the accumulator then, the programmer merely has to write:

SUB R7

and the assembler will automatically insert the three instructions above with R7 substituted for REG.

Once the assembly language source code is written it can be converted to machine executable object code by passing it through an assembler program. The MCS-48 assembler is a program which runs on the 8080based Intellec MDS system explained in the next section.

1-12

INTRODUCTION

1.3 Developing An MCS-48™ Based

Product

Although the development of a microcomputer based product may differ in detail from the development cycle of a product based on TTL logic or relays, the basic procedures are the same - only the tools are different.

1.3.1 Education

The first step of course is to become familiar with what the microcomputer is and what it can do. The first step in this education is this document, the MCS-48™ User'sManual. The user'smanual gives a detailed description of the MCS-48 family of components and how they may be used in various system configurations. Also included is a description of the 8048 instruction set and examples of how the instructions may be used. For a more complete discussion of the instruction set and programming techniques the MCS-48 Assembly Language Manual is also available.

If time is critical in getting started in microcomputers, individuals can attend one of many Intel sponsored 5-day training courses which give basic instruction in the MCS-48 as well as hands-on experience with MCS-48 development systems. These courses are a convenient means of getting started with the MCS-48, particularly for those not familiar with microprocessors.

After general familiarization is complete, either through self-instruction or a training course, the next step is to gain a better "feel" for what a microprocessor can do in your own applications by writing several exercise programs which perform basic functions. You may require such things as I/O routines, delays, counting functions, look-up tables, arithmetic functions, and logical operations which can serve as a set of building blocks for future applications programs. Several basic programming examples are included in the MCS-48 Assembly Language Manual while the Intel User'sLibrary is a source of more specific applications routines.

1.3.2 Function Definition

After a thorough understanding of the

microprocessor is achieved, the functions to be implemented can be defined using a flowchart method to describe each basic system function and the sequence in which the processor executes these functions. Once the system is flowcharted, critical timerelated functions can be identified and sample programs written to verify that performance requirements can be met.

1.3.3 Hardware Configuration

The next step involves the definition of the microcomputer hardware required to implement the function. Input/Output capability must be defined in terms of number of inputs, number of outputs, bi-directional lines, latching or non-latching I/O, output drive capability, and input impedance. The number of words of RAM storage required for intermediate results and data storage must then be determined. The type of system will dictate whether battery backup is needed to maintain data RAM during power failure.

Probably the most difficult parameter to define initially is the amount of program memory needed to store the applications program. Although previously written exercise programs will make this estimate more accurate, a generous amount of "breathing room" should be allowed in program memory until coding is complete and the exact requirements are known. Many special functions such as serial communications (TTY) or keyboard/display interfaces may be implemented in software (programs); however, in cases where these functions place a severe load on the processor in terms of time or program memory, special peripheral interface circuits such as the 8251, Universal Synchronous or Asychronous Receiver/ Transmitter (USART) or 8279 Keyboard/ Display interface may be used.

1.3.4 Code Generation

The writing of the final program code for the application can begin once the system function and hardware have been defined and can be generated in parallel with the detailed hardware design (PC card layout, power supply, etc.)

1-13

INTRODUCTION

At this point, there are two paths available to the designer/programmer and two types of design development aids provided by Intel to simplify the procedures. One system, called PROMPT 48, is a low cost development system which supports machine language programming and the second is the Intellec Microcomputer Development System which supports both machine and assembly languages. For those of you unfamiliar with the advantages and disadvantages of machine and assembly languages see Section 1.2.

1.3.5 PROMPT 48

PROMPT 48 is a low cost design aid consisting of: an 8748 processor to execute programs, control circuitry to provide debug functions such as single step and break points, a monitor program stored in ROM, an EPROM programmer, and ahexadecimal keyboard and display, There are two processor sockets on the front ofF>ROMPT 48, one for programming the 8748 and one in

which a programmed .8748 executes its program while under control of the monitor routine.

Use of PROMPT 48 involves .the following steps:

1. Loading an application program into the PROMPT RAM memory via Hex keyboard or external terminal (TTY and RS232 interface provided).

2.Inserting an erased 8748 in the programming socket and transferring the application program to its internal EPROM.

3.Transferring programmed 8748 to execution socket where program is executed and debugged under control of the monitor.

The monitor routine allows the user to single step this processor, examine or modify all internal registers and data memory; or to run at full speed and stop the processor at predetermined breakpoints. PROMPT 48

LOCKED		LOCKED
				49		H
	40		40	lEt
				50 I/O PORTS CONNECTOR 2
				prompt 48
20	21	20	21
PROGRAMMING		EXECUTION
SOCKET		SOCKET
			, __ --- 'COMMAND/FUNCTION-			GROUp·---- ...
				~FIFIBI11~IBIFIF~
				FUNC1'ION I AODf!ESS		I DATA
© POWER ON				COMMANDS	HEX DATA/FUNCTIONS
			EXAMINE/	DISPLAYI
			MODIFY	DO MODIFY
			REGISTER	'MEMORY
			GO	DO S~~~~E
			G~R~~:	PREVIOUS/
			POINTS	DO ClEAR.ENTRY
			NEXT	mI[c:JI EXi~~TEI
in~----------		~--------------		________________________- 4

1-14

INTRODUCTION

also provides 1K of writeable program memory which may be used to debug user programs. A multiple single step feature is also provided in which the processor steps through its program dumping all internal contents to external RAM where it may be later displayed or typed out on an external terminal. Paper tape input and output in Intel'shexadecimal format is also available through the TTY.

1.3.6 Intellec Development System

The Intellec Microcomputer Development System is a modular development system which can be expanded as necessary to meet the requirements of your design cycle. The system consists of the processor unit which is based on Intel's8080A microprocessor, and several optional units such as the UPP Universal PROM Programmer, the PTR High Speed Paper tape reader, the DOS Disk Operating System, and the Intellec CRT terminal.

To support the development of MCS-48 systems a macro-assembler ASM 48 is available for the Intellec System as well as a personality module for the UPP which will program the EPROM of the 8748. Also available is in-circuit emulation capability with ICE·49which will allow emulation and debug of user's8048 application programs on the 8080A-based Intellec Development System.

The Intellec system is a flexible high performance development system which can support Intel'svarious microcomputer families with various optional modules. The

macro-assembler and text editor programs provided allow the designer to write and edit his programs in assembly language and then generate the machine language output necessary to program the 8748 EPROM. The availability of a high speed CRT and a diskette operating system eliminates the laborious input and output of paper tape files normally required during the assembly process. Finally, ICE 48 allows the user to extend the resources of his entire Intellec system into the 8048 socket of his own system and use all its emulation, debug, and display facilities directly.

1.3.7 Production

Once a working program has been achieved, a preproduction phase usually follows where several prototype systems are evaluated in simulated situations or in actual operation in the field. During this period the use of the 8748 EPROM allows quick alteration of the application program when problems or suggested changes arise. Depending on the magnitude and number of future changes anticipated, the first production units may also be shipped with EPROM processor. However, to achieve the maximum cost reduction potential in high volume applications, a conversion to the 8048 ROM is usually necessary. This is an easy transition since the 8048 and 8748 are pin and machine code compatible equivalents. The user merely develops a hexadecimal tape of his 8748 program memory contents using his Intellec System or PROMPT 48 development aid and sends it to Intel along with his 8048 order. As the 8048 ROM'sarrive they can immediately replace the 8748 EPROMs.

1-15

THE SINGLE COMPONENT MCS-48™ SYSTEM

2.0 Summary

Sections 2.1 through 2.4 describe in detail the functional characteristics of the 8748 EPROM, 8048/8049 ROM and 8035/8039 single component microcomputers. Unless otherwise noted, details within these sections apply to all .versions. Sections 2.5 through 2.11 describe the operation of the 8021, while Sections 2.12 through 2.21 describe the 8022. This chapter is limited to those functions useful in single-chip implementations of the MCS-48. Chapter 3 discusses functions which allow expansion of program memory, data memory, and inputoutput capability.

Arithmetic Logic Unit

The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under control of the Instruction Decoder. The ALU can perform the following functions:

Add With or Without Carry

AND, OR, Exclusive OR

IncrementiDecrement

Bit Complement

Rotate Left, Right

Swap Nibbles

BCD Decimal Adjust

2.1 Architecture

The following sections break the 8048 into functional blocks and describe each in detail.

2.1.1 Arithmetic Section

The arithmetic section of the processor contains the basic data manipulation functions of the 8048 and can be divided into the following

blocks:

Arithmetic Logic Unit (ALU) Accumulator

Carry Flag Instruction Decoder

In a typical operation data stored in the accumulator is combined in the ALU with data from another source on the internal bus (such as a register or I/O port) and the result is stored in the accumulator or another register. The following is a more detailed description of the function of each block:

Instruction Decoder

The operation code (op code) portion of each program instruction is stored in the Instruction Decoder and converted to outputs which control the function of each of the blocks of the Arithmetic Section. These lines control the source of data and the destination register as well as the function performed in the ALU.

If the operation performed by the ALU results in a value represented by more than 8 bits (overflow of most significant bit) a Carry Flag is set in the Program Status Word.

Accumulator

The accumulator is the single most important data register in the processor, being one of the sources of input to the ALU and often the destination of the result of operations performed in the ALU. Data to and from 1/0 ports and memory also normally passes through the accumulator.

2.1.2 Program Memory

Resident program memory consists of 1024 or 2048 words eight bits wide which are addressed by the program counter. In the 8748 this memory is user programmable and erasable EPROM; in the 8048/8049 the memory is ROM which is mask programmable at the factory. The 8035/8039 has no internal program memory and is used with external devices. Program code is completely interchangeable among the various versions. See Section 2.3 for EPROM programming techniques.

2-1

	Q)
	o
	~
	Q)
	......
	Q)
	o
	~
	CO	RESIDENT
	OJ
		EPROM/ROM
	r-	1K x8
	o	(2K x 8''''
	o

"c

);

C)

:D

»

s::

r---	V	'\/	V	V	V
		A	A	7,	(B)

I\)

'"

			TEST 0
			TEST 1
			INT
		Vee	FLAG a
		.........- PROGRAM SUPPLY
			FLAG 1
	POWER	Voo	TIMER FLAG
	SUPPLY1--:--- +5V {LOW POWER STANDBYI
			CARRY
		~GND	ACC
			ACCSIT TEST

XTALl XTAL2

OSCILLATOR	ADDRESS	PROGRAM	SINGLE	READ WRITE
XTAL	LATCH	MEMORY	STEP	STROBES
	STROBE	ENABLE
	CYCLE
	CLOCK

V	PORTl
	~BUS
A	BUFFER
	AND
	LATCH

MULTIPlEXERI

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

8 lEVEL STACK

(VARIABLE LENGTH)

OPTIONAL SECOND

REGISTER BANK

DATA STORE

RESIDENT

RAM ARRAY

64x 8

(128 x 8)-<-

*8049 only

~

Z

C)

r- m

o

o s::

"0

o

Z m

Z

-I

tn

-<

tn

-I m

s::

SINGLE COMPONENT SYSTEM

There are three locations in Program Memory of special importance:

LOCATION 0

Activating the Reset line of the processor causes the first instruction to be fetched from location O.

LOCATION 3

Activating the Interrupt input line of the processor (if interrupt is enabled) causes a jump to subroutine at location 3.

LOCATION 7

A timer/counter interrupt resulting from timer/counter overflow (if enabled) causes a jump to subroutine at location 7.

Therefore, the first instruction to be executed after initialization is stored in location 0, the first word of an external interrupt service subroutine is stored in location 3, and the first word of a timer/counter service routine is stored in location 7. Program memory can be used to store constants as well as program instructions. Instructions such as MOVP and MOVP3 allow easy access to data "lookup" tables.

- 0

2048~, SELMai

2047~TSELMBO

1024 --""""""

1023

..r-- LDCATION 7 - TIMER INTERRUPT VECTORS PROGRAM HERE

..r--- LOCATION 3 - EXTERNAL INTERRUPT VECTORS

PROGRAM HERE

RESET VECTORS o 716151413121110 I--PROGRAM HERE

ADDRESS

MCS-48™ PROGRAM MEMORY MAP

Data Memory

Resident data memory is organized as 64 or 128 words 8-bits wide. All locations are indirectly addressable through either of two RAM Pointer Registers which reside at address 0 and 1 of the register array. In addition, the first 8 locations (0-7) of the array are designated as working registers and are directly addressable by several instructions. Since these registers are more easily addressed, they are usually used to store frequently accessed intermediate results. The DJNZ instruction makes very efficient use of the working registers as program loop counters by allowing the programmer to decrement and test the register in a single instruction.

By executing a Register Bank Switch instruction (SEL RB) RAM locations 24-31 are designated as the working registers in place of locations 0-7 and are then directly addressable. This second bank of working registers may be used as an extension of the first bank or reserved for use during interrupt service

63

(128 )

USER RAM

3h8

(96.8)

	32								I
	31				BANK I
					WORKING
					REGISTERS				DIRECTLY
									ADDRESSABLE
					ax8				WHEN BANK 1
		-	-	-	-RT'-	-	-	-	IS SELECTED
	2.								-.J
		-	-	-	-ROo -	-	-	-
	23
				B LEVEL STACK					ADDRESSED
					OR				INDIRECTLY
					USER RAM				THROUGH
					16 x 8				Rl OR RO
									(RO'OR Rl')
					BANKO				I
					WORKING
					REGISTERS				DIRECTLY
									ADDRESSABLE
					ax8				WHEN BANK 0
		r----------							IS SELECTED
		----~-				----

IN ADDITION RO OR Rl (RO'OR Rl')MAY BE USED TO ADDRESS 268 WORDS OF

EXTERNAL RAM.

( )8049 only

DATA MEMORY MAP

2-3