Intel PXA255 User Manual

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Intel® PXA255 Processor

Developer’s Manual

March, 2003

Order Number: 278693-001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel® PXA255 Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.

This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

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Copyright © Intel Corporation, 2003

AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

ii

Intel® PXA255 Processor Developer’s Manual

 

 

 

 

Contents

Contents

 

 

 

 

 

1

Introduction...................................................................................................................................

 

1-1

 

1.1

Intel® XScale™ Microarchitecture Features......................................................................

1-1

 

1.2

System Integration Features..............................................................................................

1-1

 

 

1.2.1

Memory Controller ................................................................................................

1-2

 

 

1.2.2

Clocks and Power Controllers...............................................................................

1-2

 

 

1.2.3

Universal Serial Bus (USB) Client.........................................................................

1-2

 

 

1.2.4

DMA Controller (DMAC) .......................................................................................

1-3

 

 

1.2.5

LCD Controller ......................................................................................................

1-3

 

 

1.2.6

AC97 Controller ....................................................................................................

1-3

 

 

1.2.7

Inter-IC Sound (I2S) Controller .............................................................................

1-3

 

 

1.2.8

Multimedia Card (MMC) Controller .......................................................................

1-3

 

 

1.2.9

Fast Infrared (FIR) Communication Port...............................................................

1-3

 

 

1.2.10

Synchronous Serial Protocol Controller (SSPC)...................................................

1-4

 

 

1.2.11

Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................

1-4

 

 

1.2.12

GPIO.....................................................................................................................

1-4

 

 

1.2.13

UARTs ..................................................................................................................

1-4

 

 

1.2.14

Real-Time Clock (RTC).........................................................................................

1-5

 

 

1.2.15

OS Timers.............................................................................................................

1-5

 

 

1.2.16

Pulse-Width Modulator (PWM) .............................................................................

1-5

 

 

1.2.17

Interrupt Control....................................................................................................

1-5

 

 

1.2.18

Network Synchronous Serial Protocol Port...........................................................

1-5

2

System Architecture .....................................................................................................................

2-1

 

2.1

Overview............................................................................................................................

2-1

 

2.2

Intel® XScale™ Microarchitecture Implementation Options..............................................

2-2

 

 

2.2.1

Coprocessor 7 Register 4 - PSFS Bit ...................................................................

2-2

 

 

2.2.2

Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................

2-3

 

 

2.2.3

Coprocessor 14 Register 6 and 7- Clock and Power Management......................

2-3

 

 

2.2.4

Coprocessor 15 Register 0 - ID Register Definition..............................................

2-3

 

 

2.2.5

Coprocessor 15 Register 1 - P-Bit ........................................................................

2-4

 

2.3

I/O Ordering .......................................................................................................................

2-5

 

2.4

Semaphores ......................................................................................................................

2-5

 

2.5

Interrupts............................................................................................................................

2-5

 

2.6

Reset .................................................................................................................................

 

2-6

 

2.7

Internal Registers...............................................................................................................

2-7

 

2.8

Selecting Peripherals vs. General Purpose I/O .................................................................

2-7

 

2.9

Power on Reset and Boot Operation .................................................................................

2-8

 

2.10

Power Management...........................................................................................................

2-8

 

2.11

Pin List ...............................................................................................................................

 

2-8

 

2.12

Memory Map....................................................................................................................

2-18

 

2.13

System Architecture Register Summary..........................................................................

2-21

3

Clocks and Power Manager .........................................................................................................

3-1

 

3.1

Clock Manager Introduction...............................................................................................

3-1

 

3.2

Power Manager Introduction..............................................................................................

3-2

 

3.3

Clock Manager...................................................................................................................

3-2

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Contents

 

 

 

 

 

3.3.1

32.768 kHz Oscillator............................................................................................

3-4

 

 

3.3.2

3.6864 MHz Oscillator ..........................................................................................

3-4

 

 

3.3.3

Core Phase Locked Loop .....................................................................................

3-4

 

 

3.3.4

95.85 MHz Peripheral Phase Locked Loop ..........................................................

3-5

 

 

3.3.5

147.46 MHz Peripheral Phase Locked Loop ........................................................

3-5

 

 

3.3.6

Clock Gating .........................................................................................................

3-6

 

3.4 Resets and Power Modes..................................................................................................

3-6

 

 

3.4.1

Hardware Reset....................................................................................................

3-6

 

 

3.4.2

Watchdog Reset ...................................................................................................

3-7

 

 

3.4.3

GPIO Reset ..........................................................................................................

3-8

 

 

3.4.4

Run Mode .............................................................................................................

3-9

 

 

3.4.5

Turbo Mode ..........................................................................................................

3-9

 

 

3.4.6

Idle Mode ............................................................................................................

3-10

 

 

3.4.7

Frequency Change Sequence............................................................................

3-11

 

 

3.4.8

33-MHz Idle Mode ..............................................................................................

3-13

 

 

3.4.9

Sleep Mode.........................................................................................................

3-15

 

 

3.4.10

Power Mode Summary .......................................................................................

3-20

 

3.5

Power Manager Registers ...............................................................................................

3-22

 

 

3.5.1

Power Manager Control Register (PMCR) .........................................................

3-23

 

 

3.5.2

Power Manager General Configuration Register (PCFR)...................................

3-24

 

 

3.5.3

Power Manager Wake-Up Enable Register (PWER)..........................................

3-25

 

 

3.5.4

Power Manager Rising-Edge Detect Enable Register (PRER) ..........................

3-26

 

 

3.5.5

Power Manager Falling-Edge Detect Enable Register (PFER) ..........................

3-27

 

 

3.5.6

Power Manager GPIO Edge Detect Status Register (PEDR).............................

3-28

 

 

3.5.7

Power Manager Sleep Status Register (PSSR) .................................................

3-29

 

 

3.5.8

Power Manager Scratch Pad Register (PSPR) ..................................................

3-30

 

 

3.5.9

Power Manager Fast Sleep Walk-up Configuration Register (PMFW)...............

3-31

 

 

3.5.10

Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2).........

3-31

 

 

3.5.11

Reset Controller Status Register (RCSR)...........................................................

3-33

 

3.6

Clocks Manager Registers...............................................................................................

3-34

 

 

3.6.1

Core Clock Configuration Register (CCCR) .......................................................

3-34

 

 

3.6.2

Clock Enable Register (CKEN)...........................................................................

3-36

 

 

3.6.3

Oscillator Configuration Register (OSCC) ..........................................................

3-38

 

3.7 Coprocessor 14: Clock and Power Management ............................................................

3-38

 

 

3.7.1

Core Clock Configuration Register (CCLKCFG).................................................

3-39

 

 

3.7.2

Power Mode Register (PWRMODE)...................................................................

3-40

 

3.8

External Hardware Considerations..................................................................................

3-40

 

 

3.8.1

Power-On-Reset Considerations ........................................................................

3-40

 

 

3.8.2

Power Supply Connectivity .................................................................................

3-40

 

 

3.8.3

Driving the Crystal Pins from an External Clock Source.....................................

3-41

 

 

3.8.4

Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............

3-41

 

3.9 Clocks and Power Manager Register Summary..............................................................

3-41

 

 

3.9.1

Clocks Manager Register Locations ...................................................................

3-41

 

 

3.9.2

Power Manager Register Summary....................................................................

3-41

4

System Integration Unit ................................................................................................................

4-1

 

4.1

General-Purpose I/O..........................................................................................................

4-1

 

 

4.1.1

GPIO Operation ....................................................................................................

4-1

 

 

4.1.2

GPIO Alternate Functions.....................................................................................

4-2

 

 

4.1.3

GPIO Register Definitions.....................................................................................

4-6

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Intel® PXA255 Processor Developer’s Manual

 

 

 

 

Contents

 

4.2

Interrupt Controller...........................................................................................................

4-20

 

 

4.2.1

Interrupt Controller Operation .............................................................................

4-20

 

 

4.2.2 Interrupt Controller Register Definitions..............................................................

4-21

 

4.3

Real-Time Clock (RTC) ...................................................................................................

4-28

 

 

4.3.1

Real-Time Clock Operation.................................................................................

4-28

 

 

4.3.2

RTC Register Definitions ....................................................................................

4-29

 

 

4.3.3

Trim Procedure ...................................................................................................

4-32

 

4.4

Operating System (OS) Timer .........................................................................................

4-34

 

 

4.4.1

Watchdog Timer Operation.................................................................................

4-35

 

 

4.4.2 OS Timer Register Definitions ............................................................................

4-35

 

4.5

Pulse Width Modulator.....................................................................................................

4-38

 

 

4.5.1 Pulse Width Modulator Operation.......................................................................

4-38

 

 

4.5.2

Register Descriptions..........................................................................................

4-40

 

 

4.5.3 Pulse Width Modulator Output Wave Example...................................................

4-43

 

4.6

System Integration Unit Register Summary.....................................................................

4-44

 

 

4.6.1

GPIO Register Locations ....................................................................................

4-44

 

 

4.6.2 Interrupt Controller Register Locations ...............................................................

4-45

 

 

4.6.3 Real-Time Clock Register Locations...................................................................

4-45

 

 

4.6.4 OS Timer Register Locations..............................................................................

4-45

 

 

4.6.5 Pulse Width Modulator Register Locations.........................................................

4-46

5

DMA Controller .............................................................................................................................

5-1

 

5.1

DMA Description................................................................................................................

5-1

 

 

5.1.1

DMAC Channels ...................................................................................................

5-2

 

 

5.1.2

Signal Descriptions ...............................................................................................

5-2

 

 

5.1.3

DMA Channel Priority Scheme .............................................................................

5-3

 

 

5.1.4

DMA Descriptors...................................................................................................

5-5

 

 

5.1.5

Channel States .....................................................................................................

5-8

 

 

5.1.6 Read and Write Order...........................................................................................

5-9

 

 

5.1.7

Byte Transfer Order ..............................................................................................

5-9

 

 

5.1.8

Trailing Bytes ......................................................................................................

5-10

 

5.2

Transferring Data.............................................................................................................

5-11

 

 

5.2.1

Servicing Internal Peripherals.............................................................................

5-11

 

 

5.2.2 Quick Reference for DMA Programming ............................................................

5-13

 

 

5.2.3 Servicing Companion Chips and External Peripherals .......................................

5-14

 

 

5.2.4

Memory-to-Memory Moves.................................................................................

5-16

 

5.3

DMAC Registers ..............................................................................................................

5-17

 

 

5.3.1

DMA Interrupt Register (DINT) ...........................................................................

5-17

 

 

5.3.2 DMA Channel Control/Status Register (DCSRx)................................................

5-17

 

 

5.3.3 DMA Request to Channel Map Registers (DRCMRx) ........................................

5-20

 

 

5.3.4 DMA Descriptor Address Registers (DDADRx) ..................................................

5-20

 

 

5.3.5 DMA Source Address Registers .........................................................................

5-21

 

 

5.3.6 DMA Target Address Registers (DTADRx).........................................................

5-22

 

 

5.3.7 DMA Command Registers (DCMDx) ..................................................................

5-23

 

5.4

Examples .........................................................................................................................

5-26

 

5.5

DMA Controller Register Summary .................................................................................

5-28

6

Memory Controller ........................................................................................................................

6-1

 

6.1

Overview............................................................................................................................

6-1

 

6.2

Functional Description .......................................................................................................

6-2

Intel® PXA255 Processor Developer’s Manual

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Contents

 

 

 

 

 

6.2.1

SDRAM Interface Overview..................................................................................

6-2

 

 

6.2.2

Static Memory Interface / Variable Latency I/O Interface .....................................

6-3

 

 

6.2.3

16-Bit PC Card / Compact Flash Interface ...........................................................

6-4

 

6.3

Memory System Examples ................................................................................................

6-4

 

6.4

Memory Accesses .............................................................................................................

6-7

 

 

6.4.1

Reads and Writes .................................................................................................

6-8

 

 

6.4.2

Aborts and Nonexistent Memory ..........................................................................

6-8

 

6.5

Synchronous DRAM Memory Interface .............................................................................

6-8

 

 

6.5.1

SDRAM MDCNFG Register (MDCNFG................................................................

6-8

 

 

6.5.2

SDRAM Mode Register Set Configuration Register (MDMRS) ..........................

6-12

 

 

6.5.3

SDRAM MDREFR Register (MDREFR) .............................................................

6-14

 

 

6.5.4

Fixed-Delay or Return-Clock Data Latching .......................................................

6-17

 

 

6.5.5

SDRAM Memory Options ...................................................................................

6-18

 

 

6.5.6

SDRAM Command Overview .............................................................................

6-27

 

 

6.5.7

SDRAM Waveforms............................................................................................

6-28

 

6.6

Synchronous Static Memory Interface.............................................................................

6-32

 

 

6.6.1

Synchronous Static Memory Configuration Register (SXCNFG)........................

6-32

 

 

6.6.2

Synchronous Static Memory Mode Register Set Configuration

 

 

 

 

Register (SXMRS) ..............................................................................................

6-37

 

 

6.6.3

Synchronous Static Memory Timing Diagrams...................................................

6-38

 

 

6.6.4

Non-SDRAM Timing SXMEM Operation ............................................................

6-39

 

6.7

Asynchronous Static Memory..........................................................................................

6-42

 

 

6.7.1

Static Memory Interface......................................................................................

6-42

 

 

6.7.2

Asynchronous Static Memory Control Registers (MSCx) ...................................

6-44

 

 

6.7.3

ROM Interface ....................................................................................................

6-48

 

 

6.7.4

SRAM Interface Overview ..................................................................................

6-51

 

 

6.7.5

Variable Latency I/O (VLIO) Interface Overview.................................................

6-53

 

 

6.7.6

FLASH Memory Interface ...................................................................................

6-56

 

6.8

16-Bit PC Card/Compact Flash Interface ........................................................................

6-58

 

 

6.8.1

Expansion Memory Timing Configuration Register ............................................

6-58

 

 

6.8.2

Expansion Memory Configuration Register (MECR) ..........................................

6-61

 

 

6.8.3

16-Bit PC Card Overview....................................................................................

6-62

 

 

6.8.4

External Logic for 16-Bit PC Card Implementation .............................................

6-64

 

 

6.8.5

Expansion Card Interface Timing Diagrams and Parameters ............................

6-67

 

6.9

Companion Chip Interface...............................................................................................

6-68

 

 

6.9.1

Alternate Bus Master Mode ................................................................................

6-70

 

6.10

Options and Settings for Boot Memory............................................................................

6-72

 

 

6.10.1

Alternate Booting ................................................................................................

6-72

 

 

6.10.2

Boot Time Defaults .............................................................................................

6-72

 

 

6.10.3

Memory Interface Reset and Initialization...........................................................

6-76

 

6.11

Hardware, Watchdog, or Sleep Reset Operation ............................................................

6-77

 

6.12

GPIO Reset Procedure....................................................................................................

6-79

 

6.13

Memory Controller Register Summary ............................................................................

6-79

7

LCD Controller

..............................................................................................................................

7-1

 

7.1

Overview............................................................................................................................

7-1

 

 

7.1.1

Features................................................................................................................

7-2

 

 

7.1.2

Pin Descriptions....................................................................................................

7-4

 

7.2

LCD Controller Operation ..................................................................................................

7-4

 

 

7.2.1

Enabling the Controller .........................................................................................

7-4

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Intel® PXA255 Processor Developer’s Manual

 

 

 

 

Contents

 

 

7.2.2

Disabling the Controller ........................................................................................

7-5

 

 

7.2.3

Resetting the Controller ........................................................................................

7-5

 

7.3

Detailed Module Descriptions ............................................................................................

7-5

 

 

7.3.1

Input FIFOs...........................................................................................................

7-5

 

 

7.3.2

Lookup Palette......................................................................................................

7-6

 

 

7.3.3

Temporal Modulated Energy Distribution (TMED) Dithering.................................

7-6

 

 

7.3.4

Output FIFOs ........................................................................................................

7-8

 

 

7.3.5

LCD Controller Pin Usage ....................................................................................

7-8

 

 

7.3.6

DMA......................................................................................................................

7-9

 

7.4

LCD External Palette and Frame Buffers ........................................................................

7-10

 

 

7.4.1

External Palette Buffer........................................................................................

7-10

 

 

7.4.2

External Frame Buffer.........................................................................................

7-11

 

7.5

Functional Timing ............................................................................................................

7-14

 

7.6

Register Descriptions.......................................................................................................

7-17

 

 

7.6.1

LCD Controller Control Register 0 (LCCR0).......................................................

7-18

 

 

7.6.2

LCD Controller Control Register 1 (LCCR1).......................................................

7-24

 

 

7.6.3

LCD Controller Control Register 2 (LCCR2).......................................................

7-26

 

 

7.6.4

LCD Controller Control Register 3 (LCCR3).......................................................

7-28

 

 

7.6.5

LCD Controller DMA ...........................................................................................

7-32

 

 

7.6.6

LCD DMA Frame Branch Registers (FBRx) .......................................................

7-37

 

 

7.6.7

LCD Controller Status Register (LCSR)..............................................................

7-38

 

 

7.6.8

LCD Controller Interrupt ID Register (LIIDR) ......................................................

7-41

 

 

7.6.9

TMED RGB Seed Register (TRGBR) .................................................................

7-42

 

 

7.6.10

TMED Control Register (TCR)............................................................................

7-43

 

7.7

LCD Controller Register Summary ..................................................................................

7-44

8

Synchronous Serial Port Controller ..............................................................................................

8-1

 

8.1

Overview............................................................................................................................

8-1

 

8.2

Signal Description..............................................................................................................

8-1

 

 

8.2.1

External Interface to Synchronous Serial Peripherals ..........................................

8-1

 

8.3

Functional Description .......................................................................................................

8-2

 

 

8.3.1

Data Transfer........................................................................................................

8-2

 

8.4

Data Formats .....................................................................................................................

8-2

 

 

8.4.1

Serial Data Formats for Transfer to/from Peripherals...........................................

8-2

 

 

8.4.2

Parallel Data Formats for FIFO Storage ...............................................................

8-6

 

8.5

FIFO Operation and Data Transfers ..................................................................................

8-7

 

 

8.5.1

Using Programmed I/O Data Transfers ................................................................

8-7

 

 

8.5.2

Using DMA Data Transfers...................................................................................

8-7

 

8.6

Baud-Rate Generation.......................................................................................................

8-7

 

8.7

SSP Serial Port Registers..................................................................................................

8-8

 

 

8.7.1

SSP Control Register 0 (SSCR0) .........................................................................

8-8

 

 

8.7.2

SSP Control Register 1 (SSCR1) .......................................................................

8-11

 

 

8.7.3

SSP Data Register (SSDR) ................................................................................

8-15

 

 

8.7.4

SSP Status Register (SSSR)..............................................................................

8-16

 

8.8

SSP Controller Register Summary ..................................................................................

8-19

9

I2C Bus Interface Unit...................................................................................................................

9-1

 

9.1

Overview............................................................................................................................

9-1

 

9.2

Signal Description..............................................................................................................

9-1

 

9.3

Functional Description .......................................................................................................

9-1

Intel® PXA255 Processor Developer’s Manual

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Contents

 

 

 

 

 

9.3.1

Operational Blocks................................................................................................

9-3

 

 

9.3.2 I2C Bus Interface Modes .....................................................................................

9-3

 

 

9.3.3

Start and Stop Bus States ....................................................................................

9-4

 

9.4

I2C Bus Operation .............................................................................................................

9-7

 

 

9.4.1

Serial Clock Line (SCL) Generation......................................................................

9-7

 

 

9.4.2

Data and Addressing Management ......................................................................

9-7

 

 

9.4.3

I2C Acknowledge..................................................................................................

9-8

 

 

9.4.4

Arbitration .............................................................................................................

9-9

 

 

9.4.5

Master Operations ..............................................................................................

9-12

 

 

9.4.6

Slave Operations ................................................................................................

9-14

 

 

9.4.7

General Call Address..........................................................................................

9-16

 

9.5

Slave Mode Programming Examples ..............................................................................

9-18

 

 

9.5.1

Initialize Unit .......................................................................................................

9-18

 

 

9.5.2

Write n Bytes as a Slave.....................................................................................

9-18

 

 

9.5.3

Read n Bytes as a Slave ....................................................................................

9-18

 

9.6

Master Programming Examples ......................................................................................

9-19

 

 

9.6.1

Initialize Unit .......................................................................................................

9-19

 

 

9.6.2

Write 1 Byte as a Master ....................................................................................

9-19

 

 

9.6.3

Read 1 Byte as a Master ....................................................................................

9-20

 

 

9.6.4

Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................

9-20

 

 

9.6.5

Read 2 Bytes as a Master - Send STOP Using the Abort ..................................

9-21

 

9.7

Glitch Suppression Logic .................................................................................................

9-21

 

9.8

Reset Conditions .............................................................................................................

9-21

 

9.9

Register Definitions..........................................................................................................

9-22

 

 

9.9.1

I2C Bus Monitor Register (IBMR) .......................................................................

9-22

 

 

9.9.2

I2C Data Buffer Register (IDBR).........................................................................

9-22

 

 

9.9.3

I2C Control Register (ICR)..................................................................................

9-23

 

 

9.9.4

I2C Status Register (ISR) ...................................................................................

9-25

 

 

9.9.5

I2C Slave Address Register (ISAR)....................................................................

9-27

10

UARTs........................................................................................................................................

 

10-1

 

10.1

Feature List......................................................................................................................

10-1

 

10.2

Overview..........................................................................................................................

10-2

 

 

10.2.1

Full Function UART ............................................................................................

10-2

 

 

10.2.2

Bluetooth UART..................................................................................................

10-2

 

 

10.2.3

Standard UART ..................................................................................................

10-2

 

 

10.2.4

Compatibility with 16550.....................................................................................

10-2

 

10.3

Signal Descriptions..........................................................................................................

10-3

 

10.4

UART Operational Description ........................................................................................

10-4

 

 

10.4.1

Reset ..................................................................................................................

10-5

 

 

10.4.2

Internal Register Descriptions.............................................................................

10-5

 

 

10.4.3

FIFO Interrupt Mode Operation ........................................................................

10-21

 

 

10.4.4

FIFO Polled Mode Operation............................................................................

10-22

 

 

10.4.5

DMA Requests..................................................................................................

10-22

 

 

10.4.6

Slow Infrared Asynchronous Interface..............................................................

10-23

 

10.5

UART Register Summary ..............................................................................................

10-26

 

 

10.5.1

UART Register Differences ..............................................................................

10-28

11

Fast Infrared Communication Port..............................................................................................

11-1

 

11.1

Signal Description............................................................................................................

11-1

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Intel® PXA255 Processor Developer’s Manual

 

 

 

Contents

11.2

FICP Operation................................................................................................................

11-1

 

11.2.1

4PPM Modulation ...............................................................................................

11-2

 

11.2.2

Frame Format .....................................................................................................

11-3

 

11.2.3

Address Field......................................................................................................

11-3

 

11.2.4

Control Field .......................................................................................................

11-3

 

11.2.5

Data Field ...........................................................................................................

11-3

 

11.2.6

CRC Field ...........................................................................................................

11-4

 

11.2.7

Baud Rate Generation ........................................................................................

11-4

 

11.2.8

Receive Operation ..............................................................................................

11-4

 

11.2.9

Transmit Operation .............................................................................................

11-5

 

11.2.10

Transmit and Receive FIFOs..............................................................................

11-6

 

11.2.11 Trailing or Error Bytes in the Receive FIFO........................................................

11-7

11.3

FICP Register Definitions ................................................................................................

11-7

 

11.3.1

FICP Control Register 0 (ICCR0)........................................................................

11-8

 

11.3.2

FICP Control Register 1 (ICCR1)......................................................................

11-10

 

11.3.3

FICP Control Register 2 (ICCR2)......................................................................

11-11

 

11.3.4

FICP Data Register (ICDR)...............................................................................

11-12

 

11.3.5

FICP Status Register 0 (ICSR0) .......................................................................

11-13

 

11.3.6

FICP Status Register 1 (ICSR1) .......................................................................

11-15

11.4

FICP Register Summary................................................................................................

11-16

12 USB Device Controller................................................................................................................

12-1

12.1

USB Overview .................................................................................................................

12-1

12.2

Device Configuration .......................................................................................................

12-2

12.3

USB Protocol ...................................................................................................................

12-2

 

12.3.1

Signalling Levels.................................................................................................

12-3

 

12.3.2

Bit Encoding........................................................................................................

12-3

 

12.3.3

Field Formats......................................................................................................

12-4

 

12.3.4

Packet Formats...................................................................................................

12-5

 

12.3.5

Transaction Formats...........................................................................................

12-6

 

12.3.6

UDC Device Requests........................................................................................

12-8

 

12.3.7

Configuration ......................................................................................................

12-9

12.4

UDC Hardware Connection ...........................................................................................

12-10

 

12.4.1

Self-Powered Device ........................................................................................

12-10

 

12.4.2

Bus-Powered Devices ......................................................................................

12-12

12.5

UDC Operation ..............................................................................................................

12-12

 

12.5.1

Case 1: EP0 Control Read ...............................................................................

12-12

 

12.5.2

Case 2: EP0 Control Read with a Premature Status Stage..............................

12-13

 

12.5.3

Case 3: EP0 Control Write With or Without a Premature Status

 

 

 

Stage ................................................................................................................

12-14

 

12.5.4

Case 4: EP0 No Data Command......................................................................

12-15

 

12.5.5

Case 5: EP1 Data Transmit (BULK-IN).............................................................

12-15

 

12.5.6

Case 6: EP2 Data Receive (BULK-OUT)..........................................................

12-16

 

12.5.7

Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)...........................................

12-17

 

12.5.8

Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................

12-18

 

12.5.9

Case 9: EP5 Data Transmit (INTERRUPT-IN) .................................................

12-20

 

12.5.10

Case 10: RESET Interrupt ................................................................................

12-20

 

12.5.11

Case 11: SUSPEND Interrupt...........................................................................

12-21

 

12.5.12 Case 12: RESUME Interrupt.............................................................................

12-21

12.6

UDC Register Definitions...............................................................................................

12-21

Intel® PXA255 Processor Developer’s Manual

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Contents

 

 

 

 

12.6.1

UDC Control Register (UDCCR).......................................................................

12-22

 

12.6.2

UDC Control Function Register (UDCCFR)......................................................

12-24

 

12.6.3

UDC Endpoint 0 Control/Status Register (UDCCS0) .......................................

12-25

 

12.6.4

UDC Endpoint x Control/Status Register (UDCCS1/6/11)................................

12-27

 

12.6.5

UDC Endpoint x Control/Status Register (UDCCS2/7/12)................................

12-29

 

12.6.6

UDC Endpoint x Control/Status Register (UDCCS3/8/13)................................

12-31

 

12.6.7

UDC Endpoint x Control/Status Register (UDCCS4/9/14)................................

12-32

 

12.6.8

UDC Endpoint x Control/Status Register (UDCCS5/10/15)..............................

12-34

 

12.6.9

UDC Interrupt Control Register 0 (UICR0) .......................................................

12-36

 

12.6.10

UDC Interrupt Control Register 1 (UICR1) .......................................................

12-38

 

12.6.11

UDC Status/Interrupt Register 0 (USIR0) .........................................................

12-39

 

12.6.12 UDC Status/Interrupt Register 1 (USIR1) .........................................................

12-41

 

12.6.13 UDC Frame Number High Register (UFNHR) ..................................................

12-42

 

12.6.14 UDC Frame Number Low Register (UFNLR) ...................................................

12-44

 

12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14) ...........................................

12-44

 

12.6.16 UDC Endpoint 0 Data Register (UDDR0) .........................................................

12-45

 

12.6.17 UDC Endpoint x Data Register (UDDR1/6/11) .................................................

12-46

 

12.6.18 UDC Endpoint x Data Register (UDDR2/7/12) .................................................

12-46

 

12.6.19 UDC Endpoint x Data Register (UDDR3/8/13) .................................................

12-47

 

12.6.20 UDC Endpoint x Data Register (UDDR4/9/14) .................................................

12-47

 

12.6.21 UDC Endpoint x Data Register (UDDR5/10/15) ...............................................

12-48

12.7

USB Device Controller Register Summary....................................................................

12-48

13 AC’97

Controller Unit..................................................................................................................

13-1

13.1

Overview..........................................................................................................................

13-1

13.2

Feature List......................................................................................................................

13-1

13.3

Signal Description............................................................................................................

13-2

 

13.3.1

Signal Configuration Steps .................................................................................

13-2

 

13.3.2

Example AC-link .................................................................................................

13-2

13.4

AC-link Digital Serial Interface Protocol...........................................................................

13-3

 

13.4.1

AC-link Audio Output Frame (SDATA_OUT)......................................................

13-4

 

13.4.2

AC-link Audio Input Frame (SDATA_IN).............................................................

13-8

13.5

AC-link Low Power Mode ..............................................................................................

13-12

 

13.5.1

Powering Down the AC-link ..............................................................................

13-12

 

13.5.2

Waking up the AC-link ......................................................................................

13-13

13.6

ACUNIT Operation.........................................................................................................

13-14

 

13.6.1

Initialization .......................................................................................................

13-15

 

13.6.2

Trailing bytes ....................................................................................................

13-17

 

13.6.3

Operational Flow for Accessing CODEC Registers..........................................

13-17

13.7

Clocks and Sampling Frequencies ................................................................................

13-17

13.8

Functional Description ...................................................................................................

13-18

 

13.8.1

FIFOs................................................................................................................

13-18

 

13.8.2

Interrupts...........................................................................................................

13-19

 

13.8.3

Registers...........................................................................................................

13-19

13.9

AC’97 Register Summary ..............................................................................................

13-35

14 Inter-Integrated-Circuit Sound (I2S) Controller...........................................................................

14-1

14.1

Overview..........................................................................................................................

14-1

14.2

Signal Descriptions..........................................................................................................

14-2

14.3

Controller Operation ........................................................................................................

14-3

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Intel® PXA255 Processor Developer’s Manual

 

 

 

Contents

 

14.3.1

Initialization .........................................................................................................

14-3

 

14.3.2

Disabling and Enabling Audio Replay.................................................................

14-4

 

14.3.3

Disabling and Enabling Audio Record ................................................................

14-4

 

14.3.4

Transmit FIFO Errors..........................................................................................

14-5

 

14.3.5

Receive FIFO Errors...........................................................................................

14-5

 

14.3.6

Trailing Bytes ......................................................................................................

14-5

14.4 Serial Audio Clocks and Sampling Frequencies..............................................................

14-5

14.5

Data Formats ...................................................................................................................

14-6

 

14.5.1

FIFO and Memory Format ..................................................................................

14-6

 

14.5.2

I2S and MSB-Justified Serial Audio Formats......................................................

14-6

14.6

Registers..........................................................................................................................

14-8

 

14.6.1

Serial Audio Controller Global Control Register (SACR0) ..................................

14-8

 

14.6.2

Serial Audio Controller I2S/MSB-Justified Control Register

 

 

 

(SACR1) ...........................................................................................................

14-10

 

14.6.3

Serial Audio Controller I2S/MSB-Justified Status Register

 

 

 

(SASR0)............................................................................................................

14-11

 

14.6.4

Serial Audio Clock Divider Register (SADIV)....................................................

14-12

 

14.6.5

Serial Audio Interrupt Clear Register (SAICR)..................................................

14-13

 

14.6.6

Serial Audio Interrupt Mask Register (SAIMR) .................................................

14-14

 

14.6.7

Serial Audio Data Register (SADR) ..................................................................

14-14

14.7

Interrupts........................................................................................................................

14-15

14.8 I2S Controller Register Summary ..................................................................................

14-15

15 MultiMediaCard Controller..........................................................................................................

15-1

15.1

Overview..........................................................................................................................

15-1

15.2 MMC Controller Functional Description ...........................................................................

15-4

 

15.2.1

Signal Description...............................................................................................

15-6

 

15.2.2

MMC Controller Reset ........................................................................................

15-6

 

15.2.3

Card Initialization Sequence ...............................................................................

15-6

 

15.2.4

MMC and SPI Modes..........................................................................................

15-6

 

15.2.5

Error Detection....................................................................................................

15-8

 

15.2.6

Interrupts.............................................................................................................

15-8

 

15.2.7

Clock Control ......................................................................................................

15-9

 

15.2.8

Data FIFOs .......................................................................................................

15-10

15.3

Card Communication Protocol.......................................................................................

15-12

 

15.3.1

Basic, No Data, Command and Response Sequence......................................

15-13

 

15.3.2

Data Transfer....................................................................................................

15-13

 

15.3.3

Busy Sequence.................................................................................................

15-16

 

15.3.4

SPI Functionality...............................................................................................

15-17

15.4

MultiMediaCard Controller Operation ............................................................................

15-17

 

15.4.1

Start and Stop Clock.........................................................................................

15-17

 

15.4.2

Initialize.............................................................................................................

15-17

 

15.4.3

Enabling SPI Mode ...........................................................................................

15-17

 

15.4.4

No Data Command and Response Sequence..................................................

15-18

 

15.4.5

Erase ................................................................................................................

15-18

 

15.4.6

Single Data Block Write ....................................................................................

15-18

 

15.4.7

Single Block Read ............................................................................................

15-19

 

15.4.8

Multiple Block Write ..........................................................................................

15-20

 

15.4.9

Multiple Block Read ..........................................................................................

15-20

 

15.4.10 Stream Write.....................................................................................................

15-21

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Contents

 

 

 

 

 

15.4.11 Stream Read.....................................................................................................

15-21

 

15.5

MMC Controller Registers .............................................................................................

15-22

 

 

15.5.1

MMC_STRPCL Register...................................................................................

15-22

 

 

15.5.2

MMC_Status Register (MMC_STAT) ...............................................................

15-23

 

 

15.5.3

MMC_CLKRT Register (MMC_CLKRT) ...........................................................

15-24

 

 

15.5.4

MMC_SPI Register (MMC_SPI) .......................................................................

15-25

 

 

15.5.5

MMC_CMDAT Register (MMC_CMDAT) .........................................................

15-26

 

 

15.5.6

MMC_RESTO Register (MMC_RESTO) ..........................................................

15-27

 

 

15.5.7

MMC_RDTO Register (MMC_RDTO) ..............................................................

15-28

 

 

15.5.8

MMC_BLKLEN Register (MMC_BLKLEN) .......................................................

15-29

 

 

15.5.9

MMC_NOB Register (MMC_NOB) ...................................................................

15-29

 

 

15.5.10 MMC_PRTBUF Register (MMC_PRTBUF) ......................................................

15-30

 

 

15.5.11 MMC_I_MASK Register (MMC_I_MASK) ........................................................

15-30

 

 

15.5.12 MMC_I_REG Register (MMC_I_REG) .............................................................

15-31

 

 

15.5.13 MMC_CMD Register (MMC_CMD) ..................................................................

15-33

 

 

15.5.14 MMC_ARGH Register (MMC_ARGH) ..............................................................

15-35

 

 

15.5.15 MMC_ARGL Register (MMC_ARGL) ...............................................................

15-35

 

 

15.5.16 MMC_RES FIFO...............................................................................................

15-36

 

 

15.5.17 MMC_RXFIFO FIFO.........................................................................................

15-36

 

 

15.5.18 MMC_TXFIFO FIFO .........................................................................................

15-37

 

15.6

MultiMediaCard Controller Register Summary ..............................................................

15-37

16

Network SSP Serial Port ............................................................................................................

16-1

 

16.1

Overview..........................................................................................................................

16-1

 

16.2

Features...........................................................................................................................

16-1

 

16.3

Signal Description............................................................................................................

16-2

 

16.4

Operation.........................................................................................................................

16-2

 

 

16.4.1 Processor and DMA FIFO Access......................................................................

16-2

 

 

16.4.2 Trailing Bytes in the Receive FIFO .....................................................................

16-3

 

 

16.4.3

Data Formats ......................................................................................................

16-3

 

 

16.4.4

Hi-Z on SSPTXD...............................................................................................

16-13

 

 

16.4.5

FIFO Operation.................................................................................................

16-17

 

 

16.4.6

Baud-Rate Generation......................................................................................

16-17

 

16.5

Register Descriptions.....................................................................................................

16-18

 

 

16.5.1 SSP Control Register 0 (SSCR0) .....................................................................

16-18

 

 

16.5.2 SSP Control Register 1 (SSCR1) .....................................................................

16-20

 

 

16.5.3 SSP Programmable Serial Protocol Register (SSPSP)....................................

16-22

 

 

16.5.4 SSP Time Out Register (SSTO) .......................................................................

16-24

 

 

16.5.5 SSP Interrupt Test Register (SSITR)................................................................

16-24

 

 

16.5.6 SSP Status Register (SSSR)............................................................................

16-25

 

 

16.5.7 SSP Data Register (SSDR) ..............................................................................

16-28

 

16.6

Network SSP Serial Port Register Summary.................................................................

16-29

17

Hardware UART .........................................................................................................................

17-1

 

17.1

Overview..........................................................................................................................

17-1

 

17.2

Features...........................................................................................................................

17-1

 

17.3

Signal Descriptions..........................................................................................................

17-3

 

17.4

Operation.........................................................................................................................

17-3

 

 

17.4.1

Reset ..................................................................................................................

17-4

 

 

17.4.2

FIFO Operation...................................................................................................

17-4

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Intel® PXA255 Processor Developer’s Manual

 

 

 

 

Contents

 

 

17.4.3

Autoflow Control .................................................................................................

17-7

 

 

17.4.4

Auto-Baud-Rate Detection..................................................................................

17-7

 

 

17.4.5

Slow Infrared Asynchronous Interface................................................................

17-8

 

17.5

Register Descriptions.....................................................................................................

17-10

 

 

17.5.1

Receive Buffer Register (RBR).........................................................................

17-10

 

 

17.5.2

Transmit Holding Register (THR)......................................................................

17-10

 

 

17.5.3

Divisor Latch Registers (DLL and DLH)............................................................

17-10

 

 

17.5.4

Interrupt Enable Register (IER) ........................................................................

17-11

 

 

17.5.5

Interrupt Identification Register (IIR).................................................................

17-13

 

 

17.5.6

FIFO Control Register (FCR)............................................................................

17-15

 

 

17.5.7

Receive FIFO Occupancy Register (FOR) .......................................................

17-16

 

 

17.5.8

Auto-Baud Control Register (ABR) ...................................................................

17-17

 

 

17.5.9

Auto-Baud Count Register (ACR).....................................................................

17-17

 

 

17.5.10

Line Control Register (LCR)..............................................................................

17-18

 

 

17.5.11

Line Status Register (LSR) ...............................................................................

17-19

 

 

17.5.12

Modem Control Register (MCR) .......................................................................

17-21

 

 

17.5.13

Modem Status Register (MSR).........................................................................

17-23

 

 

17.5.14

Scratchpad Register (SCR) ..............................................................................

17-24

 

 

17.5.15 Infrared Selection Register (ISR)......................................................................

17-24

 

17.6

Hardware UART Register Summary..............................................................................

17-25

Figures

 

 

 

2-1

Block Diagram ...........................................................................................................................

2-2

2-2

Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF..........................................

2-19

2-3

Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF ..........................................

2-20

3-1

Clocks Manager Block Diagram ................................................................................................

3-3

4-1

General-Purpose I/O Block Diagram .........................................................................................

4-2

4-2

Interrupt Controller Block Diagram ..........................................................................................

4-21

4-3

PWMn Block Diagram..............................................................................................................

4-39

4-4

Basic Pulse Width Waveform ..................................................................................................

4-43

5-1

DMAC Block Diagram................................................................................................................

5-1

5-2

DREQ timing requirements........................................................................................................

5-3

5-3

No-Descriptor Fetch Mode Channel State.................................................................................

5-6

5-4

Descriptor Fetch Mode Channel State.......................................................................................

5-8

5-5

Little Endian Transfers.............................................................................................................

5-10

6-1

General Memory Interface Configuration...................................................................................

6-2

6-2

SDRAM Memory System Example............................................................................................

6-5

6-3

Static Memory System Example................................................................................................

6-6

6-4

External to Internal Address Mapping Options ........................................................................

6-19

6-5

Basic SDRAM Timing Parameters...........................................................................................

6-29

6-6

SDRAM_Read_diffbank_diffrow ..............................................................................................

6-29

6-7

SDRAM_read_samebank_diffrow ...........................................................................................

6-30

6-8

SDRAM_read_samebank_samerow .......................................................................................

6-30

6-9

SDRAM_write ..........................................................................................................................

6-31

6-10

SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions.....................................................

6-31

6-11

SDRAM 4-Beat Write / 4-Write Same Bank, Same Row .........................................................

6-32

6-12

SMROM Read Timing Diagram Half-Memory Clock Frequency .............................................

6-39

6-13

Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................

6-41

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Contents

 

6-14

Flash Memory Reset Using State Machine .............................................................................

6-42

6-15

Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................

6-42

6-16

MSC0/1/2.................................................................................................................................

6-45

6-17

32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4,

 

 

MSC0[RDN] = 1, MSC0[RRR] = 1)..........................................................................................

6-49

6-18

Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash

 

 

(MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 0) .............................................................

6-50

6-19

32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data

 

 

Beats (MSC0[RDF] = 4, MSC0[RRR] = 1)...............................................................................

6-51

6-20

32-Bit SRAM Write Timing Diagram (4-beat Burst (MSC0[RDN] = 2,

 

 

MSC0[RRR] = 1)......................................................................................................................

6-52

6-21

32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per

 

 

Beat) (MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1) ...................................................

6-54

6-22

32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles

 

 

Per Beat) .................................................................................................................................

6-55

6-23

Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) .................................................

6-57

6-24

MCMEM1.................................................................................................................................

6-58

6-25

MCATT1 ..................................................................................................................................

6-58

6-26

16-Bit PC Card Memory Map ..................................................................................................

6-62

6-27

Expansion Card External Logic for a One-Socket Configuration.............................................

6-65

6-28

Expansion Card External Logic for a Two-Socket Configuration.............................................

6-66

6-29

16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................

6-67

6-30

16-Bit PC Card I/O 16-Bit Access to 8-Bit Device ...................................................................

6-68

6-31

Alternate Bus Master Mode .....................................................................................................

6-69

6-32

Variable Latency IO .................................................................................................................

6-69

6-33

Asynchronous Boot Time Configurations and Register Defaults.............................................

6-74

6-34

SMROM Boot Time Configurations and Register Defaults......................................................

6-75

6-35

SMROM Boot Time Configurations and Register Defaults......................................................

6-76

7-1

LCD Controller Block Diagram ..................................................................................................

7-3

7-2

Temporal Dithering Concept - Single Color...............................................................................

7-6

7-3

Compare Range for TMED........................................................................................................

7-7

7-4

TMED Block Diagram ...............................................................................................................

7-8

7-5

Palette Buffer Format ..............................................................................................................

7-11

7-6

1 Bit Per Pixel Data Memory Organization ..............................................................................

7-11

7-7

2 Bits Per Pixel Data Memory Organization ............................................................................

7-12

7-8

4 Bits Per Pixel Data Memory Organization ............................................................................

7-12

7-9

8 Bits Per Pixel Data Memory Organization ............................................................................

7-12

7-10

16 Bits Per Pixel Data Memory Organization - Passive Mode ................................................

7-13

7-11

16 Bits Per Pixel Data Memory Organization - Active Mode ...................................................

7-13

7-12

Passive Mode Start-of-Frame Timing......................................................................................

7-15

7-13

Passive Mode End-of-Frame Timing .......................................................................................

7-15

7-14

Passive Mode Pixel Clock and Data Pin Timing......................................................................

7-16

7-15

Active Mode Timing .................................................................................................................

7-16

7-16

Active Mode Pixel Clock and Data Pin Timing ........................................................................

7-17

7-17

Frame Buffer/Palette Output to LCD Data Pins in Active Mode ..............................................

7-20

7-18

LCD Data-Pin Pixel Ordering...................................................................................................

7-22

8-1

Texas Instruments’ Synchronous Serial Frame* Format...........................................................

8-4

8-2

Motorola SPI* Frame Format.....................................................................................................

8-5

8-3

National Microwire* Frame Format............................................................................................

8-6

8-4

Motorola SPI* Frame Formats for SPO and SPH Programming .............................................

8-13

9-1

I2C Bus Configuration Example.................................................................................................

9-2

xiv

Intel® PXA255 Processor Developer’s Manual

 

 

Contents

9-2

Start and Stop Conditions..........................................................................................................

9-5

9-3

START and STOP Conditions ...................................................................................................

9-6

9-4

Data Format of First Byte in Master Transaction .......................................................................

9-8

9-5

Acknowledge on the I2C Bus.....................................................................................................

9-9

9-6

Clock Synchronization During the Arbitration Procedure.........................................................

9-10

9-7

Arbitration Procedure of Two Masters .....................................................................................

9-11

9-8

Master-Receiver Read from Slave-Transmitter .......................................................................

9-14

9-9

Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-Transmitter

 

 

Write to Slave-Receiver ...........................................................................................................

9-14

9-10

A Complete Data Transfer.......................................................................................................

9-14

9-11

Master-Transmitter Write to Slave-Receiver............................................................................

9-16

9-12

Master-Receiver Read to Slave-Transmitter ...........................................................................

9-16

9-13

Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter

 

 

Write to Slave-Receiver ...........................................................................................................

9-16

9-14

General Call Address...............................................................................................................

9-17

10-1

Example UART Data Frame ....................................................................................................

10-4

10-2

Example NRZ Bit Encoding – (0b0100 1011 ...........................................................................

10-5

10-3

IR Transmit and Receive Example ........................................................................................

10-25

10-4

XMODE Example...................................................................................................................

10-25

11-1

4PPM Modulation Encodings...................................................................................................

11-2

11-2

4PPM Modulation Example .....................................................................................................

11-2

11-3

Frame Format for IrDA Transmission (4.0 Mbps) ....................................................................

11-3

12-1

NRZI Bit Encoding Example ....................................................................................................

12-4

12-2

Self-Powered Device .............................................................................................................

12-11

13-1

Data Transfer Through the AC-link..........................................................................................

13-3

13-2

AC’97 Standard Bidirectional Audio Frame .............................................................................

13-4

13-3

AC-link Audio Output Frame....................................................................................................

13-5

13-4

Start of Audio Output Frame....................................................................................................

13-5

13-5

AC’97 Input Frame...................................................................................................................

13-9

13-6

Start of an Audio Input Frame..................................................................................................

13-9

13-7

AC-link Powerdown Timing....................................................................................................

13-12

13-8

SDATA_IN Wake Up Signaling..............................................................................................

13-13

13-9

PCM Transmit and Receive Operation ..................................................................................

13-27

13-10

Mic-in Receive-Only Operation..............................................................................................

13-29

13-11

Modem Transmit and Receive Operation ..............................................................................

13-32

14-1

I2S Data Formats (16 bits).......................................................................................................

14-7

14-2

MSB-Justified Data Formats (16 bits .......................................................................................

14-7

14-3

Transmit and Receive FIFO Accesses Through the SADR...................................................

14-15

15-1

MMC System Interaction .........................................................................................................

15-1

15-2

MMC Mode Operation Without Data Token.............................................................................

15-3

15-3

MMC Mode Operation With Data Token..................................................................................

15-3

15-4

SPI Mode Operation Without Data Token ...............................................................................

15-4

15-5

SPI Mode Read Operation.......................................................................................................

15-4

15-6

SPI Mode Write Operation.......................................................................................................

15-4

16-1

Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers) .........................

16-5

16-2

Texas Instruments Synchronous Serial Frame* Protocol (single transfers) ............................

16-6

16-3

Motorola SPI* Frame Protocol (multiple transfers) ..................................................................

16-7

16-4

Motorola SPI* Frame Protocol (single transfers) .....................................................................

16-7

16-5

Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple

 

 

transfers)..................................................................................................................................

16-8

Intel® PXA255 Processor Developer’s Manual

xv

Contents

 

16-6

Motorola SPI* Frame Protocols for SPO and SPH Programming (single

 

 

transfers) .................................................................................................................................

16-9

16-7

National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................

16-10

16-8

National Semiconductor Microwire* Frame Protocol (single transfers) .................................

16-10

16-9

Programmable Serial Protocol (multiple transfers)................................................................

16-11

16-10

Programmable Serial Protocol (single transfers)...................................................................

16-12

16-11

TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................

16-13

16-12

TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................

16-14

16-13

Motorola SPI with SSCR[TTE]=1...........................................................................................

16-14

16-14

National Semiconductor Microwire with SSCR1[TTE]=1.......................................................

16-15

16-15

PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame).............................

16-15

16-16

PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) ..........................

16-16

16-17

PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to

 

 

frame) ....................................................................................................................................

16-16

17-1

Example UART Data Frame....................................................................................................

17-3

17-2

Example NRZ Bit Encoding – (0b0100 1011...........................................................................

17-4

17-3

IR Transmit and Receive Example ..........................................................................................

17-9

17-4

XMODE Example. ...................................................................................................................

17-9

Tables

 

2-1

CPU Core Fault Register Bit Definitions....................................................................................

2-3

2-2

ID Bit Definitions ........................................................................................................................

2-4

2-3

PXA255 Processor ID Values....................................................................................................

2-4

2-4

Effect of Each Type of Reset on Internal Register State ...........................................................

2-6

2-5

Processor Pin Types .................................................................................................................

2-8

2-6

Pin & Signal Descriptions for the PXA255 Processor................................................................

2-9

2-7

Pin Description Notes ..............................................................................................................

2-17

2-8

System Architecture Register Address Summary ...................................................................

2-21

3-1

Core PLL Output Frequencies for 3.6864 MHz Crystal .............................................................

3-5

3-2

95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ..................................

3-5

3-3

147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ................................

3-6

3-4

Power Mode Entry Sequence Table.......................................................................................

3-20

3-5

Power Mode Exit Sequence Table .........................................................................................

3-20

3-6

Power and Clock Supply Sources and States During Power Modes .....................................

3-22

3-7

PMCR Bit Definitions ...............................................................................................................

3-23

3-8

PCFR Bit Definitions................................................................................................................

3-24

3-9

PWER Bit Definitions...............................................................................................................

3-25

3-10

PRER Bit Definitions................................................................................................................

3-26

3-11

PFER Bit Definitions ................................................................................................................

3-27

3-12

PEDR Bit Definitions................................................................................................................

3-28

3-13

PSSR Bit Definitions................................................................................................................

3-29

3-14

PSPR Bit Definitions................................................................................................................

3-30

3-15

PMFW Register Bitmap and Bit Definitions .............................................................................

3-31

3-16

PGSR0 Bit Definitions .............................................................................................................

3-32

3-17

PGSR1 Bit Definitions .............................................................................................................

3-32

3-18

PGSR2 Bit Definitions .............................................................................................................

3-33

3-19

RCSR Bit Definitions ...............................................................................................................

3-34

3-20

CCCR Bit Definitions ...............................................................................................................

3-35

xvi

Intel® PXA255 Processor Developer’s Manual

 

 

Contents

3-21

CKEN Bit Definitions................................................................................................................

3-36

3-22

OSCC Bit Definitions ...............................................................................................................

3-38

3-23

Coprocessor 14 Clock and Power Management Summary.....................................................

3-39

3-24

CCLKCFG Bit Definitions.........................................................................................................

3-39

3-25

PWRMODE Bit Definitions.......................................................................................................

3-40

3-26

Clocks Manager Register Summary ........................................................................................

3-41

3-27

Power Manager Register Summary.........................................................................................

3-42

4-1

GPIO Alternate Functions..........................................................................................................

4-3

4-2

GPIO Register Definitions..........................................................................................................

4-6

4-3

GPLR0 Bit Definitions ................................................................................................................

4-7

4-4

GPLR1 Bit Definitions ................................................................................................................

4-8

4-5

GPLR2 Bit Definitions ................................................................................................................

4-8

4-6

GPDR0 Bit Definitions ...............................................................................................................

4-9

4-7

GPDR1 Bit Definitions ...............................................................................................................

4-9

4-8

GPDR2 Bit Definitions ...............................................................................................................

4-9

4-9

GPSR0 Bit Definitions..............................................................................................................

4-10

4-10

GPSR1 Bit Definitions..............................................................................................................

4-10

4-11

GPSR2 Bit Definitions..............................................................................................................

4-11

4-12

GPCR0 Bit Definitions .............................................................................................................

4-11

4-13

GPCR1 Bit Definitions .............................................................................................................

4-11

4-14

GPCR2 Bit Definitions .............................................................................................................

4-12

4-15

GRER0 Bit Definitions .............................................................................................................

4-13

4-16

GRER1 Bit Definitions .............................................................................................................

4-13

4-17

GRER2 Bit Definitions .............................................................................................................

4-13

4-18

GFER0 Bit Definitions..............................................................................................................

4-14

4-19

GFER1 Bit Definitions..............................................................................................................

4-14

4-20

GFER2 Bit Definitions..............................................................................................................

4-14

4-21

GEDR0 Bit Definitions .............................................................................................................

4-15

4-22

GEDR1 Bit Definitions .............................................................................................................

4-15

4-23

GEDR2 Bit Definitions .............................................................................................................

4-16

4-24

GAFR0_L Bit Definitions..........................................................................................................

4-17

4-25

GAFR0_U Bit Definitions .........................................................................................................

4-17

4-26

GAFR1_L Bit Definitions..........................................................................................................

4-18

4-27

GAFR1_U Bit Definitions .........................................................................................................

4-18

4-28

GAFR2_L Bit Definitions..........................................................................................................

4-19

4-29

GAFR2_U Bit Definitions .........................................................................................................

4-19

4-30

ICMR Bit Definitions.................................................................................................................

4-22

4-31

ICLR Bit Definitions..................................................................................................................

4-23

4-32

ICCR Bit Definitions .................................................................................................................

4-23

4-33

ICIP Bit Definitions...................................................................................................................

4-24

4-34

ICFP Bit Definitions..................................................................................................................

4-24

4-35

ICPR Bit Definitions .................................................................................................................

4-25

4-36

List of First–Level Interrupts ....................................................................................................

4-27

4-37

RTTR Bit Definitions ................................................................................................................

4-30

4-38

RTAR Bit Definitions ................................................................................................................

4-30

4-39

RCNR Bit Definitions ...............................................................................................................

4-31

4-40

RTSR Bit Definitions ................................................................................................................

4-32

4-41

OSMR[x] Bit Definitions ...........................................................................................................

4-36

4-42

OIER Bit Definitions.................................................................................................................

4-36

4-43

OWER Bit Definitions...............................................................................................................

4-37

Intel® PXA255 Processor Developer’s Manual

xvii

Contents

 

4-44

OSCR Bit Definitions ...............................................................................................................

4-37

4-45

OSSR Bit Definitions ...............................................................................................................

4-38

4-46

PWM_CTRLn Bit Definitions ...................................................................................................

4-41

4-47

PWM_DUTYn Bit Definitions ...................................................................................................

4-42

4-48

PWM_PERVALn Bit Definitions...............................................................................................

4-43

4-49

GPIO Register Addresses .......................................................................................................

4-44

4-50

Interrupt Controller Register Addresses ..................................................................................

4-45

4-51

RTC Register Addresses.........................................................................................................

4-45

4-52

OS Timer Register Addresses.................................................................................................

4-45

4-53

Pulse Width Modulator Register Addresses ............................................................................

4-46

5-1

DMAC Signal List ......................................................................................................................

5-2

5-2

Channel Priority (if all channels are running concurrently) ........................................................

5-4

5-3

Channel Priority .........................................................................................................................

5-4

5-4

Priority Schemes Examples.......................................................................................................

5-5

5-5

DMA Quick Reference for Internal Peripherals .......................................................................

5-13

5-6

DINT Bit Definitions .................................................................................................................

5-17

5-7

DCSRx Bit Definitions..............................................................................................................

5-18

5-8

DRCMRx Bit Definitions ..........................................................................................................

5-20

5-9

DDADRx Bit Definitions ...........................................................................................................

5-21

5-10

DSADRx Bit Definitions ...........................................................................................................

5-22

5-11

DTADRx Bit Definitions ...........................................................................................................

5-23

5-12

DCMDx Bit Definitions .............................................................................................................

5-24

5-13

DMA Controller Register Summary .........................................................................................

5-28

6-1

Device Transactions ..................................................................................................................

6-7

6-2

MDCNFG Bit Definitions............................................................................................................

6-9

6-3

MDMRS Bit Definitions ............................................................................................................

6-12

6-4

MDMRSLP Register Bit Definitions .........................................................................................

6-14

6-5

MDREFR Bit Definitions ..........................................................................................................

6-15

6-6

Sample SDRAM Memory Size Options ...................................................................................

6-18

6-7

External to Internal Address Mapping for Normal Bank Addressing .......................................

6-19

6-8

External to Internal Address Mapping for SA-1111 Addressing ..............................................

6-21

6-9

Pin Mapping to SDRAM Devices with Normal Bank Addressing.............................................

6-23

6-10

Pin Mapping to SDRAM Devices with SA1111 Addressing.....................................................

6-25

6-11

SDRAM Command Encoding ..................................................................................................

6-28

6-12

SDRAM Mode Register Opcode Table....................................................................................

6-28

6-13

SXCNFG Bit Definitions...........................................................................................................

6-33

6-14

SXCNFG..................................................................................................................................

6-36

6-15

Synchronous Static Memory External to Internal Address Mapping Options ..........................

6-37

6-16

SXMRS Bit Definitions.............................................................................................................

6-38

6-17

Read Configuration Register Programming Values.................................................................

6-40

6-18

Frequency Code Configuration Values Based on Clock Speed ..............................................

6-40

6-20

16-Bit Bus Write Access ..........................................................................................................

6-44

6-19

32-Bit Bus Write Access ..........................................................................................................

6-44

6-21

MSC0/1/2 Bit Definitions..........................................................................................................

6-45

6-22

Asynchronous Static Memory and Variable Latency I/O Capabilities......................................

6-48

6-23

MCMEM0/1 Bit Definitions.......................................................................................................

6-58

6-24

MCATT0/1 Bit Definitions ........................................................................................................

6-59

6-25

MCIO0/1 Bit Definitions ...........................................................................................................

6-59

6-26

Card Interface Command Assertion Code Table.....................................................................

6-60

6-27

MECR Bit Definition.................................................................................................................

6-61

xviii

Intel® PXA255 Processor Developer’s Manual

 

 

Contents

6-28

Common Memory Space Write Commands ............................................................................

6-63

6-29

Common Memory Space Read Commands ............................................................................

6-63

6-30

Attribute Memory Space Write Commands .............................................................................

6-63

6-31

Attribute Memory Space Read Commands .............................................................................

6-63

6-32

16-Bit I/O Space Write Commands (nIOIS16 = 0)...................................................................

6-63

6-33

16-Bit I/O Space Read Commands (nIOIS16 = 0)...................................................................

6-63

6-34

8-Bit I/O Space Write Commands (nIOIS16 = 1).....................................................................

6-64

6-35

8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................

6-64

6-36

BOOT_SEL Definitions ............................................................................................................

6-72

6-37

BOOT_DEF Bitmap .................................................................................................................

6-73

6-38

Valid Boot Configurations Based on Processor Type..............................................................

6-73

6-39

Memory Controller Pin Reset Values.......................................................................................

6-77

6-40

Memory Controller Register Summary ....................................................................................

6-79

7-1

Pin Descriptions.........................................................................................................................

7-4

7-2

LCD Controller Data Pin Utilization..........................................................................................

7-21

7-3

LCCR0 Bit Definitions ..............................................................................................................

7-23

7-4

LCCR1 Bit Definitions ..............................................................................................................

7-26

7-5

LCCR2 Bit Definitions ..............................................................................................................

7-28

7-6

LCCR3 Bit Definitions ..............................................................................................................

7-31

7-7

FDADRx Bit Definitions............................................................................................................

7-33

7-8

FSADRx Bit Definitions............................................................................................................

7-34

7-9

FIDRx Bit Definitions................................................................................................................

7-34

7-10

LDCMDx Bit Definitions ...........................................................................................................

7-36

7-11

FBRx Bit Definitions.................................................................................................................

7-37

7-12

LCSR Bit Definitions ................................................................................................................

7-40

7-13

LIICR Bit Definitions.................................................................................................................

7-41

7-14

TRGBR Bit Definitions .............................................................................................................

7-42

7-15

TCR Bit Definitions ..................................................................................................................

7-44

7-16

LCD Controller Register Summary ..........................................................................................

7-44

8-1

External Interface to Codec .......................................................................................................

8-1

8-2

SSCR0 Bit Definitions................................................................................................................

8-9

8-3

SSCR1 Bit Definitions..............................................................................................................

8-11

8-4

TFT and RFT Values for DMA Servicing .................................................................................

8-15

8-5

SSDR Bit Definitions................................................................................................................

8-15

8-6

SSSR Bit Definitions ................................................................................................................

8-17

8-7

SSP Controller Register Summary ..........................................................................................

8-19

9-1

I2C Signal Description ...............................................................................................................

9-1

9-2

I2C Bus Definitions ...................................................................................................................

9-2

9-3

Modes of Operation ...................................................................................................................

9-3

9-4

START and STOP Bit Definitions ..............................................................................................

9-4

9-5

Master Transactions ................................................................................................................

9-12

9-6

Slave Transactions ..................................................................................................................

9-15

9-7

General Call Address Second Byte Definitions .......................................................................

9-17

9-8

IBMR Bit Definitions................................................................................................................

9-22

9-9

IDBR Bit Definitions ................................................................................................................

9-23

9-10

ICR Bit Definitions...................................................................................................................

9-23

9-11

ISR Bit Definitions...................................................................................................................

9-26

9-12

ISAR Bit Definitions ................................................................................................................

9-27

10-1

UART Signal Descriptions .......................................................................................................

10-3

10-2

UART Register Addresses as Offsets of a Base .....................................................................

10-6

Intel® PXA255 Processor Developer’s Manual

xix

Contents

 

10-3

RBR Bit Definitions ..................................................................................................................

10-6

10-4

THR Bit Definitions ..................................................................................................................

10-7

10-5

DLL Bit Definitions ...................................................................................................................

10-8

10-6

DLH Bit Definitions ..................................................................................................................

10-8

10-7

IER Bit Definitions....................................................................................................................

10-9

10-8

Interrupt Conditions ...............................................................................................................

10-10

10-9

IIR Bit Definitions ...................................................................................................................

10-10

10-10

Interrupt Identification Register Decode ................................................................................

10-11

10-11

FCR Bit Definitions ................................................................................................................

10-12

10-12

LCR Bit Definitions ................................................................................................................

10-14

10-13

LSR Bit Definitions.................................................................................................................

10-15

10-14

MCR Bit Definitions ...............................................................................................................

10-18

10-15

MSR Bit Definitions................................................................................................................

10-20

10-16

SPR Bit Definitions ................................................................................................................

10-21

10-17

ISR Bit Definitions..................................................................................................................

10-24

10-18

FFUART Register Summary..................................................................................................

10-26

10-19

BTUART Register Summary .................................................................................................

10-26

10-20

STUART Register Summary .................................................................................................

10-27

10-21

Flow Control Registers in BTUART and STUART.................................................................

10-28

11-1

FICP Signal Description ..........................................................................................................

11-1

11-2

ICCR0 Bit Definitions...............................................................................................................

11-8

11-3

ICCR1 Bit Definitions.............................................................................................................

11-10

11-4

ICCR2 Bit Definitions.............................................................................................................

11-11

11-5

ICRD Bit Definitions...............................................................................................................

11-12

11-6

ICSR0 Bit Definitions .............................................................................................................

11-13

11-7

ICSR1 Bit Definitions .............................................................................................................

11-15

11-8

FICP Register Summary........................................................................................................

11-16

12-1

Endpoint Configuration ............................................................................................................

12-2

12-2

USB States ..............................................................................................................................

12-3

12-3

IN, OUT, and SETUP Token Packet Format ...........................................................................

12-5

12-4

SOF Token Packet Format......................................................................................................

12-5

12-5

Data Packet Format.................................................................................................................

12-6

12-6

Handshake Packet Format ......................................................................................................

12-6

12-7

Bulk Transaction Formats........................................................................................................

12-7

12-8

Isochronous Transaction Formats ...........................................................................................

12-7

12-9

Control Transaction Formats ...................................................................................................

12-7

12-10

Interrupt Transaction Formats .................................................................................................

12-8

12-11

Host Device Request Summary ..............................................................................................

12-9

12-12

UDCCR Bit Definitions...........................................................................................................

12-22

12-13

UDC Control Function Register .............................................................................................

12-24

12-14

UDCCS0 Bit Definitions.........................................................................................................

12-25

12-15

UDCCS1/6/11 Bit Definitions.................................................................................................

12-27

12-16

UDCCS2/7/12 Bit Definitions.................................................................................................

12-29

12-17

UDCCS3/8/13 Bit Definitions.................................................................................................

12-31

12-18

UDCCS4/9/14 Bit Definitions.................................................................................................

12-33

12-19

UDCCS5/10/15 Bit Definitions...............................................................................................

12-34

12-20

UICR0 Bit Definitions.............................................................................................................

12-37

12-21

UICR1 Bit Definitions.............................................................................................................

12-38

12-22

USIR0 Bit Definitions .............................................................................................................

12-39

12-23

USIR1 Bit Definitions .............................................................................................................

12-41

xx

 

Intel® PXA255 Processor Developer’s Manual

 

 

Contents

12-24

UFNHR Bit Definitions ...........................................................................................................

12-43

12-25

UFNLR Bit Definitions............................................................................................................

12-44

12-26

UBCR2/4/7/9/12/14 Bit Definitions.........................................................................................

12-45

12-27

UDDR0 Bit Definitions ...........................................................................................................

12-46

12-28

UDDR1/6/11 Bit Definitions ...................................................................................................

12-46

12-29

UDDR2/7/12 Bit Definitions ...................................................................................................

12-47

12-30

UDDR3/8/13 Bit Definitions ...................................................................................................

12-47

12-31

UDDR4/9/14 Bit Definitions ...................................................................................................

12-48

12-32

UDDR5/10/15 Bit Definitions .................................................................................................

12-48

12-33

USB Device Controller Register Summary ............................................................................

12-48

13-1

External Interface to CODECs.................................................................................................

13-2

13-2

Supported Data Stream Formats.............................................................................................

13-3

13-3

Slot 1 Bit Definitions.................................................................................................................

13-7

13-4

Slot 2 Bit Definitions.................................................................................................................

13-7

13-5

Input Slot 1 Bit Definitions......................................................................................................

13-10

13-6

Input Slot 2 Bit Definitions......................................................................................................

13-11

13-7

GCR Bit Definitions................................................................................................................

13-20

13-8

GSR Bit Definitions ................................................................................................................

13-22

13-9

POCR Bit Definitions .............................................................................................................

13-23

13-10

PICR Bit Definitions ...............................................................................................................

13-24

13-11

POSR Bit Definitions..............................................................................................................

13-25

13-12

PISR Bit Definitions ...............................................................................................................

13-25

13-13

CAR Bit Definitions ................................................................................................................

13-26

13-14

PCDR Bit Definitions..............................................................................................................

13-26

13-15

MCCR Bit Definitions .............................................................................................................

13-27

13-16

MCSR Bit Definitions .............................................................................................................

13-28

13-17

MCDR Bit Definitions .............................................................................................................

13-28

13-18

MOCR Bit Definitions.............................................................................................................

13-29

13-19

MICR Bit Definitions...............................................................................................................

13-30

13-20

MOSR Bit Definitions .............................................................................................................

13-30

13-21

MISR Bit Definitions...............................................................................................................

13-31

13-22

MODR Bit Definitions.............................................................................................................

13-31

13-23

Address Mapping for CODEC Registers ...............................................................................

13-33

13-24

Register Mapping Summary ..................................................................................................

13-35

14-1

External Interface to CODEC...................................................................................................

14-2

14-2

Supported Sampling Frequencies ...........................................................................................

14-6

14-3

SACR0 Bit Definitions..............................................................................................................

14-9

14-4

FIFO Write/Read table...........................................................................................................

14-10

14-5

TFTH and RFTH Values for DMA Servicing ..........................................................................

14-10

14-6

SACR1 Bit Definitions............................................................................................................

14-11

14-7

SASR0 Bit Definitions ............................................................................................................

14-12

14-8

SADIV Bit Definitions .............................................................................................................

14-13

14-9

SAICR Bit Definitions.............................................................................................................

14-13

14-10

SAIMR Bit Descriptions .........................................................................................................

14-14

14-11

SADR Bit Descriptions...........................................................................................................

14-14

14-12

Register Memory Map ...........................................................................................................

14-16

15-1

Command Token Format.........................................................................................................

15-2

15-2

MMC Data Token Format ........................................................................................................

15-2

15-3

SPI Data Token Format ...........................................................................................................

15-2

15-4

MMC Signal Description ..........................................................................................................

15-6

Intel® PXA255 Processor Developer’s Manual

xxi

15-5

MMC_STRPCL Bit Definitions...............................................................................................

15-23

15-6

MMC_STAT Bit Definitions....................................................................................................

15-23

15-7

MMC_CLK Bit Definitions ......................................................................................................

15-25

15-8

MMC_SPI Bit Definitions .......................................................................................................

15-25

15-9

MMC_CMDAT Bit Definitions ................................................................................................

15-26

15-10

MMC_RESTO Bit Definitions.................................................................................................

15-27

15-11

MMC_RDTO Register ...........................................................................................................

15-28

15-12

MMC_BLKLEN Bit Definitions ...............................................................................................

15-29

15-13

MMC_NOB Bit Definitions .....................................................................................................

15-29

15-14

MMC_PRTBUF Bit Definitions...............................................................................................

15-30

15-15

MMC_I_MASK Bit Definitions................................................................................................

15-30

15-16

MMC_I_REG Bit Definitions ..................................................................................................

15-32

15-17

MMC_CMD Register .............................................................................................................

15-33

15-18

Command Index Values ........................................................................................................

15-33

15-19

MMC_ARGH Bit Definitions...................................................................................................

15-35

15-20

MMC_ARGL Bit Definitions ...................................................................................................

15-35

15-21

MMC_RES, FIFO Entry .........................................................................................................

15-36

15-22

MMC_RXFIFO, FIFO Entry ...................................................................................................

15-36

15-23

MMC_TXFIFO, FIFO Entry....................................................................................................

15-37

15-24

MMC Controller Registers .....................................................................................................

15-37

16-1

SSP Serial Port I/O Signals .....................................................................................................

16-2

16-2

Programmable Serial Protocol (PSP) Parameters ................................................................

16-12

16-3

SSCR0 Bit Definitions............................................................................................................

16-19

16-4

SSCR1 Bit Definitions............................................................................................................

16-21

16-5

SSPSP Bit Definitions............................................................................................................

16-23

16-6

SSTO Bit Definitions..............................................................................................................

16-24

16-7

SSITR Bit Definitions .............................................................................................................

16-25

16-8

SSSR Bit Definitions..............................................................................................................

16-26

16-9

SSDR Bit Definitions..............................................................................................................

16-29

16-10

NSSP Register Address Map ................................................................................................

16-29

17-1

UART Signal Descriptions .......................................................................................................

17-3

17-2

RBR Bit Definitions ................................................................................................................

17-10

17-3

THR Bit Definitions ................................................................................................................

17-10

17-4

DLL Bit Definitions .................................................................................................................

17-11

17-5

Divisor Latch Register High (DLH) Bit Definitions .................................................................

17-11

17-6

IER Bit Definitions..................................................................................................................

17-12

17-7

Interrupt Conditions ...............................................................................................................

17-13

17-8

IIR Bit Definitions ...................................................................................................................

17-13

17-9

Interrupt Identification Register Decode ................................................................................

17-14

17-10

FCR Bit Definitions ................................................................................................................

17-15

17-11

FOR Bit Definitions ................................................................................................................

17-16

17-12

ABR Bit Definitions ................................................................................................................

17-17

17-13

ACR Bit Definitions ................................................................................................................

17-18

17-14

LCR Bit Definitions ................................................................................................................

17-18

17-15

LSR Bit Definitions.................................................................................................................

17-20

17-16

MCR Bit Definitions ...............................................................................................................

17-22

17-17

MSR Bit Definitions................................................................................................................

17-23

17-18

SCR Bit Definitions ................................................................................................................

17-24

17-19

ISR Bit Definitions..................................................................................................................

17-25

17-20

HWUART Register Locations ................................................................................................

17-25

Contents

Intel® PXA255 Processor Developer’s Manual

xxiii

Contents

Revision History

Date

Revision

Description

 

 

 

March 2003

-001

Initial release

 

 

 

xxiv

Intel® PXA255 Processor Developer’s Manual

Introduction

1

 

 

This document applies to the Intel® PXA255 Processor (PXA255 processor). It is an application specific standard product (ASSP) that provides industry-leading MIPS/mW performance for handheld computing applications. The processor is a highly integrated system on a chip and includes a high-performance low-power Intel® XScale™ microarchitecture with a variety of different system peripherals.

The PXA255 processor is a 17x17mm 256-pin PBGA package configuration for high performance. The 17x17mm package has a 32-bit memory data bus and the full assortment of peripherals.

1.1Intel® XScale™ Microarchitecture Features

The Intel® XScale™ microarchitecture provides these features:

ARM* Architecture Version 5TE ISA compliant.

ARM* Thumb Instruction Support

ARM* DSP Enhanced Instructions

Low power consumption and high performance

Intel® Media Processing Technology

Enhanced 16-bit Multiply

40-bit Accumulator

32-KByte Instruction Cache

32-KByte Data Cache

2-KByte Mini Data Cache

2-KByte Mini Instruction Cache

Instruction and Data Memory Management Units

Branch Target Buffer

Debug Capability via JTAG Port

Refer to the Intel® XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual for more details.

1.2System Integration Features

The processor integrates the Intel® XScale™ microarchitecture with this peripheral set:

Memory Controller

Clock and Power Controllers

Universal Serial Bus Client

Intel® PXA255 Processor Developer’s Manual

1-1

Introduction

DMA Controller

LCD Controller

AC97

I2S

MultiMediaCard

FIR Communication

Synchronous Serial Protocol Port

I2C

General Purpose I/O pins

UARTs

Real-Time Clock

OS Timers

Pulse Width Modulation

Interrupt Control

1.2.1Memory Controller

The Memory Controller provides glueless control signals with programmable timing for a wide assortment of memory-chip types and organizations. It supports up to four SDRAM partitions; six static chip selects for SRAM, SSRAM, Flash, ROM, SROM, and companion chips; support for two PCMCIA or Compact Flash slots

1.2.2Clocks and Power Controllers

The processor functional blocks are driven by clocks that are derived from a 3.6864-MHz crystal and an optional 32.768-kHz crystal.

The 3.6864-MHz crystal drives a core Phase Locked Loop (PLL) and a Peripheral PLL. The PLLs produce selected clock frequencies to run particular functional blocks.

The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset. This clock drives the Real Time Clock (RTC), Power Management Controller, and Interrupt Controller. The 32.768-kHz crystal is on a separate power island to provide an active clock while the processor is in sleep mode.

Power management controls the transition between the turbo/run, idle, and sleep operating modes.

1.2.3Universal Serial Bus (USB) Client

The USB Client Module is based on the Universal Serial Bus Specification, Revision 1.1. It supports up to sixteen endpoints and it provides an internally generated 48-MHz clock. The USB Device Controller provides FIFOs with DMA access to or from memory.

1-2

Intel® PXA255 Processor Developer’s Manual

Introduction

1.2.4DMA Controller (DMAC)

The DMAC provides sixteen prioritized channels to service transfer requests from internal peripherals and up to two data transfer requests from external companion chips. The DMAC is descriptor-based to allow command chaining and looping constructs.

The DMAC operates in Flow-Through Mode when performing peripheral-to-memory, memory-to- peripheral, and memory-to-memory transfers. The DMAC is compatible with peripherals that use word, half-word, or byte data sizes.

1.2.5LCD Controller

The LCD Controller supports both passive (DSTN) and active (TFT) flat-panel displays with a maximum supported resolution of 640x480x16-bit/pixel. An internal 256 entry palette expands 1, 2, 4, or 8-bit encoded pixels. Non-encoded 16-bit pixels bypass the palette.

Two dedicated DMA channels allow the LCD Controller to support singleand dual-panel displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode supports up to 64K colors. Active color mode supports up to 64K colors.

1.2.6AC97 Controller

The AC97 Controller supports AC97 Revision 2.0 CODECs. These CODECs can operate at sample rates up to 48 KHz. The controller provides independent 16-bit channels for Stereo PCM In, Stereo PCM Out, Modem In, Modem Out, and mono Microphone In. Each channel includes a FIFO that supports DMA access to memory.

1.2.7Inter-IC Sound (I2S) Controller

The I2S Controller provides a serial link to standard I2S CODECs for digital stereo sound. It supports both the Normal-I2S and MSB-Justified I2S formats, and provides four signals for connection to an I2S CODEC. I2S Controller signals are multiplexed with AC97 Controller pins. The controller includes FIFOs that support DMA access to memory.

1.2.8Multimedia Card (MMC) Controller

The MMC Controller provides a serial interface to standard memory cards. The controller supports up to two cards in either MMC or SPI modes with serial data transfers up to 20 Mbps. The MMC controller has FIFOs that support DMA access to and from memory.

1.2.9Fast Infrared (FIR) Communication Port

The FIR Communication Port is based on the 4-Mbps Infrared Data Association (IrDA) Specification. It operates at half-duplex and has FIFOs with DMA access to memory. The FIR Communication Port uses the STUART’s transmit and receive pins to directly connect to external IrDA LED transceivers.

Intel® PXA255 Processor Developer’s Manual

1-3

Introduction

1.2.10Synchronous Serial Protocol Controller (SSPC)

The SSP Port provides a full-duplex synchronous serial interface that operates at bit rates from 7.2 kHz to 1.84 MHz. It supports National Semiconductor’s Microwire*, Texas Instruments’ Synchronous Serial Protocol*, and Motorola’s Serial Peripheral Interface*. The SSPC has FIFOs with DMA access to memory.

1.2.11Inter-Integrated Circuit (I2C) Bus Interface Unit

The I2C Bus Interface Unit provides a general purpose 2-pin serial communication port.The interface uses one pin for data and address and a second pin for clocking.

1.2.12GPIO

Each GPIO pin can be individually programmed as an output or an input. Inputs can cause interrupts on rising or falling edges. Primary GPIO pins are not shared with peripherals while secondary GPIO pins have alternate functions which can be mapped to the peripherals.

1.2.13UARTs

The processor provides three Universal Asynchronous Receiver/Transmitters. Each UART can be used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data Association Serial Infrared (SIR) Physical Layer Link Specification.

1.2.13.1Full Function UART (FFUART)

The FFUART baud rate is programmable up to 230 Kbps. The FFUART provides a complete set of modem control pins: nCTS, nRTS, nDSR, nDTR, nRI, and nDCD. It has FIFOs with DMA access to or from memory.

1.2.13.2Bluetooth UART (BTUART)

The BTUART baud rate is programmable up to 921 Kbps. The BTUART provides a partial set of modem control pins: nCTS and nRTS. Other modem control pins can be implemented via GPIOs. The BTUART has FIFOs with DMA access to or from memory.

1.2.13.3Standard UART (STUART)

The STUART baud rate is programmable up to 230 Kbps. The STUART does not provide any modem control pins. The modem control pins can be implemented via GPIOs. The STUART has FIFOs with DMA access to or from memory.

The STUART’s transmit and receive pins are multiplexed with the Fast Infrared Communication Port.

1-4

Intel® PXA255 Processor Developer’s Manual

Introduction

1.2.13.4Hardware UART (HWUART)

The PXA255 processor has a UART with hardware flow control. The HWUART provides a partial set of modem control pins: nCTS and nRTS. These modem control pins provide full hardware flow control. Other modem control pins can be implemented via GPIOs. The HWUART baud rate is programmable up to 921.6 Kbps.

The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUART, VLIO is unavailable. The HWUART pins are also available over the BTUART pins. When operating over the BTUART pins, the HWUART pins operate at the I/O voltage.

1.2.14Real-Time Clock (RTC)

The Real-Time Clock can be clocked from either crystal. A system with a 32.768-KHz crystal consumes less power during Sleep versus a system using only the 3.6864-MHz crystal. This crystal can be removed to save system cost. The RTC provides a constant frequency output with a programmable alarm register. This alarm register can be used to wake up the processor from Sleep mode.

1.2.15OS Timers

The OS Timers can be used to provide a 3.68-MHz reference counter with four match registers. These registers can be configured to cause interrupts when equal to the reference counter. One match register can be used to cause a watchdog reset.

1.2.16Pulse-Width Modulator (PWM)

The PWM has two independent outputs that can be programmed to drive two GPIOs. The frequency and duty cycle are independently programmable. For example, one GPIO can control LCD contrast and the other LCD brightness.

1.2.17Interrupt Control

The Interrupt Controller directs the processor interrupts into the core’s IRQ and FIQ inputs. The Mask Register enables or disables individual interrupt sources.

1.2.18Network Synchronous Serial Protocol Port

The PXA255 processor has an SSP port optimized for connection to other network ASICs. This NSSP adds a Hi-Z function to TXD, the ability to control when Hi-Z occurs, and swapping the TXD/RXD pins.

This port is not multiplexed with other interfaces.

Intel® PXA255 Processor Developer’s Manual

1-5

Introduction

1-6

Intel® PXA255 Processor Developer’s Manual

System Architecture

2

 

 

2.1Overview

The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance, low power portable handheld and handset devices. It incorporates the Intel® XScale™ microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture Version 5TE instruction set compliant (excluding floating point instructions) and follows the ARM* programmer’s model.

The processor’s memory interface supports a variety of memory types to allow design flexibility. Support for the connection of two companion chips permits a glueless interface to external devices. An integrated LCD display controller provides support for displays up to 640x480 pixels, and permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels. A 256 entry/512 byte palette RAM provides flexibility in color mapping.

A set of serial devices and general system resources provide computational and connectivity capability for a variety of applications. Refer to Figure 2-1 for an overview of the microprocessor system architecture.

Intel® PXA255 Processor Developer’s Manual

2-1

System Architecture

Figure 2-1. Block Diagram

RTC

OS Timer

PWM(2)

Int.

Controller

Clocks &

Power Man.

I/O

I2S

AC97

Purpose

 

I2C

General

UARTs

 

 

NSSP

Slow IrDA

Fast IrDA

SSP

USB

Client

MMC

Peripheral Bus

DMA Controller and Bridge

 

 

 

 

 

Color or

 

Grayscale

Memory

LCD

Controller

Controller

 

 

 

 

 

Variable

 

 

 

Latency I/O

ASIC

 

System Bus

Control

 

 

 

PCMCIA

XCVR

Socket 0

 

& CF

Socket 1

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dynamic

 

 

 

 

 

SDRAM/

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

SMROM

 

 

 

 

 

 

 

 

 

 

 

IntelÆ XScaleô

 

 

Control

 

 

 

 

 

4 banks

Microarchitecture

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Static

 

 

 

 

 

ROM/

 

 

 

 

 

 

 

 

 

 

 

 

 

Flash/

 

 

 

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SRAM

 

 

 

 

 

 

 

 

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 banks

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.6864

 

32.768

 

 

 

 

 

 

 

 

 

MHz

 

KHz

 

 

 

 

 

 

 

 

 

Osc

 

Osc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.2Intel® XScale™ Microarchitecture Implementation Options

The processor incorporates the Intel® XScale™ microarchitecture which is described in a separate document. This core contains implementation options which an Application Specific Standard Product (ASSP) may elect to implement or omit. This section describes those options.

Most of these options are specified within the coprocessor register space. The processor does not implement any coprocessor registers beyond those defined in the Intel® XScale™ microarchitecture. The coprocessor registers which are ASSP specific, as stated in the Intel® XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number 278793, are defined in the following sections.

2.2.1Coprocessor 7 Register 4 - PSFS Bit

Bit 5 of this register is defined as the Power Source Fault Status bit or PSFS bit. This bit is set when either nVDD_FAULT or nBATT_FAULT pins are asserted and the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) is set.

This is a read-only register. Ignore reads from reserved bits.

2-2

Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-1. CPU Core Fault Register Bit Definitions

 

 

 

 

 

Coprocessor 7

 

 

 

 

CPU Core Fault

 

 

 

 

 

 

System Architecture

 

 

 

 

 

 

 

 

 

 

Register 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSFS

 

 

Reserved

 

 

 

Reset

0

0

 

0

 

0

0

0

0

 

0

 

0

0

0

0

0

 

0

0

0

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[31:6]

 

 

 

 

 

 

 

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read undefined.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Source Fault Status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 = nVDD_FAULT or nBATT_FAULT pin has not been asserted since it was

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

last cleared by a reset or the CPU.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

 

 

 

PSFS

 

 

 

1 = nVDD_FAULT or nBATT_FAULT pin was asserted and PMCR[IDAE] =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read only, write ignored.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cleared by Hardware, Watchdog, and GPIO Resets.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[4:0]

 

 

 

 

 

 

 

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read undefined.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.2.2Coprocessor 14 Registers 0-3 - Performance Monitoring

The processor does not define any performance monitoring features beyond those called out in the

Intel® XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number 278793. The interrupt generated by performance monitoring events is defined in Chapter 4, “System Integration Unit”. The ASSP defined performance monitoring events (events 0x10 - 0x17), defined through the PMNC register are reserved for the processor.

2.2.3Coprocessor 14 Register 6 and 7- Clock and Power Management

These registers allow software to use the clocking and power management modes. The valid operations are described in Table 3-23, “Coprocessor 14 Clock and Power Management Summary” on page 3-39.

2.2.4Coprocessor 15 Register 0 - ID Register Definition

This register may be read by software to determine the device type and revision. The contents of this register for the Intel® PXA255 Processor is defined in the table below. Combined, this register must read as 0x6905 2X0R where R = 0b0000 for the first stepping and then increments for subsequent steppings, and X is the revision of the Intel® XScale™ microarchitecture present. Please see the Intel Developer Homepage at http://developer.intel.com for updates.

This is a read-only register.

Intel® PXA255 Processor Developer’s Manual

2-3

System Architecture

Table 2-2. ID Bit Definitions

 

 

 

 

CP15 Register 0

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP15

 

 

 

 

 

 

Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Implementation

Trademark

 

 

 

 

 

 

 

 

 

 

Architecture

Version

 

 

 

 

 

 

Core

generation

 

 

Core

Revision

 

 

 

Product

Number

 

 

 

Product

Revision

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

1

1

0

1

0

 

0

 

1

0

0

 

0

0

0

1

0

 

1

 

0

 

0

 

1

 

0

0

0

0

1

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[31:24]

 

 

Implementation

 

 

Implementation trademark.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Trademark

 

 

 

0x69 Intel® Corporation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[23:16]

 

 

 

Architecture

 

 

ARM* Architecture version of the core.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Version

 

 

 

0x05 ARM* Architecture version 5TE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This field is updated when new sets of features are added to the core. This

 

 

 

 

[15:13]

 

 

Core Generation

 

 

allows software that is dependant on core features to target a specific core.

 

 

 

 

 

 

 

 

Core generation:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0b001 Intel® XScale™ core

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This field is updated each time a core is revised. Differences may include

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

errata, software workarounds, etc.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[12:10]

 

 

Core Revision

 

 

Core revision:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0b000 First version of the core.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0b010 Third version of the core.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0b011 Fourth version of the core.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[9:4]

 

 

Product Number

 

 

Product Number

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0b010000 – PXA255 processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This field tracks the different steppings for each ASSP.

 

 

 

 

 

 

 

 

 

[3:0]

 

 

Product Revision

 

 

Product Revision

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0b0110 A0 Stepping

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2-3. PXA255 Processor ID Values

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stepping

 

 

 

 

ARM ID

 

 

 

 

 

 

JTAG ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

0x6905_2D06

 

 

 

 

 

0x6926_4013

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.2.5Coprocessor 15 Register 1 - P-Bit

Bit 1 of this register is defined as the Page Table Memory Attribute bit or P-bit. It is not implemented in the processor and must be written as zero. Similarly, the P-bit in the page table descriptor in the MMU is not implemented and must be written to zero.

2-4

Intel® PXA255 Processor Developer’s Manual

System Architecture

2.3I/O Ordering

The processor uses queues that accept memory requests from the three internal masters: core, DMA Controller, and LCD Controller. Operations issued by a master are completed in the order they were received. Operations from one master may be interrupted by operations from another master. The processor does not provide a method to regulate the order of operations from different masters.

Loads and stores to internal addresses are generally completed more quickly than those issued to external addresses. The difference in completion time allows one operation to be received before another operation, but completed after the second operation.

In the following sequence, the store to the address in r4 is completed before the store to the address in r2 because the first store waits for memory in the queue while the second is not delayed.

str r1, [r2]

; store to external memory address [r2].

str r3, [r4]

; store to internal (on-chip) memory address [r4].

If the two stores are control operations that must be completed in order, the recommended sequence is to insert a load to an unbuffered, uncached memory page followed by an operation that depends on data from the load:

str r1, [r2]

; first store issued

ldr r5, [r6]

; load from external unbuffered, uncached address ([r2] if possible)

mov r5, r5

; nop stalls until r5 is loaded

str r3, [r4]

; second store completes in program order

2.4Semaphores

The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* Architecture reference, may be used for semaphore manipulation. No on-chip master or process can access a memory location between the load and store portion of a SWP or SWPB to the same location.

Note: Semaphore coherency may be interrupted because an external companion chip that uses the MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow semaphore manipulation by external companion chips, the software must manage coherency.

2.5Interrupts

The interrupt controller is described in detail in Section 4.2, “Interrupt Controller”. All on-chip interrupts are enabled, masked, and routed to the core FIQ or IRQ. Each interrupt is enabled or disabled at the source through an interrupt mask bit. Generally, all interrupt bits in a unit are ORed together and present a single value to the interrupt controller.

Intel® PXA255 Processor Developer’s Manual

2-5

System Architecture

Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken, the software may read the Interrupt Controller Pending Register to identify the source. After it identifies the interrupt source, software is responsible for servicing the interrupt and clearing it in the source unit before exiting the service routine.

Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an interrupt service routine (ISR), clear the interrupt early in the routine.

2.6Reset

The processor can be reset in any of three ways: Hardware, Watchdog, and GPIO resets. Each is described in more detail in Section 3.4, “Resets and Power Modes” on page 3-6.

Hardware reset results from asserting the nRESET pin and forces all units into reset state.

Watchdog reset results from a time-out in the OS Timer and may be used to recover from runaway code. Watchdog reset is disabled by default and must be enabled by software.

GPIO reset is a “soft reset” that is less destructive than Hardware and Watchdog resets.

Each type of reset affects the state of the processor pins. Table 2-4 shows each pin’s state after each type of reset.

Leaving Sleep Mode causes a Sleep Mode reset. Unlike other resets, Sleep Mode resets do not change the state of the pins.

The Reset Controller Status Register (RCSR) contains information on the type of reset, including Sleep Mode resets.

Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 1 of 2)

Unit

Sleep Mode

GPIO Reset

Watchdog Reset

Hard Reset

 

 

 

 

 

Core

reset

reset

reset

reset

 

 

 

 

 

Memory Controller

reset

preserved

reset

reset

 

 

 

 

 

LCD Controller

reset

reset

reset

reset

 

 

 

 

 

DMA Controller

reset

reset

reset

reset

 

 

 

 

 

Full Function UART

reset

reset

reset

reset

 

 

 

 

 

Bluetooth UART

reset

reset

reset

reset

 

 

 

 

 

Standard UART

reset

reset

reset

reset

 

 

 

 

 

Hardware UART

reset

reset

reset

reset

 

 

 

 

 

I2C

reset

reset

reset

reset

I2S

reset

reset

reset

reset

AC97

reset

reset

reset

reset

 

 

 

 

 

USB

reset

reset

reset

reset

 

 

 

 

 

ICP

reset

reset

reset

reset

 

 

 

 

 

RTC

preserved

preserved

reset (except RTTR)

reset

 

 

 

 

 

OS Timer

reset

reset

reset

reset

 

 

 

 

 

2-6 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 2 of 2)

Unit

Sleep Mode

GPIO Reset

Watchdog Reset

Hard Reset

 

 

 

 

 

PWM

reset

reset

reset

reset

 

 

 

 

 

Interrupt Controller

reset

reset

reset

reset

 

 

 

 

 

GPIO

reset

reset

reset

reset

 

 

 

 

 

Power Manager

preserved

reset

reset

reset

 

 

 

 

 

SSP

reset

reset

reset

reset

 

 

 

 

 

NSSP

reset

reset

reset

reset

 

 

 

 

 

MMC

reset

reset

reset

reset

 

 

 

 

 

Clocks

preserved (except CP14)

preserved (except CP14)

reset (except OSCC)

reset

 

 

 

 

 

2.7Internal Registers

All internal registers are mapped in physical memory space on 32-bit address boundaries. Use word access loads and stores to access internal registers. Internal register space must be mapped as non-cacheable.

Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.

Register space where a register is not specifically mapped is defined as reserved space. Reading or writing reserved space causes unpredictable results.

The processor does not use all register bit locations. The unused bit locations are marked reserved and are allocated for future use. Write reserved bit locations as zeros. Ignore the values of these bits during reads because they are unpredictable.

2.8Selecting Peripherals vs. General Purpose I/O

Most peripherals connect to the external pins through GPIOs. To use a peripheral connected through a GPIO, the software must first configure the GPIO so that the desired peripheral is connected to its pins. The default state of the pins is GPIO inputs.

To allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripheral function onto the pin by selecting the proper alternate function for the pin. Some GPIOs have multiple alternate functions. After a function is selected for a pin, all other functions are excluded. For this reason some peripherals are mapped to multiple GPIOs, as shown in Section 4.1.2, “GPIO Alternate Functions” on page 4-2. Multiple mapping does not mean multiple instances of a peripheral - only that the peripheral is connected to the pins in several ways.

Intel® PXA255 Processor Developer’s Manual

2-7

System Architecture

2.9Power on Reset and Boot Operation

Before the device that uses the processor is powered on, the system must assert nRESET and nTRST. To allow the internal clocks to stabilize, all power supplies must be stable for a specified period before nRESET or nTRST are deasserted. When nRESET is asserted, nRESET_OUT is driven active and can be used to reset other devices in the system. For additional information, see the Intel® PXA255 Processor Design Guide.

When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a specified time later and the device attempts to boot from physical address location 0x0000_0000.

The BOOT_SEL[2:0] pins are sampled when reset is deasserted and let the user specify the type and width of memory device from which the processor attempts to boot. The software can read the pins as described in Section 6.10.2, “Boot Time Defaults” on page 6-72.

2.10Power Management

The processor offers a number of modes to manage power in the system. These range widely in level of power savings and level of functionality. The following modes are supported:

Turbo Mode: low latency (nanoseconds) switch between two preprogrammed frequencies.

Run Mode: normal full function mode.

Idle Mode: core clocks are stopped - resume through an interrupt.

Sleep Mode: low power mode that does not save state but keeps I/Os powered. The RTC, Power Manager, and Clock modules are saved, except for Coprocessor 14.

Note: In low power modes, ensure that input pins are not floating and output pins are not driven by an external device that opposes how the processor is driving that pin. In either case, the system will draw excess current. Current draw that varies in sleep mode or varies greatly between parts is typically a sign of floating pins.

Section 3.4, “Resets and Power Modes” describes the modes in detail.

2.11Pin List

Some of the processor pins can be connected to multiple signals. The signal connected to the pin is determined by the GPIO Alternate Function Select Registers (GAFRn m). Some signals can go to multiple pins. The signal must be routed to only one pin by using the GAFRn m registers. Because this is true, some pins are listed twice, once in each unit that can use the pin.

Table 2-5. Processor Pin Types

Type

Function

 

 

IC

CMOS input

 

 

OC

CMOS output

 

 

OCZ

CMOS output, Hi-Z

 

 

ICOCZ

CMOS bidirectional, Hi-Z

 

 

2-8 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-5. Processor Pin Types

Type

Function

 

 

IA

Analog Input

 

 

OA

Analog output

 

 

IAOA

Analog bidirectional

 

 

SUP

Supply pin (either VCC or VSS)

 

 

Table 2-6 describes the PXA255 processor pins.

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

Memory Controller Pins

 

 

 

 

 

 

 

 

MA[25:0]

OCZ

Memory address bus. (output) Signals the address

Driven Low

Driven Low

requested for memory accesses.

 

 

 

 

 

 

 

 

 

MD[15:0]

ICOCZ

Memory data bus. (input/output) Lower 16 bits of the

Hi-Z

Driven Low

data bus.

 

 

 

 

 

 

 

 

 

MD[31:16]

ICOCZ

Memory data bus. (input/output) Used for 32-bit

Hi-Z

Driven Low

memories.

 

 

 

 

 

 

 

 

 

nOE

OCZ

Memory output enable. (output) Connect to the output

Driven High

Note [4]

enables of memory devices to control data bus drivers.

 

 

 

 

 

 

 

 

 

nWE

OCZ

Memory write enable. (output) Connect to the write

Driven High

Note [4]

enables of memory devices.

 

 

 

 

 

 

 

 

 

 

 

SDRAM CS for banks 3 through 0. (output) Connect to

 

 

nSDCS[3:0]

OCZ

the chip select (CS) pins for SDRAM. For the PXA255

Driven High

Note [5]

 

 

processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot.

 

 

 

 

 

 

 

 

 

SDRAM DQM for data bytes 3 through 0. (output)

 

 

DQM[3:0]

OCZ

Connect to the data output mask enables (DQM) for

Driven Low

Driven Low

 

 

SDRAM.

 

 

 

 

 

 

 

nSDRAS

OCZ

SDRAM RAS. (output) Connect to the row address

Driven High

Driven High

strobe (RAS) pins for all banks of SDRAM.

 

 

 

 

 

 

 

 

 

nSDCAS

OCZ

SDRAM CAS. (output) Connect to the column address

Driven High

Driven High

strobe (CAS) pins for all banks of SDRAM.

 

 

 

 

 

 

 

 

 

 

 

Synchronous Static Memory clock enable. (output)

 

 

SDCKE[0]

OC

Connect to the CKE pins of SMROM. The memory

Driven Low

Driven Low

 

 

controller provides control register bits for deassertion.

 

 

 

 

 

 

 

 

 

SDRAM and/or Synchronous Static Memory clock

 

 

 

 

enable. (output) Connect to the clock enable pins of

 

 

SDCKE[1]

OC

SDRAM. It is deasserted during sleep. SDCKE[1] is

Driven Low

Driven Low

 

 

always deasserted upon reset. The memory controller

 

 

 

 

provides control register bits for deassertion.

 

 

 

 

 

 

 

 

 

Synchronous Static Memory clock. (output) Connect to

 

 

 

 

the clock (CLK) pins of SMROM. It is driven by either the

 

 

 

 

internal memory controller clock, or the internal memory

 

 

 

 

controller clock divided by 2. At reset, all clock pins are

 

 

 

 

free running at the divide by 2 clock speed and may be

 

 

SDCLK[0]

OC

turned off via free running control register bits in the

 

 

 

 

memory controller. The memory controller also provides

 

 

 

 

control register bits for clock division and deassertion of

 

 

 

 

each SDCLK pin. SDCLK[0] control register assertion bit

 

 

 

 

defaults to on if the boot-time static memory bank 0 is

 

 

 

 

configured for SMROM.

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

2-9

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

SDCLK[1]

OCZ

SDRAM Clocks (output) Connect SDCLK[1] and

Driven Low

Driven Low

 

 

SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1

 

 

 

 

 

 

 

 

and 2/3, respectively. They are driven by either the

 

 

 

 

internal memory controller clock, or the internal memory

 

 

 

 

controller clock divided by 2. At reset, all clock pins are

 

 

SDCLK[2]

OC

free running at the divide by 2 clock speed and may be

Driven Low

Driven Low

turned off via free running control register bits in the

 

 

memory controller. The memory controller also provides

 

 

 

 

control register bits for clock division and deassertion of

 

 

 

 

each SDCLK pin. SDCLK[2:1] control register assertion

 

 

 

 

bits are always deasserted upon reset.

 

 

 

 

 

 

 

nCS[5]/

ICOCZ

 

 

 

GPIO[33]

 

 

 

 

 

 

 

 

 

 

 

 

nCS[4]/

ICOCZ

 

 

 

GPIO[80]

 

 

 

 

Static chip selects. (output) Chip selects to static

 

 

 

 

 

 

nCS[3]/

 

 

 

ICOCZ

memory devices such as ROM and Flash. Individually

Hi-Z - Note [1]

Note [4]

GPIO[79]

programmable in the memory configuration registers.

 

 

 

 

 

nCS[5:0] can be used with variable latency I/O devices.

 

 

nCS[2]/

ICOCZ

 

 

 

 

 

GPIO[78]

 

 

 

 

 

 

 

 

 

 

 

 

nCS[1]/

ICOCZ

 

 

 

GPIO[15]

 

 

 

 

 

 

 

 

 

 

 

 

nCS[0]

ICOCZ

Static chip select 0. (output) Chip select for the boot

Driven High

Note [4]

memory. nCS[0] is a dedicated pin.

 

 

 

 

 

 

 

 

 

RD/nWR

OCZ

Read/Write for static interface. (output) Signals that the

Driven Low

Holds last state

current transaction is a read or write.

 

 

 

 

 

 

 

 

 

RDY/

 

Variable Latency I/O Ready pin. (input) Notifies the

 

 

ICOCZ

memory controller when an external bus device is ready

Hi-Z - Note [1]

Note [3]

GPIO[18]

 

to transfer data.

 

 

 

 

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[8]/

 

from the LCD Controller to the external LCD panel.

 

 

ICOCZ

Memory Controller alternate bus master request.

Hi-Z - Note [1]

Note [3]

GPIO[66]

 

(input) Allows an external device to request the system

 

 

 

 

 

 

 

 

bus from the Memory Controller.

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[15]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[73]

Memory Controller grant. (output) Notifies an external

 

 

 

 

 

device that it has been granted the system bus.

 

 

 

 

 

 

 

MBGNT/

ICOCZ

Memory Controller grant. (output) Notifies an external

Hi-Z - Note [1]

Note [3]

GP[13]

device that it has been granted the system bus.

 

 

 

 

 

 

 

 

MBREQ/

 

Memory Controller alternate bus master request.

 

 

ICOCZ

(input) Allows an external device to request the system

Hi-Z - Note [1]

Note [3]

GP[14]

 

bus from the Memory Controller.

 

 

 

 

 

 

 

 

 

 

 

PCMCIA/CF Control Pins

 

 

 

 

 

 

 

 

nPOE/

ICOCZ

PCMCIA output enable. (output) Reads from PCMCIA

Hi-Z - Note [1]

Note [5]

GPIO[48]

memory and to PCMCIA attribute space.

 

 

 

 

 

 

 

 

nPWE/

 

PCMCIA write enable. (output) Performs writes to

 

 

ICOCZ

PCMCIA memory and to PCMCIA attribute space. Also

Hi-Z - Note [1]

Note [5]

GPIO[49]

 

used as the write enable signal for Variable Latency I/O.

 

 

 

 

 

 

 

 

 

 

 

2-10

Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

nPIOW/

ICOCZ

PCMCIA I/O write. (output) Performs write transactions

Hi-Z - Note [1]

Note [5]

GPIO[51]

to PCMCIA I/O space.

 

 

 

 

 

 

 

 

nPIOR/

ICOCZ

PCMCIA I/O read. (output) Performs read transactions

Hi-Z - Note [1]

Note [5]

GPIO[50]

from PCMCIA I/O space.

 

 

 

 

 

 

 

 

 

 

PCMCIA card enable 2. (output) Selects a PCMCIA

 

 

nPCE[2]/

 

card. nPCE[2] enables the high byte lane and nPCE[1]

 

 

ICOCZ

enables the low byte lane.

Hi-Z - Note [1]

Note [5]

GPIO[53]

 

MMC clock. (output) Clock signal for the MMC

 

 

 

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

nPCE[1]/

 

PCMCIA card enable 1. (outputs) Selects a PCMCIA

 

 

ICOCZ

card. nPCE[2] enables the high byte lane and nPCE[1]

Hi-Z - Note [1]

Note [5]

GPIO[52]

 

enables the low byte lane.

 

 

 

 

 

 

 

 

 

 

 

nIOIS16/

 

IO Select 16. (input) Acknowledge from the PCMCIA

 

 

ICOCZ

card that the current address is a valid 16 bit wide I/O

Hi-Z - Note [1]

Note [5]

GPIO[57]

 

address.

 

 

 

 

 

 

 

 

 

 

 

nPWAIT/

 

PCMCIA wait. (input) Driven low by the PCMCIA card to

 

 

ICOCZ

extend the length of the transfers to/from the PXA255

Hi-Z - Note [1]

Note [5]

GPIO[56]

 

processor.

 

 

 

 

 

 

 

 

 

 

 

 

 

PCMCIA socket select. (output) Used by external

 

 

PSKTSEL/

 

steering logic to route control, address, and data signals

 

 

ICOCZ

to one of the two PCMCIA sockets. When PSKTSEL is

Hi-Z - Note [1]

Note [5]

GPIO[54]

low, socket zero is selected. When PSKTSEL is high,

 

 

 

 

 

socket one is selected. Has the same timing as the

 

 

 

 

address bus.

 

 

 

 

 

 

 

nPREG/

 

PCMCIA Register select. (output) Indicates that the

 

 

ICOCZ

target address on a memory transaction is attribute

Hi-Z - Note [1]

Note [5]

GPIO[55]

 

space. Has the same timing as the address bus.

 

 

 

 

 

 

 

 

 

 

 

LCD Controller Pins

 

 

 

 

 

 

 

 

L_DD(7:0)/

ICOCZ

LCD display data. (outputs) Transfers pixel information

Hi-Z - Note [1]

Note [3]

GPIO[65:58]

from the LCD Controller to the external LCD panel.

 

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[8]/

 

from the LCD Controller to the external LCD panel.

 

 

ICOCZ

Memory Controller alternate bus master request.

Hi-Z - Note [1]

Note [3]

GPIO[66]

 

(input) Allows an external device to request the system

 

 

 

 

 

 

 

 

bus from the Memory Controller.

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[9]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[67]

MMC chip select 0. (output) Chip select 0 for the MMC

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[10]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[68]

MMC chip select 1. (output) Chip select 1 for the MMC

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

L_DD[11]/

 

LCD display data. (output) Transfers pixel information

 

 

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[69]

 

MMC clock. (output) Clock for the MMC Controller.

 

 

 

 

 

 

 

 

 

 

 

L_DD[12]/

 

LCD display data. (output) Transfers pixel information

 

 

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[70]

 

RTC clock. (output) Real time clock 1 Hz tick.

 

 

 

 

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

2-11

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[13]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[71]

3.6864 MHz clock. (output) Output from 3.6864 MHz

 

 

 

 

 

oscillator.

 

 

 

 

 

 

 

L_DD[14]/

 

LCD display data. (output) Transfers pixel information

 

 

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[72]

 

32 kHz clock. (output) Output from the 32 kHz oscillator.

 

 

 

 

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[15]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[73]

Memory Controller grant. (output) Notifies an external

 

 

 

 

 

device it has been granted the system bus.

 

 

 

 

 

 

 

L FCLK/

ICOCZ

LCD frame clock. (output) Indicates the start of a new

Hi-Z - Note [1]

Note [3]

GPIO[74]

frame. Also referred to as Vsync.

 

 

 

 

 

 

 

 

L LCLK/

ICOCZ

LCD line clock. (output) Indicates the start of a new line.

Hi-Z - Note [1]

Note [3]

GPIO[75]

Also referred to as Hsync.

 

 

 

 

 

 

 

 

L PCLK/

ICOCZ

LCD pixel clock. (output) Clocks valid pixel data into the

Hi-Z - Note [1]

Note [3]

GPIO[76]

LCD’s line shift buffer.

 

 

 

 

 

 

 

 

L BIAS/

 

AC bias drive. (output) Notifies the panel to change the

 

 

ICOCZ

polarity for some passive LCD panel. For TFT panels,

Hi-Z - Note [1]

Note [3]

GPIO[77]

 

this signal indicates valid pixel data.

 

 

 

 

 

 

 

 

 

 

 

Full Function UART Pins

 

 

 

 

 

 

 

 

FFRXD/

 

Full Function UART Receive. (input)

 

 

ICOCZ

MMC chip select 0. (output) Chip select 0 for the MMC

Hi-Z - Note [1]

Note [3]

GPIO[34]

 

Controller.

 

 

 

 

 

 

 

 

 

 

 

FFTXD/

 

Full Function UART Transmit. (output)

 

 

ICOCZ

MMC chip select 1. (output) Chip select 1 for the MMC

Hi-Z - Note [1]

Note [3]

GPIO[39]

 

Controller.

 

 

 

 

 

 

 

 

 

 

 

FFCTS/

ICOCZ

Full Function UART Clear-to-Send. (input)

Hi-Z - Note [1]

Note [3]

GPIO[35]

 

 

 

 

 

 

 

 

 

FFDCD/

ICOCZ

Full Function UART Data-Carrier-Detect. (input)

Hi-Z - Note [1]

Note [3]

GPIO[36]

 

 

 

 

 

 

 

 

 

FFDSR/

ICOCZ

Full Function UART Data-Set-Ready. (input)

Hi-Z - Note [1]

Note [3]

GPIO[37]

 

 

 

 

 

 

 

 

 

FFRI/

ICOCZ

Full Function UART Ring Indicator. (input)

Hi-Z - Note [1]

Note [3]

GPIO[38]

 

 

 

 

 

 

 

 

 

FFDTR/

ICOCZ

Full Function UART Data-Terminal-Ready. (output)

Hi-Z - Note [1]

Note [3]

GPIO[40]

 

 

 

 

 

 

 

 

 

FFRTS/

ICOCZ

Full Function UART Request-to-Send. (output)

Hi-Z - Note [1]

Note [3]

GPIO[41]

 

 

 

 

 

 

 

 

 

Bluetooth UART Pins

 

 

 

 

 

 

 

 

BTRXD/

ICOCZ

Bluetooth UART Receive. (input)

Hi-Z - Note [1]

Note [3]

GPIO[42]

 

 

 

 

 

 

 

 

 

BTTXD/

ICOCZ

Bluetooth UART Transmit. (output)

Hi-Z - Note [1]

Note [3]

GPIO[43]

 

 

 

 

 

 

 

 

 

2-12 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

BTCTS/

ICOCZ

Bluetooth UART Clear-to-Send. (input)

Hi-Z - Note [1]

Note [3]

GPIO[44]

 

 

 

 

 

 

 

 

 

BTRTS/

ICOCZ

Bluetooth UART Data-Terminal-Ready. (output)

Hi-Z - Note [1]

Note [3]

GPIO[45]

 

 

 

 

 

 

 

 

 

Standard UART and ICP Pins

 

 

 

 

 

 

 

IRRXD/

 

IrDA receive signal. (input) Receive pin for the FIR

 

 

ICOCZ

function.

Hi-Z - Note [1]

Note [3]

GPIO[46]

 

Standard UART receive. (input)

 

 

 

 

 

 

 

 

 

 

 

IRTXD/

 

IrDA transmit signal. (output) Transmit pin for the

 

 

ICOCZ

Standard UART, SIR and FIR functions.

Hi-Z - Note [1]

Note [3]

GPIO[47]

 

Standard UART transmit. (output)

 

 

 

 

 

 

 

 

 

 

 

HWUART Pins

 

 

 

 

 

 

 

 

 

HWTXD/

ICOCZ

Hardware UART Transmit Data.

Pulled High

Note [3]

GPIO[48]

Note [1]

 

 

 

 

 

 

 

 

HWRXD/

ICOCZ

Hardware UART Receive Data.

Pulled High

Note [3]

GPIO[49]

Note [1]

 

 

 

 

 

 

 

 

HWCTS/

ICOCZ

Hardware UART Clear-To-Send.

Pulled High

Note [3]

GPIO[50]

Note [1]

 

 

 

 

 

 

 

 

HWRTS/

ICOCZ

Hardware UART Request-to-Send.

Pulled High

Note [3]

GPIO[51]

Note [1]

 

 

 

 

 

 

 

 

MMC Controller Pins

 

 

 

 

 

 

 

 

MMCMD

ICOCZ

Multimedia Card Command. (bidirectional)

Hi-Z

Hi-Z

 

 

 

 

 

MMDAT

ICOCZ

Multimedia Card Data. (bidirectional)

Hi-Z

Hi-Z

 

 

 

 

 

 

 

PCMCIA card enable 2. (outputs) Selects a PCMCIA

 

 

nPCE[2]/

 

card. Bit one enables the high byte lane and bit zero

 

 

ICOCZ

enables the low byte lane.

Hi-Z - Note [1]

Note [5]

GPIO[53]

 

MMC clock. (output) Clock signal for the MMC

 

 

 

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[9]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[67]

MMC chip select 0. (output) Chip select 0 for the MMC

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers pixel information

 

 

L_DD[10]/

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[68]

MMC chip select 1. (output) Chip select 1 for the MMC

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

L_DD[11]/

 

LCD display data. (output) Transfers pixel information

 

 

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[69]

 

MMC clock. (output) Clock for the MMC Controller.

 

 

 

 

 

 

 

 

 

 

 

FFRXD/

 

Full Function UART Receive. (input)

 

 

ICOCZ

MMC chip select 0. (output) Chip select 0 for the MMC

Hi-Z - Note [1]

Note [3]

GPIO[34]

 

Controller.

 

 

 

 

 

 

 

 

 

 

 

FFTXD/

 

Full Function UART Transmit. (output)

 

 

ICOCZ

MMC chip select 1. (output) Chip select 1 for the MMC

Hi-Z - Note [1]

Note [3]

GPIO[39]

 

Controller.

 

 

 

 

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

2-13

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

MMCCLK/

ICOCZ

MMC clock. (output) Clock signal for the MMC

Hi-Z - Note [1]

Note [3]

GP[6]

Controller.

 

 

 

 

 

 

 

 

MMCCS0/

ICOCZ

MMC chip select 0. (output) Chip select 0 for the MMC

Hi-Z - Note [1]

Note [3]

GP[8]

Controller.

 

 

 

 

 

 

 

 

MMCCS1/

ICOCZ

MMC chip select 1. (output) Chip select 1 for the MMC

Hi-Z - Note [1]

Note [3]

GP[9]

Controller.

 

 

 

 

 

 

 

 

SSP Pins

 

 

 

 

 

 

 

 

 

SSPSCLK/

ICOCZ

Synchronous Serial Port Clock. (output)

Hi-Z - Note [1]

Note [3]

GPIO[23]

 

 

 

 

 

 

 

 

 

SSPSFRM/

ICOCZ

Synchronous Serial Port Frame. (output)

Hi-Z - Note [1]

Note [3]

GPIO[24]

 

 

 

 

 

 

 

 

 

SSPTXD/

ICOCZ

Synchronous Serial Port Transmit. (output)

Hi-Z - Note [1]

Note [3]

GPIO[25]

 

 

 

 

 

 

 

 

 

SSPRXD/

ICOCZ

Synchronous Serial Port Receive. (input)

Hi-Z - Note [1]

Note [3]

GPIO[26]

 

 

 

 

 

 

 

 

 

SSPEXTCLK/

ICOCZ

Synchronous Serial Port External Clock. (input)

Hi-Z - Note [1]

Note [3]

GPIO[27]

 

 

 

 

 

 

 

 

 

Network SSP pins

 

 

 

 

 

 

 

 

NSSPSCLK/

ICOCZ

Network Synchronous Serial Port Clock.

Pulled High

Note [3]

GPIO[81]

Note [1]

 

 

 

 

 

 

 

 

NSSPSFRM/

ICOCZ

Network Synchronous Serial Port Frame Signal.

Pulled High

Note [3]

GPIO[82]

Note [1]

 

 

 

 

 

 

 

 

NSSPTXD/

ICOCZ

Network Synchronous Serial Port Transmit.

Pulled High

Note [3]

GPIO[83]

Note [1]

 

 

 

 

 

 

 

 

NSSPRXD/

ICOCZ

Network Synchronous Serial Port Receive.

Pulled High

Note [3]

GPIO[84]

Note [1]

 

 

 

 

 

 

 

 

USB Client Pins

 

 

 

 

 

 

 

 

 

USB P

IAOAZ

USB Client Positive. (bidirectional)

Hi-Z

Hi-Z

 

 

 

 

 

USB N

IAOAZ

USB Client Negative pin. (bidirectional)

Hi-Z

Hi-Z

 

 

 

 

 

AC97 Controller and I2S Controller Pins

 

 

 

 

AC97 Audio Port bit clock. (input) AC97 clock is

 

 

 

 

generated by Codec 0 and fed into the PXA255

 

 

 

 

processor and Codec 1.

 

 

BITCLK/

 

AC97 Audio Port bit clock. (output) AC97 clock is

 

 

ICOCZ

generated by the PXA255 processor.

Hi-Z - Note [1]

Note [3]

GPIO[28]

 

I2S bit clock. (input) I2S clock is generated externally

 

 

 

 

 

 

 

 

and fed into PXA255 processor.

 

 

 

 

I2S bit clock. (output) I2S clock is generated by the

 

 

 

 

PXA255 processor.

 

 

 

 

 

 

 

SDATA_IN0/

ICOCZ

AC97 Audio Port data in. (input) Input line for Codec 0.

Hi-Z - Note [1]

Note [3]

GPIO[29]

I2S data in. (input) Input line for the I2S Controller.

 

 

 

SDATA_IN1/

 

AC97 Audio Port data in. (input) Input line for Codec 1.

 

 

ICOCZ

I2S system clock. (output) System clock from I2S

Hi-Z - Note [1]

Note [3]

GPIO[32]

 

Controller.

 

 

 

 

 

 

 

 

 

 

 

2-14 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

SDATA_OUT/

 

AC97 Audio Port data out. (output) Output from the

 

 

ICOCZ

PXA255 processor to Codecs 0 and 1.

Hi-Z - Note [1]

Note [3]

GPIO[30]

 

I2S data out. (output) Output line for the I2S Controller.

 

 

 

 

 

 

 

 

AC97 Audio Port sync signal. (output) Frame sync

 

 

SYNC/

ICOCZ

signal for the AC97 Controller.

Hi-Z - Note [1]

Note [3]

GPIO[31]

I2S sync. (output) Frame sync signal for the I2S

 

 

 

 

 

Controller.

 

 

 

 

 

 

 

nACRESET

OC

AC97 Audio Port reset signal. (output)

Driven Low

Driven Low

 

 

 

 

 

I2C Controller Pins

 

 

 

SCL

ICOCZ

I2C clock. (bidirectional)

Hi-Z

Hi-Z

SDA

ICOCZ

I2C data. (bidirectional).

Hi-Z

Hi-Z

PWM Pins

 

 

 

 

 

 

 

 

 

PWM[1:0]/

ICOCZ

Pulse Width Modulation channels 0 and 1. (outputs)

Hi-Z - Note [1]

Note [3]

GPIO[17:16]

 

 

 

 

 

 

 

 

 

DMA Pins

 

 

 

 

 

 

 

 

 

DREQ[1:0]/

 

DMA Request. (input) Notifies the DMA Controller that

 

 

ICOCZ

an external device requires a DMA transaction. DREQ[1]

Hi-Z - Note [1]

Note [3]

GPIO[19:20]

 

is GPIO[19]. DREQ[0] is GPIO[20].

 

 

 

 

 

 

 

 

 

 

 

GPIO Pins

 

 

 

 

 

 

 

 

 

GPIO[1:0]

ICOCZ

General Purpose I/O. Wakeup sources on both rising

Hi-Z - Note [1]

Note [3]

and falling edges on nRESET.

 

 

 

 

 

 

 

 

 

GPIO[14:2]

ICOCZ

General Purpose I/O. More wakeup sources for sleep

Hi-Z - Note [1]

Note [3]

mode.

 

 

 

 

 

 

 

 

 

GPIO[22:21]

ICOCZ

General Purpose I/O. Additional General Purpose I/O

Hi-Z - Note [1]

Note [3]

pins.

 

 

 

 

 

 

 

 

 

Crystal and Clock Pins

 

 

 

 

 

 

 

 

PXTAL

IA

3.6864 Mhz crystal input. No external caps are required.

Note [2]

Note [2]

 

 

 

 

 

PEXTAL

OA

3.6864 Mhz crystal output. No external caps are

Note [2]

Note [2]

required.

 

 

 

 

 

 

 

 

 

TXTAL

IA

32 Khz crystal input. No external caps are required.

Note [2]

Note [2]

 

 

 

 

 

TEXTAL

OA

32 Khz crystal output. No external caps are required.

Note [2]

Note [2]

 

 

 

 

 

L_DD[12]/

 

LCD display data. (output) Transfers pixel information

 

 

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[70]

 

RTC clock. (output) Real time clock 1 Hz tick.

 

 

 

 

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers the pixel

 

 

L_DD[13]/

 

information from the LCD Controller to the external LCD

 

 

ICOCZ

panel.

Hi-Z - Note [1]

Note [3]

GPIO[71]

 

3.6864 MHz clock. (output) Output from 3.6864 MHz

 

 

 

 

 

 

 

 

oscillator.

 

 

 

 

 

 

 

L_DD[14]/

 

LCD display data. (output) Transfers pixel information

 

 

ICOCZ

from the LCD Controller to the external LCD panel.

Hi-Z - Note [1]

Note [3]

GPIO[72]

 

32 kHz clock. (output) Output from the 32 kHz oscillator.

 

 

 

 

 

 

 

 

 

 

 

 

 

48 MHz clock. (output) Peripheral clock output derived

 

 

48MHz/GP[7]

ICOCZ

from the PLL.

Hi-Z - Note [1]

Note [3]

NOTE: This clock is only generated when the USB unit

 

 

 

 

 

 

clock enable is set.

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

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System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

RTCCLK/

ICOCZ

Real time clock. (output) 1 Hz output derived from the

Hi-Z - Note [1]

Note [3]

GP[10]

32kHz or 3.6864MHz output.

 

 

 

 

 

 

 

 

3.6MHz/GP[11]

ICOCZ

3.6864 MHz clock. (output) Output from 3.6864 MHz

Hi-Z - Note [1]

Note [3]

oscillator.

 

 

 

 

 

 

 

 

 

32kHz/GP[12]

ICOCZ

32 kHz clock. (output) Output from the 32 kHz oscillator.

Hi-Z - Note [1]

Note [3]

 

 

 

 

 

Miscellaneous Pins

 

 

 

 

 

 

 

 

BOOT_SEL

IC

Boot select pins. (input) Indicates type of boot device.

Input

Input

[2:0]

 

 

 

 

 

 

 

 

 

 

 

Power Enable for the power supply. (output) When

 

Driven low while

 

 

 

entering sleep

PWR_EN

OC

negated, it signals the power supply to remove power to

Driven High

mode. Driven high

 

 

the core because the system is entering sleep mode.

 

when sleep exit

 

 

 

 

sequence begins.

 

 

 

 

 

 

 

Main Battery Fault. (input) Signals that main battery is

 

 

 

 

low or removed. Assertion causes PXA255 processor to

 

 

nBATT_FAULT

IC

enter sleep mode or force an Imprecise Data Exception,

Input

Input

which cannot be masked. PXA255 processor will not

 

 

 

 

 

 

recognize a walk-up event while this signal is asserted.

 

 

 

 

Minimum assertion time for nBATT_FAULT is 1 ms.

 

 

 

 

 

 

 

 

 

VDD Fault. (input) Signals that the main power source is

 

 

 

 

going out of regulation. nVDD_FAULT causes the

 

 

 

 

PXA255 processor to enter sleep mode or force an

Input

Input

nVDD_FAULT

IC

Imprecise Data Exception, which cannot be masked.

 

 

nVDD_FAULT is ignored after a walk-up event until the

 

 

 

 

power supply timer completes (approximately 10 ms).

 

 

 

 

Minimum assertion time for nVDD_FAULT is 1 ms.

 

 

 

 

 

 

 

 

 

Hard reset. (input) Level sensitive input used to start the

 

Input. Driving low

 

 

processor from a known address. Assertion causes the

 

 

 

 

during sleep will

 

 

current instruction to terminate abnormally and causes a

 

 

 

Input

cause normal

nRESET

IC

reset. When nRESET is driven high, the processor starts

reset sequence

 

 

execution from address 0. nRESET must remain low until

 

 

 

 

and exit from sleep

 

 

the power supply is stable and the internal 3.6864 MHz

 

 

 

 

mode.

 

 

oscillator has stabilized.

 

 

 

 

 

 

 

 

 

 

 

 

Reset Out. (output) Asserted when nRESET is asserted

Driven low during

 

nRESET_OUT

OC

and deasserts after nRESET is deasserted but before the

any reset sequence

Driven Low

first instruction fetch. nRESET_OUT is also asserted for

- driven high prior to

 

 

 

 

 

“soft” reset events: sleep, watchdog reset, or GPIO reset.

first fetch.

 

 

 

 

 

 

JTAG and Test Pins

 

 

 

 

 

 

 

 

 

 

JTAG Test Interface Reset. Resets the JTAG/Debug

 

 

 

 

port. If JTAG/Debug is used, drive nTRST from low to

 

 

nTRST

IC

high either before or at the same time as nRESET. If

Input

Input

 

 

JTAG is not used, nTRST must be either tied to nRESET

 

 

 

 

or tied low.

 

 

 

 

 

 

 

 

 

JTAG test data input. (input) Data from the JTAG

 

 

TDI

IC

controller is sent to the PXA255 processor using this pin.

Input

Input

 

 

This pin has an internal pull-up resistor.

 

 

 

 

 

 

 

 

 

JTAG test data output. (output) Data from the PXA255

 

 

TDO

OCZ

processor is returned to the JTAG controller using this

Hi-Z

Hi-Z

 

 

pin.

 

 

 

 

 

 

 

 

 

JTAG test mode select. (input) Selects the test mode

 

 

TMS

IC

required from the JTAG controller. This pin has an

Input

Input

 

 

internal pull-up resistor.

 

 

 

 

 

 

 

2-16 Intel® PXA255 Processor Developer’s Manual

System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

TCK

IC

JTAG test clock. (input) Clock for all transfers on the

Input

Input

JTAG test interface.

 

 

 

 

 

 

 

 

 

TEST

IC

Test Mode. (input) Reserved. Must be grounded.

Input

Input

 

 

 

 

 

TESTCLK

IC

Test Clock. (input) Reserved. Must be grounded.

Input

Input

 

 

 

 

 

Power and Ground Pins

 

 

 

 

 

 

 

 

VCC

SUP

Positive supply for internal logic. Must be connected

Powered

Note [6]

to the low voltage supply on the PCB.

 

 

 

 

 

 

 

 

 

VSS

SUP

Ground supply for internal logic. Must be connected to

Grounded

Grounded

the common ground plane on the PCB.

 

 

 

 

 

 

 

 

 

PLL_VCC

SUP

Positive supply for PLLs and oscillators. Must be

Powered

Note [6]

connected to the common low voltage supply.

 

 

 

 

 

 

 

 

 

PLL_VSS

SUP

Ground supply for the PLL. Must be connected to

Grounded

Grounded

common ground plane on the PCB.

 

 

 

 

 

 

 

 

 

 

 

Positive supply for all CMOS I/O except memory bus

 

 

VCCQ

SUP

and PCMCIA pins. Must be connected to the common

Powered

Note [7]

 

 

3.3v supply on the PCB.

 

 

 

 

 

 

 

 

 

Ground supply for all CMOS I/O except memory bus

 

 

VSSQ

SUP

and PCMCIA pins. Must be connected to the common

Grounded

Grounded

 

 

ground plane on the PCB.

 

 

 

 

 

 

 

 

 

Positive supply for memory bus and PCMCIA pins.

 

 

VCCN

SUP

Must be connected to the common 3.3v or 2.5v supply on

Powered

Note [7]

 

 

the PCB.

 

 

 

 

 

 

 

 

 

Ground supply for memory bus and PCMCIA pins.

 

 

VSSN

SUP

Must be connected to the common ground plane on the

Grounded

Grounded

 

 

PCB.

 

 

 

 

 

 

 

Table 2-7. Pin Description Notes (Sheet 1 of 2)

Note

Description

 

 

 

GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins

[1]

are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input

paths must be enabled and the pullups turned off by clearing the Read Disable Hold (RDH) bit described in

 

Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-29. Even though sleep mode sets the

 

RDH bit, the pull-up resistors are not re-enabled by sleep mode.

 

 

[2]

Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to

Section 3.3.1, “32.768 kHz Oscillator” on page 3-4 and Section 3.3.2, “3.6864 MHz Oscillator” on page 3-4 for

 

details on Sleep Mode operation.

 

 

 

GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the

 

corresponding PGSRn. See Section 3.5.10, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1,

[3]

PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8. If

selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the

 

 

Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in Sleep Mode.

 

GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.

 

 

 

Static Memory Control Pins: During Sleep Mode, these pins can be programmed to either drive the value in the

[4]

Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the Power

Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these pins

 

function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by

 

the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.

 

 

Intel® PXA255 Processor Developer’s Manual

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System Architecture

Table 2-7. Pin Description Notes (Sheet 2 of 2)

Note

Description

PCMCIA Control Pins: During Sleep Mode: Can be programmed either to drive the value in the Sleep State

[5]Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the transition to sleep these pins function as described in [3], above.

[6]During sleep, this supply may be driven low. This supply must never be high impedance.

[7]Remains powered in sleep mode.

2.12Memory Map

Figure 2-2 and Figure 2-3 show the full processor memory map.

Any unused register space from 0x4000_0000 to 0x4BFF_FFFF is reserved.

Note: Accessing reserved portions of the memory map will give unpredictable results.

The PCMCIA interface is divided into Socket 0 and Socket 1 space. These two sockets are each subdivided into I/O, memory and attribute space. Each socket is allocated 256 MB of memory space.

2-18

Intel® PXA255 Processor Developer’s Manual

System Architecture

Figure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF

0xFFFF_FFFF 0xFC00_0000 0xF800_0000 0xF400_0000 0xF000_0000 0xEC00_0000 0xE800_0000 0xE400_0000 0xE000_0000

0xDC00_0000 0xD800_0000 0xD400_0000 0xD000_0000 0xCC00_0000 0xC800_0000 0xC400_0000 0xC000_0000

0xBC00_0000 0xB800_0000 0xB400_0000 0xB000_0000 0xAC00_0000 0xA800_0000 0xA400_0000 0xA000_0000 0x9C00_0000 0x9800_0000 0x9400_0000 0x9000_0000 0x8C00_0000 0x8800_0000 0x8400_0000 0x8000_0000

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

SDRAM Bank 3 (64 MB)

SDRAM Bank 2 (64 MB)

SDRAM Bank 1 (64 MB)

SDRAM Bank 0 (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Intel® PXA255 Processor Developer’s Manual

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System Architecture

Figure 2-3. Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF

0x7FFF FFFF 0x7C00_0000 0x7800_0000 0x7400_0000 0x7000_0000 0x6C00_0000 0x6800_0000 0x6400_0000 0x6000_0000 0x5C00_0000 0x5800_0000 0x5400_0000 0x5000_0000 0x4C00_0000 0x4800_0000 0x4400_0000 0x4000_0000

0x3C00_0000 0x3800_0000 0x3400_0000 0x3000_0000 0x2C00_0000 0x2800_0000 0x2400_0000 0x2000_0000

0x1C00_0000 0x1800_0000 0x1400_0000 0x1000_0000 0x0C00_0000 0x0800_0000

0x0400_0000

0x0000_0000

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Reserved (64 MB)

Memory Mapped registers (Memory Ctl)

Memory Mapped registers (LCD)

Memory Mapped registers (Peripherals)

PCMCIA/CFSlot 1 (256 MB)

PCMCIA/CF - Slot 0 (256MB)

Reserved (64 MB)

Reserved (64 MB)

Static Chip Select 5 (64 MB)

Static Chip Select 4 (64 MB)

Static Chip Select 3 (64 MB)

Static Chip Select 2 (64 MB)

Static Chip Select 1 (64 MB)

Static Chip Select 0 (64 MB)

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