Icom IC-F210S, IC-F211S, IC-F221S Service manual

SERVICE

MANUAL

UHF TRANSCEIVER

iF210S

iF211S

iF221S

INTRODUCTION		DANGER

This service manual describes the latest service information for the IC-F210S, IC-F211S and IC-F221S UHF MOBILE TRANSCEIVER at the time of publication.

	MODEL	VERSION	SYMBOL
	IC-F210S	Europe	EUR
		General	GEN
	IC-F211S	General	GEN
	IC-F221S	U.S.A.	USA

To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation.

NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than 16 V. This will ruin the transceiver.

DO NOT expose the transceiver to rain, snow or any liquids.

DO NOT reverse the polarities of the power supply when connecting the transceiver.

DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna connector. This could damage the transceiver’s front end.

ORDERING PARTS

Be sure to include the following four points when ordering replacement parts:

1.10-digit order numbers

2.Component part number and name

3.Equipment model name and unit name

4.Quantity required

<SAMPLE ORDER>

1110003490	S.IC	TA31136FN	IC-F210S	MAIN UNIT	5 pieces
8810009990	Screw	PH BT M3×8 ZK	IC-F210S	Bottom cover	10 pieces

Addresses are provided on the inside back cover for your convenience.

REPAIR NOTES

1.Make sure a problem is internal before disassembling the transceiver.

2.DO NOT open the transceiver until the transceiver is disconnected from its power source.

3.DO NOT force any of the variable components. Turn them slowly and smoothly.

4.DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.

5.DO NOT keep power ON for a long time when the transceiver is defective.

6.DO NOT transmit power into a signal generator or a sweep generator.

7.ALWAYS connect a 40 dB to 50 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment.

8.READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

EXPLICIT DEFINITIONS

FREQUENCY COVERAGE

Low Band	400-430 MHz
High Band	440-490 MHz

CHANNEL SPACING

Narrow/Wide-type	12.5 kHz/ 25.0 kHz
Narrow/Middle-type	12.5 kHz/ 20.0 kHz

	TABLE OF CONTENTS
SECTION 1	SPECIFICATIONS
SECTION 2	INSIDE VIEW
SECTION 3	DISASSEMBLY INSTRUCTIONS
SECTION 4	CIRCUIT DESCRIPTION
4 - 1	RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	.4 - 1
4 - 2	TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4 - 2
4 - 3	PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4 - 3
4 - 4	POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4 - 4
4 - 5	PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4 - 4
SECTION 5	ADJUSTMENT PROCEDURES
5 - 1	PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5 - 1
5 - 2	PLL ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5 - 4
5 - 3	SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5 - 5
SECTION 6	PARTS LIST
SECTION 7	MECHANICAL PARTS
SECTION 8	SEMI-CONDUCTOR INFORMATION
SECTION 9	BOARD LAYOUTS
9 - 1	FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9 - 1
9 - 2	MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9 - 3
SECTION 10	BLOCK DIAGRAM
SECTION 11	VOLTAGE DIAGRAMS

11 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 1 11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 2

	SECTION 1			SPECIFICATIONS
					[GEN], [USA]		[EUR]
	Measurement method				EIA-152-C/204D or TIA-603		EN 300 086
	Frequency coverage				400.000–430.000 MHz
					440.000–490.000 MHz
	Type of emission				N/W: (12.5 kHz; Narrow/25 kHz; Wide): 8K50F3E/16K0F3E				[EUR]
					(12.5 kHz; Narrow/25 kHz; Wide): 11K0F3E/16K0F3E			[USA], [GEN]
GENERAL					N/M: (12.5 kHz; Narrow/20 kHz; Middle): 8K50F3E/14K0F3E				[EUR]
	Number of conventional channels				TX 7.0 A (at 25 W), 13.0 A (at 45 W)
					Free: 8 channels, Bank: 4 channels × 2 banks
	Power supply voltage (negative ground)				13.6 V DC nominal		13.2 V DC nominal
	Current drain (approx.)				RX 1200 mA (maximum audio)
					300 mA (stand-by)
	Antenna impedance				50 Ω nominal (SO-239)
	Usable temperature range				–30˚C to +60˚C (–22˚F to +140˚F)		–25˚C to +55˚C (–13˚F to +131˚F)
	Dimensions (proj. not included)				150(W) × 40(H) × 117.5(D) mm; 529⁄32(W) × 19⁄16(H) × 45⁄8(D) inch				[25 W]
					150(W) × 40(H) × 167.5(D) mm; 529⁄32(W) × 19⁄16(H) × 619⁄32(D) inch				[45 W]
	Weight				0.8 kg; 1 lb 12 oz [25 W], 1.1 kg; 2 lb 7 oz [45 W]
	RF output power				High/Low2/Low1: 25 W/10 W/2.5 W				[25 W]
							50 W/25 W/4.5 W		[45 W]
	Modulation system				Variable reactance frequency modulation
	Maximum permissible deviation				±2.5 kHz [Narrow], ±4.0 kHz [Middle], ±5.0 kHz [Wide]
	Frequency error				±2.5 ppm		±1.5 kHz
TRANSMITTER	Spurious emissions				70 dBc typical		0.25 µW ≤ 1GHz, 1.0 µW > 1 GHz
	Adjacent channel power				60 dB [Narrow], 70 dB [Middle], [Wide]
	Audio frequency response				+2 dB to –8 dB of 6 dB/octave
					range from 300 Hz to 2550 Hz [Narrow]/3000 Hz [Middle], [Wide]
	Audio hormonic distortion				3% typical at 1 kHz, 40% deviation
	FM hum and noise (typical)				40 dB [Narrow], 46 dB [Wide]		——
	(without CCICT filter)
	Residual modulation (typical)				——		50 dB [Narrow], 53 dB [Middle]
	(with CCICT filter)						55 dB [Wide]
	Limitting charact of modulator				70–100% of max. deviation
	Microphone connector				8-pin modular (600 Ω)
	Receive system				Double-conversion superheterodyne system
	Intermediate frequencies				1st: 46.35 MHz, 2nd: 450 kHz
	Sensitivity (typical)				0.25 µV at 12 dB SINAD		–4 dBµV (emf) at 20 dB SINAD
RECEIVER
	Squelch sencitivity (at threshold) (typical)				0.25 µV		–4 dBµV (emf)
	Adjacent channel selectivity (typical)				65 dB [Narrow], 75 dB [Middle]/[Wide]
	Spurious response					75 dB
	Intermodulation (typical)				75 dB		67 dB
	Hum and noise		(without CCITT filter)		40 dB [Narrow], 45 dB [Wide]		——
	(typical)		(with CCITT filter)		——		50 dB [Narrow], 53 dB [Middle], 55 dB [Wide]
	Audio output power				4 W typical at 10% distortion with a 4 Ω load
	External SP connector				2-conductor 3.5 (d) mm (1⁄8")/4 Ω

All stated specifications are subject to change without notice or obligation.

1 - 1

SECTION 2

INSIDE VIEW

Antenna switch/

Low-pass filter circuit

Mixer*

(Q3: 3SK299) 2nd IF filter*

(FI2: ALFYM450F=K)

D/A converter*

(IC6: M62363FP-650C)

IF IC

(IC1: TA31136FN)

1st IF filter

FI1: FL-335 [EUR] FL-313 [USA],[GEN]

* Located under side of the point.

Final FET module

IC3

:RA30H4452M-21 [25W-H]

:RA30H4047M-21 [25W-L]

:RA45H4452M-21 [45W-H]

:RA45H4047M-21 [45W-L]

CPU 5V regulator* (IC10: AN78L05M)

8V regulator (IC9: TA7808F)

VCO circuit

AF amplifier (IC8: LA4425A)

Reference crystal oscillator* (X2: CR-741 15.3 MHz)

PLL IC

(IC4: MB15A02PFV-1)

2 - 1

SECTION 3 DISASSEMBLY INSTRUCTIONS

• Opening case and removing the front unit qUnscrew 4 screws A, and remove the bottom cover. wDisconnect the flat cable B from J2.

eDisconnect the cable C from J7.

rUnscrew 2 screws D , and remove the front unit in the direction of the arrow.

A

B

J2

J7

C

D

• Removing the main unit

qUnsolder 4 points E, and remove the plate F. wUnsolder the point G.

G E F E

eUnscrew 8 screws H.

rRemove the filter case I. tUnscrew the screw J.

yUnsolder 3 points K from the antenna connector. uUnsolder 4 points L from IC3.

H

I

K L

J

iLift up the front portion of the main unit and remove it.

• Installation location

UT-108 DTMF decoder unit

UT-109

Voice scrambler unit

UT-110

OPC-617 ACC cable (for external terminal connection)

OPC-617

UT-108

UT-109

UT-110

J6

J1

3 - 1

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)

The antenna switching circuit functions as a low-pass filter while receiving and as resonator circuit while transmitting. This circuit does not allow transmit signals to enter the receiver circuits.

Received signals enter the antenna connector and pass through the low-pass filter (L1–L3, C1, C2, C6–C8, C16). The filtered signals are then applied to the RF circuit passed through the λ⁄4 type antenna switching circuit (D5, D6).

4-1-2 RF CIRCUIT (MAIN UNIT)

The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals.

The signals from the antenna switching circuit pass through the two-stage tunable bandpass filters (D8, D4). The filtered signals are amplified at the RF amplifier (Q2) and then enter other two-stage bandpass filters (D9, D10) to suppress unwanted signals. The filtered signals are applied to the 1st mixer circuit (Q3).

The tunable bandpass filters (D4, D8–D10) employ varactor diodes to tune the center frequency of the RF passband for wide bandwidth receiving and good image response rejection. These diodes are controlled by the CPU (FRONT unit; IC1) via the D/A converter (IC6).

The gate control circuit reduces RF amplifier gain and attenuates RF signal to keep the audio output at a constant level.

The receiver gain is determined by the voltage on the “RSSI” line from the FM IF IC (IC1, pin 12). The gate control circuit (Q1) supplies control voltage to the RF amplifier (Q2) and sets the receiver gain.

When receiving strong signals, the “RSSI” voltage increases and the gate control voltage decreases. As the gate control voltage is used for the bias voltage of the RF amplifier (Q2), then the RF amplifier gain is decreased.

4-1-3 1ST MIXER AND 1ST IF CIRCUITS (MAIN UNIT)

The 1st mixer circuit converts the received signals to a fixed frequency of the 1st IF signal with the PLL output frequency. By changing the PLL frequency, only the desired frequency will pass through a MCF (Monolithic Crystal Filter; FI1) at the next stage of the 1st mixer.

The RF signals from the bandpass filter are applied to the 1st mixer circuit (Q3). The applied signals are mixed with the 1st LO signal coming from the RX VCO circuit (Q13) to produce a 46.35 MHz 1st IF signal. The 1st IF signal passes through a MCF (Monolithic Crystal Filter; FI1) to suppress out-of-band signals. The filtered signal is amplified at the 1st IF amplifier (Q4) and applied to the 2nd IF circuit.

4-1-4 2ND IF AND DEMODULATOR CIRCUITS (MAIN UNIT)

The 2nd mixer circuit converts the 1st IF signal to a 2nd IF signal. A double-conversion superheterodyne system improves the image rejection ratio and obtains stable receiver gain.

The 1st IF signal from the 1st IF amplifier (Q4) is applied to the 2nd mixer section of the FM IF IC (IC1, pin 16) and is then mixed with the 2nd LO signal for conversion to a 450 kHz 2nd IF signal.

IC1 contains the 2nd mixer, limiter amplifier, quadrature detector, active filter and noise amplifier circuits, etc. A tripled frequency from the PLL reference oscillator is used for the 2nd LO signal (45.9 MHz).

The 2nd IF signal from the 2nd mixer (IC1, pin 3) passes through a ceramic filter (FI2) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier section (IC1, pin 5) and applied to the quadrature detector section (IC1, pins 10, 11 and X1) to demodulate the 2nd IF signal into AF signals.

The AF signals are output from pin 9 (IC1) and are then applied to the AF amplifier circuit.

• 2nd IF and demodulator circuits

			2nd IF filter
			450 kHz	45.9 MHz	Q34
			FI2		3
				BPF
8	7	5	3	2
	Active	Noise			PLL
	filter	amp.
					IC
"SQIN" signal
				X2	IC4
from the D/A	Limiter		Noise
				15.3 MHz
converter IC (IC6).	amp.		comp.

AF signals

("DET" signal)

FM					2nd
detector
			RSSI		Mixer	IC1
						TA31136FN
9	10	11	12	13	16
					1st IF from the IF amplifier (Q4)
					"NOIS" signal to the CPU
			5V	"RSSI" signal to the CPU
	X1

4 - 1

4-1-5 AF AMPLIFIER CIRCUIT (MAIN UNIT)

The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker.

The AF signals from the FM IF IC (IC1, pin 9) are applied to the active filter circuit (IC16). The active filter circuit (highpass filter) removes CTCSS or DTCS signals.

The filtered AF signals are output from pin 14 (IC16) and are applied to the de-emphasis circuit (R117, C363) with frequency characteristics of –6 dB/octave, and then passed through the analog switch (IC14, pins 1, 2) and low-pass filter (IC5, PINS 1, 2). The filtered signal is applied to the electronic volume controller (IC6, pin 9).

The output AF signals from the electronic volume controller (IC6, pin 10) are passed through the analog switch (IC14 pins 10, 11) and are applied to the AF pre-amplifier (IC15) and AF power amplifier (IC8) to drive the speaker.

4-1-6 RECEIVER MUTE CIRCUITS (MAIN AND FRONT UNITS)

• NOISE SQUELCH

The noise squelch circuit cuts out AF signals when no RF signals are received. By detecting noise components in the AF signals, the squelch circuit switches the AF mute switch.

Some noise components in the AF signals from the FM IF IC (IC1, pin 9) are passed through the level controller (IC6, pins 1, 2). The level controlled signals are applied to the active filter section in the FM IF IC (IC1, pin 8) as “SQIN” signal. Noise components about 10 kHz are amplified and output from pin 7.

The filtered signals are converted to the pulse-type signals at the noise detector section and output from pin 13 (NOIS).

The “NOIS” signal from the FM IF IC is applied to the CPU (FRONT unit; IC1, pin 53). The CPU then analyzes the noise condition and controls the AF mute signal via “AFON” line (FRONT unit; IC1, pin 43) to the AF regulator (Q35, Q36, D29, D31).

• CTCSS AND DTCS

The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (CTCSS or DTCS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open.

A portion of the AF signals from the FM IF IC (IC1, pin 9) passes through the low-pass filter (IC16) to remove AF (voice) signals and is applied to the CTCSS or DTCS decoder inside the CPU (FRONT unit; IC1, pin 50) via the “CDEC” line to control the AF mute switch.

4-2 TRANSMITTER CIRCUITS

4-2-1 MICROPHONE AMPLIFIER CIRCUIT (MAIN AND FRONT UNITS)

The microphone amplifier circuit amplifies audio signals within +6 dB/octave pre-emphasis characteristics from the microphone to a level needed for the modulation circuit.

The AF signals (MIC) from the MIC jack (FRONT unit; J1) are amplified at the AF amplifier (FRONT unit; IC5) and applied to the MAIN unit via J2 (pin 13). The AF signal are applied to the limiter amplifier (IC5, pin 5).

The entered signals are pre-emphasized with +6dB/octave at a limiter amplifier, then passed through the analog switch (IC14, pins 4, 3) and splatter filter (IC5, pins 2, 1). The output signals from the splatter filter are applied to the level controller (IC6, pins 9, 10).

The deviation level controlled signals are then applied to the modulation circuit (D18) as the “MOD” signal after being passed through the analog switch (IC14, pins 9, 8).

4-2-2 MODULATION CIRCUIT (MAIN UNIT)

The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone audio signals.

The AF signals from the analog switch (IC14, pin 8) change the reactance of varactor diode (D18) to modulate the oscillated signal at the TX VCO circuit (Q14, D17). The modulated VCO signal is amplified at the buffer amplifiers (Q11, Q10) and is then applied to the drive amplifier circuit via the T/R switch (D14).

The CTCSS/DTCS signals from the CPU (FRONT unit; IC1, pins 13, 14, 19, 20) are passed through the low-pass filter (FRONT unit; IC5), mixer and splatter filter (IC5), and are then applied to the VCO circuit.

4-2-3 DRIVE AMPLIFIER CIRCUIT (MAIN UNIT)

The drive amplifier circuit amplifies the VCO oscillating signal to the level needed at the power amplifier.

The RF signal from the buffer amplifier (Q10) passes through the T/R switch (D14) and is amplified at the drive amplifier circuit (Q8). The amplified signal is applied to the power amplifier circuit.

4 - 2

4-2-4 POWER AMPLIFIER CIRCUIT (MAIN UNIT)

The power amplifier circuit amplifies the driver signal to an output power level.

The RF signal from the drive amplifier (Q8) is passed through the low-pass filter circuit (L18, C90, C89) and applied to the power module (IC3) to obtain 25 W or 45 W of RF power.

The amplified signal is passed through the antenna switching circuit (D2, D3), low-pass filter and APC detector, and is then applied to the antenna connector.

Control voltage for the power amplifier (IC3, pin 2) comes from the APC amplifier (IC2) to stabilize the output power. The transmit mute switch (D28) controls the APC amplifier when transmit mute is necessary.

4-2-5 APC CIRCUIT (MAIN UNIT)

The APC circuit protects the power amplifier from a mismatched output load and stabilizes the output power.

The APC detector circuit detects forward signals and reflection signals at D1 and D11 respectively. The combined voltage is at minimum level when the antenna impedance is matched at 50 Ω, and is increased when it is mismatched.

The detected voltage is applied to the APC amplifier (IC2, pin 3), and the power setting “T2” signal from the D/A converter (IC6, pin 22), controlled by the CPU (FRONT unit; IC1), is applied to the other input for reference. When antenna impedance is mismatched, the detected voltage exceeds the power setting voltage. Then the output voltage of the APC amplifier (IC2, pin 4) controls the input current of the drive amplifier (Q8) and power module (IC3) to reduce the output power.

• PLL circuit

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT (MAIN UNIT)

A PLL circuit provides stable oscillation of the transmit frequency and receive 1st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programable divider.

The PLL circuit contains the TX/RX VCO circuit (Q14, Q13). The oscillated signal is amplified at the buffer amplifiers (Q11, Q12) and then applied to the PLL IC (IC4, pin 8) via the low-pass filter (L32, C299, C300).

The PLL IC contains a prescaler, programable counter, programable divider and phase detector, etc. The entered signal is divided at the prescaler and programable counter section by the N-data ratio from the CPU. The reference signal is generated at the reference oscillator (X2) and is also applied to the PLL IC. The PLL IC detects the out-of-step phase using the reference frequency, and outputs it from pin 5. The output signal is passed through the loop filter (R96/C130/C147, R95/C146), and is then applied to the VCO circuit as the lock voltage.

If the oscillated signal drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency.

4-3-2 VCO CIRCUIT (MAIN UNIT)

The VCO circuit contains a separate RX VCO (Q13, D16) and TX VCO (Q14, D17). The oscillated signal is amplified at the buffer amplifiers (Q11, Q10) and is then applied to the T/R switch circuit (D14, D15). Then the receive 1st LO (RX) signal is applied to the 1st mixer (Q3) and the transmit (TX) signal to the drive amplifier circuit (Q8).

A portion of the signal from the buffer amplifier (Q11) is fed back to the PLL IC (IC4, pin 8) via the buffer amplifier (Q12) and low-pass filter (L32, C299, C300) as the comparison signal.

RX VCO

Buffer	D15			to 1st mixer circuit
Q10

		Q13, D16		Buffer				D14	to transmitter circuit
		TX VCO		Q11
						Buffer
Loop						Q12
		Q14, D17
filter
					IC4 MB15A02PFV1
		5	Phase	Programmable		Prescaler	8
			detector	counter
2nd LO signal to the FM IF IC	Tripler						9	SCK
45.9 MHz		2	Programmable
	×3				Shift register		10
								SO
			divider				11
	Q34							PLST
X2		1
15.3 MHz

4 - 3

4-4 POWER SUPPLY CIRCUITS

4-4-1 VOLTAGE LINES (MAIN UNIT)

	Line	Description
	HV	The voltage from a DC power supply.
		The same voltage as the HV line which is con-
		trolled by the power switching circuit (Q23, Q24).
	VCC	When the [POWER] switch is pushed, the CPU
		outputs the “PWON” control signal to the power
		switching circuit to turn the circuit ON.
		Common 5 V for the CPU converted from the HV
	CPU5V	line by the CPU5V regulator circuit (IC10). The
		circuit outputs the voltage regardless of the
		power ON/OFF condition.
	8V	Common 8 V converted from the VCC line by the
		8V regulator circuit (IC9).
	5V	Common 5 V converted from the VCC line by the
		5V regulator circuit (Q27, Q28).
		Receive 8 V controlled by the R8 regulator circuit
	R8V	(Q26, Q30) using the “RXC” signal from the CPU
		(FRONT unit; IC1, pin 18).
		Transmit 8 V controlled by the T8 regulator circuit
	T8V	(Q25, Q29, D23) using the “TMUT” signal from
		the CPU (FRONT unit; IC1, pin 40).

4-5 PORT ALLOCATIONS

4-5-1 LED DRIVER (FRONT UNIT; IC4)

	Pin	Port	Description
	number	name
	5–11	CH1–CH4	Output LEDs control signals.
		LP0–LP2	Low : While LEDs are ON.
	14	RLED	Outputs BUSY LED control signal.
	15	TLED	Outputs TX LED control signal.
	16	LIGT1	Outputs LED bright control signal.
	17	LIGT2	Outputs backlight control signal.
			Outputs external device control signal.
	18	HORN	High : When matched 5/2 tone signals
			are received.

4-5-2 OUTPUT EXPANDER (MAIN unit; IC6)

	Pin	Port	Description
	number	name
	2	VOUT1	Outputs squelch control signal.
	3	VOUT2	Outputs deviation (Tone) control signal.
	10	VOUT3	Outputs deviation control signal.
	11	VOUT4	Outputs DTCS control signal.
	14	VOUT5	Outputs RX BPF control signal.
	15	VOUT6	Outputs AGC control signal.
	22	VOUT7	Outputs TX RF power control signal.
	23	VOUT8	Outputs PLL reference control signal.

4-5-3 CPU (FRONT UNIT; IC1)

	Pin	Port	Description
	number	name
	1	TEMP	Input port for the internal temperature.
	2	BATV	Input port for low voltage detection
			from the connected power supply.
	7	RES	Input port for the reset signal.
	13, 14	SENC0,	Output ports for 5/2 tone and DTMF
		SENC1	signals.
	15	CSFT	Outputs the CPU clock shift signal.
			Outputs the cut-off frequency control
	16	DUSE	signal to the low-pass filter (MAIN; unit
			IC5) for CTCSS/DTCS switching.
	17	UNLK	Input port for the PLL unlock signal
			from the PLL IC (MAIN unit; IC4).
	18	RXC	Outputs the R8V regulator circuit
			(MAIN unit; Q26, Q30) control signal.
	19, 20	SENC0,	Output ports for 5/2 tone and DTMF
		SENC1	signals.
	21, 22	P0, P1	Input ports for key matrix.
	23–25	CENO0–	Output ports for CTCSS/DTCS signals.
		CENO2
	26, 27	P2, P3	Input ports for key matrix.
			Outputs clock signal to the PLL IC
			(MAIN unit; IC4), D/A converter (MAIN
	28	SCK	unit IC6), LED driver (FRONT unit; IC4)
			and optional board (connect to MAIN
			unit; J1).
			Outputs data signal to the PLL IC
			(MAIN unit; IC4), D/A converter (MAIN
	29	SO	unit; IC6), LED driver (FRONT unit;
			IC4) and optional board (connect to
			MAIN unit; J1).
	30	BEEP	Output port for beep sound signal.
	31	ESDA	I/O port for the data signal for the EEP-
			ROM (FRONT unit; IC3)
	32	ESCL	Outputs clock signal for the EEPROM
			(FRONT unit; IC3).
	33	MMUT	Input port for the MIC mute signal from
			the optional board via MAIN unit, J1.
	34	RMUT	Input port for the AF mute signal from
			the optional board via MAIN unit, J1.
	36	PLST	Outputs strobe signal for the PLL IC
			(MAIN unit; IC4).
	37	DAST	Outputs strobe signal for the D/A con-
			verter IC (MAIN unit; IC6).
	38	EXST	Outputs strobe signal for LED driver IC
			(FRONT unit; IC4).
	39	EXOE	Outputs control signal for the LED dri-
			ver IC (FRONT unit; IC4).
	40	TMUT	Outputs the T8V regulator circuit
			(MAIN unit; Q25, Q29, D23) control
			signal.

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CPU-Continued

	Pin	Port	Description
	number	name
			Outputs control signal for the power
	41	PWON	switching circuit (MAIN unit; Q23,
			Q24).
	42	NWC	Outputs IF bandwidth control signal.
			Low : While IF bandwidth is narrow.
			Outputs control signal for the AF mute
	43	AFON	circuit (MAIN unit; Q35, Q36, D29).
			High : While AF amplifier (MAIN unit;
			IC8) is activated.
	44–46	OPT3–	I/O ports for the optional board control
		OPT1	signals.
	47	BUSY	Outputs BUSY detection signal for the
			optional board via MAIN unit, J1.
	48	SI	Input port for the clock signal from the
			optional board via MAIN unit, J1.
	49	CLI	Input port for the cloning signal.
	50	CLO	Output port for the cloning signal.
	51	POSW	Input for the POWER switch.
	52	IGSW	Input port for the remort control signal
			from external connector (Main unit; J6).
	53	NOIS	Input port for the “NOIS” signal which is
			used noise squelch operation from the
			FM IC (MAIN unit; IC1)
	54	CIRQ	Input port for the interruption signal
			from the optional board via MAIN unit,
			J1.
	55	CCS	Outputs the chip select signal for the
			optional board via MAIN unit, J1.
	56	PTT	Input port for the PTT switch from
			microphone.
			Input port for the PTT switch from the
	57	EPTT	external connector (MAIN unit; J6).
			Low : External PTT switch is ON.
			Input port for the microphone hanger
	58	HANG	detection signal.
			Low :The microphone on hook.
			Input port for the AF volume control
	59	AFVI	(FRONT unit; R14).
			High : [VOL] is maximum clockwise.
	60	CDEC	Input port for CTCSS/DTCS decoding
			signals.
	61	SDEC	Input port for the single tone decoding
			signals.
	62	OPV1V2	Input port for the optional board detec-
			tion signal.
	63	RSSI	Input port for the decoding signal of the
			received signal strength.
	64	LVIN	Input port for the PLL lock voltage.

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