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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003.
These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Renesas Technology Corp.
Hitachi Single-Chip Microcomputer
H8/3437 Series
H8/3437
HD6473437, HD6433437
H8/3436
HD6433436
H8/3434
HD6473434, HD6433434
H8/3437W
HD6433437W
H8/3436W
HD6433436W
H8/3434W
HD6433434W
H8/3437F-ZTAT™
HD64F3437
H8/3437SF-ZTAT™
HD64F3437S
H8/3434F-ZTAT™
HD64F3434
Hardware Manual
ADE-602-077F Rev. 7.0 3/14/02 Hitachi, Ltd.
Cautions
1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
2.Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.
3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.
4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
5.This product is not designed to be radiation resistant.
6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.
7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s operation is not guaranteed if they are accessed.
Preface
The H8/3437 Series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300 CPU featuring a 32-bit internal architecture as its core.
On-chip peripheral functions include ROM, RAM, four kinds of timers, a serial communication
interface (SCI), host interface (HIF), keyboard controller, D/A converter, A/D converter, and I/O ports, enabling the H8/3437 Series to be used as a microcontroller for embedding in high-speed
control systems. Flash memory (F-ZTAT™ *), PROM (ZTAT® *), and mask ROM are available as on-chip ROM, enabling users to respond quickly and flexibly to changing application
specifications and the demands of the transition from initial to full-fledged volume production.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.
ZTAT is a registered trademark of Hitachi, Ltd.
Intended Readership: This manual is intended for users undertaking the design of an application system using a H8/3437 Series microcomputer. Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers.
Purpose: |
The purpose of this manual is to give users an understanding of the |
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hardware functions and electrical characteristics of the H8/3437 Series. |
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Details of execution instructions can be found in the H8/300 Series |
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Programming Manual, which should be read in conjunction with the present |
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manual. |
Using this Manual: |
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•For an overall understanding of the H8/3437 Series’ functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics.
•For a detailed understanding of CPU functions
Refer to the separate publication H8/300 Series Programming Manual.
•For a detailed description of a register’s function when the register name is known. Information on addresses, bit contents, and initialization is summarized in Appendix B, Internal I/O Register.
Note on bit notation: Bits are shown in high-to-low order from left to right.
Related Material: The latest information is available at our Web Site. Please make sure that you have the most up-to-date information available. http://www.hitachisemiconductor.com/
User's Manuals on the H8/3437 Series:
Manual Title |
ADE No. |
H8/3437 Series Hardware Manual |
This manual |
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H8/300 Series Programming Manual |
ADE-602-025 |
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Users manuals for development tools:
Manual Title |
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ADE No. |
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C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual |
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ADE-702-247 |
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Simulator Debugger Users Manual |
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ADE-702-282 |
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Hitachi Debugging Interface Users Manual |
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ADE-702-161 |
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Hitachi Embedded Workshop Users Manual |
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ADE-702-201 |
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H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging |
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ADE-702-231 |
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Interface Users Manual |
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Notes on S-Mask Model (Single-Power-Supply Specification)
There are two versions of the H8/3437F with on-chip flash memory: a dual-power-supply version and a single-power-supply (S-mask) version. Points to be noted when using the H8/3437F single- power-supply S-mask model are given below.
1.Notes on Voltage Application
12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.
The flash memory programming power supply for the S-mask model (single-power-supply |
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specification) is V |
CC . The programming power supply for the dual-power-supply model is the FV |
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PP |
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pin (12 V), but the single-power-supply model (S-mask model) does not have an FV |
PP |
pin. |
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Also, in boot mode, 12 V has to be applied to the MD |
1 pin in the dual-power-supply model, but 12 |
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V application is not necessary in the single-power-supply model (S-mask model). |
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The maximum rating of the MD |
1 pin is V |
CC +0.3 V. Applying a voltage in excess of the |
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maximum rating will permanently damage the device. |
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Do not select the HN28F101 programmer setting for the S-mask model (single-power-supply specification). If this setting is made by mistake, 12 V will be applied to the STBY pin, possibly causing permanent damage to the device.
When using a PROM programmer to program the on-chip flash memory in the S-mask model (single-power-supply specification), use a PROM programmer that supports Hitachi
microcomputer devices with 64-kbyte on-chip flash memory. Also, only use the specified socket adapter. Using the wrong PROM programmer or socket adapter may damage the device.
The following PROM programmers support the S-mask model (single-power-supply specification).
DATA I/O: UNISITE, 2900, 3900, etc.
Minato: 1892, 1891, 1890, etc.
2.Product Type Names and Markings
Table 1 shows examples of product type names and markings for the H8/3437F (dual-power- supply specification) and H8/3437SF (single-power-supply specification), and the differences in flash memory programming power supply.
Table 1 Differences in H8/3437F and H8/3437F S-Mask Model Markings
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Dual-Power-Supply Model: |
Single-Power-Supply Model: |
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H8/3437F |
H8/3437F S-Mask Model |
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Product type name |
HD64F3437F16/TF16 |
HD64F3437SF16/TF16 |
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Sample markings |
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H8/3437 |
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H8/3437 |
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8M3 |
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8M3 |
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HD |
HD S |
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64F3437F16 |
64F3437F16 |
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JAPAN |
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JAPAN |
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“S” is printed above the type name |
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Flash memory |
V PP power supply |
V CC power supply |
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programming power |
(12.0 V ±0.6 V) |
(5.0 V ±10%) |
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supply
3.Differences in S-Mask Model
Table 2 shows the differences between the H8/3437F (dual-power-supply specification) and
H8/3437SF (single-power-supply specification).
Table 2 Differences between H8/3437F and H8/3437F S-Mask Model
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Dual-Power-Supply Model: |
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Single-Power-Supply Model: |
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Item |
H8/3437F |
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H8/3437F S-Mask Model |
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Program/ |
12 V must be applied from off-chip |
12 V application not required |
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erase voltage |
V PP |
(12.0 V ±0.6 V) |
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V CC |
single-power-supply programming |
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V CC |
(5.0 V ±10%) |
FV PP (FWE) |
Dual function as FV |
PP power supply |
No programming control pin |
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pin function |
and STBY function |
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Programming |
• |
Writer mode |
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(See section 21 for the use of these |
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• |
On-board |
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Boot mode
User programming mode
Operating |
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Writer mode |
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modes allowing |
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Boot mode |
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modes) |
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on-board |
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User programming mode |
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programming |
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On-board |
1-byte-unit programming |
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programming |
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Programming |
Select Hitachi stand-alone flash |
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Special programming mode setting |
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with PROM |
memory HN28F101 setting |
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required. Use of PROM programmer |
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programmer |
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that supports Hitachi microcomputer |
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device types with 64-kbyte on-chip flash |
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memory. (128-byte-unit fast page |
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programming) |
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Boot mode |
Reset release after MD |
1 = FV PP |
/STBY = |
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Pin |
MD 1 |
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MD 0 |
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P9 2 |
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P9 1 |
P9 0 |
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setting |
12 V application |
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Setting level |
0 |
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Reset release after above pin settings |
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User program |
FV |
PP = 12 V application |
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mode setting |
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method
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Dual-Power-Supply Model: |
Single-Power-Supply Model: |
Item |
H8/3437F |
H8/3437F S-Mask Model |
Programming |
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tMDS |
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tMDS |
mode timing |
RES |
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RES |
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MD |
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MD |
1, |
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MD |
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12 V |
P9 |
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Min 0 |
s |
P9 |
1, |
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P9 |
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tMDS: 4tcyc (min.) |
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Prewrite |
Required before erasing |
Not required |
processing |
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Programming |
Block corresponding to programming |
Settings at left not required |
processing |
address must be set in EBR1/EBR2 |
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registers before programming |
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EBR register |
EBR1, EBR2 |
EBR2 |
configuration |
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Memory map (block configuration)
SB0 (128 bytes) |
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EB0 (1 kbyte) |
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SB1 (128 bytes) |
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EB1 (1 kbyte) |
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SB2 (128 bytes) |
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EB2 (1 kbyte) |
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SB3 (128 bytes) |
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EB3 (1 kbyte) |
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SB4 (512 bytes) |
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SB5 (1 kbyte) |
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SB6 (1 kbyte) |
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SB7 (1 kbyte) |
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LB0 (4 kbytes) |
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60 |
kbytes |
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EB4 (24 kbytes) |
60 |
kbytes |
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LB1(8 kbytes) |
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LB2 (8 kbytes) |
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LB3 (8 kbytes) |
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EB5 (16 kbytes) |
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LB4 (8 kbytes) |
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LB5 (8 kbytes) |
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EB6 (12 kbytes) |
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LB6 (12 kbytes) |
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LB7 (2 kbytes) |
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EB7 (2 kbytes) |
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Reset during |
Drive RES pin low for at least 10 |
RES pulse |
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Drive RES pin low for at least 20 |
RES pulse |
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operation |
system clock cycles (10ø). ( |
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system clock cycles (20ø). ( |
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width t RESW = min. 10t cyc ) |
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width t RESW = min. 20t cyc ) |
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Dual-Power-Supply Model: |
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Single-Power-Supply Model: |
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Item |
H8/3437F |
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H8/3437F S-Mask Model |
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MDCR |
7 |
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6 |
5 |
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4 |
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2 |
1 |
0 |
7 |
6 |
5 |
4 |
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1 |
0 |
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MDS1 |
MDS0 |
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EXPE |
— |
— |
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— |
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MDS1 |
MDS0 |
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Bit 7: Expanded mode enable (EXPE) |
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WSCR |
7 |
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6 |
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0 |
7 |
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RAMS RAM0 |
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CKDBL |
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WMS1WMS0 |
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WC1 |
WC0 |
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CKDBL |
FLSHE |
WMS1WMS0 |
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WC1 |
WC0 |
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Bit 4: Flash memory control register |
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enable (FLSHE) |
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FLMCR1 |
7 |
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6 |
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0 |
7 |
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V PP |
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EV |
PV |
E |
P |
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FWE |
SWE |
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EV |
PV |
E |
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Bit 7: Flash write enable (FWE)
Bit 6: Software write enable (SWE)
FLMCR2 —
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
FLER |
— |
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ESU |
PSU |
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Bit 7: Flash memory error (FLER) |
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Bit 1: Erase setup (ESU) |
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Bit 0: Program setup (PSU) |
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EBR1 |
7 |
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LB7 |
LB6 |
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LB5 |
LB4 |
LB3 |
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LB2 |
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LB1 |
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LB0 |
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This address is not used. |
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EBR2 |
7 |
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0 |
7 |
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SB7 |
SB6 |
SB5 |
SB4 |
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SB3 |
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SB2 |
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SB1 |
SB0 |
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EB7 |
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EB6 |
EB5 |
EB4 |
EB3 |
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EB2 |
EB1 |
EB0 |
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Erase block register (EBR2) |
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EB0 (1 kbyte): |
H'0000 to H'03FF |
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EB1 (1 kbyte): |
H'0400 to H'07FF |
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EB2 (1 kbyte): |
H'0800 to H'0BFF |
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EB3 (1 kbyte): |
H'0C00 to H'0FFF |
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EB4 (28 kbytes): H'1000 to H'7FFF |
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EB5 (16 kbytes): H'8000 to H'BFFF |
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EB6 (12 kbytes): H'C000 to H'EF7F |
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EB7 (2 kbytes): |
H'EF00 to H'F77F |
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Details |
See section 20, ROM (Dual-Power- |
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See section 21, ROM (Single-Power- |
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concerning |
Supply 60-Kbyte Flash Memory |
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Supply 60-Kbyte Flash Memory |
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flash memory |
Version) |
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Version) |
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Electrical |
See section 23, Electrical |
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See section 23, Electrical |
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characteristics |
Characteristics |
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Characteristics |
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Registers |
See Appendix B, Registers |
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See Appendix B, Registers |
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Table 3 shows differences in the development environments of the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification).
Table 3 H8/3437F and H8/3437F S-Mask Model Development Environments
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Dual-Power-Supply Model: |
Single-Power-Supply Model: |
Item |
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H8/3437F |
H8/3437F S-Mask Model |
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E6000 |
Emulator |
Hitachi |
Hitachi |
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emulator |
unit |
HS3008EPI60H |
HS3008EPI60H |
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User |
Hitachi |
Hitachi |
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cable |
HS3437ECH61H |
HS3437ECH61H |
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Programming |
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Hitachi |
Minato |
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socket adapter |
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HS3434ESHF1H |
DATA I/O |
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Adapter board |
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Hitachi |
Hitachi |
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HS0008EASF1H/2H |
HS0008EASF3H |
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Windows interface |
Hitachi |
Hitachi |
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software |
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HS6400FWIW2SF |
HS6400FWIW2SF |
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Table 4 shows differences in the pin settings of the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification).
Table 4 H8/3437F and H8/3437F S-Mask Model Pin Settings
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Dual-Power-Supply Model: |
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Single-Power-Supply Model: |
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Item |
H8/3437F |
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H8/3437F S-Mask Model |
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Boot mode |
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H8/3437F |
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H8/3437SF |
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12 V |
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V CC (5 V) |
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23 |
P9 |
2 |
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24 |
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8 |
FV |
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/STBY |
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P9 |
1 |
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PP |
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25 |
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5 |
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P9 0 |
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MD |
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5 |
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1 |
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MD |
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1 |
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6 |
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MD |
0 |
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V SS |
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(GND) |
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User programming |
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H8/3437F |
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There are no state transitions due to pin |
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mode |
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states. Transitions should be implemented |
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12 V |
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by means of register settings by software. |
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8 |
FV |
PP |
/STBY |
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List of Items Revised or Added for This Version
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Description |
Section |
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Page |
Item |
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(see Manual for details) |
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Notes on S-Mask Model |
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Table 1 Differences in |
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Single-Power-Supply |
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(Single-Power-Supply |
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H8/3437F and H8/3437F S- |
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Model: H8/3437F S- |
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Specification) |
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Mask Model Markings |
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mask model sample |
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marking amended |
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1.1 Overview |
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3 |
Table 1.1 |
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Features |
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“Other features” |
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specifications amended. |
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H8/3434F-ZTAT ROM |
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amended in “Series |
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Lineup” specifications. |
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Notes 1 and 3 deleted |
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1.3.1 |
Pin Arrangement |
6 |
Figure 1.2 |
Pin Arrangement |
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Rotated 90 degrees to |
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(FP-100B, TFP-100B, Top |
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View) |
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the bottom left. |
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6.2.2 |
Oscillator Circuit |
95 to 99 |
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Added |
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(H8/3437SF) |
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12.3.2 |
Asynchronous |
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264 |
Figure 12.5 |
Sample Flowchart |
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Flowchart amended. |
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Mode |
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for Transmitting Serial Data |
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Procedure 1 description |
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added. |
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Section 13 |
I |
2C Bus |
283 |
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Descriptions 1 and 3 |
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Interface [Option] |
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deleted |
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13.4 |
Application Notes |
311 to 315 |
• Note on Issuance of |
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Added |
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Retransmission Start |
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Condition |
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• Note on Issuance of Stop |
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Condition |
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Countermeasure |
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Additional Note |
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• |
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Precautions when Clearing |
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the IRIC Flag when Using |
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the Wait Function |
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15.6 |
Application Notes |
354 |
Figure 15.10 |
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Example of |
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Figure amended |
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Analog Input Circuit |
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18.3.2 |
Notes on |
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373 |
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(1) description added. |
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Programming |
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19.6.1 |
Writer Mode |
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418 |
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Description amended |
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Setting |
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Description |
Section |
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(see Manual for details) |
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21.1.7 |
Flash Memory |
504 |
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Figure 21.2 |
Flash Memory |
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“SWE” amended to |
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Operating Modes |
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Related State Transitions |
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“FLSHE”. |
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Figure 21.3 |
Boot Mode |
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Procedure 2 amended. |
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Figure 21.4 |
User |
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Procedure 2 amended. |
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Programming Mode (Example) |
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21.2.3 |
Erase Block |
511 |
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Bit 7 * and Note |
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Register 2 (EBR2) |
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21.3.1 |
Boot Mode |
516 |
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RAM Area Allocation in Boot |
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Description amended. |
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Mode |
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517 |
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Figure 21.9 |
RAM Areas in |
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Amended |
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Boot Mode |
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Notes on Use of Boot Mode |
5 description amended. |
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21.4 to 21.4.4 |
520 to 524 |
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Entire description |
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amended. |
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21.5.1 |
Writer Mode |
528 |
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* and Note description |
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Setting |
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21.5.3 |
Operation in |
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Figure 21.22 |
Status Read |
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Note amended |
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Writer Mode |
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Table 21.19 |
Status Read |
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21.6 |
Flash Memory |
540 |
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(1) Program with the specified |
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Programming and Erasing |
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voltage and timing |
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Precautions |
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541 |
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Table 21.22 |
Area Accessed in |
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FLSHE = 1 mode 2 |
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Each Mode with FLSHE = 0 |
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and FLSHE = 1 |
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22.3.5 |
Application Note |
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2 description deleted. |
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23 |
Electrical |
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553 to 604 |
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Heading number |
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Characteristics |
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23.3 |
Electrical |
579 |
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Entire description newly |
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Characteristics |
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(H8/3437SF Low-Voltage |
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B.2 |
Function |
665 |
I |
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2C Bus Control Register |
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Table amended and note |
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Bit 2 to 0: I2C Transfer Rate |
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Select |
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Contents |
Section 1 |
Overview |
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1.1 |
Overview................................................................. |
1 |
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1.2 |
Block Diagram ................................................................ |
5 |
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1.3Pin Assignments and Functions
1.3.1Pin Arrangement .........................................................
1.3.2Pin Functions ..................................................................................................................
Section 2 |
CPU |
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2.1 Overview................................................................ |
19 |
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2.1.1 Features ............................................................. |
19 |
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2.1.2Address Space.........................................................
2.1.3Register Configuration......................................................
2.2 |
Register Descriptions ...................................................... |
......21 |
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2.2.1 |
General Registers ........................................................ |
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2.2.2 |
Control Registers ........................................................ |
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2.2.3 |
Initial Register Values .................................................... |
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2.3 |
Data Formats |
...................................................... ....... .... |
23 |
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2.3.1 |
Data Formats in General Registers ................................................. |
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2.3.2 ........................................................ |
Memory Data Formats |
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2.4 |
Addressing ..............................................................Modes |
26 |
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2.4.1 ........................................................ |
Addressing Mode |
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2.4.2 ............................................... |
Calculation of Effective Address |
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2.5 |
Instruction ..............................................................Set |
32 |
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2.5.1Data Transfer Instructions ...................................................
2.5.2Arithmetic Operations .....................................................
2.5.3Logic Operations ........................................................
2.5.4Shift Operations ........................................................
2.5.5Bit Manipulations.......................................................
2.5.6Branching Instructions.....................................................
2.5.7System Control Instructions...................................................
2.5.8Block Data Transfer Instruction................................................
2.6 CPU States ............................................................. |
...49 |
2.6.1Overview..........................................................
2.6.2Program Execution State ....................................................
2.6.3Exception-Handling State ....................................................
2.6.4Power-Down State .......................................................
2.7Access Timing and Bus Cycle ........................................................
2.7.1Access to On-Chip Memory (RAM and ROM).............................................
2.7.2Access to On-Chip Register Field and External Devices .....................................
i
Section 3 |
MCU Operating Modes and Address Space |
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3.1 |
Overview................................................................. |
57 |
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3.1.1Mode Selection ..........................................................
3.1.2Mode and System Control Registers .................................................
3.2System Control Register (SYSCR)........................................................
3.3Mode Control Register (MDCR) ..........................................................
3.4Address Space Map in Each Operating Mode ..................................................
Section 4 |
Exception Handling |
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4.1 |
Overview................................................................. |
65 |
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4.2Reset......................................................
4.2.1Overview...........................................................
4.2.2Reset Sequence ..........................................................
4.2.3Disabling of Interrupts after Reset...............................................................
4.3 |
Interrupts .................................................................. |
68 |
4.3.1Overview...........................................................
4.3.2Interrupt-Related Registers ....................................................
4.3.3External Interrupts .......................................................
4.3.4Internal Interrupts........................................................
4.3.5Interrupt Handling ........................................................
4.3.6Interrupt Response Time......................................................
4.3.7Precaution ............................................................
4.4 Note on Stack Handling ............................................................82
Section 5 |
Wait-State Controller |
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5.1 |
Overview |
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83 |
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5.1.1 |
Features ............................................................. |
83 |
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5.1.2Block Diagram..........................................................
5.1.3Input/Output Pins........................................................
5.1.4Register Configuration.......................................................
5.2 |
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Register Description....................................................... |
.......84 |
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5.2.1 Wait-State Control Register (WSCR)................................................. |
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5.3 |
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Wait Modes.................................................................. |
86 |
Section 6 |
Clock Pulse Generator .............................................. |
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6.1 |
Overview................................................................. |
89 |
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6.1.1Block Diagram..........................................................
6.1.2Wait-State Control Register (WSCR)..................................................
6.2 |
Oscillator Circuit.......................................................... |
.....91 |
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6.2.1 |
Oscillator (Generic Device) .................................................... |
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6.2.2 |
Oscillator Circuit (H8/3437S).................................................... |
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6.3 |
Duty Adjustment Circuit............................................................ |
99 |
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6.4 |
Prescaler |
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....9 |
ii
Section 7 |
I/O Ports |
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7.1 |
Overview |
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101 |
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7.2 |
Port 1................................................................... |
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7.2.1 .......................................................... |
Overview |
4 |
7.2.2Register Configuration and Descriptions
7.2.3Pin Functions in Each Mode ...................................................
7.2.4Input Pull-Up Transistors....................................................
7.3Port 2.................................................................................................................
7.3.1 |
Overview |
...........................................................0 |
7.3.2Register Configuration and Descriptions
7.3.3Pin Functions in Each Mode ...................................................
7.3.4Input Pull-Up Transistors....................................................
7.4Port 3.................................................................................................................
7.4.1 |
Overview |
...........................................................6 |
7.4.2Register Configuration and Descriptions
7.4.3Pin Functions in Each Mode ...................................................
7.4.4Input Pull-Up Transistors....................................................
7.5Port 4.................................................................................................................
7.5.1 |
Overview |
..........................................................1 |
7.5.2Register Configuration and Descriptions
7.5.3Pin Functions ..........................................................
7.6Port 5.................................................................................................................
7.6.1 |
Overview |
...........................................................6 |
7.6.2Register Configuration and Descriptions
7.6.3Pin Functions ..........................................................
7.7Port 6.................................................................................................................
7.7.1 |
Overview |
...........................................................9 |
7.7.2Register Configuration and Descriptions
7.7.3Pin Functions ..........................................................
7.7.4Input Pull-Up Transistors....................................................
7.8Port 7.................................................................................................................
7.8.1 |
Overview |
...........................................................5 |
7.8.2Register Configuration and Descriptions
7.9Port 8................................................................................................................
7.9.1 Overview |
..........................................................6 |
7.9.2Register Configuration and Descriptions
7.9.3Pin Functions .........................................................
7.10Port 9.................................................................................................................
7.10.1 Overview |
...........................................................41 |
7.10.2Register Configuration and Descriptions
7.10.3Pin Functions ..........................................................
7.11Port A .................................................................................................................
7.11.1 Overview |
...........................................................46 |
iii
7.11.2Register Configuration and Descriptions................................................
7.11.3Pin Functions in Each Mode ....................................................
7.11.4Input Pull-Up Transistors.....................................................
7.12 Port B .................................................................. |
..15 |
7.12.1 Overview............................................................ |
50 |
7.12.2Register Configuration and Descriptions
7.12.3Pin Functions in Each Mode ....................................................
7.12.4Input Pull-Up Transistors.....................................................................................................
Section 8 |
16-Bit Free-Running Timer |
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8.1 |
Overview |
................................................................. |
155 |
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8.1.1 |
Features .............................................................. |
155 |
8.1.2Block Diagram..........................................................
8.1.3Input and Output Pins ......................................................
8.1.4Register Configuration.......................................................
8.2 |
Register Descriptions ............................................................. |
159 |
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8.2.1 |
Free-Running Counter (FRC) ..................................................... |
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8.2.2 |
Output Compare Registers A and B (OCRA and OCRB) .................................... |
159 |
8.2.3Input Capture Registers A to D (ICRA to ICRD)
8.2.4Timer Interrupt Enable Register (TIER)............................................
8.2.5Timer Control/Status Register (TCSR) ................................................
8.2.6Timer Control Register (TCR)....................................................
8.2.7Timer Output Compare Control Register (TOCR) ......................................................................................
8.3 |
CPU Interface........................................................... |
.....170 |
8.4 |
Operation................................................................... |
173 |
8.4.1FRC Increment Timing .......................................................
8.4.2Output Compare Timing .......................................................
8.4.3FRC Clear Timing ..........................................................
8.4.4Input Capture Timing........................................................
8.4.5Timing of Input Capture Flag (ICF) Setting .............................................
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8.4.6 |
Setting of Output Compare Flags A and B (OCFA and OCFB) .......................... |
179 |
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8.4.7 |
Setting of FRC Overflow Flag (OVF) ............................................... |
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8.5 |
Interrupts |
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...181 |
8.6 |
Sample Application........................................................ |
.......182 |
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8.7 |
Application ........................................................ .......Notes |
183 |
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Section 9 |
8-Bit Timers |
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9.1 Overview................................................................. |
189 |
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9.1.1 Features ............................................................. |
189 |
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9.1.2Block Diagram.........................................................
9.1.3Input and Output Pins .....................................................
9.1.4Register Configuration.......................................................
iv
9.2 Register Descriptions ............................................................ |
192 |
9.2.1 Timer Counter (TCNT)...................................................... |
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9.2.2 Time Constant Registers A and B (TCORA and TCORB) .................................. |
19 |
9.2.3Timer Control Register (TCR)..................................................
9.2.4Timer Control/Status Register (TCSR) ..............................................
9.2.5Serial/Timer Control Register (STCR) ..............................................
9.3 Operation............................................................... |
..19 |
9.3.1TCNT Increment Timing .....................................................
9.3.2Compare-Match Timing.......................................................
9.3.3External Reset of TCNT ...................................................
9.3.4Setting of TCSR Overflow Flag (OVF).............................................
9.4 |
Interrupts ................................................................ |
20 |
9.5 |
Sample Application............................................................. |
204 |
9.6 |
Application Notes ............................................................. |
205 |
9.6.1Contention between TCNT Write and Clear ...........................................
9.6.2Contention between TCNT Write and Increment.........................................
9.6.3 |
Contention between TCOR Write and Compare - Match ...................................... |
20 |
9.6.4 |
Contention between Compare - Match A and Compare - Match B .......................... |
208 |
9.6.5 |
Increment Caused by Changing of Internal Clock Source .................................... |
2 |
Section 10 PWM Timers .................................................... |
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10.1 Overview |
................................................................. |
211 |
10.1.1 ............................................................. |
Features |
211 |
10.1.2Block Diagram.........................................................
10.1.3Input and Output Pins .....................................................
10.1.4Register Configuration.......................................................
10.2 Register Descriptions ....................................................... |
......213 |
10.2.1Timer Counter (TCNT).......................................................
10.2.2Duty Register (DTR) .......................................................
10.2.3Timer Control Register (TCR)....................................................
10.3 Operation |
..................................................................21 |
10.3.1Timer Increment..........................................................
10.3.2PWM Operation..........................................................
10.4 Application Notes ......................................................... |
.....219 |
Section 11 Watchdog Timer ..................................................
11.1 |
Overview |
................................................................. |
221 |
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11.1.1 ............................................................. |
Features |
221 |
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11.1.2 .......................................................... |
Block Diagram |
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11.1.3 ........................................................... |
Output Pin |
22 |
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11.1.4 ....................................................... |
Register Configuration |
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11.2 |
Register Descriptions ....................................................... ...... |
223 |
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11.2.1 ....................................................... |
Timer Counter (TCNT) |
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v
11.2.2Timer Control/Status Register (TCSR)
11.2.3System Control Register (SYSCR)..................................................
11.2.4Register Access..........................................................................................................
11.3 Operation |
...................................................................227 |
11.3.1Watchdog Timer Mode ........................................................
11.3.2Interval Timer Mode .......................................................
11.3.3Setting the Overflow Flag.....................................................
11.3.4RESO Signal Output Timing...................................................
11.4 Application Notes ............................................................... |
230 |
11.4.1Contention between TCNT Write and Increment
11.4.2Changing the Clock Select Bits (CKS2 to CKS0)............................................
11.4.3Recovery from Software Standby Mode ..........................................................................................
11.4.4 |
Switching between Watchdog Timer Mode and Interval Timer Mode ................ |
231 |
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11.4.5 |
System Reset by |
RESO Signal ............................................. |
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11.4.6 Detection of Program Runaway.................................................... |
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Section 12 Serial Communication Interface ...................................... |
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12.1 Overview |
.................................................................. |
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233 |
12.1.1 |
Features .............................................................. |
|
233 |
12.1.2Block Diagram..........................................................
12.1.3Input and Output Pins ......................................................
12.1.4Register Configuration........................................................
12.2 Register Descriptions ....................................................... |
.......237 |
12.2.1Receive Shift Register (RSR) ....................................................
12.2.2Receive Data Register (RDR)....................................................
12.2.3Transmit Shift Register (TSR)....................................................
12.2.4Transmit Data Register (TDR)....................................................
12.2.5Serial Mode Register (SMR) ....................................................
12.2.6Serial Control Register (SCR) ....................................................
12.2.7Serial Status Register (SSR) ....................................................
12.2.8Bit Rate Register (BRR) .....................................................
12.2.9Serial/Timer Control Register (STCR) ................................................
12.3 Operation................................................................... |
258 |
12.3.1 Overview............................................................ |
58 |
12.3.2Asynchronous Mode
12.3.3Synchronous Mode ...................................................................................................................
12.4 |
Interrupts .................................................... |
............ ..27 |
12.5 |
Application Notes ............................................................... |
279 |
Section 13 I |
2 C Bus Interface [Option] |
.......................................... |
13.1 Overview |
.................................................................. |
283 |
13.1.1 .............................................................. |
Features |
283 |
13.1.2 ........................................................... |
Block Diagram |
|
vi
13.1.3Input/Output Pins........................................................
13.1.4Register Configuration.......................................................
13.2 Register Descriptions ............................................................. |
287 |
13.2.1I2 C Bus Data Register (ICDR)..................................................
13.2.2Slave Address Register (SAR)..................................................
13.2.3I2 C Bus Mode Register (ICMR).................................................
13.2.4I2 C Bus Control Register (ICCR).................................................
13.2.5I2 C Bus Status Register (ICSR) .................................................
13.2.6Serial/Timer Control Register (STCR) ................................................
13.3 Operation |
...................................................................2 |
13.3.1I 2 C Bus Data Format .......................................................
13.3.2Master Transmit Operation .....................................................
13.3.3Master Receive Operation .....................................................
13.3.4Slave Transmit Operation .....................................................
13.3.5Slave Receive Operation.....................................................
13.3.6IRIC Set Timing and SCL Control .................................................
13.3.7Noise Canceler..........................................................
13.3.8Sample Flowcharts........................................................
13.4 |
Application Notes .............................................................. |
311 |
Section 14 Host Interface .................................................... |
|
|
14.1 |
Overview................................................................. |
317 |
14.1.1Block Diagram..........................................................
14.1.2Input and Output Pins .....................................................
14.1.3Register Configuration.......................................................
14.2 Register Descriptions ............................................................. |
321 |
14.2.1System Control Register (SYSCR)..................................................
14.2.2Host Interface Control Register (HICR) ..............................................
14.2.3Input Data Register 1 (IDR1)...................................................
14.2.4Output Data Register 1 (ODR1) ..................................................
14.2.5Status Register 1 (STR1) .....................................................
14.2.6Input Data Register 2 (IDR2)...................................................
14.2.7Output Data Register 2 (ODR2) ..................................................
14.2.8Status Register 2 (STR2) .....................................................
14.2.9Serial/Timer Control Register (STCR) ...............................................
14.3 |
Operation................................................................... |
|
|
32 |
|
14.3.1 |
Host Interface Operation..................................................... |
|
|
|
14.3.2 |
Control States........................................................... |
8 |
|
|
14.3.3 |
A 20 |
Gate........................................................... |
|
14.4 |
Interrupts .................................................... |
|
|
..............3 |
|
14.4.1 |
IBF1, IBF2......................................................... |
2 |
|
|
14.4.2 |
HIRQ |
11 , HIRQ 1 , and HIRQ |
12 ............................................ |
14.5 |
Application Note.................................................... |
|
..........333 |
|
vii
Section 15 A/D Converter ....................................................
15.1 |
Overview |
.................................................... |
.......... ...335 |
|
15.1.1 |
Features .................................................... . ......... |
335 |
|
15.1.2 |
Block Diagram .......................................................... |
|
|
15.1.3 |
Input Pins ............................................................ |
337 |
|
15.1.4 ....................................................... |
Register Configuration |
|
15.2 |
Register Descriptions .............................................................. |
339 |
|
15.2.1A/D Data Registers A to D (ADDRA to ADDRD)
15.2.2A/D Control/Status Register (ADCSR) ................................................
15.2.3A/D Control Register (ADCR) ................................................................................................
15.3 |
CPU Interface |
................................................................342 |
15.4 |
Operation................................................................... |
344 |
15.4.1Single Mode (SCAN = 0) .....................................................
15.4.2Scan Mode (SCAN = 1)......................................................
15.4.3Input Sampling and A/D Conversion Time ..............................................
15.4.4External Trigger Input Timing..................................................
15.5 |
Interrupts .................................................................. |
35 |
15.6 |
Application Notes ............................................................... |
350 |
Section 16 D/A Converter .................................................... |
|
|
16.1 |
Overview.................................................................. |
355 |
|
16.1.1 Features .............................................................. |
355 |
16.1.2Block Diagram...........................................................
16.1.3Input and Output Pins ......................................................
16.1.4Register Configuration.........................................................
16.2 Register Descriptions .............................................................. |
358 |
16.2.1D/A Data Registers 0 and 1 (DADR0, DADR1)
16.2.2D/A Control Register (DACR) .................................................................................................
16.3 Operation |
...................................................................360 |
Section 17 RAM ............................................................
17.1 |
Overview |
.................................................................. |
361 |
|
17.1.1 ........................................................... |
Block Diagram |
|
|
17.1.2 ....................... |
RAM Enable Bit (RAME) in System Control Register (SYSCR) |
362 |
17.2 |
Operation................................................................... |
|
362 |
17.2.1Expanded Modes (Modes 1 and 2)
17.2.2Single-Chip Mode (Mode 3).....................................................................................................
Section 18 ROM (Mask ROM Version/ZTAT Version) |
............................ |
18.1 Overview.................................................................. |
363 |
18.1.1Block Diagram...........................................................
18.2Writer Mode (H8/3437, H8/3434) .........................................................
18.2.1Writer Mode Setup..........................................................
viii
18.2.2 Socket Adapter Pin Assignments and Memory Map |
.......................................... |
18.3 PROM Programming .............................................................. |
68 |
18.3.1Programming and Verification ...................................................
18.3.2Notes on Programming .......................................................
18.3.3Reliability of Programmed Data ..................................................
Section 19 ROM (32-kbyte Dual-Power-Supply Flash Memory Version) |
......... 375 |
|
19.1 Flash Memory Overview .......................................................... |
5 |
|
19.1.1 |
Flash Memory Operating Principle ................................................. |
|
19.1.2 Mode Programming and Flash Memory Address Space ...................................... |
376 |
|
19.1.3 |
Features............................................................ |
376 |
19.1.4Block Diagram.........................................................
19.1.5Input/Output Pins.......................................................
19.1.6Register Configuration......................................................
19.2Flash Memory Register Descriptions.......................................................
19.2.1Flash Memory Control Register (FLMCR) ...............................................
19.2.2Erase Block Register 1 (EBR1) ..............................................
19.2.3Erase Block Register 2 (EBR2) ..............................................
19.2.4Wait-State Control Register (WSCR)................................................
19.3On-Board Programming Modes........................................................
19.3.1Boot Mode ...........................................................
19.3.2User Programming Mode.....................................................
19.4Programming and Erasing Flash Memory ....................................................
19.4.1Program Mode ..........................................................
19.4.2Program-Verify Mode ......................................................
19.4.3Programming Flowchart and Sample Program............................................
19.4.4Erase Mode ..........................................................
19.4.5Erase-Verify Mode......................................................
19.4.6Erasing Flowchart and Sample Program .............................................
19.4.7Prewrite Verify Mode ....................................................
19.4.8Protect Modes .........................................................
19.4.9 Interrupt Handling during Flash Memory Programming and Erasing.................. |
413 |
19.5Flash Memory Emulation by RAM ......................................................
19.6Flash Memory Writer Mode (H8/3434F) ......................................................
19.6.1Writer Mode Setting .......................................................
19.6.2Socket Adapter and Memory Map.................................................
19.6.3Operation in Writer Mode.....................................................
19.7Flash Memory Programming and Erasing Precautions...............................................
Section 20 ROM (60-kbyte Dual-Power-Supply Flash Memory Version) |
......... 437 |
20.1 Flash Memory Overview ........................................................... |
7 |
20.1.1 Flash Memory Operating Principle ................................................. |
|
20.1.2 Mode Programming and Flash Memory Address Space ...................................... |
438 |
ix
20.1.3 Features .............................................................. |
438 |
20.1.4Block Diagram..........................................................
20.1.5Input/Output Pins........................................................
20.1.6Register Configuration........................................................
20.2Flash Memory Register Descriptions........................................................
20.2.1Flash Memory Control Register (FLMCR) ................................................
20.2.2Erase Block Register 1 (EBR1) ................................................
20.2.3Erase Block Register 2 (EBR2) ................................................
20.2.4Wait-State Control Register (WSCR)..................................................
20.3On-Board Programming Modes.........................................................
20.3.1Boot Mode ............................................................
20.3.2User Programming Mode.......................................................
20.4Programming and Erasing Flash Memory .....................................................
20.4.1Program Mode ...........................................................
20.4.2Program-Verify Mode .......................................................
20.4.3Programming Flowchart and Sample Program.............................................
20.4.4Erase Mode ...........................................................
20.4.5Erase-Verify Mode........................................................
20.4.6Erasing Flowchart and Sample Program ..............................................
20.4.7Prewrite Verify Mode ......................................................
20.4.8Protect Modes ...........................................................
20.4.9 Interrupt Handling during Flash Memory Programming and Erasing.................. |
475 |
20.5Flash Memory Emulation by RAM ........................................................
20.6Flash Memory Writer Mode (H8/3437F) .......................................................
20.6.1Writer Mode Setting ........................................................
20.6.2Socket Adapter and Memory Map...................................................
20.6.3Operation in Writer Mode ......................................................
20.7Flash Memory Programming and Erasing Precautions................................................
Section 21 ROM (60-kbyte Single-Power-Supply Flash Memory Version) |
...... 499 |
21.1 Flash Memory Overview ............................................................ |
9 |
21.1.1 Mode Pin Settings and ROM Space.................................................. |
|
21.1.2 Features .............................................................. |
500 |
21.1.3Block Diagram...........................................................
21.1.4Input/Output Pins.........................................................
21.1.5Register Configuration.......................................................
21.1.6Mode Control Register (MDCR) ....................................................
21.1.7Flash Memory Operating Modes ....................................................
21.2Flash Memory Register Descriptions........................................................
21.2.1Flash Memory Control Register 1 (FLMCR1) ...............................................
21.2.2Flash Memory Control Register 2 (FLMCR2) ..............................................
21.2.3Erase Block Register 2 (EBR2) ................................................
21.2.4Wait-State Control Register (WSCR)..................................................
x
21.3On-Board Programming Modes.........................................................
21.3.1Boot Mode ...........................................................
21.3.2User Programming Mode......................................................
21.4Programming/Erasing Flash Memory.......................................................
21.4.1Program Mode ..........................................................
21.4.2Program-Verify Mode ......................................................
21.4.3Erase Mode ...........................................................
21.4.4Erase-Verify Mode.......................................................
21.4.5Protect Modes .........................................................
21.4.6 Interrupt Handling during Flash Memory Programming and Erasing.................. |
527 |
21.5Flash Memory Writer Mode (H8/3437SF) .....................................................
21.5.1Writer Mode Setting .......................................................
21.5.2Socket Adapter and Memory Map..................................................
21.5.3Operation in Writer Mode ....................................................
21.6Flash Memory Programming and Erasing Precautions...............................................
Section 22 Power-Down State |
................................................ |
|
22.1 |
Overview................................................................. |
543 |
|
22.1.1 System Control Register (SYSCR)................................................. |
|
22.2 |
Sleep Mode ................................................................. |
546 |
22.2.1Transition to Sleep Mode
22.2.2Exit from Sleep Mode..........................................................................................................
22.3 Software Standby Mode |
...........................................................547 |
22.3.1Transition to Software Standby Mode
22.3.2Exit from Software Standby Mode .............................................................................................
22.3.3 Clock Settling Time for Exit from Software Standby Mode ................................ |
548 |
22.3.4Sample Application of Software Standby Mode
22.3.5Application Note...................................................................................................
22.4 Hardware Standby Mode |
..........................................................1 |
22.4.1Transition to Hardware Standby Mode..............................................
22.4.2Recovery from Hardware Standby Mode .............................................
22.4.3Timing Relationships.......................................................
Section 23 Electrical Specifications |
............................................ |
|
23.1 |
Absolute Maximum Ratings .......................................................... |
|
23.2 |
Electrical Characteristics.......................................................... |
554 |
23.2.1DC Characteristics ........................................................
23.2.2AC Characteristics ........................................................
23.2.3A/D Converter Characteristics...................................................
23.2.4D/A Converter Characteristics...................................................
23.2.5Flash Memory Characteristics (H8/3437SF Only) ...........................................
23.3 |
Absolute Maximum Ratings (H8/3437SF Low-Voltage Version) .................................... |
579 |
23.4 |
Electrical Characteristics (H8/3437SF Low-Voltage Version).......................................... |
|
xi
23.4.1DC Characteristics .........................................................
23.4.2AC Characteristics .........................................................
23.4.3A/D Converter Characteristics....................................................
23.4.4D/A Converter Characteristics....................................................
23.4.5Flash Memory Characteristics ....................................................
23.5 MCU Operational Timing |
............................................................5 |
23.5.1Bus Timing ...........................................................
23.5.2Control Signal Timing .......................................................
23.5.316-Bit Free-Running Timer Timing..................................................
23.5.48-Bit Timer Timing........................................................
23.5.5Pulse Width Modulation Timer Timing................................................
23.5.6Serial Communication Interface Timing ................................................
23.5.7I/O Port Timing.........................................................
23.5.8Host Interface Timing .......................................................
23.5.92IC Bus Timing (Option) .....................................................
23.5.10Reset Output Timing........................................................
23.5.11External Clock Output Timing...................................................
Appendix A CPU Instruction Set .............................................. |
|
|
A.1 |
Instruction Set List ........................................................ |
......605 |
A.2 |
Operation Code Map.............................................................. |
613 |
A.3 |
Number of States Required for Execution ................................................... |
|
Appendix B Internal I/O Register .............................................. |
|
|
B.1 |
Addresses ................................................................ |
621 |
B.2 |
Function .............................................................. |
.....626 |
Appendix C I/O Port Block Diagrams .......................................... |
|
|
C.1 |
Port 1 Block Diagram ............................................................. |
684 |
C.2 |
Port 2 Block Diagram ............................................................ |
685 |
C.3 |
Port 3 Block Diagram ............................................................. |
686 |
C.4 |
Port 4 Block Diagrams ............................................................ |
687 |
C.5 |
Port 5 Block Diagrams ............................................................ |
691 |
C.6 |
Port 6 Block Diagrams ............................................................ |
694 |
C.7 |
Port 7 Block Diagrams ............................................................ |
698 |
C.8 |
Port 8 Block Diagrams ............................................................ |
699 |
C.9 |
Port 9 Block Diagrams ........................................................... |
705 |
C.10 |
Port A Block Diagram............................................................. |
711 |
C.11 |
Port B Block Diagram..................................................... |
........712 |
Appendix D Port States in Each Processing State ................................ |
|
|
xii
Appendix E |
Timing of Transition to and Recovery |
|
from Hardware Standby Mode .................................... |
Appendix F |
Option Lists ................................................... |
Appendix G Product Code Lineup ............................................ |
|
Appendix H |
Package Dimensions ............................................ |
xiii
xiv
Section 1 Overview
1.1Overview
The H8/3437 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions.
The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-
manipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM,
RAM, four types of timers (a 16-bit free-running timer, 8-bit timers, PWM timers, and a watchdog
timer), a serial communication interface (SCI), an I 2C bus interface [option], a host interface (HIF), an A/D converter, a D/A converter, and I/O ports.
The H8/3437 Series can operate in single-chip mode or in two expanded modes, depending on the requirements of the application.
Besides the mask-ROM versions of the H8/3437 Series, there are ZTAT™ |
*1 versions with on-chip |
||||
PROM, and an F-ZTAT™ |
*2 version with on-chip flash memory. The F-ZTAT™ version can be |
||||
programmed or reprogrammed on-board in application systems. |
|
|
|||
Notes: *1 ZTAT™ (zero turn-around time) is a trademark of Hitachi, Ltd. |
|||||
*2 |
F-ZTAT™ (flexible-ZTAT) is a trademark of Hitachi, Ltd. |
||||
|
The guaranteed voltage range is different for the F-ZTAT LH version. |
||||
|
|
|
LH Version |
General Version |
|
|
|
|
|
|
|
|
V CC |
|
3.0 V to 5.5 V |
2.7 V to 5.5 V |
|
|
AV |
CC |
|
|
|
|
|
|
|
|
|
Table 1.1 lists the features of the H8/3437 Series.
1
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