Features
•Industry Standard Architecture
–Emulates Many 24-Pin PALs ®
–Low Cost Easy-to-Use Software Tools
•High-Speed Electrically Erasable Programmable Logic Devices
–7.5 ns Maximum Pin-to-Pin Delay
•Several Power Saving Options
Device |
ICC, Stand-By |
ICC, Active |
ATF20V8B |
50 mA |
55 mA |
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ATF20V8BQ |
35 mA |
40 mA |
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ATF20V8BQL |
5 mA |
20 mA |
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•CMOS and TTL Compatible Inputs and Outputs
•Input and I/O Pull-Up Resistors
•Advanced Flash Technology
–Reprogrammable
–100% Tested
•High Reliability CMOS Process
–20 Year Data Retention
–100 Erase/Write Cycles
–2,000V ESD Protection
–200 mA Latchup Immunity
•Commercial and Industrial Temperature Ranges
•Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
Pin Configurations
Pin Name |
Function |
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CLK |
Clock |
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I |
Logic Inputs |
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I/O |
Bidirectional Buffers |
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OE |
Output Enable |
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* |
No Internal Connection |
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VCC |
+5V Supply |
TSSOP Top View
CLK/IN |
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1 |
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24 |
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VCC |
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IN |
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2 |
23 |
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IN |
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IN |
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3 |
22 |
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I/O |
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IN |
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4 |
21 |
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I/O |
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IN |
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5 |
20 |
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I/O |
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IN |
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6 |
19 |
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I/O |
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IN |
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7 |
18 |
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I/O |
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IN |
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8 |
17 |
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I/O |
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IN |
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9 |
16 |
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I/O |
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IN |
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10 |
15 |
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I/O |
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IN |
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11 |
14 |
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IN |
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GND |
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12 |
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13 |
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OE/IN |
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DIP/SOIC |
PLCC Top View |
High- |
Performance |
EE PLD |
ATF20V8B |
Rev. 0407E–05/98 |
1 |
Description
The ATF20V8B is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 7.5 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges.
Several low power options allow selection of the best solution for various types of power-limited applications. Each of
these options significantly reduces total system power and enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 20R8 family and most 24-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
Absolute Maximum Ratings*
Temperature Under Bias................................ |
-55°C to +125°C |
Storage Temperature ..................................... |
-65°C to +150°C |
Voltage on Any Pin with |
-2.0V to +7.0V(1) |
Respect to Ground ......................................... |
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Voltage on Input Pins |
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with Respect to Ground |
-2.0V to +14.0V(1) |
During Programming..................................... |
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Programming Voltage with |
-2.0V to +14.0V(1) |
Respect to Ground ....................................... |
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
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Commercial |
Industrial |
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Operating Temperature (Case) |
0°C - 70°C |
-40°C - 85°C |
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VCC Power Supply |
5V ± 5% |
5V ± 10% |
2 |
ATF20V8B |
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ATF20V8B
DC Characteristics
Symbol |
Parameter |
Condition |
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Min |
Typ |
Max |
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Units |
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IIL |
Input or I/O Low |
0 ≤ VIN ≤ VIL(MAX) |
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-35 |
-100 |
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μA |
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Leakage Current |
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IIH |
Input or I/O High |
3.5 |
≤ VIN ≤ VCC |
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10 |
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μA |
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Leakage Current |
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B-7, -10 |
Com. |
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60 |
90 |
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mA |
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Ind. |
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60 |
100 |
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mA |
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VCC = MAX, |
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B-15, -25 |
Com. |
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60 |
80 |
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mA |
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Power Supply |
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ICC |
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Ind. |
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60 |
90 |
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mA |
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VIN = MAX, |
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Current, Standby |
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Outputs Open |
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BQ-10 |
Com. |
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35 |
55 |
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mA |
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BQL-15, -25 |
Com. |
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5 |
10 |
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mA |
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Ind. |
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5 |
15 |
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mA |
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B-7, -10 |
Com. |
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80 |
110 |
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mA |
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VCC = MAX, |
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Ind. |
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80 |
125 |
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mA |
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Clocked Power |
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Outputs Open, |
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Com. |
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60 |
90 |
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mA |
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Supply Current |
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B-15, -25 |
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ICC2 |
f = 15 MHz |
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Ind. |
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60 |
105 |
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mA |
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BQ-10 |
Com. |
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40 |
55 |
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mA |
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BQL-15, -25 |
Com. |
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20 |
35 |
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mA |
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Ind. |
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20 |
40 |
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mA |
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IOS(1) |
Output Short |
V |
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= 0.5V |
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-130 |
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mA |
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Circuit Current |
OUT |
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VIL |
Input Low Voltage |
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-0.5 |
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0.8 |
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V |
VIH |
Input High Voltage |
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2.0 |
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VCC + 0.75 |
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V |
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VIN = VIH or VIL, |
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IOL = 24 mA |
Com., |
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0.5 |
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V |
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VOL |
Output Low Voltage |
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Ind. |
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VCC |
= MIN |
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IOL = 16 mA |
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0.5 |
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V |
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VOH |
Output High Voltage |
VIN = VIH or VIL, |
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IOH = -4.0 mA |
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2.4 |
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V |
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VCC |
= MIN |
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Note: 1. |
Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. |
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3
AC Waveforms(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics(1)
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-7 |
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-10 |
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-15 |
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-25 |
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Symbol |
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Parameter |
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Min |
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Max |
Min |
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Max |
Min |
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Max |
Min |
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Max |
Units |
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tPD |
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Input or Feedback to |
8 outputs switching |
3 |
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7.5 |
3 |
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10 |
3 |
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15 |
3 |
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25 |
ns |
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Non-Registered Output |
1 output switching |
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7 |
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ns |
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tCF |
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Clock to Feedback |
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3 |
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6 |
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8 |
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10 |
ns |
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tCO |
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Clock to Output |
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2 |
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5 |
2 |
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7 |
2 |
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10 |
2 |
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12 |
ns |
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tS |
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Input or Feedback |
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5 |
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7.5 |
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12 |
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15 |
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ns |
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Setup Time |
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tH |
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Hold Time |
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0 |
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0 |
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0 |
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0 |
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ns |
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tP |
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Clock Period |
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8 |
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12 |
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16 |
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24 |
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ns |
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tW |
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Clock Width |
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4 |
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6 |
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8 |
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12 |
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ns |
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External Feedback 1/(tS + tCO) |
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100 |
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68 |
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45 |
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37 |
MHz |
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FMAX |
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Internal Feedback 1/(tS + tCF) |
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125 |
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74 |
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50 |
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40 |
MHz |
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No Feedback 1/(tP) |
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125 |
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83 |
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62 |
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41 |
MHz |
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tEA |
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Input to Output |
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3 |
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9 |
3 |
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10 |
3 |
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15 |
3 |
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20 |
ns |
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Enable — Product Term |
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tER |
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Input to Output |
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2 |
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9 |
2 |
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10 |
2 |
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15 |
2 |
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20 |
ns |
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Disable —Product Term |
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tPZX |
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pin to Output Enable |
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2 |
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6 |
2 |
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10 |
2 |
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15 |
2 |
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20 |
ns |
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OE |
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tPXZ |
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pin to Output Disable |
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1.5 |
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6 |
1.5 |
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10 |
1.5 |
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15 |
1.5 |
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20 |
ns |
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OE |
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Note: 1. |
See ordering information for valid part numbers and speed grades. |
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4 |
ATF20V8B |
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ATF20V8B
Input Test Waveforms and |
Output Test Loads |
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Measurement Levels |
Commercial |
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tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C (1)
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Typ |
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Max |
Units |
Conditions |
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CIN |
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5 |
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8 |
pF |
VIN = 0V |
COUT |
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6 |
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8 |
pF |
VOUT = 0V |
Note: |
1. Typical values for nominal supply voltage. |
This parameter is only sampled and is not 100% tested. |
Power Up Reset
The registers in the ATF20V8Bs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:
1.The VCC rise must be monotonic,
2.After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and
3.The clock must remain stable during tPR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.
Parameter |
Description |
Typ |
Max |
Units |
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tPR |
Power-Up Reset Time |
600 |
1,000 |
ns |
VRST |
Power-Up Reset Voltage |
3.8 |
4.5 |
V |
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, “CMOS PLD Programming Hardware and Software Support.”
5
Input and I/O Pull-Ups
All ATF20V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below).
Input Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.
The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF20V8B universal architecture can be programmed to emulate many 24-pin PAL devices. These architectural
I/O Diagram
subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF20V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the content of the ATF20V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the Security Fuse.
6 |
ATF20V8B |
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