Atmel ATmega16U4, ATmega32U4 User Manual

ATmega16U4/ATmega32U4

8-bit Microcontroller with 16/32K bytes of ISP Flash and USB Controller

DATASHEET

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

–135 Powerful Instructions – Most Single Clock Cycle Execution

–32 x 8 General Purpose Working Registers

–Fully Static Operation

–Up to 16 MIPS Throughput at 16MHz

–On-Chip 2-cycle Multiplier

•Non-volatile Program and Data Memories

–16/32KB of In-System Self-Programmable Flash

–1.25/2.5KB Internal SRAM

–512Bytes/1KB Internal EEPROM

–Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

–Data retention: 20 years at 85 C/ 100 years at 25 C(1)

–Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation

Parts using external XTAL clock are pre-programed with a default USB bootloader

–Programming Lock for Software Security

•JTAG (IEEE® std. 1149.1 compliant) Interface

–Boundary-scan Capabilities According to the JTAG Standard

–Extensive On-chip Debug Support

–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

–Complies fully with Universal Serial Bus Specification Rev 2.0

–Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s

–Endpoint 0 for Control Transfers: up to 64-bytes

–Six Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or Isochronous Transfers

–Configurable Endpoints size up to 256 bytes in double bank mode

–Fully independent 832 bytes USB DPRAM for endpoint memory allocation

–Suspend/Resume Interrupts

–CPU Reset possible on USB Bus Reset detection

–48MHz from PLL for Full-speed Bus Operation

–USB Bus Connection/Disconnection on Microcontroller Request

–Crystal-less operation for Low Speed mode

•Peripheral Features

–On-chip PLL for USB and High Speed Timer: 32 up to 96MHz operation

–One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

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–Two 16-bit Timer/Counter with Separate Prescaler, Compareand Capture Mode

–One 10-bit High-Speed Timer/Counter with PLL (64MHz) and Compare Mode

–Four 8-bit PWM Channels

–Four PWM Channels with Programmable Resolution from 2 to 16 Bits

–Six PWM Channels for High Speed Operation, with Programmable Resolution from 2 to 11 Bits

–Output Compare Modulator

–12-channels, 10-bit ADC (features Differential Channels with Programmable Gain)

–Programmable Serial USART with Hardware Flow Control

–Master/Slave SPI Serial Interface

–Byte Oriented 2-wire Serial Interface

–Programmable Watchdog Timer with Separate On-chip Oscillator

–On-chip Analog Comparator

–Interrupt and Wake-up on Pin Change

–On-chip Temperature Sensor

•Special Microcontroller Features

–Power-on Reset and Programmable Brown-out Detection

–Internal 8MHz Calibrated Oscillator

–Internal clock prescaler and On-the-fly Clock Switching (Int RC / Ext Osc)

–External and Internal Interrupt Sources

–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

•I/O and Packages

–All I/O combine CMOS outputs and LVTTL inputs

–26 Programmable I/O Lines

–44-lead TQFP Package, 10x10mm

–44-lead QFN Package, 7x7mm

•Operating Voltages

–2.7 - 5.5V

•Operating temperature

–Industrial (-40°C to +85°C)

•Maximum Frequency

–8MHz at 2.7V - Industrial range

–16MHz at 4.5V - Industrial range

Note: 1. See “Data Retention” on page 8 for details.

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1.Pin Configurations

Figure 1-1. Pinout

(INT.6/AIN0) PE6	1
UVcc	2
D-	3
D+	4
UGnd	5
UCap	6
VBus	7
(SS/PCINT0) PB0	8
(PCINT1/SCLK) PB1	9
(PDI/PCINT2/MOSI) PB2
	10
(PDO/PCINT3/MISO) PB3
	11

AVCC		GND		AREF		PF0(ADC0)		PF1(ADC1)		PF4(ADC4/TCK)		PF5(ADC5/TMS)		PF6(ADC6/TDO)		PF7(ADC7/TDI)		GND		VCC
44		43		42		41		40		39		38		37		36		35		34

INDEX CORNER

ATmega32U4

ATmega16U4

44-pin QFN/TQFP

	12		13		14		15		16		17		18		19		20		21		22
	(PCINT7/OC0A/OC1C/RTS)PB7		RESET		VCC		GND		XTAL2		XTAL1		(OC0B/SCL/INT0)PD0		(SDA/INT1)PD1		(RXD1/INT2)PD2		(TXD1/INT3)PD3		(XCK1/CTS)PD5

33 PE2 (HWB)

32 PC7 (ICP3/CLK0/OC4A)

31 PC6 OC3A/OC4A)(

30 PB6 (PCINT6/OC1B/OC4B/AD

29 PB5 (PCINT5/OC1A/OC4B/AD

28 PB4 (PCINT4/ADC11)

27 PD7 (T0/OC4D/ADC10)

26 PD6 (T1/OC4D/ADC9)

25 PD4 (ICP1/ADC8)

24 AVCC

23 GND

2.Overview

The ATmega16U4/ATmega32U4 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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2.1Block Diagram

Figure 2-1. Block Diagram

	PF7 - PF4	PF1 PF0			PC7 PC6	XTAL1	XTAL2	RESET
VCC	PORTF DRIVERS				PORTC DRIVERS
GND
	DATA REGISTER	DATA DIR.			DATA REGISTER	DATA DIR.
	PORTF	REG. PORTF			PORTC	REG. PORTC
				8-BIT DA TA BUS
			POR - BOD
			RESET	INTERNAL
					CALIB. OSC
				OSCILLATOR
				WATCHDOG	OSCILLATOR
	JTAG TAP	PROGRAM	STACK	TIMER
		COUNTER	POINTER
	ON-CHIP DEBUG	PROGRAM	SRAM	MCU CONTROL	TIMING AND
		FLASH		REGISTER	CONTROL
	BOUNDARY-			TIMERS/
		INSTRUCTION	GENERAL	COUNTERS
	SCAN
		REGISTER
			PURPOSE
			REGISTERS	INTERRUPT					UVcc
	PROGRAMMING		X	UNIT
		INSTRUCTION	Y
	LOGIC
		DECODER	Z				ON-CHIP
				EEPROM
							USB PAD 3V
							REGULATOR		UCap
	TEMPERATURE	CONTROL
	SENSOR		ALU						1uF
		LINES
AVCC				HIGH SPEED	PLL
AGND	ADC		STATUS	TIMER/PWM
									VBUS
AREF			REGISTER
									DP
	ANALOG				USB 2.0				DM
		USART1		SPI		TWO-WIRE SERIAL
	COMPARATOR					INTERFACE

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

PORTE

REG. PORTE

PORTB

REG. PORTB

PORTD

REG. PORTD

PORTE DRIVERS

PORTB DRIVERS

PORTD DRIVERS

PE6

PE2

PB7 - PB0

PD7 - PD0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The device provides the following features: 16/32K bytes of In-System Programmable Flash with Read-While- Write capabilities, 512Bytes/1K bytes EEPROM, 1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32 general purpose working registers, four flexible Timer/Counters with compare modes and PWM, one more high-speed Timer/Counter with compare modes and PLL adjustable source, one USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable

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power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using the Atmel® high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the device is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega16U4/ATmega32U4 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2Pin Descriptions

2.2.1VCC

Digital supply voltage.

2.2.2GND

Ground.

2.2.3Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the device as listed on page 74.

2.2.4Port C (PC7,PC6)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running.

Only bits 6 and 7 are present on the product pinout.

Port C also serves the functions of special features of the device as listed on page 77.

2.2.5Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.

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Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 78.

2.2.6Port E (PE6,PE2)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tristated when a reset condition becomes active, even if the clock is not running.

Only bits 2 and 6 are present on the product pinout.

Port E also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 81.

2.2.7Port F (PF7..PF4, PF1,PF0)

Port F serves as analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels are not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Bits 2 and 3 are not present on the product pinout.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

2.2.8D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D- connector pin with a serial 22 resistor.

2.2.9D+

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 resistor.

2.2.10UGND

USB Pads Ground.

2.2.11UVCC

USB Pads Internal Regulator Input supply voltage.

2.2.12UCAP

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

2.2.13VBUS

USB VBUS monitor input.

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2.2.14RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-2 on page 53. Shorter pulses are not guaranteed to generate a reset.

2.2.15XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.16XTAL2

Output from the inverting Oscillator amplifier.

2.2.17AVCC

AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used, it should be externally connected to VCC. If the ADC is used, it should be connected to VCC through a low-pass filter.

2.2.18AREF

This is the analog reference pin (input) for the A/D Converter.

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3.About

3.1Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max. values will be available after the device is characterized.

3.2Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

3.3Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.

These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

3.4Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1PPM over 20 years at 85°C or 100 years at 25°C.

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4.AVR CPU Core

4.1Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.2Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

			Data Bus 8-bit
Flash	Program		Status
	Counter		and Control
Program
Memory
			32 x 8	Interrupt
Instruction				Unit
			General
Register			Purpose	SPI
			Registrers
				Unit
Instruction				Watchdog
Decoder	AddressingDirect	AddressingIndirect		Timer
			ALU	Analog
Control Lines				Comparator
				I/O Module1
			Data	I/O Module 2
			SRAM
				I/O Module n
			EEPROM
			I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two

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operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing

– enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z- register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega16U4/ATmega32U4 has Extended I/O space from 0x60 - 0x0FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

4.3ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See “Instruction Set Summary” on page 418 for a detailed description.

4.4Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

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The AVR Status Register – SREG – is defined as:

Bit	7	6	5	4	3	2	1	0	SREG
	I	T	H	S	V	N	Z	C
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s arithmetic complements. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See “Instruction Set Summary” on page 418 for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See “Instruction Set Summary” on page 418 for detailed information.

4.5General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

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Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

	7	0	Addr.
			0x00
	R0
	R1		0x01
	R2		0x02
	…
	R13		0x0D
General	R14		0x0E
Purpose	R15		0x0F
Working	R16		0x10
Registers	R17		0x11
	…
	R26		0x1A	X-register Low Byte
	R27		0x1B	X-register High Byte
	R28		0x1C	Y-register Low Byte
	R29		0x1D	Y-register High Byte
	R30		0x1E	Z-register Low Byte
	R31		0x1F	Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

4.5.1The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.

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Figure 4-3.	The X-, Y-, and Z-registers
	15		XH		XL	0
X-register		7		0	7	0
		R27 (0x1B)			R26 (0x1A)

	15	YH		YL	0
Y-register	7		0	7	0
	R29 (0x1D)			R28 (0x1C)

	15	ZH	ZL	0
Z-register	7	0	7	0
	R31 (0x1F)		R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (See “Instruction Set Summary” on page 418 for detailed information).

4.6Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit	15	14	13	12	11	10	9	8
	SP15	SP14	SP13	SP12	SP11	SP10	SP9	SP8	SPH
	SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0	SPL
	7	6	5	4	3	2	1	0
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	1	0	0	0	0	0
	1	1	1	1	1	1	1	1

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4.6.1Extended Z-pointer Register for ELPM/SPM - RAMPZ

Bit	7	6	5	4	3	2	1	0	RAMPZ
Read/Write	RAMPZ7	RAMPZ6	RAMPZ5	RAMPZ4	RAMPZ3	RAMPZ2	RAMPZ1	RAMPZ0
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.

Figure 4-4. The Z-pointer used by ELPM and SPM

Bit (Individually)	7	0	7	0	7	0
Bit (Z-pointer)	RAMPZ		ZH		ZL
	23	16	15	8	7	0

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero.

4.7Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 4-5. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

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Figure 4-6. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

4.8Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 353 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 63. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 353.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

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When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in	r16, SREG	;
store SREG value		; disable interrupts during
cli
timed sequence
sbi	EECR, EEMPE	;
start EEPROM write
sbi	EECR, EEPE
out	SREG, r16	;
restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;		/*
store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei	;	set Global Interrupt	Enable
sleep	;	enter sleep, waiting	for interrupt

;note: will enter sleep before any pending

;interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.8.1Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

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A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

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5.AVR Memories

This section describes the different memories in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

Table 5-1.	Memory Mapping
Memory			Mnemonic		ATmega32U4	ATmega16U4
		Size	Flash size		32KB	16KB
		Start Address	-
Flash			0x0000
		End Address	Flash end		0x7FFF(1)	0x3FFF(1)
					0x3FFF(2)	0x1FFF(2)
		Size	-		32 bytes	32 bytes
32 Registers		Start Address	-		0x0000	0x0000
		End Address	-		0x001F	0x001F
		Size	-		64 bytes	64 bytes
I/O Registers		Start Address	-		0x0020	0x0020
		End Address	-		0x005F	0x005F
		Size	-		160 bytes	160 bytes
Ext I/O Registers		Start Address	-		0x0060	0x0060
		End Address	-		0x00FF	0x00FF
		Size	ISRAM size		2.5KB	1.25KB
Internal SRAM		Start Address	ISRAM start		0x100	0x100
		End Address	ISRAM end		0x0AFF	0x05FF
External Memory				Not Present.
EEPROM		Size	E2 size		1KB	512 bytes
		End Address	E2 end		0x03FF	0x01FF

Notes: 1. Byte address.

2.Word (16-bit) address.

5.1In-System Reprogrammable Flash Program Memory

The device contains 16/32K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The device Program Counter (PC) is 16 bits wide, thus addressing the 32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Memory Programming” on

page 353. “Memory Programming” on page 353 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface.

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Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description and ELPM - Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 14.

Figure 5-1. Program Memory Map

Program Memory

0x00000

Application Flash Section

Boot Flash Section

0x7FFF (32KBytes)

5.2SRAM Data Memory

Figure 5-2 on page 20 shows how the device SRAM Memory is organized.

The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 2,816 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory and the next 2,560 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z- register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 1.25/2.5Kbytes of internal data SRAM in the device are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 11.

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Figure 5-2. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

160 E xt I/O Reg.

Internal S RAM

$0000 - $001F $0020 - $005F $0060 - $00FF ISRAM start : $0100

ISRAM end : $05FF / $0AFF

$FFFF

5.2.1Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

T1 T2 T3

clkCPU

Address Compute Address Address valid

Data

WR

Data

RD

Read Write

Memory Access Instruction

Next Instruction

5.3EEPROM Data Memory

The device contains 512Bytes/1K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 367, page 371, and page 356 respectively.

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5.3.1EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 5-3 on page 23. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the

EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2The EEPROM Address Register – EEARH and EEARL

Bit	15	14	13	12	11	10	9	8	EEARH
	–	–	–	–	EEAR11	EEAR10	EEAR9	EEAR8
	EEAR7	EEAR6	EEAR5	EEAR4	EEAR3	EEAR2	EEAR1	EEAR0	EEARL
	7	6	5	4	3	2	1	0
Read/Write	R	R	R	R	R/W	R/W	R/W	R/W
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	X	X	X	X
	X	X	X	X	X	X	X	X

• Bits 15..12 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bits 11..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512Bytes/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and E2_END. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

5.3.3The EEPROM Data Register – EEDR

Bit	7	6	5	4	3	2	1	0	EEDR
	MSB							LSB
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.4The EEPROM Control Register – EECR

Bit	7	6	5	4	3	2	1	0	EECR
Read/Write	–	–	EEPM1	EEPM0	EERIE	EEMPE	EEPE	EERE
	R	R	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	X	X	0	0	X	0

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• Bits 7..6 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in the table below. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 5-2.	EEPROM Mode Bits
EEPM1	EEPM0	Programming Time	Operation
0	0	3.4ms	Erase and Write in one operation (Atomic Operation)
0	1	1.8ms	Erase Only
1	0	1.8ms	Write Only
1	1	–	Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1.Wait until EEPE becomes zero.

2.Wait until SELFPRGEN in SPMCSR becomes zero.

3.Write new EEPROM address to EEAR (optional).

4.Write new EEPROM data to EEDR (optional).

5.Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6.Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Memory Programming” on page 353 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the

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EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. The following table lists the typical programming time for EEPROM access from the CPU.

Table 5-3.	EEPROM Programming Time
Symbol		Number of Calibrated RC Oscillator Cycles	Typ Programming Time
EEPROM write		26,368	3.3ms
(from CPU)

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

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Assembly Code Example(1)

EEPROM_write:

; Wait for completion of previous write

sbic	EECR,EEPE
rjmp	EEPROM_write

; Set up address (r18:r17) in address register

out	EEARH,	r18
out	EEARL,	r17

; Write data (r16) to Data Register

out	EEDR,r16
; Write logical one to EEMPE
sbi	EECR,EEMPE

; Start eeprom write by setting EEPE

sbi	EECR,EEPE
ret

C Code Example(1)

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */ EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

Note: 1. See “Code Examples” on page 8.

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

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Assembly Code Example(1)

EEPROM_read:

; Wait for completion of previous write

sbic	EECR,EEPE
rjmp	EEPROM_read

; Set up address (r18:r17) in address register

out	EEARH,	r18
out	EEARL,	r17

;	Start eeprom read by writing EERE
sbi		EECR,EERE
;	Read data from Data Register
in		r16,EEDR
ret

C Code Example(1)

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

;

/* Set up address register */ EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */ return EEDR;

}

Note: 1. See “Code Examples” on page 8.

5.3.5Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the

needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

5.4I/O Memory

The I/O space definition of the device is shown in “Register Summary” on page 414.

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All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1General Purpose I/O Registers

The device contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.4.2General Purpose I/O Register 2 – GPIOR2

Bit	7	6	5	4	3	2	1	0
	MSB							LSB	GPIOR2
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

5.4.3General Purpose I/O Register 1 – GPIOR1

Bit	7	6	5	4	3	2	1	0
	MSB							LSB	GPIOR1
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

5.4.4General Purpose I/O Register 0 – GPIOR0

Bit	7	6	5	4	3	2	1	0	GPIOR0
	MSB							LSB
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

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6.System Clock and Clock Options

6.1Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 43. The clock systems are detailed below.

Figure 6-1.

Clock Distribution

USB

High Speed

General I/O

ADC

CPU Core

RAM

Flash and

Timer

Modules

EEPROM

USB (48MHz)

TMR

clkADC

clk

clk

(1)

(2)

clkI/O

AVR Clock

clkCPU

Control Unit

PLL Postcaler

clkFLASH

clkPLL

Reset Logic

Watchdog Timer

PLL

Source clock

System Clock

Watchdog

PLL Input

Prescaler

clock

Multiplexer

clkPllPresc

PLL Clock

Prescaler

Clock

Multiplexer

Clock Switch

Crystal	External Clock		Watchdog		Calibrated RC
Oscillator			Oscillator		Oscillator

6.1.1CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also, TWI address recognition is handled in all sleep modes.

6.1.3Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

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6.1.4ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

6.1.5PLL Prescaler Clock – clkPllPresc

The PLL requires a 8MHz input. A prescaler allows user to use either a 8MHz or a 16MHz source (from a crystal or an external source), using a divider (by 2) if necessary. The output of the prescaler goes into the PLL Input multiplexer, that allows the user to select either the prescaler output of the System Clock Multiplexer, or the Internal 8MHz Calibrated Oscillator.

6.1.6PLL Output Clock – clkPll

When enabled, the PLL outputs one frequency among numerous choices between 32MHz and 96MHz. The output frequency is determined by the PLL clock register. The frequency is independent of the power supply voltage. The PLL Output is connected to a postscaler that allows user to generate two different frequencies (clkUSB and clkTMR) from the common PLL signal, each on them resulting of a selected division ratio (/1, /1.5, /2).

6.1.7High-Speed Timer Clock– clkTMR

When enabled, the PLL outputs one frequency among numerous choices between 32MHz and 96MHz, that goes into the PLL Postcaler. The High Speed Timer frequency input is generated from the PLL Postcaler, that proposes /1, /1.5 and /2 ratios. That can be determined from the PLL clock register. The High Speed Timer maximum frequency input depends on the power supply voltage and reaches its maximum of 64MHz at 5V.

6.1.8USB Clock – clkUSB

The USB hardware module needs for a 48MHz clock. This clock is generated from the on-chip PLL. The output of the PLL passes through the PLL Postcaler where the frequency can be either divided by 2 or directly connected to the clkUSB signal.

6.2Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 6-1.	Device Clocking Options Select(1)
Device Clocking Option			CKSEL[3:0] (or EXCKSEL[3:0])
Low Power Crystal Oscillator			1111 - 1000
Reserved			0111 - 0110
Low Frequency Crystal Oscillator			0101 - 0100
Reserved			0011
Calibrated Internal RC Oscillator			0010
External Clock			0000
Reserved			0001
Note: 1.	For all fuses “1” means unprogrammed while “0” means programmed.

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6.2.1 Default Clock Source ATmega16U4 and ATmega32U4

The device is shipped with Low Power Crystal Oscillator (8.0 - 16MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock with an 8MHz crystal. See Table 28-5 on page 355 for an overview of the default Clock Selection Fuse setting.

6.2.2 Default Clock Source ATmega16U4RC and ATmega32U4RC

The device is shipped with Calibrated Internal RC oscillator (8.0MHz) enabled and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. See Table 28-5 on page 355 for an overview of the default Clock Selection Fuse setting.

6.2.3 Clock Startup Sequence

Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable.

To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by all other reset sources. “On-chip Debug System” on page 46 describes the start conditions for the internal reset. The delay (tTOUT) is timed from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in the following table. The frequency of the Watchdog Oscillator is voltage dependent as shown in this table.

Table 6-2.	Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 5.0V)		Typ Time-out (VCC = 3.0V)	Number of Cycles
	0ms	0ms	0
	4.1ms	4.3ms	512
	65ms	69ms	8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The delay will not monitor the actual voltage and it will be required to select a delay longer than the VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from six cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, VCC is assumed to be at a sufficient level and only the start-up time is included.

6.3Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs.

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C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in the below table. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 6-2. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL[3..1] as shown in this table.

Table 6-3.	Low Power Crystal Oscillator Operating Modes
Frequency Range(1) [MHz]		CKSEL3..1	Recommended Range for Capacitors C1 and C2 [pF]
	0.4 - 0.9	100(2)	–
	0.9 - 3.0	101	12 - 22
	3.0 - 8.0	110	12 - 22
	8.0 - 16.0	111	12 - 22

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

2.If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in this table.

	Table 6-4.	Start-up Times for the Low Power Crystal Oscillator Clock Selection
			Start-up Time from	Additional Delay from
	Oscillator Source /		Power-down and	Reset
	Power Conditions		Power-save	(VCC = 5.0V)	CKSEL0	SUT1..0
	Ceramic resonator,		258CK	14CK + 4.1ms(1)	0	00
	fast rising power
	Ceramic resonator,		258CK	14CK + 65ms(1)	0	01
	slowly rising power
	Ceramic resonator,		1K CK	14CK(2)	0	10
	BOD enabled
	Ceramic resonator,		1K CK	14CK + 4.1ms(2)	0	11
	fast rising power
	Ceramic resonator,		1K CK	14CK + 65ms(2)	1	00
	slowly rising power

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