ATMEL ATmega8535, ATmega8535L User Manual

BDTIC www.bdtic.com/ATMEL

Features

•High-performance, Low-power AVR® 8-bit Microcontroller

•Advanced RISC Architecture

–130 Powerful Instructions – Most Single Clock Cycle Execution

–32 x 8 General Purpose Working Registers

–Fully Static Operation

–Up to 16 MIPS Throughput at 16 MHz

–On-chip 2-cycle Multiplier

•Nonvolatile Program and Data Memories

–8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

–Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation

–512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

–512 Bytes Internal SRAM

–Programming Lock for Software Security

•Peripheral Features

–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

–Real Time Counter with Separate Oscillator

–Four PWM Channels

–8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels for TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP Package Only

–Byte-oriented Two-wire Serial Interface

–Programmable Serial USART

–Master/Slave SPI Serial Interface

–Programmable Watchdog Timer with Separate On-chip Oscillator

–On-chip Analog Comparator

•Special Microcontroller Features

–Power-on Reset and Programmable Brown-out Detection

–Internal Calibrated RC Oscillator

–External and Internal Interrupt Sources

–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby

•I/O and Packages

–32 Programmable I/O Lines

–40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF

•Operating Voltages

–2.7 - 5.5V for ATmega8535L

–4.5 - 5.5V for ATmega8535

•Speed Grades

–0 - 8 MHz for ATmega8535L

–0 - 16 MHz for ATmega8535

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

ATmega8535

ATmega8535L

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Pin Configurations
	Figure 1. Pinout ATmega8535
			(XCK/T0) PB0							PA0 (ADC0)
				(T1) PB1						PA1 (ADC1)
		(INT2/AIN0) PB2								PA2 (ADC2)
		(OC0/AIN1) PB3								PA3 (ADC3)
				(SS) PB4						PA4 (ADC4)
				(MOSI) PB5						PA5 (ADC5)
				(MISO) PB6						PA6 (ADC6)
				(SCK) PB7						PA7 (ADC7)
				RESET						AREF
				VCC						GND
				GND						AVCC
				XTAL2						PC7 (TOSC2)
				XTAL1						PC6 (TOSC1)
				(RXD) PD0						PC5
				(TXD) PD1						PC4
				(INT0) PD2						PC3
				(INT1) PD3						PC2
				(OC1B) PD4						PC1 (SDA)
				(OC1A) PD5						PC0 (SCL)
				(ICP1) PD6						PD7 (OC2)

(MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3 RESET 4 VCC 5 GND 6 XTAL2 7 XTAL1 8

(RXD) PD0 9 (TXD) PD1 10 (INT0) PD2 11

																	PLCC
44 PB4 (SS)	43 PB3 (AIN1/OC0)	42 PB2 (AIN0/INT2)	41 PB1 (T1)	40 PB0 (XCK/T0)	39 GND	38 VCC	37 PA0 (ADC0)	36 PA1 (ADC1)	35 PA2 (ADC2)	34 PA3 (ADC3)			PB4 (SS)	PB3 (AIN1/OC0)	PB2 (AIN0/INT2)	PB1 (T1)	PB0 (XCK/T0)	GND	VCC	PA0 (ADC0)	PA1 (ADC1)	PA2 (ADC2)	PA3 (ADC3)
										33	PA4 (ADC4)	(MOSI) PB5	6	5	4	3	2	1	44	43	42	41	40	PA4 (ADC4)
													7										39
										32	PA5 (ADC5)	(MISO) PB6	8										38	PA5 (ADC5)
										31	PA6 (ADC6)	(SCK) PB7	9										37	PA6 (ADC6)
										30	PA7 (ADC7)	RESET	10										36	PA7 (ADC7)
										29	AREF	VCC	11										35	AREF
										28	GND	GND	12										34	GND
										27	AVCC	XTAL2	13										33	AVCC
										26	PC7 (TOSC2)	XTAL1	14										32	PC7 (TOSC2)
										25	PC6 (TOSC1)	(RXD) PD0	15										31	PC6 (TOSC1)
										24	PC5	(TXD) PD1	16										30	PC5
										23	PC4	(INT0) PD2	17	19	20	21	22	23	24	25	26	27	29	PC4
12	13	14	15	16	17	18	19	20	21	22			18										28
													(INT1) PD3	(OC1B) PD4	(OC1A) PD5	(ICP1) PD6	(OC2) PD7	VCC	GND	(SCL) PC0	(SDA) PC1	PC2	PC3
(INT1) PD3	(OC1B) PD4	(OC1A) PD5	(ICP1) PD6	(OC2) PD7	VCC	GND	(SCL) PC0	(SDA) PC1	PC2	PC3

NOTE: MLF Bottom pad should be soldered to ground.

Disclaimer	Typical values contained in this data sheet are based on simulations and characteriza-
	tion of other AVR microcontrollers manufactured on the same process technology. Min
	and Max values will be available after the device is characterized.

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ATmega8535(L)

Overview

Block Diagram

The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Figure 2.	Block Diagram
	PA0 - PA7			PC0 - PC7
VCC
	PORTA DRIVERS/BUFFERS		PORTC DRIVERS/BUFFERS
GND	PORTA DIGITAL INTERFACE		PORTC DIGITAL INTERFACE
AVCC
	MUX &	ADC	TWI
		INTERFACE
	ADC
AREF
	PROGRAM	STACK	TIMERS/	OSCILLATOR
			COUNTERS
	COUNTER	POINTER
	PROGRAM	SRAM	INTERNAL
	FLASH		OSCILLATOR
					XTAL1
	INSTRUCTION	GENERAL	WATCHDOG	OSCILLATOR
	REGISTER		TIMER
		PURPOSE
		REGISTERS
		X			XTAL2
	INSTRUCTION	Y	MCU CTRL.		RESET
	DECODER		& TIMING
		Z

	CONTROL		INTERRUPT	INTERNAL
				CALIBRATED
	LINES	ALU	UNIT
				OSCILLATOR
	AVR CPU	STATUS	EEPROM
		REGISTER
	PROGRAMMING	SPI	USART
	LOGIC
	+	COMP.
	-	INTERFACE

PORTB DIGITAL INTERFACE		PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS		PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

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The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8535 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain in TQFP package, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega8535 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, InCircuit Emulators, and evaluation kits.

AT90S8535 Compatibility The ATmega8535 provides all the features of the AT90S8535. In addition, several new features are added. The ATmega8535 is backward compatible with AT90S8535 in most cases. However, some incompatibilities between the two microcontrollers exist. To solve this problem, an AT90S8535 compatibility mode can be selected by programming the S8535C fuse. ATmega8535 is pin compatible with AT90S8535, and can replace the AT90S8535 on current Printed Circuit Boards. However, the location of fuse bits and the electrical characteristics differs between the two devices.

AT90S8535 Compatibility

Mode

Programming the S8535C fuse will change the following functionality:

•The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for details.

•The double buffering of the USART Receive Register is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 146 for details.

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ATmega8535(L)

Pin Descriptions

VCC		Digital supply voltage.
GND		Ground.
Port A (PA7..PA0)		Port A serves as the analog inputs to the A/D Converter.
		Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
		Port pins can provide internal pull-up resistors (selected for each bit). The Port A output
		buffers have symmetrical drive characteristics with both high sink and source capability.
		When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source
		current if the internal pull-up resistors are activated. The Port A pins are tri-stated when
		a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)		Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
		bit). The Port B output buffers have symmetrical drive characteristics with both high sink
		and source capability. As inputs, Port B pins that are externally pulled low will source
		current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
		condition becomes active, even if the clock is not running.
		Port B also serves the functions of various special features of the ATmega8535 as listed
		on page 60.
Port C (PC7..PC0)		Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
		bit). The Port C output buffers have symmetrical drive characteristics with both high sink
		and source capability. As inputs, Port C pins that are externally pulled low will source
		current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
		condition becomes active, even if the clock is not running.
Port D (PD7..PD0)		Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
		bit). The Port D output buffers have symmetrical drive characteristics with both high sink
		and source capability. As inputs, Port D pins that are externally pulled low will source
		current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
		condition becomes active, even if the clock is not running.
		Port D also serves the functions of various special features of the ATmega8535 as listed
		on page 64.
		Reset input. A low level on this pin for longer than the minimum pulse length will gener-
RESET
		ate a reset, even if the clock is not running. The minimum pulse length is given in Table
		15 on page 37. Shorter pulses are not guaranteed to generate a reset.
XTAL1		Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2		Output from the inverting Oscillator amplifier.
AVCC		AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally
		connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
		nected to VCC through a low-pass filter.
AREF		AREF is the analog reference pin for the A/D Converter.

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Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

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About Code

Examples

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ATmega8535(L)

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.

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AVR CPU Core

Introduction

Architectural Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 3. Block Diagram of the AVR MCU Architecture

			8-bit Data Bus
Flash	Program		Status
	Counter		and Control
Program
Memory
			32 x 8	Interrupt
Instruction				Unit
			General
Register			Purpose	SPI
			Registrers
				Unit
Instruction				Watchdog
Decoder	AddressingDirect	AddressingIndirect		Timer
			ALU	Analog
Control Lines				Comparator
				I/O Module1
			Data	I/O Module 2
			SRAM
				I/O Module n
			EEPROM
			I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is InSystem Re-Programmable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

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ATmega8535(L)

ALU – Arithmetic Logic

Unit

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-registers, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

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Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will, in many cases, remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit	7	6	5	4	3	2	1	0
	I	T	H	S	V	N	Z	C	SREG
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I- bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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General Purpose

Register File

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ATmega8535(L)

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

•One 8-bit output operand and one 8-bit result input

•Two 8-bit output operands and one 8-bit result input

•Two 8-bit output operands and one 16-bit result input

•One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

7			0	Addr.
			R0	0x00
			R1	0x01
			R2	0x02
			…
			R13	0x0D
General			R14	0x0E
Purpose			R15	0x0F
Working			R16	0x10
Registers			R17	0x11
			…
			R26	0x1A	X-register Low Byte
			R27	0x1B	X-register High Byte
			R28	0x1C	Y-register Low Byte
			R29	0x1D	Y-register High Byte
			R30	0x1E	Z-register Low Byte
			R31	0x1F	Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

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The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are 16-bit address pointers for indirect addressing of the Data Space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

Stack Pointer

	15	XH		XL	0
X-register	7	0	7		0
		R27 (0x1B)		R26 (0x1A)
	15	YH		YL	0
Y-register	7	0	7		0
		R29 (0x1D)		R28 (0x1C)
	15	ZH		ZL	0
Z-register	7	0	7	0
		R31 (0x1F)		R30 (0x1E)

In the different addressing modes, these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit	15	14	13	12	11	10	9	8
	-	-	-	-	-	-	SP9	SP8	SPH
	SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0	SPL
	7	6	5	4	3	2	1	0
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0
	0	0	0	0	0	0	0	0

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Instruction Execution

Timing

ATmega8535(L)

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

Reset and Interrupt

Handling

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The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 237 for details.

The lowest addresses in the program memory space are, by default, defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 46. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level is. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 46 for more information. The Reset Vector can

13

also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 224.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in	r16, SREG	; store SREG value
cli		; disable interrupts during timed sequence
sbi	EECR, EEMWE	; start EEPROM write
sbi	EECR, EEWE
out SREG, r16		; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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ATmega8535(L)

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt

;note: will enter sleep before any pending

;interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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AVR ATmega8535

Memories

In-System

Reprogrammable Flash

Program Memory

This section describes the different memories in the ATmega8535. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8535 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

The ATmega8535 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8535 Program Counter (PC) is 12 bits wide, thus addressing the 4K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read- While-Write Self-Programming” on page 224. “Memory Programming” on page 237 contains a detailed description on Flash Programming in SPI or Parallel Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 13.

Figure 8. Program Memory Map

$000

Application Flash Section

Boot Flash Section

$FFF

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ATmega8535(L)

SRAM Data Memory

Figure 9 shows how the ATmega8535 SRAM Memory is organized.

The 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 512 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of internal data SRAM in the ATmega8535 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 11.

Figure 9. Data Memory Map

Register File

R0

R1

R2

...

R29

R30

R31

I/O Registers

$00

$01

$02

...

$3D

$3E

$3F

Data Address Space

$0000

$0001

$0002

...

$001D

$001E

$001F

$0020

$0021

$0022

...

$005D

$005E

$005F

Internal SRAM

$0060

$0061

...

$025E

$025F

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Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

T1

T2

T3

clkCPU

Address

Compute Address

Address valid

Data

WR

Data

RD

Read Write

Memory Access Instruction

Next Instruction

EEPROM Data Memory The ATmega8535 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 237 contains a detailed description on EEPROM Programming in SPI or Parallel Programming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device, for some period of time, to run at a voltage lower than specified as minimum for the clock frequency used, see “Preventing EEPROM Corruption” on page 22 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

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ATmega8535(L)

The EEPROM Address

Register – EEARH and EEARL

Bit	15	14	13	12	11	10	9	8
	–	–	–	–	–	–	–	EEAR8	EEARH
	EEAR7	EEAR6	EEAR5	EEAR4	EEAR3	EEAR2	EEAR1	EEAR0	EEARL
	7	6	5	4	3	2	1	0
Read/Write	R	R	R	R	R	R	R	R/W
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	X
	X	X	X	X	X	X	X	X

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega8535 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

The EEPROM Data Register –

EEDR

Bit	7	6	5	4	3	2	1	0
	MSB							LSB	EEDR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bits 7..0 – EEDR7..0: EEPROM Data

The EEPROM Control Register

– EECR

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit	7	6	5	4	3	2	1	0
	–	–	–	–	EERIE	EEMWE	EEWE	EERE	EECR
Read/Write	R	R	R	R	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	X	0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega8535 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the

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value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1.Wait until EEWE becomes zero.

2.Wait until SPMEN in SPMCR becomes zero.

3.Write new EEPROM address to EEAR (optional).

4.Write new EEPROM data to EEDR (optional).

5.Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6.Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 224 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

	Number of Calibrated	Typ
Symbol	RC Oscillator Cycles(1)	Programming Time
EEPROM Write (from CPU)	8448	8.4 ms

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

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ATmega8535(L)

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register out EEDR,r16

; Write logical one to EEMWE sbi EECR,EEMWE

; Start eeprom write by setting EEWE sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up Address and Data Registers */ EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in Address Register out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE sbi EECR,EERE

; Read data from Data Register in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up Address Register */ EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */ return EEDR;

}

EEPROM Write During Power- When entering Power-down sleep mode while an EEPROM write operation is active, the

down Sleep Mode	EEPROM write operation will continue, and will complete before the write access time
	has passed. However, when the write operation is completed, the Oscillator continues
	running, and as a consequence, the device does not enter Power-down entirely. It is
	therefore recommended to verify that the EEPROM write operation is completed before
	entering Power-down.
Preventing EEPROM	During periods of low VCC, the EEPROM data can be corrupted because the supply volt-
Corruption	age is too low for the CPU and the EEPROM to operate properly. These issues are the
	same as for board level systems using EEPROM and the same design solutions should
	be applied.
	An EEPROM data corruption can be caused by two situations when the voltage is too
	low. First, a regular write sequence to the EEPROM requires a minimum voltage to
	operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
	supply voltage is too low.

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ATmega8535(L)

EEPROM data corruption can easily be avoided by following this design recommendation:

I/O Memory

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

The I/O space definition of the ATmega8535 is shown in page 299.

All ATmega8535 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

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System Clock and

Clock Options

Clock Systems and their Distribution

Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed below.

Figure 11. Clock Distribution

Asynchronous		General I/O
Timer/Counter		Modules

clkI/O

clkASY

Timer/Counter			External RC
Oscillator			Oscillator

	ADC	CPU Core	RAM	Flash and
				EEPROM
	clkADC
	AVR Clock	clkCPU
	Control Unit
		clkFLASH
		Reset Logic	Watchdog Timer
	Source clock		Watchdog clock
	Clock		Watchdog
	Multiplexer		Oscillator
	External Clock	Crystal	Low-frequency	Calibrated RC
		Oscillator	Crystal Oscillator	Oscillator

CPU Clock – clkCPU	The CPU clock is routed to parts of the system concerned with operation of the AVR
	core. Examples of such modules are the General Purpose Register File, the Status Reg-
	ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
	core from performing general operations and calculations.
I/O Clock – clkI/O	The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
	USART. The I/O clock is also used by the External Interrupt module, but note that some
	external interrupts are detected by asynchronous logic, allowing such interrupts to be
	detected even if the I/O clock is halted. Also note that address recognition in the TWI
	module is carried out asynchronously when clkI/O is halted, enabling TWI address recep-
	tion in all sleep modes.
Flash Clock – clkFLASH	The Flash clock controls operation of the Flash interface. The Flash clock is usually
	active simultaneously with the CPU clock.

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ATmega8535(L)

Asynchronous Timer Clock – The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked

clkASY	directly from an external 32 kHz clock crystal. The dedicated clock domain allows using
	this Timer/Counter as a real-time counter even when the device is in sleep mode.
ADC Clock – clkADC	The ADC is provided with a dedicated clock domain. This allows halting the CPU and
	I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-
	rate ADC conversion results.

Clock Sources

Default Clock Source

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 2. Device Clocking Options Select(1)

Device Clocking Option	CKSEL3..0
External Crystal/Ceramic Resonator	1111 - 1010
External Low-frequency Crystal	1001
External RC Oscillator	1000 - 0101
Calibrated Internal RC Oscillator	0100 - 0001
External Clock	0000

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from Reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega8535 Typical Characteristics” on page 266.

Table 3. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V)	Typ Time-out (VCC = 3.0V)	Number of Cycles
4.1 ms	4.3 ms	4K	(4,096)
65 ms	69 ms	64K	(65,536)

The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an InSystem or Parallel Programmer.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces power consumption considerably.

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This mode has a limited frequency range and it can not be used to drive other clock buffers.

For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 4. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 12. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4.

Table 4. Crystal Oscillator Operating Modes

		Frequency Range	Recommended Range for Capacitors
CKOPT	CKSEL3..1	(MHz)	C1 and C2 for Use with Crystals (pF)
1	101(2)	0.4 - 0.9	–
1	110	0.9 - 3.0	12 - 22
1	111	3.0 - 8.0	12 - 22
0	101, 110, 111	1.0 - 16.0	12 - 22

2. This option should not be used with crystals, only with ceramic resonators.

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ATmega8535(L)

The CKSEL0 fuse together with the SUT1..0 Fuses select the start-up times as shown in

Table 5.

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

		Start-up Time from	Additional Delay
		Power-down and	from Reset
CKSEL0	SUT1..0	Power-save	(VCC = 5.0V)	Recommended Usage
0	00	258 CK(1)	4.1 ms	Ceramic resonator, fast
				rising power
0	01	258 CK(1)	65 ms	Ceramic resonator,
				slowly rising power
0	10	1K CK(2)	–	Ceramic resonator, BOD
				enabled
0	11	1K CK(2)	4.1 ms	Ceramic resonator, fast
				rising power
1	00	1K CK(2)	65 ms	Ceramic resonator,
				slowly rising power
1	01	16K CK	–	Crystal Oscillator, BOD
				enabled
1	10	16K CK	4.1 ms	Crystal Oscillator, fast
				rising power
1	11	16K CK	65 ms	Crystal Oscillator, slowly
				rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2.These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

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Low-frequency Crystal

Oscillator

External RC Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF.

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 6.

Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

	Start-up Time from	Additional Delay
	Power-down and	from Reset
SUT1..0	Power-save	(VCC = 5.0V)		Recommended Usage
00	1K CK(1)	4.1 ms		Fast rising power or BOD enabled
01	1K CK(1)	65 ms		Slowly rising power
10	32K CK	65 ms		Stable frequency at start-up
11		Reserved

Note: 1. These options should only be used if frequency stability at start-up is not important for the application.

For timing insensitive applications, the external RC configuration shown in Figure 13 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. For more information on Oscillator operation and details on how to choose R and C, refer to the External RC Oscillator application note.

Figure 13. External RC Configuration

	VCC
R	NC	XTAL2
		XTAL1
C
		GND

The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7.

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Calibrated Internal RC

Oscillator

2502K–AVR–10/06

		ATmega8535(L)
Table 7. External RC Oscillator Operating Modes
CKSEL3..0		Frequency Range (MHz)
0101		0.1 - 0.9
0110		0.9 - 3.0
0111		3.0 - 8.0
1000		8.0 - 12.0

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 8.

Table 8. Start-up Times for the External RC Oscillator Clock Selection

	Start-up Time from	Additional Delay
	Power-down and	from Reset
SUT1..0	Power-save	(VCC = 5.0V)	Recommended Usage
00	18 CK	–	BOD enabled
01	18 CK	4.1 ms	Fast rising power
10	18 CK	65 ms	Slowly rising power
11	6 CK(1)	4.1 ms	Fast rising power or BOD enabled

Note: 1. This option should not be used when operating close to the maximum frequency of the device.

The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option. During Reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a frequency within ± 3% of the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ±1% accuracy at any given VCC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 239.

Table 9. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0	Nominal Frequency (MHz)
0001(1)	1.0
0010	2.0
0011	4.0
0100	8.0

Note: 1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC).

29

Oscillator Calibration Register

– OSCCAL

Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

Start-up Time from Power-

Additional Delay from

SUT1..0

down and Power-save

Reset (VCC = 5.0V)

Recommended Usage

00

6 CK

–

BOD enabled

01

6 CK

4.1 ms

Fast rising power

10(1)

6 CK

65 ms

Slowly rising power

11

Reserved

Note: 1.

The device is shipped with this option selected.

Bit

7

6

5

4

3

2

1

0

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency. During Reset, the 1 MHz calibration value which is located in the signature row high byte (address 0x00) is automatically loaded into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration values must be loaded manually. This can be done by first reading the signature row by a programmer, and then store the calibration values in the Flash or EEPROM. Then the value can be read by software and loaded into the OSCCAL Register.

When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 11.

Table 11. Internal RC Oscillator Frequency Range.

	Min Frequency in Percentage of	Max Frequency in Percentage of
OSCCAL Value	Nominal Frequency (%)	Nominal Frequency (%)
0x00	50	100
0x7F	75	150
0xFF	100	200

30 ATmega8535(L)

2502K–AVR–10/06