ATMEL AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 User Manual

Features

•Incorporates the ARM7TDMI® ARM® Thumb® Processor

–High-performance 32-bit RISC Architecture

–High-density 16-bit Instruction Set

–Leader in MIPS/Watt

–EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support

•Internal High-speed Flash

–512 Kbytes (AT91SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes (Dual Plane)

–256 kbytes(AT91SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)

–128 Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)

–64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)

–32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)

–Single Cycle Access at Up to 30 MHz in Worst Case Conditions

–Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

–Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms

–10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit

–Fast Flash Programming Interface for High Volume Production

•Internal High-speed SRAM, Single-cycle Access at Maximum Speed

–64 kbytes (AT91SAM7S512/256)

–32 kbytes (AT91SAM7S128)

–16 kbytes (AT91SAM7S64)

–8 kbytes (AT91SAM7S321/32)

•Memory Controller (MC)

–Embedded Flash Controller, Abort Status and Misalignment Detection

•Reset Controller (RSTC)

–Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector

–Provides External Reset Signal Shaping and Reset Source Status

•Clock Generator (CKGR)

–Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

•Power Management Controller (PMC)

–Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode

–Three Programmable External Clock Signals

•Advanced Interrupt Controller (AIC)

–Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

–Two (AT91SAM7S512/256/128/64/321) or One (AT91SAM7S32) External Interrupt Source(s) and One Fast Interrupt Source, Spurious Interrupt Protected

•Debug Unit (DBGU)

–2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention

•Periodic Interval Timer (PIT)

–20-bit Programmable Counter plus 12-bit Interval Counter

•Windowed Watchdog (WDT)

–12-bit key-protected Programmable Counter

–Provides Reset or Interrupt Signals to the System

–Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

AT91 ARM

Thumb-based

Microcontrollers

AT91SAM7S512

AT91SAM7S256

AT91SAM7S128

AT91SAM7S64

AT91SAM7S321

AT91SAM7S32

Preliminary

6175G–ATARM–22-Nov-06

•Real-time Timer (RTT)

–32-bit Free-running Counter with Alarm

–Runs Off the Internal RC Oscillator

•One Parallel Input/Output Controller (PIOA)

–Thirty-two (AT91SAM7S512/256/128/64/321) or twenty-one (AT91SAM7S32) Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os

–Input Change Interrupt Capability on Each I/O Line

–Individually Programmable Open-drain, Pull-up resistor and Synchronous Output

•Eleven (AT91SAM7S512/256/128/64/321) or Nine (AT91SAM7S32) Peripheral DMA Controller (PDC) Channels

•One USB 2.0 Full Speed (12 Mbits per Second) Device Port (Except for the AT91SAM7S32).

–On-chip Transceiver, 328-byte Configurable Integrated FIFOs

•One Synchronous Serial Controller (SSC)

–Independent Clock and Frame Sync Signals for Each Receiver and Transmitter

–I²S Analog Interface Support, Time Division Multiplex Support

–High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

•Two (AT91SAM7S512/256/128/64/321) or One (AT91SAM7S32) Universal Synchronous/Asynchronous Receiver Transmitters (USART)

–Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation

–Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support

–Full Modem Line Support on USART1 (AT91SAM7S512/256/128/64/321)

•One Master/Slave Serial Peripheral Interface (SPI)

–8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

•One Three (AT91SAM7S512/256/128/64/321)-channel or Two (AT91SAM7S32)-channel 16-bit Timer/Counter (TC)

–Three (AT91SAM7S512/256/128/64/321) or One (AT91SAM7S32) External Clock Input(s), Two Multi-purpose I/O Pins per Channel

–Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

•One Four-channel 16-bit PWM Controller (PWMC)

•One Two-wire Interface (TWI)

–Master Mode Support Only, All Two-wire Atmel EEPROMs Supported

•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

•SAM-BA™ Boot Assistant

–Default Boot program

–Interface with SAM-BA Graphic User Interface

•IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins

•5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each

•Power Supplies

–Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components

–3.3V or 1.8V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply

–1.8V VDDCORE Core Power Supply with Brown-out Detector

•Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions

•Available in 64-lead LQFP Green or 64-pad QFN Green Package (AT91SAM7S512/256/128/64/321) and 48-lead LQFP Green or 48-pad QFN Green Package (AT91SAM7S32)

2 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

1. Description

Atmel’s AT91SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a high-speed Flash and an SRAM, a large set of peripherals, including a USB 2.0 device (except for the AT91SAM7S32), and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.

The AT91SAM7S Series system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.

The AT91SAM7S Series are general-purpose microcontrollers. Their integrated USB Device port makes them ideal devices for peripheral applications requiring connectivity to a PC or cellular phone. Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market.

Note: References to the AT91SAM7S512 in this document concern a future product under development.

1.1Configuration Summary of the AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 and AT91SAM7S32

The AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 and AT91SAM7S32 differ in memory size, peripheral set and package. Table 1-1 summarizes the configuration of the six devices.

Except for the AT91SAM7S32, all other AT91SAM7S devices are package and pinout compatible.

Table 1-1.

Configuration Summary

USB

External

Flash

Device

Interrupt

PDC

TC

I/O

Device

Flash

Organization

SRAM

Port

USART

Source

Channels

Channels

Lines

Package

AT91SAM7S512

512K byte

dual plane

64K byte

1

2(1)

(2)

2

11

3

32

LQFP/

QFN 64

AT91SAM7S256

256K byte

single plane

64K byte

1

2(1)

(2)

2

11

3

32

LQFP/

QFN 64

AT91SAM7S128

128K byte

single plane

32K byte

1

2(1)

(2)

2

11

3

32

LQFP/

QFN 64

AT91SAM7S64

64K byte

single plane

16K byte

1

2(2)

2

11

3

32

LQFP/

QFN 64

AT91SAM7S321

32K byte

single plane

8K byte

1

2(2)

2

11

3

32

LQFP/

QFN 64

AT91SAM7S32

32K byte

single plane

8K byte

not

1

1

9

2

21

LQFP/

present

QFN 48

Notes: 1. Fractional Baud Rate.

2. Full modem line support on USART1.

3

6175G–ATARM–22-Nov-06

2. Block Diagram

Figure 2-1. AT91SAM7S512/256/128/64/321 Block Diagram

TDI
TDO		JTAG	ICE	ARM7TDMI
TMS
		SCAN		Processor
TCK
JTAGSEL
						1.8 V		VDDIN
	System Controller					Voltage		GND
TST						Regulator		VDDOUT
FIQ								VDDCORE
		AIC
IRQ0-IRQ1				Memory Controller				VDDIO
	PIO					SRAM
				Embedded
					Address
						64/32/16/8 Kbytes
PCK0-PCK2				Flash	Decoder
				Controller
PLLRC	PLL	PMC		Abort
XIN	OSC				Misalignment
				Status	Detection			VDDFLASH
XOUT
	RCOSC					Flash		ERASE
						512/256/
						128/64/32 Kbytes
VDDCORE	BOD			Peripheral Bridge
VDDCORE	POR	Reset
		Controller		Peripheral Data		ROM
								PGMRDY
NRST				Controller
						Fast Flash		PGMNVALID
				11 Channels				PGMNOE
		PIT				Programming		PGMCK
						Interface		PGMM0-PGMM3
				APB				PGMD0-PGMD15
		WDT						PGMNCMD
								PGMEN0-PGMEN2
		RTT				SAM-BA
DRXD	PIO	PDC
		DBGU
DTXD					FIFO		Transceiver
		PDC						DDM
						USB Device
								DDP
		PIOA

RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1			PIO
RI1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK

ADTRG

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADVREF

PDC

USART0

PDC

PDC

USART1

PDC

PDC

SPI

PDC

PDC

ADC

PWMC

PDC

SSC

PDC

Timer Counter

TC0

TC1

TC2

TWI

PIO

PWM0

PWM1

PWM2

PWM3 TF TK TD RD RK RF

TCLK0

TCLK1

TCLK2

TIOA0

TIOB0

TIOA1

TIOB1

TIOA2

TIOB2

TWD TWCK

4 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

Figure 2-2. AT91SAM7S32 Block Diagram

TDI
TDO	JTAG	ICE
TMS
	SCAN
TCK

JTAGSEL

System Controller

	TST
	FIQ
	IRQ0		AIC
		PIO
	PCK0-PCK2
	PLLRC	PLL	PMC
	XIN
		OSC
	XOUT
			RCOSC
	VDDCORE	BOD
		POR	Reset
	VDDCORE		Controller
	NRST
			PIT
			WDT
			RTT
	DRXD	PIO	PDC
			DBGU
	DTXD
			PDC
			PIOA

	RXD0
	TXD0	USART0
	SCK0
	RTS0	PIO
	CTS0
	NPCS0
	NPCS1
	NPCS2	SPI
	NPCS3
	MISO
	MOSI
	SPCK
	ADTRG
	AD0
	AD1
	AD2
	AD3	ADC
	AD4
	AD5
	AD6
	AD7
	ADVREF

ARM7TDMI

Processor

1.8 V

VDDIN

Voltage

GND

Regulator

VDDOUT

VDDCORE

Memory Controller

SRAM

VDDIO

Embedded

Address

8 Kbytes

Flash

Decoder

Controller

Abort

Misalignment

Status

Detection

VDDFLASH

Flash

ERASE

32 Kbytes

Peripheral Bridge

Peripheral DMA

ROM

Controller

PGMRDY

9 Channels

PGMNVALID

Fast Flash

PGMNOE

APB

Programming

PGMCK

PGMM0-PGMM3

Interface

PGMD0-PGMD7

PGMNCMD

PGMEN0-PGMEN2

SAM-BA

									PWMC
PDC
							PDC
									SSC
PDC
PDC
							PDC
								Timer Counter
PDC									TC0
PDC
									TC1
									TC2
									TWI

			PWM0
			PWM1
			PWM2
			PWM3
			TF
			TK
			TD
			RD
			RK
PIO
			RF
			TCLK0
			TIOA0
			TIOB0
			TIOA1
			TIOB1
			TWD
			TWCK

5

6175G–ATARM–22-Nov-06

3. Signal Description

Table 3-1.	Signal Description List
					Active
Signal Name		Function		Type	Level	Comments
		Power
VDDIN		Voltage and ADC Regulator Power Supply Input		Power		3.0 to 3.6V
VDDOUT		Voltage Regulator Output		Power		1.85V nominal
VDDFLASH		Flash Power Supply		Power		3.0V to 3.6V
VDDIO		I/O Lines Power Supply		Power		3.0V to 3.6V or 1.65V to 1.95V
VDDCORE		Core Power Supply		Power		1.65V to 1.95V
VDDPLL		PLL		Power		1.65V to 1.95V
GND		Ground		Ground
		Clocks, Oscillators and PLLs
XIN		Main Oscillator Input		Input
XOUT		Main Oscillator Output		Output
PLLRC		PLL Filter		Input
PCK0 - PCK2		Programmable Clock Output		Output
		ICE and JTAG
TCK		Test Clock		Input		No pull-up resistor
TDI		Test Data In		Input		No pull-up resistor
TDO		Test Data Out		Output
TMS		Test Mode Select		Input		No pull-up resistor
JTAGSEL		JTAG Selection		Input		Pull-down resistor
		Flash Memory
ERASE		Flash and NVM Configuration Bits Erase		Input	High	Pull-down resistor
		Command
		Reset/Test
NRST		Microcontroller Reset		I/O	Low	Open-drain with pull-Up resistor
TST		Test Mode Select		Input	High	Pull-down resistor
		Debug Unit
DRXD		Debug Receive Data		Input
DTXD		Debug Transmit Data		Output
		AIC
IRQ0 - IRQ1		External Interrupt Inputs		Input		IRQ1 not present on AT91SAM7S32
FIQ		Fast Interrupt Input		Input
		PIO
PA0 - PA31		Parallel IO Controller A		I/O		Pulled-up input at reset
						PA0 - PA20 only on AT91SAM7S32

6 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

Table 3-1.	Signal Description List (Continued)
					Active
Signal Name		Function		Type	Level	Comments
			USB Device Port
DDM		USB Device Port Data -		Analog		not present on AT91SAM7S32
DDP		USB Device Port Data +		Analog		not present on AT91SAM7S32
			USART
SCK0 - SCK1		Serial Clock		I/O		SCK1 not present on AT91SAM7S32
TXD0 - TXD1		Transmit Data		I/O		TXD1 not present on AT91SAM7S32
RXD0 - RXD1		Receive Data		Input		RXD1 not present on AT91SAM7S32
RTS0 - RTS1		Request To Send		Output		RTS1 not present on AT91SAM7S32
CTS0 - CTS1		Clear To Send		Input		CTS1 not present on AT91SAM7S32
DCD1		Data Carrier Detect		Input		not present on AT91SAM7S32
DTR1		Data Terminal Ready		Output		not present on AT91SAM7S32
DSR1		Data Set Ready		Input		not present on AT91SAM7S32
RI1		Ring Indicator		Input		not present on AT91SAM7S32
		Synchronous Serial Controller
TD		Transmit Data		Output
RD		Receive Data		Input
TK		Transmit Clock		I/O
RK		Receive Clock		I/O
TF		Transmit Frame Sync		I/O
RF		Receive Frame Sync		I/O
			Timer/Counter
TCLK0 - TCLK2		External Clock Inputs		Input		TCLK1 and TCLK2 not present on
						AT91SAM7S32
TIOA0 - TIOA2		I/O Line A		I/O		TIOA2 not present on AT91SAM7S32
TIOB0 - TIOB2		I/O Line B		I/O		TIOB2 not present on AT91SAM7S32
			PWM Controller
PWM0 - PWM3		PWM Channels		Output
			SPI
MISO		Master In Slave Out		I/O
MOSI		Master Out Slave In		I/O
SPCK		SPI Serial Clock		I/O
NPCS0		SPI Peripheral Chip Select 0		I/O	Low
NPCS1-NPCS3		SPI Peripheral Chip Select 1 to 3		Output	Low

7

6175G–ATARM–22-Nov-06

Table 3-1.
	Signal Description List (Continued)
									Active
Signal Name		Function				Type			Level	Comments
			Two-Wire Interface
TWD		Two-wire Serial Data				I/O
TWCK		Two-wire Serial Clock				I/O
			Analog-to-Digital Converter
AD0-AD3		Analog Inputs				Analog				Digital pulled-up inputs at reset
AD4-AD7		Analog Inputs				Analog				Analog Inputs
ADTRG		ADC Trigger				Input
ADVREF		ADC Reference				Analog
			Fast Flash Programming Interface
PGMEN0-PGMEN2		Programming Enabling				Input
PGMM0-PGMM3		Programming Mode				Input
PGMD0-PGMD15		Programming Data				I/O				PGMD0-PGMD7 only on
										AT91SAM7S32
PGMRDY		Programming Ready				Output			High
PGMNVALID		Data Direction				Output			Low
PGMNOE		Programming Read				Input			Low
PGMCK		Programming Clock				Input
PGMNCMD		Programming Command				Input			Low

8 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

4. Package and Pinout

The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package.

The AT91SAM7S32 is available in a 48-lead LQFP or 48-pad QFN package.

4.164-lead LQFP and 64-pad QFN Package Outlines

Figure 4-1 and Figure 4-2 show the orientation of the 64-lead LQFP and the 64-pad QFN package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet.

Figure 4-1. 64-lead LQFP Package (Top View)

48	33
49	32

64

					17
1					16
Figure 4-2. 64-pad QFN Package (Top View)
	48				33
49									32

64	17
1	16

9

6175G–ATARM–22-Nov-06

4.264-lead LQFP and 64-pad QFN Pinout

Table 4-1.		AT91SAM7S512/256/128/64/321 Pinout(1)
1		ADVREF		17	GND		33		TDI		49	TDO
2		GND		18	VDDIO		34		PA6/PGMNOE		50	JTAGSEL
3		AD4		19	PA16/PGMD4		35		PA5/PGMRDY		51	TMS
4		AD5		20	PA15/PGMD3		36		PA4/PGMNCMD		52	PA31
5		AD6		21	PA14/PGMD2		37		PA27/PGMD15		53	TCK
6		AD7		22	PA13/PGMD1		38		PA28		54	VDDCORE
7		VDDIN		23	PA24/PGMD12		39		NRST		55	ERASE
8		VDDOUT		24	VDDCORE		40		TST		56	DDM
9	PA17/PGMD5/AD0			25	PA25/PGMD13		41		PA29		57	DDP
10	PA18/PGMD6/AD1			26	PA26/PGMD14		42		PA30		58	VDDIO
11		PA21/PGMD9		27	PA12/PGMD0		43		PA3		59	VDDFLASH
12		VDDCORE		28	PA11/PGMM3		44		PA2/PGMEN2		60	GND
13	PA19/PGMD7/AD2			29	PA10/PGMM2		45		VDDIO		61	XOUT
14		PA22/PGMD10		30	PA9/PGMM1		46		GND		62	XIN/PGMCK
15		PA23/PGMD11		31	PA8/PGMM0		47		PA1/PGMEN1		63	PLLRC
16	PA20/PGMD8/AD3			32	PA7/PGMNVALID		48		PA0/PGMEN0		64	VDDPLL
Note:	1.	The bottom pad of the QFN package must be connected to ground.

10 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

4.348-lead LQFP and 48-pad QFN Package Outlines

Figure 4-3 and Figure 4-4 show the orientation of the 48-lead LQFP and the 48-pad QFN package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet.

Figure 4-3. 48-lead LQFP Package (Top View)

36	25
37	24

48

					13
1					12
Figure 4-4. 48-pad QFN Package (Top View)
36					25
37									24

48	13
1	12

4.448-lead LQFP and 48-pad QFN Pinout

Table 4-2.		AT91SAM7S32 Pinout(1)
1		ADVREF		13	VDDIO		25		TDI		37	TDO
2		GND		14	PA16/PGMD4		26		PA6/PGMNOE		38	JTAGSEL
3		AD4		15	PA15/PGMD3		27		PA5/PGMRDY		39	TMS
4		AD5		16	PA14/PGMD2		28		PA4/PGMNCMD		40	TCK
5		AD6		17	PA13/PGMD1		29		NRST		41	VDDCORE
6		AD7		18	VDDCORE		30		TST		42	ERASE
7		VDDIN		19	PA12/PGMD0		31		PA3		43	VDDFLASH
8		VDDOUT		20	PA11/PGMM3		32		PA2/PGMEN2		44	GND
9	PA17/PGMD5/AD0			21	PA10/PGMM2		33		VDDIO		45	XOUT
10	PA18/PGMD6/AD1			22	PA9/PGMM1		34		GND		46	XIN/PGMCK
11	PA19/PGMD7/AD2			23	PA8/PGMM0		35		PA1/PGMEN1		47	PLLRC
12		PA20/AD3		24	PA7/PGMNVALID		36		PA0/PGMEN0		48	VDDPLL
Note:	1.	The bottom pad of the QFN package must be connected to ground.

11

6175G–ATARM–22-Nov-06

5. Power Considerations

5.1Power Supplies

The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:

•VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

•VDDOUT pin. It is the output of the 1.8V voltage regulator.

•VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V, 3.3V nominal or from 1.65V to 1.95V, 1.8V nominal. Note that supplying less than 3.0V to VDDIO prevents any use of the USB transceivers.

•VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

•VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.

During startup, core supply voltage (VDDCORE) slope must be superior or equal to 6V/ms.

•VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.

No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.

In order to decrease current consumption, if the voltage regulator and the ADC are not used,

VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND. In this case

VDDOUT should be left unconnected.

5.2Power Consumption

The AT91SAM7S Series has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset. When the brown-out detector is activated, 20 µA static current is added.

The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.

5.3Voltage Regulator

The AT91SAM7S Series embeds a voltage regulator that is managed by the System

Controller.

In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.

The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the

12 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

5.4Typical Powering Schematics

The AT91SAM7S Series supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems.

Figure 5-1. 3.3V System Single Power Supply Schematic

Power Source

VDDFLASH

VDDIO

ranges

DC/DC Converter

from 4.5V (USB)

to 18V

VDDIN

Voltage

3.3V

Regulator

VDDOUT

VDDCORE

VDDPLL

13

6175G–ATARM–22-Nov-06

6. I/O Lines Considerations

6.1JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS,

TDI and TCK do not integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

6.2Test Pin

The TST pin is used for manufacturing test, fast programming mode or SAM-BA Boot Recovery of the AT91SAM7S Series when asserted high. The TST pin integrates a permanent pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low.

To enter SAM-BA Boot Recovery, the TST pin and the PA0, PA1 and PA2 pins should be tied high.

Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.

6.3Reset Pin

The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system.

The NRST pin integrates a permanent pull-up resistor to VDDIO.

6.4ERASE Pin

The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

6.5PIO Controller A Lines

All the I/O lines PA0 to PA31 (PA0 to PA20 on AT91SAM7S32) are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.

5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled will create a current path through the pullup resistor from the I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.

14 AT91SAM7S Series Preliminary

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AT91SAM7S Series Preliminary

6.6I/O Line Drive Levels

The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.

The remaining I/O lines can draw only 8 mA.

However, the total current drawn by all the I/O lines cannot exceed 150 mA (100mA for

AT91SAM7S32).

15

6175G–ATARM–22-Nov-06

7. Processor and Architecture

7.1ARM7TDMI Processor

•RISC processor based on ARMv4T Von Neumann architecture

–Runs at up to 55 MHz, providing 0.9 MIPS/MHz

•Two instruction sets

–ARM® high-performance 32-bit instruction set

–Thumb® high code density 16-bit instruction set

•Three-stage pipeline architecture

–Instruction Fetch (F)

–Instruction Decode (D)

–Execute (E)

7.2Debug and Test Features

•Integrated EmbeddedICE™ (embedded in-circuit emulator)

–Two watchpoint units

–Test access port accessible through a JTAG protocol

–Debug communication channel

•Debug Unit

–Two-pin UART

–Debug communication channel interrupt handling

–Chip ID Register

•IEEE1149.1 JTAG Boundary-scan on all digital pins

7.3Memory Controller

•Bus Arbiter

–Handles requests from the ARM7TDMI and the Peripheral DMA Controller

•Address decoder provides selection signals for

–Three internal 1 Mbyte memory areas

–One 256 Mbyte embedded peripheral area

•Abort Status Registers

–Source, Type and all parameters of the access leading to an abort are saved

–Facilitates debug by detection of bad pointers

•Misalignment Detector

–Alignment checking of all data accesses

–Abort generation in case of misalignment

•Remap Command

–Remaps the SRAM in place of the embedded non-volatile memory

–Allows handling of dynamic exception vectors

•Embedded Flash Controller

–Embedded Flash interface, up to three programmable wait states

16 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

–Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states

–Key-protected program, erase and lock/unlock sequencer

–Single command for erasing, programming and locking operations

–Interrupt generation in case of forbidden operation

7.4Peripheral DMA Controller

•Handles data transfer between peripherals and memories

•Eleven channels: AT91SAM7S512/256/128/64/321

•Nine channels: AT91SAM7S32

–Two for each USART

–Two for the Debug Unit

–Two for the Serial Synchronous Controller

–Two for the Serial Peripheral Interface

–One for the Analog-to-digital Converter

•Low bus arbitration overhead

–One Master Clock cycle needed for a transfer from memory to peripheral

–Two Master Clock cycles needed for a transfer from peripheral to memory

•Next Pointer management for reducing interrupt latency requirements

17

6175G–ATARM–22-Nov-06

8. Memories

8.1AT91SAM7S512

•512 Kbytes of Flash Memory, dual plane

–2 contiguous banks of 1024 pages of 256 bytes

–Fast access time, 30 MHz single-cycle access in Worst Case conditions

–Page programming time: 6 ms, including page auto-erase

–Page programming without auto-erase: 3 ms

–Full chip erase time: 15 ms

–10,000 write cycles, 10-year data retention capability

–32 lock bits, protecting 32 sectors of 64 pages

–Protection Mode to secure contents of the Flash

•64 Kbytes of Fast SRAM

–Single-cycle access at full speed

8.2AT91SAM7S256

•256 Kbytes of Flash Memory, single plane

–1024 pages of 256 bytes

–Fast access time, 30 MHz single-cycle access in Worst Case conditions

–Page programming time: 6 ms, including page auto-erase

–Page programming without auto-erase: 3 ms

–Full chip erase time: 15 ms

–10,000 write cycles, 10-year data retention capability

–16 lock bits, protecting 16 sectors of 64 pages

–Protection Mode to secure contents of the Flash

•64 Kbytes of Fast SRAM

–Single-cycle access at full speed

8.3AT91SAM7S128

•128 Kbytes of Flash Memory, single plane

–512 pages of 256 bytes

–Fast access time, 30 MHz single-cycle access in Worst Case conditions

–Page programming time: 6 ms, including page auto-erase

–Page programming without auto-erase: 3 ms

–Full chip erase time: 15 ms

–10,000 write cycles, 10-year data retention capability

–8 lock bits, protecting 8 sectors of 64 pages

–Protection Mode to secure contents of the Flash

•32 Kbytes of Fast SRAM

–Single-cycle access at full speed

18 AT91SAM7S Series Preliminary

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AT91SAM7S Series Preliminary

8.4AT91SAM7S64

•64 Kbytes of Flash Memory, single plane

–512 pages of 128 bytes

–Fast access time, 30 MHz single-cycle access in Worst Case conditions

–Page programming time: 6 ms, including page auto-erase

–Page programming without auto-erase: 3 ms

–Full chip erase time: 15 ms

–10,000 write cycles, 10-year data retention capability

–16 lock bits, protecting 16 sectors of 32 pages

–Protection Mode to secure contents of the Flash

•16 Kbytes of Fast SRAM

–Single-cycle access at full speed

8.5AT91SAM7S321/32

•32 Kbytes of Flash Memory, single plane

–256 pages of 128 bytes

–Fast access time, 30 MHz single-cycle access in Worst Case conditions

–Page programming time: 6 ms, including page auto-erase

–Page programming without auto-erase: 3 ms

–Full chip erase time: 15 ms

–10,000 write cycles, 10-year data retention capability

–8 lock bits, protecting 8 sectors of 32 pages

–Protection Mode to secure contents of the Flash

•8 Kbytes of Fast SRAM

–Single-cycle access at full speed

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6175G–ATARM–22-Nov-06

Figure 8-1. AT91SAM7S512/256/128/64/321/32 Memory Mapping

Internal Memory Mapping

		0x0000 0000
			(1)
			Flash before Remap	1 MBytes
			SRAM after Remap
		0x000F FFF
		0x0010 0000
			Internal Flash	1 MBytes
		0x001F FFF
		0x0020 0000
			Internal SRAM	1 MBytes
		0x002F FFF
		0x0030 0000
Address Memory Space
0x0000 0000			Reserved	253 MBytes
	Internal Memories 256 MBytes
		0x0FFF FFFF
0x0FFF FFFF
0x1000 0000

			Peripheral Mapping
			0xF000 0000
	Undefined	14 x 256 MBytes		Reserved
	(Abort)	3,584 MBytes	0xFFF9 FFFF
			0xFFFA 0000	TC0, TC1, TC2	16 Kbytes
			0xFFFA 3FFF
			0xFFFA 4000	Reserved
			0xFFFA FFFF		16 Kbytes
			0xFFFB 0000	UDP
					(Reserved on
			0xFFFB 3FFF
					AT91SAM7S32)
			0xFFFB 4000	Reserved
			0xFFFB 7FFF
			0xFFFB 8000	TWI	16 Kbytes
	0xEFFF FFFF		0xFFFB BFFF
	0xF000 0000		0xFFFB C000	Reserved
			0xFFFB FFFF
			0xFFFC 0000	USART0	16 Kbytes
			0xFFFC 3FFF
	Internal Peripherals	256M Bytes			16 Kbytes
			0xFFFC 4000	USART1
					(Reserved on
			0xFFFC 7FFF
					AT91SAM7S32
			0xFFFC 8000	Reserved
	0xFFFF FFFF		0xFFFC BFFF
			0xFFFC C000	PWMC	16 Kbytes
			0xFFFC FFFF
			0xFFFD 0000	Reserved
			0xFFFD 3FFF
			0xFFFD 4000	SSC	16 Kbytes
			0xFFFD 7FFF
			0xFFFD 8000	ADC	16 Kbytes
			0xFFFD BFFF
			0xFFFD C000	Reserved
			0xFFFD FFFF
			0xFFFE 0000	SPI	16 Kbytes
			0xFFFE 3FFF
			0xFFFE 4000	Reserved
			0xFFFF EFFF
			0xFFFF F000	SYSC
			0xFFFF FFFF

Note:

(1) Can be Flash or SRAM depending on REMAP.

System Controller Mapping

0xFFFF F000

0xFFFF F1FF 0xFFFF F200

0xFFFF F3FF 0xFFFF F400

0xFFFF F5FF 0xFFFF F600

0xFFFF FBFF 0xFFFF FC00

0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F

0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30

0xFFFF FC3F 0xFFFF FD40

0xFFFF FD4F

0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00

AIC

DBGU

PIOA

Reserved

PMC

RSTC

Reserved

RTT

PIT

WDT

Reserved

VREG

Reserved

MC

0xFFFF FFFF

512 Bytes/

128 registers

512 Bytes/

128 registers

512 Bytes/

128 registers

256 Bytes/

64 registers

16 Bytes/

4 registers

16 Bytes/

4 registers

16 Bytes/

4 registers

16 Bytes/

4 registers

4 Bytes/

1 register

256 Bytes/

64 registers

20 AT91SAM7S Series Preliminary

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AT91SAM7S Series Preliminary

8.6Memory Mapping

8.6.1Internal SRAM

•The AT91SAM7S512 embeds a high-speed 64 Kbyte SRAM bank.

•The AT91SAM7S256 embeds a high-speed 64 Kbyte SRAM bank.

•The AT91SAM7S128 embeds a high-speed 32 Kbyte SRAM bank.

•The AT91SAM7S64 embeds a high-speed 16 Kbyte SRAM bank.

•The AT91SAM7S321 embeds a high-speed 8 Kbyte SRAM bank.

•The AT91SAM7S32 embeds a high-speed 8 Kbyte SRAM bank.

After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.

8.6.2Internal ROM

The AT91SAM7S Series embeds an Internal ROM. The ROM contains the FFPI and the

SAM-BA program.

The internal ROM is not mapped by default.

8.6.3Internal Flash

•The AT91SAM7S512 features two contiguous banks (dual plane) of 256 Kbytes of Flash.

•The AT91SAM7S256 features one bank (single plane) of 256 Kbytes of Flash.

•The AT91SAM7S128 features one bank (single plane) of 128 Kbytes of Flash.

•The AT91SAM7S64 features one bank (single plane) of 64 Kbytes of Flash.

•The AT91SAM7S321/32 features one bank (single plane) of 32 Kbytes of Flash.

At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command.

Figure 8-2. Internal Memory Mapping

	0x0000 0000	Flash Before Remap		1 MBytes
	0x000F FFFF	SRAM After Remap
	0x0010 0000
		Internal Flash		1 MBytes
	0x001F FFFF
	0x0020 0000
256 MBytes		Internal SRAM		1 MBytes
	0x002F FFFF
	0x0030 0000
		Undefined Areas		253 MBytes
		(Abort)
	0x0FFF FFFF

21

6175G–ATARM–22-Nov-06

8.7Embedded Flash

8.7.1Flash Overview

•The Flash of the AT91SAM7S512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words.

•The Flash of the AT91SAM7S256 is organized in 1024 pages (single plane) of 256 bytes. The 262,144 bytes are organized in 32-bit words.

•The Flash of the AT91SAM7S128 is organized in 512 pages (single plane) of 256 bytes. The 131,072 bytes are organized in 32-bit words.

•The Flash of the AT91SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized in 32-bit words.

•The Flash of the AT91SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The 32,768 bytes are organized in 32-bit words.

•The Flash of the AT91SAM7S512/256/128 contains a 256-byte write buffer, accessible through a 32-bit interface..

•The Flash of the AT91SAM7S64/321/32 contains a 128-byte write buffer, accessible through a 32-bit interface.

The Flash benefits from the integration of a power reset cell and from the brownout detector.

This prevents code corruption during power supply changes, even in the worst conditions.

When Flash is not used (read or write access), it is automatically placed into standby mode.

8.7.2Embedded Flash Controller

The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:

•programming of the access parameters of the Flash (number of wait states, timings, etc.)

•starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.

•getting the end status of the last command

•getting error status

•programming interrupts on the end of the last commands or on errors

The Embedded Flash Controller also provides a dual 32-bit prefetch buffer that optimizes 16bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.

Two EFCs are embedded in the SAM7S512 to control each bank of 256 KBytes. Dual plane organization allows concurrent Read and Program. Read from one memory plane may be performed even while program or erase functions are being executed in the other memory plane.

One EFC is embedded in the SAM7S256/128/64/32/321 to control the single plane 256/128/64/32 KBytes.

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AT91SAM7S Series Preliminary

8.7.3Lock Regions

8.7.3.1AT91SAM7S512

Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 16 NVM bits (or 32 NVM bits) are software programmable through the corresponding EFC

User Interface. The command “Set Lock Bit” enables the protection. The command “Clear

Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.7.3.2AT91SAM7S256

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.7.3.3AT91SAM7S128

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.7.3.4AT91SAM7S64

The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S64 contains 16 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

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6175G–ATARM–22-Nov-06

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.7.3.5AT91SAM7S321/32

The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S321/32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

Table 8-1 summarizes the configuration of the six devices.

Table 8-1.	Flash Configuration Summary
Device		Number of Lock Bits	Number of Pages in the Lock Region	Page Size
AT91SAM7S512		32	64	256 bytes
AT91SAM7S256		16	64	256 bytes
AT91SAM7S128		8	64	256 bytes
AT91SAM7S64		16	32	128 bytes
AT91SAM7S321/32		8	32	128 bytes

8.7.4Security Bit Feature

The AT91SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.

8.7.5Non-volatile Brownout Detector Control

Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.

These two GPNVM bits can be cleared or set respectively through the commands “Clear Gen- eral-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

•GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.

24 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

•The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.

8.7.6Calibration Bits

Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.

8.8Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-pro- gramming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low.

8.9SAM-BA Boot Assistant

The SAM-BA™ Boot Recovery restores the SAM-BA Boot in the first two sectors of the on-chip Flash memory. The SAM-BA Boot recovery is performed when the TST pin and the PA0, PA1 and PA2 pins are all tied high.

The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication through the DBGU or through the

USB Device Port. (The AT91SAM7S32 has no USB Device Port.)

•Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection.

•Communication through the USB Device Port is limited to an 18.432 MHz crystal. (

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

25

6175G–ATARM–22-Nov-06

9. System Controller

The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.

The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF.

Figure 9-1 on page 27 and Figure 9-2 on page 28 show the product specific System Controller

Block Diagrams.

Figure 8-1 on page 20 shows the mapping of the of the User Interface of the System Controller peripherals. Note that the memory controller configuration user interface is also mapped within this address space.

26 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

						AT91SAM7S Series Preliminary
Figure 9-1.	System Controller Block Diagram (AT91SAM7S512/256/128/64/321)
				System Controller				jtag_nreset	Boundary Scan
									TAP Controller
			irq0-irq1					nirq
					Advanced			nfiq
			fiq
					Interrupt
								proc_nreset	ARM7TDMI
		periph_irq[2..14]			Controller
						int		PCK
		pit_irq						debug
		rtt_irq
		wdt_irq
		dbgu_irq						power_on_reset
		pmc_irq
		rstc_irq						force_ntrst
			MCK		Debug	dbgu_irq
		periph_nreset				force_ntrst
					Unit
		dbgu_rxd				dbgu_txd
					Periodic			security_bit
			MCK
			debug		Interval	pit_irq
		periph_nreset			Timer
			SLCK		Real-Time	rtt_irq		flash_poe	Embedded
		periph_nreset			Timer			flash_wrdis	Flash
			SLCK					cal
					Watchdog
			debug			wdt_irq		gpnvm[0..1]
			idle		Timer
		proc_nreset
		cal		gpnvm[1]	wdt_fault
		gpnvm[0]
					WDRPROC
								MCK
		en			bod_rst_en				Memory
				flash_wrdis
		BOD						proc_nreset	Controller
				power_on_reset	Reset	periph_nreset
				jtag_nreset
		POR			Controller	proc_nreset	Voltage
				flash_poe			Regulator	standby
							Mode
									Voltage
	NRST					rstc_irq	Controller		Regulator
								cal
			SLCK
		RCOSC	SLCK			periph_clk[2..14]		UDPCK
						pck[0-2]
								periph_clk[11]	USB Device
	XIN				Power
		OSC	MAINCK						Port
					Management	PCK		periph_nreset
	XOUT				Controller	UDPCK		periph_irq[11]
						MCK
								usb_suspend
	PLLRC	PLL	PLLCK
						pmc_irq
			int
		periph_nreset				idle
								periph_clk[4..14]
		usb_suspend
								periph_nreset	Embedded
		periph_nreset				periph_irq{2]			Peripherals
		periph_clk[2]				irq0-irq1		periph_irq[4..14]
		dbgu_rxd			PIO	fiq
					Controller	dbgu_txd
	PA0-PA31							in
								out
								enable
									27
6175G–ATARM–22-Nov-06

Figure 9-2. System Controller Block Diagram (AT91SAM7S32)

			System Controller				jtag_nreset	Boundary Scan
								TAP Controller
		irq0					nirq
				Advanced			nfiq
		fiq
				Interrupt
							proc_nreset	ARM7TDMI
	periph_irq[2..14]			Controller
					int		PCK
	pit_irq						debug
	rtt_irq
	wdt_irq
	dbgu_irq						power_on_reset
	pmc_irq
	rstc_irq						force_ntrst
		MCK		Debug	dbgu_irq
	periph_nreset				force_ntrst
				Unit
		dbgu_rxd			dbgu_txd
				Periodic			security_bit
		MCK
		debug		Interval	pit_irq
	periph_nreset			Timer
		SLCK		Real-Time	rtt_irq		flash_poe	Embedded
	periph_nreset			Timer			flash_wrdis	Flash
		SLCK		Watchdog			cal
		debug			wdt_irq		gpnvm[0..1]
		idle		Timer
	proc_nreset
	cal		gpnvm[1]	wdt_fault
	gpnvm[0]
				WDRPROC
							MCK
	en			bod_rst_en				Memory
	BOD		flash_wrdis				proc_nreset	Controller
			power_on_reset	Reset	periph_nreset
			jtag_nreset
	POR			Controller	proc_nreset	Voltage
			flash_poe			Regulator	standby
						Mode		Voltage
NRST					rstc_irq	Controller		Regulator
							cal
		SLCK
	RCOSC	SLCK			periph_clk[2..14]
					pck[0-2]
XIN	OSC	MAINCK		Power
				Management	PCK
XOUT
				Controller
					MCK
PLLRC	PLL	PLLCK
					pmc_irq
		int
	periph_nreset				idle
							periph_clk[4..14]
							periph_nreset	Embedded
	periph_nreset				periph_irq{2]			Peripherals
	periph_clk[2]				irq0		periph_irq[4..14]
	dbgu_rxd			PIO	fiq
				Controller	dbgu_txd
PA0-PA20							in
							out
							enable

28 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06

AT91SAM7S Series Preliminary

9.1Reset Controller

The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin open-drain output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.

Note that if NRST is used as a reset output signal for external devices during power-off, the brownout detector must be activated.

9.1.1Brownout Detector and Power-on Reset

The AT91SAM7S Series embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply.

The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.

The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE.

Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other power supply of the device cannot affect the Flash.

When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediately activated.

When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated.

The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.

29

6175G–ATARM–22-Nov-06

9.2Clock Generator

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:

•RC Oscillator ranges between 22 kHz and 42 kHz

•Main Oscillator frequency ranges between 3 and 20 MHz

•Main Oscillator can be bypassed

•PLL output ranges between 80 and 220 MHz

It provides SLCK, MAINCK and PLLCK.

Figure 9-3. Clock Generator Block Diagram

Clock Generator

Embedded

Slow Clock

RC

SLCK

Oscillator

XIN

Main

Main Clock

XOUT

Oscillator

MAINCK

PLL and

PLL Clock

PLLRC

Divider

PLLCK

Status

Control

Power

Management

Controller

9.3Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

•the Processor Clock PCK

•the Master Clock MCK

•the USB Clock UDPCK (not present on AT91SAM7S32)

•all the peripheral clocks, independently controllable

•three programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt.

30 AT91SAM7S Series Preliminary

6175G–ATARM–22-Nov-06