ATMEL ATmega8515, ATmega8515L User Manual

Features

•High-performance, Low-power AVR®8-bit Microcontroller

•RISC Architecture

–130 Powerful Instructions – Most Single Clock Cycle Execution

–32 x 8 General Purpose Working Registers

–Fully Static Operation

–Up to 16 MIPS Throughput at 16 MHz

–On-chip 2-cycle Multiplier

•Nonvolatile Program and Data Memories

–8K Bytes of In-System Self-programmable Flash

Endurance: 10,000 Write/Erase Cycles

–Optional Boot Code Section with Independent Lock bits In-System Programming by On-chip Boot Program True Read-While-Write Operation

–512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

–512 Bytes Internal SRAM

–Up to 64K Bytes Optional External Memory Space

–Programming Lock for Software Security

•Peripheral Features

–One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

–Three PWM Channels

–Programmable Serial USART

–Master/Slave SPI Serial Interface

–Programmable Watchdog Timer with Separate On-chip Oscillator

–On-chip Analog Comparator

•Special Microcontroller Features

–Power-on Reset and Programmable Brown-out Detection

–Internal Calibrated RC Oscillator

–External and Internal Interrupt Sources

–Three Sleep Modes: Idle, Power-down and Standby

•I/O and Packages

–35 Programmable I/O Lines

–40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad MLF

•Operating Voltages

–2.7 - 5.5V for ATmega8515L

–4.5 - 5.5V for ATmega8515

•Speed Grades

–0 - 8 MHz for ATmega8515L

–0 - 16 MHz for ATmega8515

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

ATmega8515

ATmega8515L

Rev. 2512F–AVR–12/03

Pin Configurations

Figure 1. Pinout ATmega8515

(MOSI) PB5 1 (MISO) PB6 2 (SCK) PB7 3

RESET 4 (RXD) PD0 5 NC* 6 (TXD) PD1 7

(INT0) PD2 8 (INT1) PD3 9 (XCK) PD4 10 (OC1A) PD5 11

PDIP

(OC0/T0) PB0							1	40		VCC
		(T1) PB1					2	39		PA0 (AD0)
(AIN0) PB2							3	38		PA1 (AD1)
(AIN1) PB3							4	37		PA2 (AD2)
	(SS) PB4						5	36		PA3 (AD3)
(MOSI) PB5							6	35		PA4 (AD4)
(MISO) PB6							7	34		PA5 (AD5)
(SCK) PB7							8	33		PA6 (AD6)
							9	32		PA7 (AD7)
			RESET
(RXD) PD0							10	31		PE0 (ICP/INT2)
(TDX) PD1							11	30		PE1 (ALE)
(INT0) PD2							12	29		PE2 (OC1B)
(INT1) PD3							13	28		PC7 (A15)
(XCK) PD4							14	27		PC6 (A14)
(OC1A) PD5							15	26		PC5 (A13)
(WR) PD6							16	25		PC4 (A12)
							17	24		PC3 (A11)
		(RD)		PD7
			XTAL2				18	23		PC2 (A10)
			XTAL1				19	22		PC1 (A9)
				GND			20	21		PC0 (A8)

					TQFP/MLF																	PLCC
	PB4 (SS)		PB3 (AIN1)	PB2 (AIN0)	PB1 (T1)	PB0 (OC0/T0)	NC*	VCC	PA0 (AD0)	PA1 (AD1)	PA2 (AD2)	PA3 (AD3)					PB4 (SS)		PB3 (AIN1)	PB2 (AIN0)	PB1 (T1)	PB0 (OC0/T0)	NC*	VCC	PA0 (AD0)	PA1 (AD1)	PA2 (AD2)	PA3 (AD3)
44		43		42	41	40	39	38	37	36	35	34				6		5		4	3	2	1	44	43	42	41	40
														(MOSI) PB5															PA4 (AD4)
												33	PA4 (AD4)			7												39
												32	PA5 (AD5)	(MISO) PB6		8												38	PA5 (AD5)
												31	PA6 (AD6)	(SCK) PB7		9												37	PA6 (AD6)
												30	PA7 (AD7)		RESET	10												36	PA7 (AD7)
												29	PE0 (ICP/INT2)	(RXD) PD0		11												35	PE0 (ICP/INT2)
												28	NC*		NC*	12												34	NC*
												27	PE1 (ALE)	(TXD) PD1		13												33	PE1 (ALE)
												26	PE2 (OC1B)	(INT0) PD2		14												32	PE2 (OC1B)
												25	PC7 (A15)	(INT1) PD3		15												31	PC7 (A15)
												24	PC6 (A14)	(XCK) PD4		16												30	PC6 (A14)
												23	PC5 (A13)	(OC1A) PD5		17												29	PC5 (A13)
																18		19		20	21	22	23	24	25	26	27	28
	(WR) PD6 12		(RD) PD7 13	XTAL2 14	XTAL1 15	GND 16	NC* 17	(A8) PC0 18	(A9) PC1 19	(A10) PC2 20	(A11) PC3 21	(A12) PC4 22					(WR) PD6		(RD) PD7	XTAL2	XTAL1	GND	NC*	(A8) PC0	(A9) PC1	(A10) PC2	(A11) PC3	(A12) PC4

NOTES:

1.MLF bottom pad should be soldered to ground.

2.* NC = Do not connect (May be used in future devices)

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ATmega8515(L)

Overview

The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram	Figure 2. Block Diagram
		PA0 - PA7	PE0 - PE2	PC0 - PC7
	VCC
			PORTE
		PORTA DRIVERS/BUFFERS	DRIVERS/	PORTC DRIVERS/BUFFERS
			BUFFERS
			PORTE
	GND	PORTA DIGITAL INTERFACE	DIGITAL	PORTC DIGITAL INTERFACE
			INTERFACE

	PROGRAM	STACK	TIMERS/
			COUNTERS
	COUNTER	POINTER
	PROGRAM	SRAM	INTERNAL
	FLASH		OSCILLATOR
				XTAL1
	INSTRUCTION	GENERAL	WATCHDOG	OSCILLATOR
	REGISTER		TIMER
		PURPOSE
		REGISTERS
		X		XTAL2
	INSTRUCTION	Y	MCU CTRL.	RESET
	DECODER		& TIMING
		Z
	CONTROL		INTERRUPT	INTERNAL
				CALIBRATED
	LINES	ALU	UNIT
				OSCILLATOR
	AVR CPU	STATUS	EEPROM
		REGISTER
	PROGRAMMING	SPI	USART
	LOGIC
	+	COMP.
	-	INTERFACE

PORTB DIGITAL INTERFACE	PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS	PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

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	The AVR core combines a rich instruction set with 32 general purpose working registers.
	All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
	two independent registers to be accessed in one single instruction executed in one clock
	cycle. The resulting architecture is more code efficient while achieving throughputs up to
	ten times faster than conventional CISC microcontrollers.
	The ATmega8515 provides the following features: 8K bytes of In-System Programmable
	Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an
	External memory interface, 35 general purpose I/O lines, 32 general purpose working
	registers, two flexible Timer/Counters with compare modes, Internal and External inter-
	rupts, a Serial Programmable USART, a programmable Watchdog Timer with internal
	Oscillator, a SPI serial port, and three software selectable power saving modes. The Idle
	mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt
	system to continue functioning. The Power-down mode saves the Register contents but
	freezes the Oscillator, disabling all other chip functions until the next interrupt or hard-
	ware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of
	the device is sleeping. This allows very fast start-up combined with low-power
	consumption.
	The device is manufactured using Atmel’s high density nonvolatile memory technology.
	The On-chip ISP Flash allows the Program memory to be reprogrammed In-System
	through an SPI serial interface, by a conventional nonvolatile memory programmer, or
	by an On-chip Boot program running on the AVR core. The boot program can use any
	interface to download the application program in the Application Flash memory. Soft-
	ware in the Boot Flash section will continue to run while the Application Flash section is
	updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
	with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515
	is a powerful microcontroller that provides a highly flexible and cost effective solution to
	many embedded control applications.
	The ATmega8515 is supported with a full suite of program and system development
	tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-cir-
	cuit Emulators, and Evaluation kits.
Disclaimer	Typical values contained in this datasheet are based on simulations and characteriza-
	tion of other AVR microcontrollers manufactured on the same process technology. Min
	and Max values will be available after the device is characterized.

AT90S4414/8515 and

ATmega8515

Compatibility

The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several new features are added . The ATmega8515 is backward compatible with AT90S4414/8515 in most cases. However, some incompatibilities between the two microcontrollers exist. To solve this problem, an AT90S4414/8515 compatibility mode can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compatible with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed circuit boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices.

AT90S4414/8515 Compatibility

Mode

Programming the S8515C Fuse will change the following functionality:

•The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 52 for details.

•The double buffering of the USART Receive Registers is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 135 for details.

•PORTE(2:1) will be set as output, and PORTE0 will be set as input.

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								ATmega8515(L)
	Pin Descriptions
	VCC		Digital supply voltage.
	GND		Ground.
	Port A (PA7..PA0)		Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
			bit). The Port A output buffers have symmetrical drive characteristics with both high sink
			and source capability. When pins PA0 to PA7 are used as inputs and are externally
			pulled low, they will source current if the internal pull-up resistors are activated. The Port
			A pins are tri-stated when a reset condition becomes active, even if the clock is not
			running.
			Port A also serves the functions of various special features of the ATmega8515 as listed
			on page 66.
	Port B (PB7..PB0)		Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
			bit). The Port B output buffers have symmetrical drive characteristics with both high sink
			and source capability. As inputs, Port B pins that are externally pulled low will source
			current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
			condition becomes active, even if the clock is not running.
			Port B also serves the functions of various special features of the ATmega8515 as listed
			on page 66.
	Port C (PC7..PC0)		Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
			bit). The Port C output buffers have symmetrical drive characteristics with both high sink
			and source capability. As inputs, Port C pins that are externally pulled low will source
			current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
			condition becomes active, even if the clock is not running.
	Port D (PD7..PD0)		Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
			bit). The Port D output buffers have symmetrical drive characteristics with both high sink
			and source capability. As inputs, Port D pins that are externally pulled low will source
			current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
			condition becomes active, even if the clock is not running.
			Port D also serves the functions of various special features of the ATmega8515 as listed
			on page 71.
	Port E(PE2..PE0)		Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each
			bit). The Port E output buffers have symmetrical drive characteristics with both high sink
			and source capability. As inputs, Port E pins that are externally pulled low will source
			current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
			condition becomes active, even if the clock is not running.
			Port E also serves the functions of various special features of the ATmega8515 as listed
			on page 73.
			Reset input. A low level on this pin for longer than the minimum pulse length will gener-
	RESET
			ate a reset, even if the clock is not running. The minimum pulse length is given in Table
			18 on page 45. Shorter pulses are not guaranteed to generate a reset.
	XTAL1		Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
	XTAL2		Output from the inverting Oscillator amplifier.
							5
	2512F–AVR–12/03

About Code

Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.

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ATmega8515(L)

AVR CPU Core

Introduction

Architectural Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 3. Block Diagram of the AVR Architecture

			Data Bus 8-bit
Flash	Program		Status
	Counter		and Control
Program
Memory
			32 x 8	Interrupt
Instruction				Unit
			General
Register			Purpose	SPI
			Registrers
				Unit
Instruction				Watchdog
Decoder	AddressingDirect	AddressingIndirect		Timer
			ALU	Analog
Control Lines				Comparator
				I/O Module1
			Data	I/O Module 2
			SRAM
				I/O Module n
			EEPROM
			I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is InSystem re programmable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

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ALU – Arithmetic Logic

Unit

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its Control Registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate interrupt vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

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ATmega8515(L)

Status Register

The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to

perform conditional operations. Note that the Status Register is updated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the dedicated compare instructions, resulting in faster and

more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

SREG

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate Control Registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I- bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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General Purpose

Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

•One 8-bit output operand and one 8-bit result input

•Two 8-bit output operands and one 8-bit result input

•Two 8-bit output operands and one 16-bit result input

•One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

7			0	Addr.
			R0	$00
			R1	$01
			R2	$02
			…
			R13	$0D
General			R14	$0E
Purpose			R15	$0F
Working			R16	$10
Registers			R17	$11
			…
			R26	$1A	X-register Low Byte
			R27	$1B	X-register High Byte
			R28	$1C	Y-register Low Byte
			R29	$1D	Y-register High Byte
			R30	$1E	Z-register Low Byte
			R31	$1F	Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

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ATmega8515(L)

The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are 16-bit address pointers for indirect addressing of the Data Space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5.	The X-, Y-, and Z-registers
	15		XH		XL	0
X-register		7		0	7	0
		R27 ($1B)			R26 ($1A)
	15		YH		YL	0
Y-register		7		0	7	0
		R29 ($1D)			R28 ($1C)
	15		ZH		ZL	0
Z-register		7	0		7	0
		R31 ($1F)			R30 ($1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set reference for details).

Stack Pointer	The Stack is mainly used for storing temporary data, for storing local variables and for
	storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-
	ter always points to the top of the Stack. Note that the Stack is implemented as growing
	from higher memory locations to lower memory locations. This implies that a Stack
	PUSH command decreases the Stack Pointer.
	The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-
	rupt Stacks are located. This Stack space in the data SRAM must be defined by the
	program before any subroutine calls are executed or interrupts are enabled. The Stack
	Pointer must be set to point above $60. The Stack Pointer is decremented by one when
	data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
	when the return address is pushed onto the Stack with subroutine call or interrupt. The
	Stack Pointer is incremented by one when data is popped from the Stack with the POP
	instruction, and it is incremented by two when address is popped from the Stack with
	return from subroutine RET or return from interrupt RETI.
	The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The num-
	ber of bits actually used is implementation dependent. Note that the data space in some
	implementations of the AVR architecture is so small that only SPL is needed. In this
	case, the SPH Register will not be present.
	Bit	15	14	13	12		11	10	9	8
		SP15	SP14	SP13	SP12		SP11	SP10	SP9	SP8	SPH
											SPL
		SP7	SP6	SP5	SP4		SP3	SP2	SP1	SP0
		7	6	5	4		3	2	1	0
	Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
		R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
	Initial Value	0	0	0	0		0	0	0	0
		0	0	0	0		0	0	0	0

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Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

Reset and Interrupt

Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 177 for details.

The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 53. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 53 for more information. The Reset Vector can

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ATmega8515(L)

also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 164.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding Interrupt Enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set global interrupt enable

sleep; enter sleep, waiting for interrupt

;note: will enter sleep before any pending

;interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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AVR ATmega8515

Memories

In-System Reprogrammable Flash Program memory

2512F–AVR–12/03

ATmega8515(L)

This section describes the different memories in the ATmega8515. The AVR architecture has two main memory spaces, the Data Memory and the Program memory space. In addition, the ATmega8515 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

The ATmega8515 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8515 Program Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read- While-Write Self-Programming” on page 164. “Memory Programming” on page 177 contains a detailed description on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space, see the LPM – Load Program memory instruction description.

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 12.

Figure 8. Program memory Map

$000

Application Flash Section

Boot Flash Section

$FFF

15

SRAM Data Memory Figure 9 shows how the ATmega8515 SRAM Memory is organized.

The lower 608 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 512 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega8515. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register File, I/O, Extended I/O and Internal SRAM occupies the lowest 608 bytes in normal mode, so when using 64KB (65536 bytes) of External Memory, 64928 Bytes of External Memory are available. See “External Memory Interface” on page 24 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal Data memory locations, the external data SRAM is accessed using the same instructions as for the internal Data memory access. When the internal data memories are accessed, the read and write strobe pins (PD7 and PD6) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the two-byte Program Counter is pushed and popped, and external memory access does not take advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of internal data SRAM in the ATmega8515 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.

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				ATmega8515(L)
	Figure 9. Data Memory Map
		Data Memory
			$0000 - $001F
		32 Registers
		64 I/O Registers	$0020 - $005F
		Internal SRAM	$0060
		(512 x 8)	$025F
		External SRAM	$0260
		(0 - 64K x 8)

$FFFF

Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

T1

T2

T3

clkCPU

Address

Compute Address

Address Valid

Data

WR

Data

RD

Read Write

Memory Access Instruction

Next Instruction

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EEPROM Data Memory The ATmega8515 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 177 contains a detailed description on EEPROM Programming in SPI or Parallel Programming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 23. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

The EEPROM Address

Register – EEARH and EEARL

Bit	15	14	13	12	11	10	9	8
	–	–	–	–	–	–	–	EEAR8	EEARH
	EEAR7	EEAR6	EEAR5	EEAR4	EEAR3	EEAR2	EEAR1	EEAR0	EEARL
	7	6	5	4	3	2	1	0
Read/Write	R	R	R	R	R	R	R	R/W
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	X
	X	X	X	X	X	X	X	X

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega8515 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

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ATmega8515(L)

The EEPROM Data Register –

EEDR

Bit	7	6	5	4	3	2	1	0
	MSB							LSB	EEDR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

The EEPROM Control Register

– EECR

Bit	7	6	5	4	3	2	1	0
	–	–	–	–	EERIE	EEMWE	EEWE	EERE	EECR
Read/Write	R	R	R	R	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	X	0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega8515 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1.Wait until EEWE becomes zero.

2.Wait until SPMEN in SPMCR becomes zero.

3.Write new EEPROM address to EEAR (optional).

4.Write new EEPROM data to EEDR (optional).

5.Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6.Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 164 for details about boot programming.

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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

	Number of Calibrated RC
Symbol	Oscillator Cycles(1)	Typ Programming Time
EEPROM Write (from CPU)	8448	8.5 ms

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

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ATmega8515(L)

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Write data (r16) to data register out EEDR,r16

; Write logical one to EEMWE sbi EECR,EEMWE

; Start eeprom write by setting EEWE sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up address and data registers */ EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE sbi EECR,EERE

; Read data from data register in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up address register */ EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */ return EEDR;

}

EEPROM Write During Power- When entering Power-down Sleep mode while an EEPROM write operation is active, down Sleep Mode the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the crystal Oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is com-

pleted before entering Power-down.

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			ATmega8515(L)
	Preventing EEPROM
		During periods of low VCC, the EEPROM data can be corrupted because the supply volt-
	Corruption	age is too low for the CPU and the EEPROM to operate properly. These issues are the
		same as for board level systems using EEPROM, and the same design solutions should
		be applied.
		An EEPROM data corruption can be caused by two situations when the voltage is too
		low. First, a regular write sequence to the EEPROM requires a minimum voltage to
		operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
		supply voltage is too low.
		EEPROM data corruption can easily be avoided by following this design
		recommendation:
		Keep the AVR RESET active (low) during periods of insufficient power supply volt-
		age. This can be done by enabling the internal Brown-out Detector (BOD). If the
		detection level of the internal BOD does not match the needed detection level, an
		external low VCC Reset Protection circuit can be used. If a Reset occurs while a
		write operation is in progress, the write operation will be completed provided that the
		power supply voltage is sufficient.
	I/O Memory	The I/O space definition of the ATmega8515 is shown in “Register Summary” on page
		237.
		All ATmega8515 I/Os and peripherals are placed in the I/O space. The I/O locations are
		accessed by the IN and OUT instructions, transferring data between the 32 general pur-
		pose working registers and the I/O space. I/O Registers within the address range $00 -
		$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
		value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
		the instruction set section for more details. When using the I/O specific commands IN
		and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as
		data space using LD and ST instructions, $20 must be added to these addresses.
		For compatibility with future devices, reserved bits should be written to zero if accessed.
		Reserved I/O memory addresses should never be written.
		Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI
		and SBI instructions will operate on all bits in the I/O Register, writing a one back into
		any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-
		isters $00 to $1F only.
		The I/O and Peripherals Control Registers are explained in later sections.

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External Memory

Interface

Overview

With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are:

•Four Different Wait State Settings (Including No wait State)

•Independent Wait State Setting for Different External Memory Sectors (Configurable Sector Size)

•The Number of Bits Dedicated to Address High Byte is Selectable

•Bus Keepers on Data Lines to Minimize Current Consumption (Optional)

When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated external memory pins (see Figure 1 on page 2, Table 26 on page 65, Table 32 on page 69, and Table 38 on page 73). The memory configuration is shown in Figure 11.

Figure 11. External Memory with Sector Select

0x0000

Internal Memory

0x25F

0x260

Lower Sector

SRW01

SRW00

SRL[2..0]

	External Memory	Upper Sector
	(0-64K x 8)

SRW11

SRW10

0xFFFF

Using the External Memory

Interface

The interface consists of:

•AD7:0: Multiplexed low-order address bus and data bus

•A15:8: High-order address bus (configurable number of bits)

•ALE: Address latch enable

•RD: Read strobe

•WR: Write strobe

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ATmega8515(L)

The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR.

When the XMEM interface is enabled, it will override the settings in the data direction registers corresponding to the ports dedicated to the interface. For details about this port override, see the alternate functions in section “I/O Ports” on page 58. The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Figure 13 (this figure shows the wave forms without wait states). When ALE goes from high to low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an internal access will cause activity on address-, data-, and ALE ports, but the RD and WR strobes will not toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal latch (typically “74x573” or equivalent) which is transparent when G is high.

Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the typical old style 74HC series latch becomes inadequate. The external memory interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are:

•D to Q propagation delay (tpd)

•Data setup time before G low (tsu)

•Data (address) hold time after G low (th)

The external memory interface is designed to guaranty minimum address hold time after

G is asserted low of th = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 98 to Table 105 on page 202). The D to Q propagation delay (tpd) must be taken into consideration when calculat-

ing the access time requirement of the external component. The data setup time before

G low (tsu) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

			D[7:0]
AD7:0	D	Q	A[7:0]
ALE	G		SRAM
AVR
A15:8			A[15:8]
RD			RD
WR			WR

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Pull-up and Bus Keeper
	The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port
	Register is written to one. To reduce power consumption in sleep mode, it is recom-
	mended to disable the pull-ups by writing the Port Register to zero before entering
	sleep.
	The XMEM interface also provides a bus keeper on the AD7:0 lines. The bus keeper
	can be disabled and enabled in software as described in “Special Function IO Register –
	SFIOR” on page 30. When enabled, the bus keeper will keep the previous value on the
	AD7:0 bus while these lines are tri-stated by the XMEM interface.
Timing	External memory devices have various timing requirements. To meet these require-
	ments, the ATmega8515 XMEM interface provides four different wait states as shown in
	Table 3. It is important to consider the timing specification of the external memory
	device before selecting the wait state. The most important parameters are the access
	time for the external memory in conjunction with the set-up requirement of the
	ATmega8515. The access time for the external memory is defined to be the time from
	receiving the chip select/address until the data of this address actually is driven on the
	bus. The access time cannot exceed the time from the ALE pulse is asserted low until
	data must be stable during a read sequence (tLLRL+ tRLRH - tDVRH in Table 98 to Table
	105 on page 202). The different wait states are set up in software. As an additional fea-
	ture, it is possible to divide the external memory space in two sectors with individual wait
	state settings. This makes it possible to connect two different memory devices with dif-
	ferent timing requirements to the same XMEM interface. For XMEM interface timing
	details, please refer to Figure 89 to Figure 92, and Table 98 to Table 105.
	Note that the XMEM interface is asynchronous and that the waveforms in the figures
	below are related to the internal system clock. The skew between the Internal and Exter-
	nal clock (XTAL1) is not guaranteed (it varies between devices, temperature, and supply
	voltage). Consequently, the XMEM interface is not suited for synchronous operation.
	Figure 13. External Data Memory Cycles without Wait State (SRWn1 = 0 and
	SRWn0 = 0)(1)
		T1			T2	T3	T4

System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data

Write

Read

RD

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector)

The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

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ATmega8515(L)

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

	T1	T2	T3	T4	T5
System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data
RD

Write

Read

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector)

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)

	T1	T2	T3	T4	T5	T6
System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data

Write

Read

RD

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector)

The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).

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XMEM Register

Description

MCU Control Register –

MCUCR

Extended MCU Control

Register – EMCUCR

Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)

	T1	T2	T3	T4	T5	T6	T7
System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data				Write
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data				Read
RD

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector)

The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external).

Bit	7	6	5	4	3	2	1	0
	SRE	SRW10	SE	SM1	ISC11	ISC10	ISC01	ISC00	MCUCR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective Data Direction Registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detailed description, see common description for the SRWn bits below (EMCUCR description).

Bit	7	6	5	4	3	2	1	0
	SM0	SRL2	SRL1	SRL0	SRW01	SRW00	SRW11	ISC2	EMCUCR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit

It is possible to configure different wait states for different external memory addresses. The External Memory address space can be divided in two sectors that have separate wait state bits. The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire External Memory address space is treated as one sector. When the entire

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SRAM address space is configured as one sector, the wait states are configured by the

SRW11 and SRW10 bits.

Table 2. Sector Limits with Different Settings of SRL2..0

	SRL2	SRL1	SRL0	Sector Limits
	0	0	0	Lower sector = N/A
				Upper sector = 0x0260 - 0xFFFF
	0	0	1	Lower sector = 0x0260 - 0x1FFF
				Upper sector = 0x2000 - 0xFFFF
	0	1	0	Lower sector = 0x0260 - 0x3FFF
				Upper sector = 0x4000 - 0xFFFF
	0	1	1	Lower sector = 0x0260 - 0x5FFF
				Upper sector = 0x6000 - 0xFFFF
	1	0	0	Lower sector = 0x0260 - 0x7FFF
				Upper sector = 0x8000 - 0xFFFF
	1	0	1	Lower sector = 0x0260 - 0x9FFF
				Upper sector = 0xA000 - 0xFFFF
	1	1	0	Lower sector = 0x0260 - 0xBFFF
				Upper sector = 0xC000 - 0xFFFF
	1	1	1	Lower sector = 0x0260 - 0xDFFF
				Upper sector = 0xE000 - 0xFFFF

•Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait states for the upper sector of the External Memory address space, see Table 3.

• Bit 3..2 – SRW01, SRW00: Wait State Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait states for the lower sector of the External Memory address space, see Table 3.

Table 3. Wait States(1)

	SRWn1	SRWn0	Wait States
	0	0	No wait states.
	0	1	Wait one cycle during read/write strobe.
	1	0	Wait two cycles during read/write strobe.
	1	1	Wait two cycles during read/write and wait one cycle before driving out
			new address.
	Note: 1.	n = 0 or 1 (lower/upper sector).
		For further details of the timing and wait states of the External Memory Interface, see
		Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.

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Special Function IO Register –

SFIOR

Bit	7	6		5			4	3	2	1	0
	–	XMBK		XMM2			XMM1	XMM0	PUD	–	PSR10	SFIOR
Read/Write	R/W	R/W			R/W		R/W	R/W	R/W	R/W	R/W
Initial Value	0	0		0			0	0	0	0	0

• Bit 6 – XMBK: External Memory Bus Keeper Enable

Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the Bus Keepers are still activated as long as XMBK is one.

• Bit 5..3 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are used for the high address byte by default. If the full 64,928 bytes address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in “Using all 64KB Locations of External Memory” on page 32, it is possible to use the XMMn bits to access all 64KB locations of the External Memory.

Table 4. Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2	XMM1	XMM0	# Bits for External Memory Address	Released Port Pins
0	0	0	8 (Full 64,928 Bytes Space)	None
0	0	1	7	PC7
0	1	0	6	PC7 - PC6
0	1	1	5	PC7 - PC5
1	0	0	4	PC7 - PC4
1	0	1	3	PC7 - PC3
1	1	0	2	PC7 - PC2
1	1	1	No Address High bits	Full Port C

Using all Locations of External Memory Smaller than 64 KB

Since the external memory is mapped after the internal memory as shown in Figure 11, the external memory is not addressed when addressing the first 608 bytes of data space. It may appear that the first 608 bytes of the external memory are inaccessible (external memory addresses 0x0000 to 0x025F). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed simply by addressing from address 0x8000 to 0x825F. Since the External Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x825F will appear as addresses 0x0000 to 0x025F for the external memory. Addressing above address 0x825F is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x0260 to 0x825F. This is illustrated in Figure 17.

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