ATMEL ATmega325, ATmega325V, ATmega3250, ATmega3250V, ATmega645 User Manual

BDTIC www.bdtic.com/ATMEL

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

–130 Powerful Instructions – Most Single Clock Cycle Execution

–32 x 8 General Purpose Working Registers

–Fully Static Operation

–Up to 16 MIPS Throughput at 16 MHz

–On-Chip 2-cycle Multiplier

•High Endurance Non-volatile Memory Segments

–In-System Self-programmable Flash Program Memory

•32K Bytes (ATmega325/ATmega3250)

•64K Bytes (ATmega645/ATmega6450)

–EEPROM

•1K bytes (ATmega325/ATmega3250)

•2K bytes (ATmega645/ATmega6450)

–Internal SRAM

•2K bytes (ATmega325/ATmega3250)

•4K bytes (ATmega645/ATmega6450)

–Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

–Data retention: 20 years at 85°C/100 years at 25°C(1)

–Optional Boot Code Section with Independent Lock Bits

•In-System Programming by On-chip Boot Program

•True Read-While-Write Operation

–Programming Lock for Software Security

•JTAG (IEEE std. 1149.1 compliant) Interface

–Boundary-scan Capabilities According to the JTAG Standard

–Extensive On-chip Debug Support

–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

–Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

–Real Time Counter with Separate Oscillator

–Four PWM Channels

–8-channel, 10-bit ADC

–Programmable Serial USART

–Master/Slave SPI Serial Interface

–Universal Serial Interface with Start Condition Detector

–Programmable Watchdog Timer with Separate On-chip Oscillator

–On-chip Analog Comparator

–Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

–Power-on Reset and Programmable Brown-out Detection

–Internal Calibrated Oscillator

–External and Internal Interrupt Sources

–Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby

•I/O and Packages

–53/68 Programmable I/O Lines

–64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

•Speed Grade:

–ATmega325V/ATmega3250V/ATmega645V/ATmega6450V:

•0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

–ATmega325/3250/645/6450:

•0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

•Temperature range:

–-40°C to 85°C Industrial

•Ultra-Low Power Consumption

–Active Mode:

1 MHz, 1.8V: 350 µA

32 kHz, 1.8V: 20 µA (including Oscillator)

– Power-down Mode:

100 nA at 1.8V

8-bit

Microcontroller with In-System Programmable Flash

ATmega325/V

ATmega3250/V

ATmega645/V

ATmega6450/V

Preliminary

Summary

1. Pin Configurations

Figure 1-1.	Pinout ATmega3250/6450
						AVCC		AGND		AREF		PF0 (ADC0)		PF1(ADC1)	PF2 (ADC2)	PF3 (ADC3)		PF4 (ADC4/TCK)		PF5 (ADC5/TMS)		PF6 (ADC6/TDO)		PF7 (ADC7/TDI)		DNC		DNC		PH7 (PCINT23)		PH6 (PCINT22)		PH5 (PCINT21)		PH4 (PCINT20)		DNC		DNC		GND		VCC		DNC		PA0		PA1		PA2
						100		99		98		97		96	95	94		93		92		91		90		89		88		87		86		85		84		83		82		81		80		79		78		77		76
			DNC	1
(RXD/PCINT0) PE0				2
													INDEX CORNER
	(TXD/PCINT1) PE1			3
(XCK/AIN0/PCINT2) PE2				4
(AIN1/PCINT3) PE3				5
(USCK/SCL/PCINT4) PE4				6
(DI/SDA/PCINT5) PE5				7
	(DO/PCINT6) PE6			8
(CLKO/PCINT7) PE7				9
			VCC	10
			GND	11
			DNC	12
																							ATmega3250/6450
	(PCINT24) PJ0			13
	(PCINT25) PJ1			14
			DNC	15
			DNC	16
			DNC	17
			DNC	18
	(SS/PCINT8) PB0			19
	(SCK/PCINT9) PB1			20
(MOSI/PCINT10) PB2				21
(MISO/PCINT11) PB3				22
(OC0A/PCINT12) PB4				23
(OC1A/PCINT13) PB5				24
(OC1B/PCINT14) PB6				25
						26		27		28		29		30	31	32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50
						(OC2A/PCINT15) PB7		DNC		(T1) PG3		(T0) PG4		RESET/PG5	VCC	GND		XTAL2 (TOSC2)		XTAL1 (TOSC1)		DNC		DNC		(PCINT26) PJ2		(PCINT27) PJ3		(PCINT28) PJ4		(PCINT29) PJ5		(PCINT30) PJ6		DNC		(ICP1) PD0		(INT0) PD1		PD2		PD3		PD4		PD5		PD6		PD7

75		PA3
74		PA4
73		PA5
72		PA6
71		PA7
70		PG2
69		PC7
68		PC6
67		DNC
66		PH3 (PCINT19)
65		PH2 (PCINT18)
64		PH1 (PCINT17)
63		PH0 (PCINT16)
62		DNC
61		DNC
60		DNC
59		DNC
58		PC5
57		PC4
56		PC3
55		PC2
54		PC1
53		PC0
52		PG1
51		PG0

2 ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

Figure 1-2. Pinout ATmega325/645

DNC
	1
(RXD/PCINT0) PE0
	2
(TXD/PCINT1) PE1
	3
(XCK/AIN0/PCINT2) PE2
	4
(AIN1/PCINT3) PE3
	5
(USCK/SCL/PCINT4) PE4
	6
(DI/SDA/PCINT5) PE5
	7
(DO/PCINT6) PE6
	8
(CLKO/PCINT7) PE7
	9
(SS/PCINT8) PB0
	10
(SCK/PCINT9) PB1
	11
(MOSI/PCINT10) PB2
	12
(MISO/PCINT11) PB3
	13
(OC0A/PCINT12) PB4
	14
(OC1A/PCINT13) PB5
	15
(OC1B/PCINT14) PB6
	16

AVCC		GND		AREF		PF0 (ADC0)		PF1 (ADC1)		PF2 (ADC2)		PF3 (ADC3)		PF4 (ADC4/TCK)		PF5 (ADC5/TMS)		PF6 (ADC6/TDO)		PF7 (ADC7/TDI)		GND		VCC		PA0		PA1		PA2
64		63		62		61		60		59		58		57		56		55		54		53		52		51		50		49

INDEX CORNER

ATmega325/645

17		18		19		20			21		22		23		24		25		26		27		28		29		30		31		32
(OC2A/PCINT15) PB7		(T1) PG3		(T0) PG4			RESET/PG5		VCC		GND		XTAL2 (TOSC2)		XTAL1 (TOSC1)		(ICP1) PD0		PD1 (INT0)		PD2		PD3		PD4		PD5		PD6		PD7

48 PA3

47 PA4

46 PA5

45 PA6

44 PA7

43 PG2

42 PC7

41 PC6

40 PC5

39 PC4

38 PC3

37 PC2

36 PC1

35 PC0

34 PG1

33 PG0

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

2. Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

3. Overview

The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

3

2570LS–AVR–08/07

3.1Block Diagram

Figure 3-1. Block Diagram

	PF0 - PF7
GND	VCC
	PORTF DRIVERS
	DATA REGISTER	DATA DIR.
	PORTF	REG. PORTF

AVCC

PA0 - PA7

PC0 - PC7

PORTA DRIVERS

PORTC DRIVERS

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

PORTA

REG. PORTA

PORTC

REG. PORTC

8-BIT DATA BUS

XTAL1			XTAL2

AGND

ADC

INTERNAL

CALIB. OSC

AREF

OSCILLATOR

OSCILLATOR

JTAG TAP

PROGRAM

STACK

WATCHDOG

COUNTER

POINTER

TIMER

TIMING AND

PH7-

DRIVERS

DIR.DATA

PORTHREG.

BOUNDARY-

CONTROL

ON-CHIP DEBUG

PROGRAM

SRAM

MCU CONTROL

FLASH

REGISTER

PH0

PORTH

REGISTERDATA

PORTH

SCAN

INSTRUCTION

GENERAL

TIMER/

REGISTER

COUNTERS

PURPOSE

REGISTERS

PROGRAMMING

X

INSTRUCTION

Y

INTERRUPT

LOGIC

DECODER

Z

UNIT

DRIVERS

DIR.DATA

PORTJREG.

PJ6-

CONTROL

ALU

EEPROM

RESET

LINES

STATUS

AVR CPU

REGISTER

REGISTERDATA

ANALOG COMPARATOR

PJ0

PORTJ

PORTJ

+ -

USART

UNIVERSAL

SPI

SERIAL INTERFACE

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

DATA REG.

DATA DIR.

PORTE

REG. PORTE

PORTB

REG. PORTB

PORTD

REG. PORTD

PORTG

REG. PORTG

PORTE DRIVERS

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

4 ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer will continue to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega325/3250/645/6450 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

3.2Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450

The ATmega325, ATmega3250, ATmega645, and ATmega6450 differs only in memory sizes, pin count and pinout. Table 3-1 on page 5 summarizes the different configurations for the four devices.

Table 3-1.	Configuration Summary
					General Purpose
Device		Flash	EEPROM	RAM	I/O Pins
ATmega325		32K bytes	1K bytes	2K bytes	54
ATmega3250		32K bytes	1K bytes	2K bytes	69
ATmega645		64K bytes	2K bytes	4K bytes	54
ATmega6450		64K bytes	2K bytes	4K bytes	69

3.3Pin Descriptions

The following section describes the I/O-pin special functions.

5

2570LS–AVR–08/07

3.3.1VCC

Digital supply voltage.

3.3.2GND

Ground.

3.3.3Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

3.3.4Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 67.

3.3.5Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

3.3.6Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 70.

3.3.7Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 71.

6 ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

3.3.8Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

3.3.9Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the ATmega325/3250/645/6450 as listed on page 71.

3.3.10Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250/6450 as listed on page 71.

3.3.11Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3250/6450 as listed on page 71.

3.3.12RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page 300. Shorter pulses are not guaranteed to generate a reset.

3.3.13XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

7

2570LS–AVR–08/07

3.3.14XTAL2

Output from the inverting Oscillator amplifier.

3.3.15AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

3.3.16AREF

This is the analog reference pin for the A/D Converter.

4. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

8 ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

6.	Register Summary
			Note:		Registers with bold type only available in ATmega3250/6450.
Address		Name	Bit 7		Bit 6	Bit 5	Bit 4	Bit 3	Bit 2		Bit 1	Bit 0	Page
	(0xFF)	Reserved	-		-	-	-	-	-		-	-
	(0xFE)	Reserved	-		-	-	-	-	-		-	-
	(0xFD)	Reserved	-		-	-	-	-	-		-	-
	(0xFC)	Reserved	-		-	-	-	-	-		-	-
	(0xFB)	Reserved	-		-	-	-	-	-		-	-
	(0xFA)	Reserved	-		-	-	-	-	-		-	-
	(0xF9)	Reserved	-		-	-	-	-	-		-	-
	(0xF8)	Reserved	-		-	-	-	-	-		-	-
	(0xF7)	Reserved	-		-	-	-	-	-		-	-
	(0xF6)	Reserved	-		-	-	-	-	-		-	-
	(0xF5)	Reserved	-		-	-	-	-	-		-	-
	(0xF4)	Reserved	-		-	-	-	-	-		-	-
	(0xF3)	Reserved	-		-	-	-	-	-		-	-
	(0xF2)	Reserved	-		-	-	-	-	-		-	-
	(0xF1)	Reserved	-		-	-	-	-	-		-	-
	(0xF0)	Reserved	-		-	-	-	-	-		-	-
	(0xEF)	Reserved	-		-	-	-	-	-		-	-
	(0xEE)	Reserved	-		-	-	-	-	-		-	-
	(0xED)	Reserved	-		-	-	-	-	-		-	-
	(0xEC)	Reserved	-		-	-	-	-	-		-	-
	(0xEB)	Reserved	-		-	-	-	-	-		-	-
	(0xEA)	Reserved	-		-	-	-	-	-		-	-
	(0xE9)	Reserved	-		-	-	-	-	-		-	-
	(0xE8)	Reserved	-		-	-	-	-	-		-	-
	(0xE7)	Reserved	-		-	-	-	-	-		-	-
	(0xE6)	Reserved	-		-	-	-	-	-		-	-
	(0xE5)	Reserved	-		-	-	-	-	-		-	-
	(0xE4)	Reserved	-		-	-	-	-	-		-	-
	(0xE3)	Reserved	-		-	-	-	-	-		-	-
	(0xE2)	Reserved	-		-	-	-	-	-		-	-
	(0xE1)	Reserved	-		-	-	-	-	-		-	-
	(0xE0)	Reserved	-		-	-	-	-	-		-	-
	(0xDF)	Reserved	-		-	-	-	-	-		-	-
	(0xDE)	Reserved	-		-	-	-	-	-		-	-
	(0xDD)	PORTJ	-		PORTJ6	PORTJ5	PORTJ4	PORTJ3	PORTJ2		PORTJ1	PORTJ0	83
	(0xDC)	DDRJ	-		DDJ6	DDJ5	DDJ4	DDJ3	DDJ2		DDJ1	DDJ0	83
	(0xDB)	PINJ	-		PINJ6	PINJ5	PINJ4	PINJ3	PINJ2		PINJ1	PINJ0	83
	(0xDA)	PORTH	PORTH7		PORTH6	PORTH5	PORTH4	PORTH3	PORTH2		PORTH1	PORTH0	83
	(0xD9)	DDRH	DDH7		DDH6	DDH5	DDH4	DDH3	DDH2		DDH1	DDH0	83
	(0xD8)	PINH	PINH7		PINH6	PINH5	PINH4	PINH3	PINH2		PINH1	PINH0	83
	(0xD7)	Reserved	-		-	-	-	-	-		-	-
	(0xD6)	Reserved	-		-	-	-	-	-		-	-
	(0xD5)	Reserved	-		-	-	-	-	-		-	-
	(0xD4)	Reserved	-		-	-	-	-	-		-	-
	(0xD3)	Reserved	-		-	-	-	-	-		-	-
	(0xD2)	Reserved	-		-	-	-	-	-		-	-
	(0xD1)	Reserved	-		-	-	-	-	-		-	-
	(0xD0)	Reserved	-		-	-	-	-	-		-	-
	(0xCF)	Reserved	-		-	-	-	-	-		-	-
	(0xCE)	Reserved	-		-	-	-	-	-		-	-
	(0xCD)	Reserved	-		-	-	-	-	-		-	-
	(0xCC)	Reserved	-		-	-	-	-	-		-	-
	(0xCB)	Reserved	-		-	-	-	-	-		-	-
	(0xCA)	Reserved	-		-	-	-	-	-		-	-
	(0xC9)	Reserved	-		-	-	-	-	-		-	-
	(0xC8)	Reserved	-		-	-	-	-	-		-	-
	(0xC7)	Reserved	-		-	-	-	-	-		-	-
	(0xC6)	UDR0					USART0 Data Register						178
	(0xC5)	UBRR0H							USART0 Baud Rate Register High				183
	(0xC4)	UBRR0L					USART0 Baud Rate Register Low						183

9

2570LS–AVR–08/07