ATMEL ATmega2560 User Manual

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Features

• High Performance, Low Power AVR

8-Bit Microcontroller

• Advanced RISC Architecture

– 135 Powe rful Instructions – Most Single Clock Cy cle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– 64K/128K/256K Bytes of In-System Self-Programmable Flash

– 4K Bytes EEPROM

– 8K Bytes Internal SRAM

– Write/Erase Cycles:10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

Endurance: Up to 64K Bytes Optional External Memory Space

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode

– Real Time Counter with Separate Oscillator

– Four 8-bit PWM Channels

– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits

(ATmega1281/2561, ATmega640/1280/2560)

– Output Compare Modulator

– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)

– Two/Four Programmable Serial USART (ATmega1281/2561,ATmega640/1280/2560)

– Master/Slave SPI Serial Interface

– Byte Oriented 2-wire Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Pr ogrammab l e Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Redu ction, Power-save, Power-down, Standby,

and Extended Standby

• I/O and Pac kages

– 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)

– 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)

– 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)

– RoHS/Fully Green

• Temperature Range:

–-40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode: 1 MHz, 1.8V: 500 µA

– Power-down Mode: 0.1 µA at 1.8V

• Speed Grade:

– ATmega640V/ATmega1280V/ATmega1281V:

0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega2560V/ATmega2561V:

0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega640/ATmega1280/A Tmega1281:

0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

– ATmega2560/ATmega2561:

0 - 16 MHz @ 4.5 - 5.5V

8-bit

Microcontroller

with

64K/128K/256K

Bytes In-System

Programmable

Flash

ATmega640/V

ATmega1280/V

ATmega1281/V

ATmega2560/V

ATmega2561/V

Preliminary

Summary

BDTIC www.bdtic.com/ATMEL

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

1. Pin Configurations

Figure 1-1. TQFP-pinout ATmega640/1280/2560

GND

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PG2 (ALE)

AVCC

GND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

26 28 29 3127 3630 32 35 3733 34 38 39 40 41 42 43 44 45 46 47 48 49 50

PK0 (ADC8/PCINT16)

PK1 (ADC9/PCINT17)

PK2 (ADC10/PCINT18)

PK3 (ADC11/PCINT19)

PK4 (ADC12/PCINT20)

PK5 (ADC13/PCINT21)

PK6 (ADC14/PCINT22)

PK7 (ADC15/PC

INT23)

(OC2B) PH6

(TOSC2) PG3

(TOSC1) PG4

RESET

(T4) PH7

(ICP4) PL0

VCC

GND

XTAL2

XTAL1

PL6

PL7

GND

VCC

(OC0B) PG5

VCC

GND

(RXD2) PH0

(TXD2) PH1

(XCK2) PH2

(OC4A) PH3

(OC4B) PH4

(OC4C) PH5

(RXD0/PCINT8) PE0

(TXD0) PE1

(XCK0/AIN0) PE2

(OC3A/AIN1) PE3

(OC3B/INT4) PE4

(OC3C/INT5) PE5

(T3/INT6) PE6

(CLKO/ICP3/INT7) PE7

(SS/PCINT0) PB0

(SCK/PCINT1) PB1

(MOSI/PCINT2) PB2

(MISO/PCINT3) PB3

(OC2A/PCINT4) PB4

(OC1A/PCINT5) PB5

(OC1B/PCINT6) PB6

(OC0A/OC1C/PCINT7) PB7

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PG1 (RD)

PG0 (WR)

(TXD1/INT3) PD3

(ICP1) PD4

(XCK1) PD5

(T1) PD6

(T0) PD7

(SCL/INT0) PD0

(SDA/INT1) PD1

(RXD1/INT2) PD2

(ICP5) PL1

(T5) PL2

(OC5A) PL3

(OC5B) PL4

PJ6 (PCINT15)

PJ5 (PCINT14)

PJ4 (PCINT13)

PJ3 (PCINT12)

PJ2 (XCK3/PCINT11)

PJ1 (TXD3/PCINT10)

PJ0 (RXD3/PCINT9)

PJ7

(OC5C) PL5

INDEX CORNER

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

Figure 1-2. CBGA-pinout ATmega640/1280/2560

Table 1-1. CBGA-pinout ATmega640/1280/2560.

1 2 3 4 5 678910

A GND AREF PF0 PF2 PF5 PK0 PK3 PK6 GND VCC

B AVCC PG5 PF1 PF3 PF6 PK1 PK4 PK7 PA0 PA2

C PE2 PE0 PE1 PF4 PF7 PK2 PK5 PJ7 PA1 PA3

D PE3 PE4 PE5 PE6 PH2 PA4 PA5 PA6 PA7 PG2

E PE7 PH0 PH1 PH3 PH5 PJ6 PJ5 PJ4 PJ3 PJ2

F VCC PH4 PH6 PB0 PL4 PD1 PJ1 PJ0 PC7 GND

G GND PB1 PB2 PB5 PL2 PD0 PD5 PC5 PC6 VCC

H PB3 PB4 RESET PL1 PL3 PL7 PD4 PC4 PC3 PC2

J PH7 PG3 PB6 PL0 XTAL2 PL6 PD3 PC1 PC0 PG1

K PB7 PG4 VCC GND XTAL1 PL5 PD2 PD6 PD7 PG0

1 2345678910

10987654321

Top view

Bottom view

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

Figure 1-3. Pinout ATmega1281/2561

Note: The large center pad underneath the QFN/MLF package is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If

the center pad is left unconnected, the package might loosen from the board.

1.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min. and Max val-

ues will be available after the device is characterized.

ATmega1281/2561

(RXD0/PCINT8/PDI) PE0

(TXD0/PDO) PE1

(XCK0/AIN0) PE2

(OC3A/AIN1) PE3

(OC3B/INT4) PE4

(OC3C/INT5) PE5

(T3/INT6) PE6

(ICP3/CLKO/INT7) PE7

(SS/PCINT0) PB0

(OC0B) PG5

(SCK/ PCINT1) PB1

(MOSI/ PCINT2) PB2

(MISO/ PCINT3) PB3

(OC2A/ PCINT4) PB4

(OC1A/PCINT5) PB5

(OC1B/PCINT6) PB6

(OC0A/OC1C/

PCINT7

) PB7

(TOSC2) PG3

(TOSC1) PG4

RESET

VCC

GND

XTAL2

XTAL1

(SCL/INT0) PD0

(SDA/INT1) PD1

(RXD1/INT2) PD2

(TXD1/INT3) PD3

(ICP1) PD4

(XCK1) PD5

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PG2 (ALE)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PG1 (RD)

PG0 (WR)

AVCC

GND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

GND

VCC

PA0 (AD0)

PA 1

(AD1)

PA 2

(AD2)

(T1) PD6

(T0) PD7

INDEX CORNER

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

2. Overview

The ATmega640/1280/1281/2560/2561 is a lo w-power CMOS 8-bit microcontrol ler based on the

AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega640/1280/1281/2560/2561 achieves t hroughputs appr oaching 1 MIPS per MHz allowing

the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

CPU

GND

VCC

RESET

Power

Supervision

POR / BOD &

RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

XTAL1

XTAL2

PC7..0 PORT C (8)

PA7..0

PORT A (8)

PORT D (8)

PD7..0

PORT B (8)

PB7..0

PORT E (8)

PE7..0

PORT F (8)

PF7..0

PORT J (8)

PJ7..0

PG5..0 PORT G (6)

PORT H (8)

PH7..0

PORT K (8)

PK7..0

PORT L (8)

PL7..0

XRAM

TWI SPI

EEPROM

JTAG

8bit T/C 0 8bit T/C 2

16bit T/C 1

16bit T/C 3

SRAMFLASH

16bit T/C 4

16bit T/C 5

USART 2

USART 1

USART 0

Internal

Bandgap reference

Analog

Comparator

A/D

Converter

USART 3

NOTE:

Shaded parts only available

in the 100-pin version.

Complete functionality for

the ADC, T/C4, and T/C5 only

available in the 100-pin version.

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega640/1280/1281/2560/2561 provides the following features: 64K/ 128K/256K bytes of

In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 8K

bytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time

Counter (RTC), six flexible Timer/Counters with compare modes and PWM, 4 USARTs, a byte

oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage

with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial

port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip

Debug system and programming and six software selectable power saving modes. The Idle

mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system

to continue functioning. The Power-down mode saves the register contents but freezes the

Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-

save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base

while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all

I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC

conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the

device is sleeping. This allows very fast start-up combined with low power consumption. In

Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly

flexible and cost effective solution to many embedded control applications.

The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and sys-

tem development tools including: C compilers, macro assemblers, program

debugger/simulators, in-circuit emulators, and evaluation kits.

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560

Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and

number of pins. Table 2-1 summarizes the different configurations for the six devices.

2.3 Pin Descriptions

2.3.1 VCC

Digital supply voltage.

2.3.2 GND

Ground.

2.3.3 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the

ATmega640/1280/1281/2560/2561 as listed on page 78.

2.3.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the

ATmega640/1280/1281/2560/2561 as listed on page 79.

2.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

Table 2-1. Configuration Summary

Device Flash EEPROM RAM

General

Purpose I/O pins

16 bits resolution

PWM channels

Serial

USARTs

ADC

Channels

ATmega640 64KB 4KB 8KB 86 12 4 16

ATmega1280 128KB 4KB 8KB 86 12 4 16

ATmega1281 128KB 4KB 8KB 54 6 2 8

ATmega2560 256KB 4KB 8KB 86 12 4 16

ATmega2561 256KB 4KB 8KB 54 6 2 8

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as

listed on page 82.

2.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the

ATmega640/1280/1281/2560/2561 as listed on page 83.

2.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the

ATmega640/1280/1281/2560/2561 as listed on page 86.

2.3.8 Port F (PF7..PF0)

Port F serves as analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.3.9 Port G (PG5..PG0)

Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output

buffers have symmetrical drive characteristics with both high sink and source capability. As

inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are

activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Port G also serves the functions of various special features of the

ATmega640/1280/1281/2560/2561 as listed on page 90.

2.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port H output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port H also serves the functions of various special features of the ATmega640/1280/2560 as

listed on page 92.

2.3.11 Port J (PJ7..PJ0)

Port J is a 8-bit bi-directional I/O port with internal pull-up re sistors (selected for each bit). The

Port J output buffers have symmetrical drive characteristics with both high sink and source capa-

bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port J also serves the functions of various special features of the ATmega640/1280/2560 as

listed on page 95.

2.3.12 Port K (PK7..PK0)

Port K serves as analog inputs to the A/D Converter.

Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port K output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port K pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Port K also serves the functions of various special features of the ATmega640/1280/2560 as

listed on page 96.

2.3.13 Port L (PL7..PL0)

Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port L output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port L pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port L also serves the functions of various special features of the ATmega 640/1280/2560 as

listed on page 98.

2.3.14 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in “System and Reset

Characteristics” on page 375. Shorter pulses are not guaranteed to generate a reset.

2.3.15 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.3.16 XTAL2

Output from the inverting Oscillator amplifier.

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

2.3.17 AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

2.3.18 AREF

This is the analog reference pin for the A/D Converter.

3. Resources

A comprehensive set of development tools and application notes, and datasheets are available

for download on http://www.atmel.com/avr.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

5. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0x1FF) Reserved - - - - - - - -

... Reserved - - - - - - - -

(0x13F) Reserved

(0x13E) Reserved

(0x13D) Reserved

(0x13C) Reserved

(0x13B) Reserved

(0x13A) Reserved

(0x139) Reserved

(0x138) Reserved

(0x137) Reserved

(0x136) UDR3 USART3 I/O Data Register page 223

(0x135) UBRR3H - - - - USART3 Baud Rate Register High Byte page 227

(0x134) UBRR3L USART3 Baud Rate Register Low Byte page 227

(0x133) Reserved - - - - - - - -

(0x132) UCSR3C UMSEL31 UMSEL30 UPM31 UPM30 USBS3 UCSZ31 UCSZ30 UCPOL3 page 239

(0x131) UCSR3B RXCIE3 TXCIE3 UDRIE3 RXEN3 TXEN3 UCSZ32 RXB83 TXB83 page 238

(0x130) UCSR3A RXC3 TXC3 UDRE3 FE3 DOR3 UPE3 U2X3 MPCM3 page 238

(0x12F) Reserved - - - - - - - -

(0x12E) Reserved - - - - - - - -

(0x12D) OCR5CH Timer/Counter5 - Output Compare Register C High Byte page 166

(0x12C) OCR5CL Timer /Counter5 - Output Compare Register C Low Byte page 166

(0x12B) OCR5BH Timer/Counter5 - Output Compare Register B High Byte page 166

(0x12A) OCR5BL Timer/Counter5 - Output Compare Register B Low Byte page 166

(0x129) OCR5AH Timer/Counter5 - Output Compare Register A High Byte page 166

(0x128) OCR5AL Timer/Counter5 - Output Compare Register A Low Byte page 166

(0x127) ICR5H Timer/Counter5 - Input Capture Register High Byte page 167

(0x126) ICR5L Timer/Counter5 - Input Capture Register Low Byte page 167

(0x125) TCNT5H Timer/Counter5 - Counter Register High Byte page 163

(0x124) TCNT5L Timer/Counter5 - Counter Regi st e r Lo w By te page 163

(0x123) Reserved - - - - - - - -

(0x122) TCCR5C FOC5A FOC5B FOC5C - - - - - page 162

(0x121) TCCR5B ICNC5 ICES5 - WGM53 WGM52 CS52 CS51 CS50 page 161

(0x120) TCCR5A COM5A1 COM5A0 COM5B1 COM5B0 COM5C1 COM5C0 WGM51 WGM50 page 158

(0x11F) Reserved - - - - - - - -

(0x11E) Reserved - - - - - - - -

(0x11D) Reserved - - - - - - - -

(0x11C) Reserved - - - - - - - -

(0x11B) Reserved - - - - - - - -

(0x11A) Reserved - - - - - - - -

(0x119) Reserved - - - - - - - -

(0x118) Reserved - - - - - - - -

(0x117) Reserved - - - - - - - -

(0x116) Reserved

- - - - - - - -

(0x115) Reserved

- - - - - - - -

(0x114) Reserved - - - - - - - -

(0x113) Reserved

- - - - - - - -

(0x112) Reserved

- - - - - - - -

(0x111) Reserved

- - - - - - - -

(0x110) Reserved - - - - - - - -

(0x10F) Reserved

- - - - - - - -

(0x10E) Reserved

- - - - - - - -

(0x10D) Reserved - - - - - - - -

(0x10C) Reserved

- - - - - - - -

(0x10B) PORTL PORTL7 PORTL6 PORTL5 PORTL4 PORTL3 PORTL2 PORTL1 PORTL0 page 104

(0x10A) DDRL DDL7 DDL6 DDL5 DDL4 DDL3 DDL2 DDL1 DDL0 page 104

(0x109) PINL PINL7 PINL6 PINL5 PINL4 PINL3 PINL2 PINL1 PINL0 page 104

(0x108) PORTK PORTK7 PORTK6 PORTK5 PORTK4 PORTK3 PORTK2 PORTK1 PORTK0 page 103

(0x107) DDRK DDK7 DDK6 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 page 103

(0x106) PINK PINK7 PINK6 PINK5 PINK4 PINK3 PINK2 PINK1 PINK0 page 104

(0x105) PORTJ PORTJ7 PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 page 103

(0x104) DDRJ DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 page 103

(0x103) PINJ PINJ7 PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 page 103

(0x102) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 page 10 3

(0x101) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 page 103

2549LS–AVR–08/07

ATmega640/1280/1281/2560/2561

(0x100) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 page 103

(0xFF) Reserved - - - - - - - -

(0xFE) Reserved - - - - - - - -

(0xFD) Reserved - - - - - - - -

(0xFC) Reserved - - - - - - - -

(0xFB) Reserved

- - - - - - - -

(0xFA) Reserved

- - - - - - - -

(0xF9) Reserved - - - - - - - -

(0xF8) Reserved - - - - - - - -

(0xF7) Reserved - - - - - - - -

(0xF6) Reserved - - - - - - - -

(0xF5) Reserved - - - - - - - -

(0xF4) Reserved - - - - - - - -

(0xF3) Reserved - - - - - - - -

(0xF2) Reserved - - - - - - - -

(0xF1) Reserved - - - - - - - -

(0xF0) Reserved - - - - - - - -

(0xEF) Reserved

- - - - - - - -

(0xEE) Reserved

- - - - - - - -

(0xED) Reserved - - - - - - - -

(0xEC) Reserved - - - - - - - -

(0xEB) Reserved - - - - - - -

(0xEA) Reserved - - - - - - - -

(0xE9) Reserved - - - - - - - -

(0xE8) Reserved - - - - - - - -

(0xE7) Reserved - - - - - - -

(0xE6) Reserved - - - - - - - -

(0xE5) Reserved - - - - - - - -

(0xE4) Reserved - - - - - - - -

(0xE3) Reserved - - - - - - -

(0xE2) Reserved - - - - - - - -

(0xE1) Reserved - - - - - - -

(0xE0) Reserved - - - - - - -

(0xDF) Reserved - - - - - - - -

(0xDE) Reserved - - - - - - - -

(0xDD) Reserved - - - - - - -

(0xDC) Reserved - - - - - - - -

(0xDB) Reserved - - - - - - - -

(0xDA) Reserved - - - - - - - -

(0xD9) Reserved - - - - - - -

(0xD8) Reserved - - - - - - - -

(0xD7) Reserved - - - - - - - -

(0xD6) UDR2 USART2 I/O Data Register page 223

(0xD5) UBRR2H - - - - USART2 Baud Rate Register High Byte page 227

(0xD4) UBRR2L USART2 Baud Rate Register Low Byte page 227

(0xD3) Reserved - - - - - - - -

(0xD2) UCSR2C UMSEL21 UMSEL20 UPM21 UPM20 USBS2 UCSZ21 UCSZ20 UCPOL2 page 239

(0xD1) UCSR2B RXCIE2 TXCIE2 UDRIE2 RXEN2 TXEN2 UCSZ22 RXB82 TXB82 page 238

(0xD0) UCSR2A RXC2 TXC2 UDRE2 FE2 DOR2 UPE2 U2X2 MPCM2 page 238

(0xCF) Reserved

- - - - - - - -

(0xCE) UDR1 USART1 I/O Data Register page 223

(0xCD) UBRR1H

- - - - USART1 Baud Rate Register High Byte page 227

(0xCC) UBRR1L USART1 Baud Rate Register Low Byte page 227

(0xCB) Reserved

- - - - - - - -

(0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 page 239

(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 page 238

(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 page 238

(0xC7) Reserved

- - - - - - - -

(0xC6) UDR0 USART0 I/O Data Register page 223

(0xC5) UBRR0H

- - - - USART0 Baud Rate Register High Byte page 227

(0xC4) UBRR0L USART0 Baud Rate Register Low Byte page 227

(0xC3) Reserved

- - - - - - - -

(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 page 239

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 page 238

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 page 238

(0xBF) Reserved

- - - - - - - -

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

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