ATMEL ATmega64, ATmega64L User Manual

Features

•High-performance, Low-power AVR® 8-bit Microcontroller

•Advanced RISC Architecture

–130 Powerful Instructions – Most Single Clock Cycle Execution

–32 x 8 General Purpose Working Registers + Peripheral Control Registers

–Fully Static Operation

–Up to 16 MIPS Throughput at 16 MHz

–On-chip 2-cycle Multiplier

•Non-volatile Program and Data Memories

–64K Bytes of In-System Reprogrammable Flash

Endurance: 10,000 Write/Erase Cycles

–Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation

–2K Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

–4K Bytes Internal SRAM

–Up to 64K Bytes Optional External Memory Space

–Programming Lock for Software Security

–SPI Interface for In-System Programming

•JTAG (IEEE std. 1149.1 Compliant) Interface

–Boundary-scan Capabilities According to the JTAG Standard

–Extensive On-chip Debug Support

–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

–Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode

–Real Time Counter with Separate Oscillator

–Two 8-bit PWM Channels

–6 PWM Channels with Programmable Resolution from 1 to 16 Bits

–8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain (1x, 10x, 200x)

–Byte-oriented Two-wire Serial Interface

–Dual Programmable Serial USARTs

–Master/Slave SPI Serial Interface

–Programmable Watchdog Timer with On-chip Oscillator

–On-chip Analog Comparator

•Special Microcontroller Features

–Power-on Reset and Programmable Brown-out Detection

–Internal Calibrated RC Oscillator

–External and Internal Interrupt Sources

–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby

–Software Selectable Clock Frequency

–ATmega103 Compatibility Mode Selected by a Fuse

–Global Pull-up Disable

•I/O and Packages

–53 Programmable I/O Lines

–64-lead TQFP and 64-pad MLF

•Operating Voltages

–2.7 - 5.5V for ATmega64L

–4.5 - 5.5V for ATmega64

•Speed Grades

–0 - 8 MHz for ATmega64L

–0 - 16 MHz for ATmega64

8-bit Microcontroller with 64K Bytes In-System Programmable Flash

ATmega64

ATmega64L

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Pin Configuration

Figure 1. Pinout ATmega64

TQFP/MLF

PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5

(T3/INT6) PE6 (ICP3/INT7) PE7

(SS) PB0

(SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4

(OC1A) PB5 (OC1B) PB6

AVCC

64 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 17

PB7(OC2/OC1C)

63 GND

TOSC2/PG3 18

AREF	PF0 (ADC0)	PF1 (ADC1)	PF2 (ADC2)	PF3 (ADC3)	PF4 (ADC4/TCK)	PF5 (ADC5/TMS)	PF6 (ADC6/TDO)	PF7 (ADC7/TDI)	GND	VCC	PA0 (AD0)	PA1 (AD1)
62	61	60	59	58	57	56	55	54	53	52	51	50

19	20		21	22	23	24	25	26	27	28	29	30	31
TOSC1/PG4		RESET	VCC	GND	XTAL2	XTAL1	(SCL/INT0) PD0	(SDA/INT1) PD1	(RXD1/INT2) PD2	(TXD1/INT3) PD3	(ICP1) PD4	(XCK1) PD5	(T1) PD6

PA2 (AD2)
49		PA3 (AD3)
48
47		PA4 (AD4)
46		PA5 (AD5)
45		PA6 (AD6)
44		PA7 (AD7)
43		PG2(ALE)
42		PC7 (A15)
41		PC6 (A14)
40		PC5 (A13)
39		PC4 (A12)
38		PC3 (A11)
37		PC2 (A10
36		PC1 (A9)
35		PC0 (A8)
34
		PG1(RD)
33
		PG0(WR)
32
(T2) PD7

Note: The bottom pad under the MLF package should be soldered to ground.

Disclaimer	Typical values contained in this data sheet are based on simulations and characteriza-
	tion of other AVR microcontrollers manufactured on the same process technology. Min
	and Max values will be available after the device is characterized.

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ATmega64(L)

Overview

The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC
GND
			PORTF DRIVERS		PORTA DRIVERS		PORTC DRIVERS
AVCC
		DATA REGISTER		DATA DIR.	DATA REGISTER	DATA DIR.	DATA REGISTER	DATA DIR.
			PORTF	REG. PORTF	PORTA	REG. PORTA	PORTC	REG. PORTC
									8-BIT DATA BUS
AGND										XTAL1
AREF							CALIB. OSC
						INTERNAL
				ADC
						OSCILLATOR
							OSCILLATOR			XTAL2
		JTAG TAP		PROGRAM	STACK	WATCHDOG
				COUNTER	POINTER	TIMER
							OSCILLATOR
	ON-CHIP DEBUG			PROGRAM	SRAM	MCU CONTROL	TIMING AND
				FLASH		REGISTER	CONTROL
										RESET
		BOUNDARY-		INSTRUCTION	GENERAL	TIMER/
		SCAN
				REGISTER		COUNTERS
					PURPOSE
					REGISTERS
PEN	PROGRAMMING			INSTRUCTION	X	INTERRUPT
					Y
		LOGIC
				DECODER	Z	UNIT
				CONTROL	ALU	EEPROM
				LINES
					STATUS
					REGISTER
			USART0			SPI	USART1	2-WIRE SERIAL
								INTERFACE
	ANALOG COMPARATOR	+ -		DATA DIR.	DATA REGISTER	DATA DIR.	DATA REGISTER	DATA DIR.	DATA REG. DATA DIR.
		DATA REGISTER
			PORTE	REG. PORTE	PORTB	REG. PORTB	PORTD	REG. PORTD	PORTG	REG. PORTG
			PORTE DRIVERS		PORTB DRIVERS		PORTD DRIVERS		PORTG DRIVERS
			PE0 - PE7		PB0 - PB7		PD0 - PD7		PG0 - PG4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

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ATmega103 and

ATmega64 Compatibility

The ATmega64 provides the following features: 64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.

The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.

The ATmega64 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir- cuit Emulators, and evaluation kits.

The ATmega64 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64. Most additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF (i.e., in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed.

The ATmega64 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current printed circuit boards. The application notes “Replacing ATmega103 by ATmega128” and “Migration between ATmega64 and ATmega128” describes what the user should be aware of replacing the ATmega103 by an ATmega128 or ATmega64.

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			ATmega64(L)
	ATmega103 Compatibility
		By programming the M103C Fuse, the ATmega64 will be compatible with the
	Mode	ATmega103 regards to RAM, I/O pins and Interrupt Vectors as described above. How-
		ever, some new features in ATmega64 are not available in this compatibility mode,
		these features are listed below:
		• One USART instead of two, asynchronous mode only. Only the eight least
		significant bits of the Baud Rate Register is available.
		• One 16 bits Timer/Counter with two compare registers instead of two 16 bits
		Timer/Counters with three compare registers.
		• Two-wire serial interface is not supported.
		• Port G serves alternate functions only (not a general I/O port).
		• Port F serves as digital input only in addition to analog input to the ADC.
		• Boot Loader capabilities is not supported.
		• It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
		• The External Memory Interface can not release any Address pins for general I/O,
		neither configure different wait states to different External Memory Address
		sections.
		• Only EXTRF and PORF exist in the MCUCSR Register.
		• No timed sequence is required for Watchdog Timeout change.
		• Only low-level external interrupts can be used on four of the eight External Interrupt
		sources.
		• Port C is output only.
		• USART has no FIFO buffer, so Data OverRun comes earlier.
		• The user must have set unused I/O bits to 0 in ATmega103 programs.
	Pin Descriptions
	VCC	Digital supply voltage.
	GND	Ground.
	Port A (PA7..PA0)	Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
		bit). The Port A output buffers have symmetrical drive characteristics with both high sink
		and source capability. As inputs, Port A pins that are externally pulled low will source
		current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
		condition becomes active, even if the clock is not running.
		Port A also serves the functions of various special features of the ATmega64 as listed
		on page 72.
	Port B (PB7..PB0)	Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
		bit). The Port B output buffers have symmetrical drive characteristics with both high sink
		and source capability. As inputs, Port B pins that are externally pulled low will source
		current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
		condition becomes active, even if the clock is not running.
		Port B also serves the functions of various special features of the ATmega64 as listed
		on page 73.

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Port C (PC7..PC0)
	Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
	bit). The Port C output buffers have symmetrical drive characteristics with both high sink
	and source capability. As inputs, Port C pins that are externally pulled low will source
	current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
	condition becomes active, even if the clock is not running.
	Port C also serves the functions of special features of the ATmega64 as listed on page
	76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not
	tri-stated when a reset condition becomes active.
Port D (PD7..PD0)	Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
	bit). The Port D output buffers have symmetrical drive characteristics with both high sink
	and source capability. As inputs, Port D pins that are externally pulled low will source
	current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
	condition becomes active, even if the clock is not running.
	Port D also serves the functions of various special features of the ATmega64 as listed
	on page 77.
Port E (PE7..PE0)	Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
	bit). The Port E output buffers have symmetrical drive characteristics with both high sink
	and source capability. As inputs, Port E pins that are externally pulled low will source
	current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
	condition becomes active, even if the clock is not running.
	Port E also serves the functions of various special features of the ATmega64 as listed
	on page 80.
Port F (PF7..PF0)	Port F serves as the analog inputs to the A/D Converter.
	Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
	Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
	buffers have symmetrical drive characteristics with both high sink and source capability.
	As inputs, Port F pins that are externally pulled low will source current if the pull-up
	resistors are activated. The Port F pins are tri-stated when a reset condition becomes
	active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-
	tors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.
	The TDO pin is tri-stated unless TAP states that shift out data are entered.
	Port F also serves the functions of the JTAG interface.
	In ATmega103 compatibility mode, Port F is an input port only.
Port G (PG4..PG0)	Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each
	bit). The Port G output buffers have symmetrical drive characteristics with both high sink
	and source capability. As inputs, Port G pins that are externally pulled low will source
	current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset
	condition becomes active, even if the clock is not running.
	Port G also serves the functions of various special features.
	In ATmega103 compatibility mode, these pins only serves as strobes signals to the
	external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to
	PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes
	active, even if the clock is not running. PG3 and PG4 are Oscillator pins.

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						ATmega64(L)
			Reset input. A low level on this pin for longer than the minimum pulse length will gener-
	RESET
			ate a reset, even if the clock is not running. The minimum pulse length is given in Table
			19 on page 51. Shorter pulses are not guaranteed to generate a reset.
	XTAL1		Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
	XTAL2		Output from the inverting Oscillator amplifier.
	AVCC		AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally
			connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
			nected to VCC through a low-pass filter.
	AREF		AREF is the analog reference pin for the A/D Converter.
	PEN		This is a programming enable pin for the SPI Serial Programming mode. By holding this
			pin low during a Power-on Reset, the device will enter the SPI Serial Programming
			mode.	PEN	has no function during normal operation.

About Code

Examples

This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

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AVR CPU Core

Introduction

Architectural Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 3. Block Diagram of the AVR MCU Architecture

			Data Bus 8-bit
Flash	Program		Status
	Counter		and Control
Program
Memory
			32 x 8	Interrupt
Instruction				Unit
			General
Register			Purpose	SPI
			Registrers
				Unit
Instruction				Watchdog
Decoder	AddressingDirect	AddressingIndirect		Timer
			ALU	Analog
Control Lines				Comparator
				I/O Module1
			Data	I/O Module 2
			SRAM
				I/O Module n
			EEPROM
			I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

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ATmega64(L)

ALU – Arithmetic Logic

Unit

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega64 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

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Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit	7	6	5	4	3	2	1	0
	I	T	H	S	V	N	Z	C	SREG
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I- bit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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General Purpose

Register File

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ATmega64(L)

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

•One 8-bit output operand and one 8-bit result input.

•Two 8-bit output operands and one 8-bit result input.

•Two 8-bit output operands and one 16-bit result input.

•One 16-bit output operand and one 16-bit result input.

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

7		0	Addr.
		R0	0x00
		R1	0x01
		R2	0x02
		…
		R13	0x0D
General		R14	0x0E
Purpose		R15	0x0F
Working		R16	0x10
Registers		R17	0x11
		…
		R26	0x1A	X-register Low Byte
		R27	0x1B	X-register High Byte
		R28	0x1C	Y-register Low Byte
		R29	0x1D	Y-register High Byte
		R30	0x1E	Z-register Low Byte
		R31	0x1F	Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

11

X-, Y-, and Z-register
	The registers R26..R31 have some added functions to their general purpose usage.
	These registers are 16-bit address pointers for indirect addressing of the data space.
	The three indirect address registers X, Y, and Z are defined as described in Figure 5.
	Figure 5.	The X-, Y-, and Z-Registers
		15				XH			XL	0
	X - register
			7					0	7	0
			R27 (0x1B)						R26 (0x1A)
		15				YH			YL	0
	Y - register		7					0	7	0
			R29 (0x1D)						R28 (0x1C)
		15				ZH			ZL	0
	Z - register
			7					0	7	0
			R31 (0x1F)						R30 (0x1E)

Stack Pointer

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. If software reads the Program Counter from the Stack after a call or an interrupt, unused bits (bit 15) should be masked out.

The Stack Pointer points to the data SRAM Stack area where the subroutine and interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit	15	14	13	12	11	10	9	8
	SP15	SP14	SP13	SP12	SP11	SP10	SP9	SP8	SPH
	SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0	SPL
	7	6	5	4	3	2	1	0
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0
	0	0	0	0	0	0	0	0

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Instruction Execution

Timing

ATmega64(L)

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

Reset and Interrupt

Handling

2490I–AVR–11/04

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 291 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 60. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0

– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information. The Reset Vector can also be

13

moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-programming” on page 278.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in	r16, SREG		; store		SREG value
cli	; disable interrupts during timed sequence
sbi	EECR, EEMWE		;	start	EEPROM	write
sbi	EECR,	EEWE
out	SREG,	r16	;	restore SREG		value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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ATmega64(L)

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

;note: will enter sleep before any pending

;interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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AVR ATmega64

Memories

In-System

Reprogrammable Flash

Program Memory

This section describes the different memories in the ATmega64. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega64 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

The ATmega64 contains 64K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega64 Program Counter (PC) is 15 bits wide, thus addressing the 32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read- While-Write Self-programming” on page 278. “Memory Programming” on page 291 contains a detailed description on Flash programming in SPI, JTAG, or Parallel Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 13.

Figure 8. Program Memory Map

$0000

Application Flash Section

Boot Flash Section

$7FFF

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ATmega64(L)

SRAM Data Memory

The ATmega64 supports two different configurations for the SRAM data memory as listed in Table 1.

Table 1. Memory Configurations

	Internal SRAM	External SRAM
Configuration	Data Memory	Data Memory
Normal mode	4096	up to 64K
ATmega103 compatibility mode	4000	up to 64K

Figure 9 on page 18 shows how the ATmega64 SRAM Memory is organized.

The ATmega64 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the ATmega64 is in the ATmega103 compatibility mode.

The first 4,352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4,096 locations address the internal data SRAM.

In ATmega103 compatibility mode, the first 4,096 data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, and the next 4,000 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega64. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register File, I/O, Extended I/O and internal SRAM occupy the lowest 4,352 bytes in Normal mode, and the lowest 4,096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so when using 64KB (65,536 bytes) of External memory, 61,184 Bytes of External memory are available in Normal mode, and 61,440 Bytes in ATmega103 compatibility mode. See “External Memory Interface” on page 25 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the 2-byte Program Counter is pushed and popped, and external memory access does not take advantage of the internal pipeline memory access. When external SRAM interface is used with wait state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait states respectively. Interrupt, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the AVR Instruction Set manual for one, two, and three waitstates.

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The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 extended I/O Registers, and the 4,096 bytes of internal data SRAM in the ATmega64 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 11.

Figure 9. Data Memory Map
	Memory Configuration A					Memory Configuration B
		Data Memory					Data Memory
				$0000 - $001F				$0000 - $001F
		32 Registers					32 Registers
		64 I/O Registers		$0020 - $005F			64 I/O Registers	$0020 - $005F
		160 Ext I/O Reg.		$0060 - $00FF				$0060
							Internal SRAM
				$0100
		Internal SRAM					(4000 x 8)	$0FFF
		(4096 x 8)
				$10FF				$1000
			$1100
		External SRAM					External SRAM
		(0 - 64K x 8)					(0 - 64K x 8)

$FFFF

$FFFF

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ATmega64(L)

Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

T1

T2

T3

clkCPU

Address

Compute Address

Address Valid

Data

WR

Data

RD

Read Write

Memory Access Instruction

Next Instruction

EEPROM Data Memory The ATmega64 contains 2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 291 contains a detailed description on EEPROM programming in SPI, JTAG, or Parallel Programming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 2 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Powerup/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 24. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

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EEPROM Address Register –

EEARH and EEARL

Bit

15

14

13

12

11

10

9

8

–

–

–

–

–

EEAR10

EEAR9

EEAR8

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

7

6

5

4

3

2

1

0

Read/Write

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

X

X

X

X

X

X

X

X

X

X

X

EEPROM Data Register –

EEDR

• Bits 15..11 – Res: Reserved Bits

These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.

• Bits 10..0 – EEAR10..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 2,048. The Initial Value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

Bit	7	6	5	4	3	2	1	0
	MSB							LSB	EEDR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bits 7..0 – EEDR7.0: EEPROM Data

EEPROM Control Register –

EECR

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit	7	6	5	4	3	2	1	0
	–	–	–	–	EERIE	EEMWE	EEWE	EERE	EECR
Read/Write	R	R	R	R	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	X	0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega64 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared.

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ATmega64(L)

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1.Wait until EEWE becomes zero.

2.Wait until SPMEN in SPMCSR becomes zero.

3.Write new EEPROM address to EEAR (optional).

4.Write new EEPROM data to EEDR (optional).

5.Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6.Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on page 278 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the four last steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical programming time for EEPROM access from the CPU.

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Table 2. EEPROM Programming Time(1)

	Number of Calibrated RC
Symbol	Oscillator Cycles	Typ Programming Time
EEPROM write (from CPU)	8448	8.4 ms

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Write data (r16) to data register out EEDR,r16

; Write logical one to EEMWE sbi EECR,EEMWE

; Start eeprom write by setting EEWE sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up address and data registers */ EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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ATmega64(L)

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE sbi EECR,EERE

; Read data from data register in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

;

/* Set up address register */ EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */ return EEDR;

}

EEPROM Write During Power- When entering Power-down Sleep mode while an EEPROM write operation is active, down Sleep Mode the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before

entering Power-down.

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Preventing EEPROM
	During periods of low VCC, the EEPROM data can be corrupted because the supply volt-
Corruption	age is too low for the CPU and the EEPROM to operate properly. These issues are the
	same as for board level systems using EEPROM, and the same design solutions should
	be applied.
	An EEPROM data corruption can be caused by two situations when the voltage is too
	low. First, a regular write sequence to the EEPROM requires a minimum voltage to
	operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
	supply voltage is too low.
	EEPROM data corruption can easily be avoided by following this design
	recommendation:

I/O Memory

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

The I/O space definition of the ATmega64 is shown in “Register Summary” on page 372.

All ATmega64 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega64 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is replaced with SRAM locations when the ATmega64 is in the ATmega103 compatibility mode.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

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External Memory

Interface

Overview

2490I–AVR–11/04

ATmega64(L)

With all the features that the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and Flash, and peripherals such as LCD-display, A/D, and D/A. The main features are:

•Four different wait-state settings (Including no wait-state).

•Independent wait-state setting for different external memory sectors (configurable sector size).

•The number of bits dedicated to address high byte is selectable.

•Bus Keepers on data lines to minimize current consumption (optional).

When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated external memory pins (see Figure 1 on page 2, Table 27 on page 72, Table 33 on page 76, and Table 45 on page 84). The memory configuration is shown in Figure 11.

Figure 11. External Memory with Sector Select(1)

	Memory Configuration A				Memory Configuration B
			0x0000				0x0000
		Internal Memory				Internal Memory
							0x0FFF
			0x10FF				0x1000
			0x1100
		Lower Sector
		SRW01
		SRW00
				SRL[2..0]		SRW10
	External Memory				External Memory
		Upper Sector
	(0-60K x 8)				(0-60K x 8)
		SRW11
		SRW10

0xFFFF	0xFFFF

Note: 1. ATmega64 in non ATmega103 compatibility mode: Memory Configuration A is available (Memory Configuration B N/A).

ATmega64 in mega103 compatibility mode: Memory Configuration B is available (Memory Configuration A N/A).

25

ATmega103 Compatibility

Using the External Memory

Interface

Both External Memory Control Registers, XMCRA and XMCRB, are placed in Extended I/O space. In ATmega103 compatibility mode, these registers are not available, and the features selected by these registers are not available. The device is still ATmega103 compatible, as these features did not exist in ATmega103. The limitations in ATmega103 compatibility mode are:

•Only two wait-state settings are available (SRW1n = 0b00 and SRW1n = 0b01).

•The number of bits that are assigned to address high byte are fixed.

•The external memory section cannot be divided into sectors with different wait-state settings.

•Bus Keeper is not available.

•RD, WR, and ALE pins are output only (Port G in ATmega64).

The interface consists of:

•AD7:0: Multiplexed low-order address bus and data bus.

•A15:8: High-order address bus (configurable number of bits).

•ALE: Address latch enable.

•RD: Read strobe.

•WR: Write strobe.

The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the Data Direction Registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “I/O Ports” on page 65. The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Figure 13 (this figure shows the wave forms without wait states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an internal access will cause activity on address-, dataand ALE ports, but the RD and WR strobes will not toggle during internal access. When the external memory interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal latch (typically 74 x 573 or equivalent) which is transparent when G is high.

Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the typical old style 74HC series latch becomes inadequate. The external memory interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are:

•D to Q propagation delay (tpd).

•Data setup time before G low (tsu).

•Data (address) hold time after G low (th).

The external memory interface is designed to guaranty minimum address hold time after

G is asserted low of th = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 137 to Table 144 on page 339). The D to Q propagation delay (tpd) must be taken into consideration when

calculating the access time requirement of the external component. The data setup time

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Pull-up and Bus Keeper

Timing

before G low (tsu) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

			D[7:0]
AD7:0	D	Q	A[7:0]
ALE	G		SRAM
AVR
A15:8			A[15:8]
RD			RD
WR			WR

The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port Register to zero before entering sleep.

The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper can be disabled and enabled in software as described in “External Memory Control Register B – XMCRB” on page 32. When enabled, the Bus Keeper will ensure a defined logic level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.

External memory devices have different timing requirements. To meet these requirements, the ATmega64 XMEM interface provides four different wait states as shown in Table 4. It is important to consider the timing specification of the external memory device before selecting the wait-state. The most important parameters are the access time for the external memory compared to the set-up requirement of the ATmega64. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse is asserted low until data must

be stable during a read sequence (tLLRL+ tRLRH - tDVRH in Table 137 to Table 144 on page 339). The different wait states are set up in software. As an additional feature, it is possi-

ble to divide the external memory space in two sectors with individual wait-state settings. This makes it possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Figure 159 to Figure 162, and Table 137 to Table 144.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guaranteed (varies between devices, temperature, and supply voltage). Consequently the XMEM interface is not suited for synchronous operation.

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Figure 13. External Data Memory Cycles without Wait State(1) (SRWn1 = 0 and SRWn0 =0)

	T1	T2		T3	T4
System Clock (CLKCPU)
ALE
A15:8	Prev. addr.			Address
DA7:0	Prev. data	Address	XX	Data
WR
DA7:0 (XMBK = 0)	Prev. data	Address		Data
DA7:0 (XMBK = 1)	Prev. data	Address	XXXXX	Data	XXXXXXXX
RD

Write

Read

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).

The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

	T1	T2	T3	T4	T5
System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data

Write

Read

RD

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).

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Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)

	T1	T2	T3	T4	T5	T6
System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data
RD

Write

Read

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).

Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)

	T1	T2	T3	T4	T5	T6	T7
System Clock (CLKCPU)
ALE
A15:8	Prev. Addr.		Address
DA7:0	Prev. Data	Address XX	Data
WR
DA7:0 (XMBK = 0)	Prev. Data	Address	Data
DA7:0 (XMBK = 1)	Prev. Data	Address	Data

Write

Read

RD

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external).

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XMEM Register

Description

MCU Control Register –

MCUCR

External Memory Control

Register A – XMCRA

Bit	7	6		5				4	3	2	1	0
													MCUCR
	SRE	SRW10			SE			SM1	SM0	SM2	IVSEL	IVCE
Read/Write	R/W	R/W			R/W			R/W	R/W	R/W	R/W	R/W
Initial Value	0	0		0				0	0	0	0	0

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detailed description in non ATmega103 compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.

Bit	7	6	5	4	3	2	1	0
	–	SRL2	SRL1	SRL0	SRW01	SRW00	SRW11	–	XMCRA
Read/Write	R	R/W	R/W	R/W	R/W	R/W	R/W	R
Initial Value	0	0	0	0	0	0	0	0

• Bit 7 – Res: Reserved Bit

This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices.

• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit

It is possible to configure different wait states for different external memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits.

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