ATMEL ATmega644 User Manual

4 (1)

Features

High-performance, Low-power AVR® 8-bit Microcontroller

Advanced RISC Architecture

131 Powerful Instructions – Most Single-clock Cycle Execution

32 x 8 General Purpose Working Registers

Fully Static Operation

Up to 20 MIPS Throughput at 20 MHz

High Endurance Non-volatile Memory segments

64K Bytes of In-System Self-programmable Flash program memory

2K Bytes EEPROM

4K Bytes Internal SRAM

Write/Erase cyles: 10,000 Flash/100,000 EEPROM(1)(3)

Data retention: 20 years at 85°C/100 years at 25°C(2)(3)

Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface

Boundary-scan Capabilities According to the JTAG Standard

Extensive On-chip Debug Support

Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

Real Time Counter with Separate Oscillator

Six PWM Channels

8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x

Byte-oriented Two-wire Serial Interface

One Programmable Serial USART

Master/Slave SPI Serial Interface

Programmable Watchdog Timer with Separate On-chip Oscillator

On-chip Analog Comparator

Interrupt and Wake-up on Pin Change

Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection

Internal Calibrated RC Oscillator

External and Internal Interrupt Sources

Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby

I/O and Packages

32 Programmable I/O Lines

40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

Speed Grades

ATmega644V: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V

ATmega644: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V

Power Consumption at 1 MHz, 3V, 25°C

Active: 240 µA @ 1.8V, 1MHz

Power-down Mode: 0.1 µA @ 1.8V

Notes: 1. Worst case temperature. Guaranteed after last write cycle.

2.Failure rate less than 1 ppm.

3.Characterized through accelerated tests.

8-bit

Microcontroller with 64K Bytes In-System Programmable Flash

ATmega644/V

Preliminary

2593M–AVR–08/07

1. Pin Configurations

Figure 1-1. Pinout ATmega644

PDIP

(PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET

VCC

GND

XTAL2

XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/INT0) PD2 (PCINT27/INT1) PD3 (PCINT28/OC1B) PD4 (PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF

GND

AVCC

PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16)

PD7 (OC2A/PCINT31)

TQFP/QFN/MLF

 

 

 

 

 

 

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

 

 

 

 

 

 

 

 

 

 

 

 

 

(PCINT13/MOSI) PB5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PA4 (ADC4/PCINT4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(PCINT14/MISO) PB6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PA5 (ADC5/PCINT5)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(PCINT15/SCK) PB7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PA6 (ADC6/PCINT6)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PA7 (ADC7/PCINT7)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AREF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AVCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC7 (TOSC2/PCINT23)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(PCINT24/RXD0) PD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC6 (TOSC1/PCINT22)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(PCINT25/TXD0) PD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC5 (TDI/PCINT21)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(PCINT26/INT0) PD2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC4 (TDO/PCINT20)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PD3

 

PD4

PD5

PD6

PD7

VCC

GND

PC0

PC1

PC2

PC3

 

 

 

 

 

 

 

(PCINT27/INT1)

 

(PCINT28/OC1B)

(PCINT29/OC1A)

(PCINT30/OC2B/ICP)

(PCINT31/OC2A)

 

 

 

 

(PCINT16/SCL)

(PCINT17/SDA)

(PCINT18/TCK)

(PCINT19/TMS)

Note:

The large center pad underneath the QFN/MLF package should be soldered to ground on the

board to ensure good mechanical stability.

2 ATmega644

2593M–AVR–08/07

ATMEL ATmega644 User Manual

ATmega644

1.1Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

2. Overview

The ATmega644 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1Block Diagram

Figure 2-1. Block Diagram

VCC

RESET

GND

XTAL1

XTAL2

 

PA7..0

 

 

PB7..0

 

Power

 

 

 

 

 

Supervision

PORT A (8)

 

 

PORT B (8)

 

POR / BOD &

 

 

 

RESET

 

 

 

 

 

Watchdog

 

 

 

 

 

Timer

 

 

 

 

 

Watchdog

A/D

 

 

Analog

USART 0

Oscillator

Converter

 

 

Comparator

 

 

 

Oscillator

EEPROM

 

Internal

SPI

 

Circuits /

Bandgap reference

 

Clock

 

 

 

 

 

Generation

 

 

 

 

 

 

 

 

 

16bit T/C 1

 

 

 

 

CPU

 

 

 

JTAG

 

 

8bit T/C 0

 

 

 

 

 

 

 

TWI

FLASH

SRAM

8bit T/C 2

 

 

PORT C (8)

 

 

PORT D (8)

 

 

PC7..0

 

 

PD7..0

 

3

2593M–AVR–08/07

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega644 provides the following features: 64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega644 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega644 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2Pin Descriptions

2.2.1VCC

Digital supply voltage.

2.2.2GND

Ground.

2.2.3Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink

4 ATmega644

2593M–AVR–08/07

ATmega644

and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega644 as listed on page 73.

2.2.4Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega644 as listed on page 75.

2.2.5Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the ATmega644 as listed on page 78.

2.2.6Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega644 as listed on page 80.

2.2.7RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset Characteristics” on page 320. Shorter pulses are not guaranteed to generate a reset.

2.2.8XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.9XTAL2

Output from the inverting Oscillator amplifier.

5

2593M–AVR–08/07

2.2.10AVCC

AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

2.2.11AREF

This is the analog reference pin for the Analog-to-digital Converter.

6 ATmega644

2593M–AVR–08/07

ATmega644

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.

7

2593M–AVR–08/07

4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

8 ATmega644

2593M–AVR–08/07

ATmega644

5. AVR CPU Core

5.1Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

5.2Architectural Overview

Figure 5-1. Block Diagram of the AVR Architecture

 

 

 

Data Bus 8-bit

 

Flash

Program

 

Status

 

Counter

 

and Control

 

Program

 

 

 

 

 

 

Memory

 

 

 

 

 

 

 

32 x 8

Interrupt

Instruction

 

 

Unit

 

 

General

 

Register

 

 

Purpose

SPI

 

 

 

Registrers

 

 

 

Unit

 

 

 

 

Instruction

 

 

 

Watchdog

Decoder

AddressingDirect

AddressingIndirect

 

Timer

 

ALU

Analog

 

 

 

 

 

 

 

Control Lines

 

 

 

Comparator

 

 

 

 

I/O Module1

 

 

 

Data

I/O Module 2

 

 

 

SRAM

 

 

 

 

 

 

 

 

I/O Module n

 

 

 

EEPROM

 

 

 

 

I/O Lines

 

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

9

2593M–AVR–08/07

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega644 has Extended I/O space from 0x100 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

5.3ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

10 ATmega644

2593M–AVR–08/07

ATmega644

5.4Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

5.4.1SREG – Status Register

The AVR Status Register – SREG – is defined as:

Bit

7

6

5

4

3

2

1

0

 

0x3F (0x5F)

I

T

H

S

V

N

Z

C

SREG

 

 

 

 

 

 

 

 

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

11

2593M–AVR–08/07

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

5.5General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 5-2. AVR CPU General Purpose Working Registers

7

0

Addr.

 

 

 

 

 

 

 

 

 

 

R0

0x00

 

 

 

 

 

 

 

 

 

 

R1

0x01

 

 

 

 

 

 

 

 

 

 

R2

0x02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R13

0x0D

 

 

 

 

 

 

 

General

 

R14

0x0E

 

 

 

 

 

 

 

Purpose

 

R15

0x0F

 

 

 

 

 

 

 

Working

 

R16

0x10

 

 

 

 

 

 

 

Registers

 

R17

0x11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R26

0x1A

X-register Low Byte

 

 

 

 

 

 

 

 

 

R27

0x1B

X-register High Byte

 

 

 

 

 

 

 

 

 

R28

0x1C

Y-register Low Byte

 

 

 

 

 

 

 

 

 

R29

0x1D

Y-register High Byte

 

 

 

 

 

 

 

 

 

R30

0x1E

Z-register Low Byte

 

 

 

 

 

 

 

 

 

R31

0x1F

Z-register High Byte

 

 

 

 

 

 

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 5-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

12 ATmega644

2593M–AVR–08/07

ATmega644

5.5.1The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3.

Figure 5-3. The X-, Y-, and Z-registers

 

 

15

XH

 

XL

0

X-register

7

 

0

7

0

 

 

R27 (0x1B)

 

 

R26 (0x1A)

 

 

 

15

YH

 

YL

0

 

 

 

 

 

 

Y-register

7

 

0

7

0

 

 

R29 (0x1D)

 

 

R28 (0x1C)

 

 

 

15

ZH

 

ZL

0

Z-register

7

0

 

7

0

 

 

R31 (0x1F)

 

 

R30 (0x1E)

 

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

5.6Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit

15

14

13

12

11

10

9

8

 

0x3E (0x5E)

SP12

SP11

SP10

SP9

SP8

SPH

 

 

 

 

 

 

 

 

 

 

0x3D (0x5D)

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

Read/Write

R

R

R

R/W

R/W

R/W

R/W

R/W

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

1

0

0

0

0

 

 

1

1

1

1

1

1

1

1

 

13

2593M–AVR–08/07

5.7Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 5-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 5-5. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

5.8Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory Programming” on page 284 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 55. The list also determines the priority levels of the different interrupts. The lower the address the higher is the

14 ATmega644

2593M–AVR–08/07

ATmega644

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 55 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see ”Memory Programming” on page 284.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

15

2593M–AVR–08/07

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

;note: will enter sleep before any pending

;interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

5.8.1Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

16 ATmega644

2593M–AVR–08/07

ATmega644

6. AVR Memories

This section describes the different memories in the ATmega644. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega644 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

6.1In-System Reprogrammable Flash Program Memory

The ATmega644 contains 64K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 32/64 x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega644 Program Counter (PC) is 15/16 bits wide, thus addressing the 32/64K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in ”Memory Programming” on page 284. ”Memory Programming” on page 284 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description.

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Timing” on page 14.

Figure 6-1. Program Memory Map

Application Flash Section

Boot Flash Section

17

2593M–AVR–08/07

6.2SRAM Data Memory

Figure 6-2 shows how the ATmega644 SRAM Memory is organized.

The ATmega644 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 4,352 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory and the next 4,096 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 4096 bytes of internal data SRAM in the ATmega644 are all accessible through all these addressing modes. The Register File is described in ”General Purpose Register File” on page 12.

Figure 6-2. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(4096 x 8)

$0000 - $001F $0020 - $005F $0060 - $00FF $0100

$10FF

18 ATmega644

2593M–AVR–08/07

ATmega644

6.2.1Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 6-3.

Figure 6-3. On-chip Data SRAM Access Cycles

T1 T2 T3

clkCPU

Address Compute Address Address valid

Data

WR

Data

RD

Read Write

Memory Access Instruction

Next Instruction

6.3EEPROM Data Memory

The ATmega644 contains 2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 299, page 303, and page 287 respectively.

6.3.1EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 6-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Section “6.3.2” on page 20. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

19

2593M–AVR–08/07

6.3.2Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

6.4I/O Memory

The I/O space definition of the ATmega644 is shown in ”Register Summary” on page 354.

All ATmega644 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega644 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

6.4.1General Purpose I/O Registers

The ATmega644 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bitaccessible using the SBI, CBI, SBIS, and SBIC instructions.

20 ATmega644

2593M–AVR–08/07

ATmega644

6.5Register Description

6.5.1EEARH and EEARL – The EEPROM Address Register

Bit

15

14

13

12

11

10

9

8

 

0x22 (0x42)

EEAR11

EEAR10

EEAR9

EEAR8

EEARH

 

 

 

 

 

 

 

 

 

 

 

0x21 (0x41)

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

 

 

 

 

 

 

 

 

 

 

 

 

 

7

6

5

4

3

2

1

0

 

Read/Write

R

R

R

R

R/W

R/W

R/W

R/W

 

 

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

X

X

X

X

 

 

 

X

X

X

X

X

X

X

X

 

• Bits 15:12 – Res: Reserved Bits

These bits are reserved bits in the ATmega644 and will always read as zero.

• Bits 11:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

6.5.2EEDR – The EEPROM Data Register

Bit

7

6

5

4

3

2

1

0

 

0x20 (0x40)

MSB

 

 

 

 

 

 

LSB

EEDR

 

 

 

 

 

 

 

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

6.5.3EECR – The EEPROM Control Register

Bit

7

6

5

4

3

2

1

0

 

0x1F (0x3F)

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

EECR

 

 

 

 

 

 

 

 

 

 

 

Read/Write

R

R

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

X

X

0

0

X

0

 

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATmega644 and will always read as zero.

• Bits 5:4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 6-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

21

2593M–AVR–08/07

Table 6-1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EEPROM Mode Bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Programming

 

 

 

EEPM1

EEPM0

Time

Operation

 

 

 

 

 

 

 

 

 

0

0

3.4 ms

Erase and Write in one operation (Atomic Operation)

 

 

 

 

 

 

 

 

 

0

1

1.8 ms

Erase Only

 

 

 

 

 

 

 

 

 

1

0

1.8 ms

Write Only

 

 

 

 

 

 

 

 

 

1

1

Reserved for future use

 

 

 

 

 

 

 

 

 

 

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1.Wait until EEPE becomes zero.

2.Wait until SELFPRGEN in SPMCSR becomes zero.

3.Write new EEPROM address to EEAR (optional).

4.Write new EEPROM data to EEDR (optional).

5.Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6.Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ”Memory Programming” on page 284 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

22 ATmega644

2593M–AVR–08/07

ATmega644

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 6-2 lists the typical programming time for EEPROM access from the CPU.

Table 6-2.

EEPROM Programming Time

 

Symbol

 

Number of Calibrated RC Oscillator Cycles

Typ Programming Time

 

 

 

EEPROM write

26,368

3.3 ms

(from CPU)

 

 

 

 

 

 

 

 

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

23

2593M–AVR–08/07

Assembly Code Example(1)

EEPROM_write:

; Wait for completion of previous write sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register out EEDR,r16

; Write logical one to EEMPE sbi EECR,EEMPE

; Start eeprom write by setting EEPE sbi EECR,EEPE

ret

C Code Example(1)

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */ EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

Note: 1. See “About Code Examples” on page 8.

24 ATmega644

2593M–AVR–08/07

ATmega644

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example(1)

EEPROM_read:

; Wait for completion of previous write sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE sbi EECR,EERE

; Read data from Data Register in r16,EEDR

ret

C Code Example(1)

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

;

/* Set up address register */ EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */ return EEDR;

}

Note: 1. See “About Code Examples” on page 8.

6.5.4GPIOR2 – General Purpose I/O Register 2

Bit

7

6

5

4

3

2

1

0

 

0x2B (0x4B)

MSB

 

 

 

 

 

 

LSB

GPIOR2

 

 

 

 

 

 

 

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

6.5.5GPIOR1 – General Purpose I/O Register 1

Bit

7

6

5

4

3

2

1

0

 

0x2A (0x4A)

MSB

 

 

 

 

 

 

LSB

GPIOR1

 

 

 

 

 

 

 

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

25

2593M–AVR–08/07

6.5.6GPIOR0 – General Purpose I/O Register 0

Bit

7

6

5

4

3

2

1

0

 

0x1E (0x3E)

 

MSB

 

 

 

 

 

 

LSB

GPIOR0

 

 

 

 

 

 

 

 

 

 

 

Read/Write

 

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

 

Initial Value

0

0

0

0

0

0

0

0

 

Note: 1.

SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

 

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction

 

accesses the RAM (internal or external).

 

 

 

 

 

26 ATmega644

2593M–AVR–08/07

ATmega644

7. System Clock and Clock Options

7.1Clock Systems and their Distribution

Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 39. The clock systems are detailed below.

Figure 7-1.

Clock Distribution

 

 

 

 

Asynchronous

General I/O

ADC

CPU Core

RAM

Flash and

Timer/Counter

Modules

EEPROM

 

 

 

 

 

 

clkADC

 

 

 

 

 

clkI/O

AVR Clock

clkCPU

 

 

 

 

 

Control Unit

 

 

 

 

 

clkASY

 

clkFLASH

 

 

 

 

 

 

Reset Logic

Watchdog Timer

 

 

 

 

Source clock

Watchdog clock

 

 

 

 

System Clock

 

Watchdog

 

 

 

 

Prescaler

 

Oscillator

 

 

 

 

Clock

 

 

 

 

 

 

Multiplexer

 

 

 

Timer/Counter

External Clock

Crystal

Low-frequency

Calibrated RC

 

Oscillator

Oscillator

Crystal Oscillator

Oscillator

 

 

7.1.1CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

7.1.2I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clkI/O is halted, TWI address recognition in all sleep modes.

27

2593M–AVR–08/07

7.1.3Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

7.1.4Asynchronous Timer Clock – clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.

7.1.5ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

7.2Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

 

 

Table 7-1.

Device Clocking Options Select(1)

 

 

 

Device Clocking Option

 

CKSEL3..0

 

 

 

 

 

 

 

Low Power Crystal Oscillator

 

1111 - 1000

 

 

 

 

 

 

 

Full Swing Crystal Oscillator

 

0111 - 0110

 

 

 

 

 

 

 

Low Frequency Crystal Oscillator

 

0101 - 0100

 

 

 

 

 

 

 

Internal 128 kHz RC Oscillator

 

0011

 

 

 

 

 

 

 

Calibrated Internal RC Oscillator

 

0010

 

 

 

 

 

 

 

External Clock

 

0000

 

 

 

 

 

 

 

 

Reserved

 

 

0001

 

 

 

 

 

 

 

 

Note: 1.

For all fuses “1” means unprogrammed while “0” means programmed.

 

7.2.1

Default Clock Source

 

 

 

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting using any available programming interface.

7.2.2Clock Startup Sequence

Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable.

To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by all other reset sources. ”On-chip Debug System” on page 43 describes the start conditions for the internal reset. The delay (tTOUT) is timed from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The

28 ATmega644

2593M–AVR–08/07

ATmega644

selectable delays are shown in Table 7-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics” on page 326.

Table 7-2.

Number of Watchdog Oscillator Cycles

 

Typ Time-out (VCC = 5.0V)

Typ Time-out (VCC = 3.0V)

Number of Cycles

 

0 ms

0 ms

0

 

 

 

 

 

4.1 ms

4.3 ms

512

 

 

 

 

 

65 ms

69 ms

8K (8,192)

 

 

 

 

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is assumed to be at a sufficient level and only the start-up time is included.

7.2.3Clock Source Connections

The pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 7-2. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. For ceramic resonators, the capacitor values given by the manufacturer should be used.

Figure 7-2. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

29

2593M–AVR–08/07

7.3Low Power Crystal Oscillator

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the ”Full Swing Crystal Oscillator” on page 31.

Some initial guidelines for choosing capacitors for use with crystals are given in Table 7-3. The crystal should be connected as described in ”Clock Source Connections” on page 29.

The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 7-3.

Table 7-3.

Low Power Crystal Oscillator Operating Modes(3)

Frequency Range(1) (MHz)

 

Recommended Range for Capacitors C1

CKSEL3..1

and C2 (pF)

 

0.4 - 0.9

100(2)

 

0.9 - 3.0

101

12 - 22

 

 

 

 

 

3.0 - 8.0

110

12 - 22

 

 

 

 

 

8.0 - 16.0

111

12 - 22

 

 

 

 

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2.This option should not be used with crystals, only with ceramic resonators.

3.If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

7-4.

 

 

 

 

 

Table 7-4.

Start-up Times for the Low Power Crystal Oscillator Clock Selection

 

 

 

 

 

 

 

 

 

Start-up Time from

Additional Delay

 

 

Oscillator Source /

Power-down and

from Reset

 

 

Power Conditions

Power-save

(VCC = 5.0V)

CKSEL0

SUT1..0

Ceramic resonator, fast

258 CK

14CK + 4.1 ms(1)

0

00

rising power

 

 

 

 

 

 

 

 

 

 

 

Ceramic resonator, slowly

258 CK

14CK + 65 ms(1)

0

01

rising power

 

 

 

 

 

 

 

 

 

 

 

Ceramic resonator, BOD

1K CK

14CK(2)

0

10

enabled

 

 

 

 

 

 

 

 

 

 

 

Ceramic resonator, fast

1K CK

14CK + 4.1 ms(2)

0

11

rising power

 

 

 

 

 

 

 

 

 

 

 

Ceramic resonator, slowly

1K CK

14CK + 65 ms(2)

1

00

rising power

 

 

 

 

 

 

 

 

 

 

 

 

30 ATmega644

2593M–AVR–08/07

Loading...
+ 346 hidden pages