Apple iMac 27 A1419 Schematics

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISION

CK APPD

21

1245678

B

D

6543

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

D

SIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

TABLE_TABLEOFCONTENTS_ITEM

D8 MLB

1 OF 117

2012-08-28

ENGINEERING RELEASED

1 OF 143

7.0.0

051-9504

7

0001607307

prefsb

60

65

D8_DIRK

AUDIO: Jack, Mikey, CHS Switch

06/29/2012

TITLE=K22 ABBREV=DRAWING

LAST_MODIFIED=Mon Aug 27 13:24:34 2012

N/A

1

MASTER

Table of Contents

Contents

Date

(.csa)

SyncPage Sync

Date

Page

(.csa)

Contents

SCH,D8,MLB

61

66

D8_DAVID

Audio: Spkr/Mic Conn.

06/13/2012

62

67

D8_DAVID

AUDIO: Detects/Grounding

06/13/2012

63

68

D8_DAVID

AUDIO: Speaker ID

06/13/2012

64

69

D8_MARK

PM Regulator Enables

04/23/2012

65

70

D8_MARK

PM Power Good

04/23/2012

66

71

D8_MLB

VReg CPU Core/AXG Cntl

02/28/2012

67

72

D8_MLB

VReg CPU Core Phases

02/28/2012

68

73

D8_MLB

VReg CPU AXG Phases

02/28/2012

69

74

D8_KOSECOFF

VReg CPU 1.05V S0

02/25/2012

70

75

D8_KOSECOFF

VReg CPU VccSA S0

02/25/2012

71

76

D8_MLB

VReg 3.3V S5/5V S4

02/28/2012

72

77

D8_KOSECOFF

VReg VDDQ and 1.8V S0

02/25/2012

73

78

D8_MLB

VREG 3.42V G3HOT

04/11/2012

74

79

D8_MLB

FET-Controlled S0 and S4

05/14/2012

75

80

D8_AARON

KEPLER PCI-E

03/13/2012

76

81

D8_YAN

KEPLER CORE/FB POWER

04/09/2012

77

82

D8_YAN

KEPLER FRAME BUFFER I/F

05/15/2012

78

83

D8_YAN

GPU SIGNAL & POWER ALIASES

04/09/2012

79

84

D8_YAN

GDDR5 Frame Buffer A

04/09/2012

80

85

D8_YAN

GDDR5 Frame Buffer B

04/09/2012

81

86

D8_YAN

KEPLER EDP/DP/GPIO

04/09/2012

82

87

D8_YAN

KEPLER GPIOS,CLK & STRAPS

07/27/2012

83

88

D8_YAN

KEPLER PEX PWR/GNDS

04/09/2012

84

92

D8_AARON

Internal DP MUXing

03/13/2012

85

93

D7_MLB

TBT DDC Crossbar

03/15/2012

86

94

D8_AARON

Thunderbolt Connector A

03/13/2012

87

95

D8_MLB

Internal DP Support

03/21/2012

88

96

D8_AARON

Thunderbolt Connector B

03/13/2012

89

97

D8_MLB

Backlight Controller MCU

04/23/2012

90

98

D8_MLB

Backlight LED Driver

04/23/2012

91

99

D8_MLB

Backlight Controller

04/23/2012

92

114

D8_MLB

VReg GPU Core Phases

02/28/2012

93

115

D8_MLB

VReg GPU Core Phases

02/25/2012

94

116

D8_MLB

VREG GPU CORE PHASE 4

02/06/2012

95

117

D8_MLB

GPU VDDQ AND 1V05 GPU/PCH/TBT VREGS

04/18/2012

96

120

D8_KOSECOFF

D8 RULE DEFINITIONS

03/19/2012

97

121

D8_KOSECOFF

DDR3 Constraints

03/19/2012

98

122

D8_AARON

CPU PCIe Constraints

03/13/2012

99

123

D8_ROSITA

CPU MISC/DMI/FDI/XDP Constraints

03/23/2012

100

124

D8_MARK

SATA/FDI/XDP Constraints

02/10/2012

101

125

D8_MARK

PCH and BR Constraints

02/10/2012

102

126

D8_KOSECOFF

USB/Camera Constraints

06/22/2012

103

127

D8_MARK

SMBus/Sensor Constraints

04/23/2012

104

128

D8_MARK

VReg Constraints

02/10/2012

105

129

D8_MARK

CPU VReg Constraints

02/10/2012

106

130

D8_MARK

Platform VReg Constraints

02/10/2012

107

131

D8_AARON

TBT/DP Constraints

03/13/2012

108

132

D8_AARON

GDDR5/GPU Constraints

03/13/2012

109

134

D8_MLB

BLC Constraints

12/19/2011

110

135

D8_MARK

GPU VREG CONSTRAINTS

02/10/2012

111

136

D8_FIYIN

ETHERNET/SD CONSTRAINTS

07/02/2012

112

138

D8_MARK

AUTO-CONSTRAINTS 1

04/23/2012

113

139

D8_MARK

AUTO-CONSTRAINTS 2

04/23/2012

114

140

D8_MARK

AUTO-CONSTRAINTS 3

04/23/2012

115

141

D8_MARK

AUTO-CONSTRAINTS 4

04/23/2012

116

142

D8_MARK

AUTO-CONSTRAINTS 5

04/23/2012

117

143

D8_MARK

AUTO-CONSTRAINTS 6

04/23/2012

01/05/2012

2

D8_MLB

System Block Diagram

04/23/2012

3

D8_MARK

Power Block Diagram

12/19/2011

4

D8_MLB

BOM Configuration

06/22/2012

5

D8_TAVYS

DEBUG LEDS

06/20/2012

6

D8_DOUG

Power Connectors/Aliases

03/25/2012

7

D8_MLB

Holes/PD parts

04/02/2012

8

D8_MLB_ULTIMATE

Unused Signal Aliases

08/23/2011

9

K70_MLB

Signal Aliases

03/23/2012

10

D8_ROSITA

CPU DMI/PEG/FDI/RSVD

03/15/2012

11

D7_MLB

CPU CLOCK/MISC/JTAG

03/15/2012

12

D7_MLB

CPU DDR3 INTERFACES

03/15/2012

13

D7_MLB

CPU POWER

03/15/2012

14

D7_MLB

CPU GROUNDS

03/29/2012

15

D8_MLB

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

12/20/2011

16

D7_MLB

CPU NON-GFX DECOUPLING

01/26/2012

17

D8_KOSECOFF

GFX DECOUPLING & PCH PWR ALIAS

N/A

18

D8_MLB

PCH SATA/PCIE/CLK/LPC/SPI

03/15/2012

19

D7_MLB

PCH DMI/FDI/GRAPHICS

03/15/2012

20

D7_MLB

PCH PCI/USB

N/A

21

D8_MLB

PCH MISC

N/A

22

D8_MLB

PCH POWER

03/15/2012

23

D7_MLB

PCH GROUNDS

N/A

24

D8_MLB

PCH DECOUPLING

01/26/2012

25

D7_MLB

CPU and PCH XDP

N/A

26

D8_MLB

CHIPSET SUPPORT

03/23/2012

27

D8_ROSITA

USB 2.0 HUB (BT/SMC)

04/23/2012

28

D8_MARK

CPU Memory S3 Support

03/19/2012

29

D8_KOSECOFF

DDR3 SO-DIMM Connector A Slot0

03/19/2012

30

D8_KOSECOFF

DDR3 SO-DIMM Connector A Slot1

03/19/2012

31

D8_KOSECOFF

DDR3 SO-DIMM CONNECTOR B SLOT0

03/19/2012

32

D8_KOSECOFF

DDR3 SO-DIMM CONNECTOR B SLOT1

03/19/2012

33

D8_KOSECOFF

DDR3 ALIASES AND BITSWAPS

03/19/2012

34

D8_KOSECOFF

DDR3/FRAMEBUF VREF MARGINING

07/02/2012

35

D8_FIYIN

AIRPORT/BT

N/A

36

D8_MLB

Thunderbolt Host (1 of 2)

03/15/2012

37

D7_MLB

Thunderbolt Host (2 of 2)

03/15/2012

38

D7_MLB

Thunderbolt Power Support

07/02/2012

39

D8_FIYIN

ETHERNET PHY (CAESAR IV+)

07/02/2012

40

D8_FIYIN

Ethernet Support & Connector

07/02/2012

41

D8_FIYIN

SD READER CONNECTOR

03/23/2012

42

D8_ROSITA

Camera Controller

03/15/2012

43

D7_MLB

Camera Controller Support

01/31/2012

45

44

D8_JERRY

SATA Connectors

03/23/2012

46

45

D8_ROSITA

EXTERNAL USB PORTS A & B

03/23/2012

47

46

D8_ROSITA

EXTERNAL USB PORTS C & D

03/22/2012

49

47

D8_MARK

SMC

07/19/2012

50

48

D8_DOUG

SMC Support

N/A

51

49

D8_MLB

SPI and Debug Connector

06/22/2012

52

50

D8_TAVYS

SMBus Connections

06/20/2012

53

51

D8_DOUG

I and V Sense 1

02/25/2012

54

52

D8_JERRY

HDD/SSD Temp Sense

06/07/2012

55

53

D8_DOUG

Temperature Sensors

07/19/2012

56

54

D8_DOUG

System Fan

04/23/2012

59

55

D8_MARK

I and V Sense 2

06/13/2012

61

56

D8_DAVID

AUDIO: CODEC/REGULATORS

06/13/2012

62

57

D8_DAVID

AUDIO: HEADPHONE AMP

06/13/2012

63

58

D8_DAVID

AUDIO: LEFT SPKR AMP

06/13/2012

64

59

D8_DAVID

AUDIO: RIGHT SPKR AMP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

System Block diagram can be found on Kismet

PATH: Kismet > K70/72 > Block Diagrams > K70 Block Diagram

D8_MLB

01/05/2012

System Block Diagram

prefsb

051-9504

7.0.0

2 OF 143

2 OF 117

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Regulator

U7600

PP3V42_G3H

IW0R

Fan

TBT IO

Speaker amps

GPU

LCD

PPVCCSA_S0

PP1V05_S0_CPU

PPVCORE_S0_CPU

PPVAXG_S0

PPFBVDDQ_S0_GPU

PPVCORE_S0_GPU

GPU (Core)

GPU (FB)

CPU (AXG)

CPU

CPU (Core)

CPU (VccIO)

PP1V05_TBTCIO

PP1V05_TBTLC

P1V05_S0_PCH

P1V05_S0

TBT Router

GPU (IOVDD, PLLVDD)

PCH (VCC, VccIO)

PP12V_S0_HDD

HDD (12V)

PH0R

PGTR

=

PH02+PH05

=

PCTR

SMC, RTC, MojoMux

PP12V_G3H

en

Regulator

VD2R

PR1R

IR1R

RegS0

Vin

UB700

en

S0

1V05

SD Card, DP Mux, DP X-bar

VD2R

PG0F

VD2R

IG0F

PC0S

Regulator

S0

FBVDDQ

GPU

3.3V

PCH, PwrCtl

Regulator

U7801

Reg

Vin

G3H G3H

3V42

VccIO

S0S0 Reg

Vin en

Regulator

U7400

Bootrom, PCH, SMC, XDP,

Audio, LCD TCON, SnsCtl, VRD, PCH

PP5V_S0

VRegCtl, SnsCtl

Audio, PCH

PP5V_S0_HDD

HDD (5V)

PP5V_S4

CAM, USB Ports, VRegCtl

PH05

IH05

VH05

SSD

PP3V3_S0_SSD

PH1R

IW1R

V3V3

PP3V3_S0

VG0C

VC0C

USB Hub, SMC, TBT I/O

PP3V3_S4_ENET

PP3V3_S4

WIFI

PP3V3_S4_AP

PW0R

V3V3

SD Card, USB Mux, VRD, PwrCtl

PP3V3_TBTLC

TBT Router

Ethernet

IC0S

S4RegS4

en 5V

S0LDOS0

en

VTT

LDO S3

S3Reg

en

S3

Regulator

U7700

Vin

VDDQ

IM0R

VM0R

PM0R

PPDDRVTT_S0

DIMM (VTT)

DIMM VREF Margining CA

IC0M

VC0M

PC0M

PPDDRVTT_S3

PP1V5_S0

PPVDDQ_S3_DDR

PP1V5_S0_CPU_MEM

CPU (Mem)

Audio

DIMM (1V5)

Vin

PH02

IH02

VD2R

UB750

Regulator

Loads

IN1R

VN1R

PN1R

en

S0 Reg

GPU

S0

UB400

Vin en

S0Reg

IG0C

PG0C

U7100

Vin

S0

Regulator

AXG

VC0G

IC0G

PC0G

S0Reg

Core

IC0C

PC0C

en

Reg

VccSA

S0

VD2R

IC0I

PC0I

Regulator

U7500

Vin

PPHV_SW_TBTAPWR

PPHV_SW_TBTBPWR

TBT Port A

TBT Port B

PD2R

ID2R

Supply Module

PP5V_S0

en

Vin

S0

U7750

Regulator

Reg S0

1.8V

PP1V8_S0_REG

CPU PLL

en

PP12V_S5

S5Reg

Vin

PP5V_S5

PP12V_S0_BLC

S5 LDO5VS5

PP12V_ACDC

12V

G3H

AC/DC

Reg

ALS, CAM, BT

en

PP3V3_S5

S0

PP12V_S0

S0Reg

PC0I

+

PC0S

+

)

PC0MPC0G

+

PC0C

(

+

5.7 (GK104/GK107_BLENDED_CONSTANT)

+

PG0F

+

PG0C

1.176 *

High-side Component Total Power Keys

SYNC_DATE=04/23/2012

SYNC_MASTER=D8_MARK

Power Block Diagram

prefsb

051-9504

7.0.0

3 OF 143

3 OF 117

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_ALT_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_BOMGROUP_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM Groups

CPUs

Programmable Parts

ALTERNATE:335S0854

ASICs

ALTERNATE:335S0812

BOM Variants

CPU SOCKET ALTERNATES

D8 SCHEMATIC / PCB #’S

CPU SOCKET

D8 ALTERNATES

VRAM MODULE PARTS

Bar Code Labels / EEEE #’s

D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F49T

639-3952

PCBA,MLB,3.1G,4C,GK107,SAM,D8

D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F653

639-4092

PCBA,MLB,2.9G,4C,GK107,HYN.D8

639-4093

D8_COMMON,D8,CPU:4C_3P1GHZ,GPU:107EGE,FB:BOTH_HYNIX,EEEE:F654

PCBA,MLB,3.1G,4C,GK107,HYN.D8

PCBA,MLB,DEV,D8

085-4433

DEVELOPMENT,D8_DEVEL

IC, GPU, NV GK107-GE-PS-A2

337S4280

U8000

CRITICAL

GPU:107EGE

1

825-7896

LABEL,MLB,2D

EEEE_DHNM

CRITICAL

1

EEEE:DHNM

CRITICAL

FB:BOTH_SAMSUNG

333S0619

IC,SGRAM,GDDR5,32MX32,1.5GHz,G-DIE,HF

U8400,U8450,U8500,U8550

4

333S0620

4

IC,GDDR5,32MX32,1.5GHZ,VEGA 44NM,B-DIE

FB:BOTH_HYNIX

U8400,U8450,U8500,U8550

CRITICAL

377S0147

ALL

USB diodes

377S0126

U3990

CRITICAL

CIVROM:PROG

1

341S3645

IC,ENET 1MBIT, SPI,ROM, V1.13 D8

CAMROM:BLANK

CRITICAL

1

U4202

335S0852

IC,FLASH,SPI,1MBIT,3V3

338S1098

U4900

SMC:BLANK

IC,SMC,LX4FS1AH5BBCIGA3

1

CRITICAL

SMC:PROGCRITICAL

1

U4900

341S3394

IC,PROGRMD,SMC,A3,V2.2A32,D8

CRITICAL

U4202

CAMROM:PROG

1

341S3675

IC,CAMERA FLASH,V7228,D7/D8

511S0071

ALL

511S0073

TYCO SOCKET

511S0073

ALL

511S0072

FOXCONN SOCKET

U1000

511S0073 CRITICAL

1

SOCKET,MOLEX,LGA1155,CPU-LF

D8_COMMON,D8,CPU:4C_2P9GHZ,GPU:107EGE,FB:BOTH_SAMSUNG,EEEE:F2FR

639-3816

PCBA,MLB,2.9G,4C,GK107,SAM,D8

157S0084

Enet Magnetics

ALL

157S0058

IC,BCM57766A1,ENET&SD,8X8

343S0616

1

U3900

CRITICAL

IC,TBT,CR-4C,B1,PRQ,288 FCBGA,12X12MM

338S1113

U3600

CRITICAL

1

IC,PANTHER POINT,C1,SLJC7,PRQ,BD82Z77

337S4277

U1800

CRITICAL

1

337S3978

CRITICAL

BLCMCU:BLANK

U9700

IC,BLC MCU LPC2132FBD64/01, LQFP64

TBTROM:PROG

CRITICAL

1

U3690

341S3672

IC,EEPROM,CR,V14.1 (B1),D8

1

CRITICAL

U3690

TBTROM:BLANK

IC,EEPROM,SERIAL,8KB,MLP8

335S0865

U9700

BLCMCU:PROG

CRITICAL

341S3674

IC,BLC,MCU, PRPOGRAMMED, V0204, D8

1

U3990

CRITICAL

CIVROM:BLANK

335S0862

IC,SERIAL FLASH,2MBIT, 2.7V, REF F

335S0807

1

BOOTROM:BLANK

CRITICAL

U5110

IC,64 MBIT SPI SERIAL FLASH

CRITICAL

BOOTROM:PROG

1

U5110

IC,PROGRMD,EFI ROM,V00FC,D7/D8

341S3673

376S0975

ALL

376S1081

P/NCH DUAL FET

PCBF,MLB,D8

CRITICALPCB1

1

D8820-3298

1

CRITICALSCH1 D8SCH,MLB,D8051-9504

341S3644

U3990

CIVROM

341S3645

150UF CAPS BLK

128S0368128S0365

ALL

102S0880

0.010 OHM,1%,1206

102S0879

ALL

138S0804

2.2UF CAPS SOFT

138S0803

825-7896

LABEL,MLB,2D

EEEE_F2FR

1

CRITICAL

EEEE:F2FR

LABEL,MLB,2D

CRITICAL

1

EEEE:F49VEEEE_F49V

825-7896

337S4372 CRITICAL

1

CPU

IVB,SR0T9,PRQ,N0,3.1,65W,4+1,1.1,6M,LGA

CPU:4C_3P1GHZ

BOM Configuration

SYNC_MASTER=D8_MLB

SYNC_DATE=12/19/2011

1

LABEL,MLB,2D

CRITICAL

EEEE:F653EEEE_F653

825-7896

337S4355

CPU

1

CRITICAL

IVB,SR0TA,PRQ,N1,2.9,65W,4+1,1.1,6M,LGA

CPU:4C_2P9GHZ

D8_DEVEL

XDP_CONN,LPCPLUS,VREFMRGN:EXT,DEVEL_AUDIO,TEMPSNSDEV

SMC:PROG,BOOTROM:PROG,TBTROM:PROG,CIVROM:PROG,CAMROM:PROG,BLCMCU:PROG

D8_PROGPARTS

XDP,RSMRST:GATE,SPEAKERID,VREF:CPU,TBTHV:P12V,FBA,FBB

D8_COMMON1

D8_PRODUCTION

VREFMRGN:N,PRODUCTION

D8_COMMON

COMMON,ALTERNATE,D8_COMMON1,D8_PROGPARTS,D8_PRODUCTION

825-7896

EEEE:F654EEEE_F654

CRITICAL

LABEL,MLB,2D

1

825-7896

LABEL,MLB,2D

EEEE_F49T

CRITICAL

1

EEEE:F49T

prefsb

051-9504

7.0.0

4 OF 143

4 OF 117

IN

G

D

S

IN

G

D

S

IN

G

D

S

IN

G

D

S

G

D

S

IN

G

D

S

IN

G

D

S

IN

G

D

S

IN

G

D

S

IN

G

D

S

IN

G

D

S

IN

G

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEM 1V5_S3 LED

LED GND ISOLATION SWITCH

ALL_SYS_PWRGD LED

S5 LED

CPU 1V05_S0 LED

S4 (SLEEP) LED

GPU FBVDD LED

CPU VCORE LED

BLC_EN LED

CPU AXG LED

PCH/GPU 1V05 LED

GPU_GOOD LED VIDEO_ON LED

GPU VCORE LED

SLP_S3 LED

APN: 705S0137

64 69

115

5% 1/16W

1K

402

R507

DEVELOPMENT

MF-LF

2.0X1.25MM-SM

GREEN-3.6MCD

LED507

DEVELOPMENT

SOT-363

Q507

2N7002DW-X-G

DEVELOPMENT

64 95

115

402

MF-LF

5% 1/16W

1K

R502

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

LED502

DEVELOPMENT

1/16W MF-LF

5%

402

1K

R512

LED512

GREEN-3.6MCD

SILK_PART=3

2.0X1.25MM-SM

PLACE_SIDE=BOTTOM

2N7002DW-X-G

SOT-363

Q511

1/16W

1K

5%

402

R511

MF-LF

SILK_PART=2

LED511

PLACE_SIDE=BOTTOM

GREEN-3.6MCD

2.0X1.25MM-SM

21 99

Q511

SOT-363

2N7002DW-X-G

47 65

112

MF-LF 402

1K

5% 1/16W

R501

2.0X1.25MM-SM

SILK_PART=1

LED501

PLACE_SIDE=BOTTOM

GREEN-3.6MCD

5% 1/16W

R513

1K

MF-LF 402

GREEN-3.6MCD

2.0X1.25MM-SM

LED513

SILK_PART=4

PLACE_SIDE=BOTTOM

SOT-363

2N7002DW-X-G

Q513

1/16W MF-LF

5%

1K

402

R514

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

LED514

DEVELOPMENT

SOT-363

2N7002DW-X-G

Q513

DEVELOPMENT

89

87

107

SM

SW500

KMT221GLHS

DEVELOPMENT

1/16W

1K

5%

R505

402

MF-LF

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

LED505

DEVELOPMENT

SOT-363

Q505

2N7002DW-X-G

DEVELOPMENT

64 92

110

402

MF-LF

1/16W

5%

R506

1K

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

LED506

DEVELOPMENT

Q505

SOT-363

2N7002DW-X-G

DEVELOPMENT

64 95

115

402

5%

1K

1/16W MF-LF

R503

DEVELOPMENT

LED503

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

SOT-363

Q503

2N7002DW-X-G

DEVELOPMENT

64 72

115

1/16W MF-LF

5%

1K

402

R504

DEVELOPMENT

GREEN-3.6MCD

LED504

DEVELOPMENT

2.0X1.25MM-SM

2N7002DW-X-G

Q503

SOT-363

DEVELOPMENT

15 19 28 40 47 48 64

115

5%

1K

MF-LF

1/16W

402

R510

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

LED510

DEVELOPMENT

GREEN-3.6MCD

LED509

2.0X1.25MM-SM

DEVELOPMENT

402

1K

5% 1/16W MF-LF

R509

DEVELOPMENT

SOT-363

2N7002DW-X-G

Q509

DEVELOPMENT

25 65 66

115

Q509

SOT-363

2N7002DW-X-G

DEVELOPMENT

1/16W MF-LF

5%

1K

402

R508

DEVELOPMENT

GREEN-3.6MCD

LED508

DEVELOPMENT

2.0X1.25MM-SM

66

116

2N7002DW-X-G

Q507

DEVELOPMENT

SOT-363

SYNC_MASTER=D8_TAVYS

DEBUG LEDS

SYNC_DATE=06/22/2012

ALL_SYS_PWRGD

PM_LED_A_PGOOD_REG_GPUCORE_S0

=PP3V3_S5_LED

GPU_GOOD

PM_LED_K_ALL_SYS_PWRGD

PM_LED_K_GPU_GOOD

=PP3V3_S4_LED =PP3V3_S0_LED =PP3V3_S0_LED

PM_LED_A_VIDEO_ON

VIDEO_ON_L

NO_TEST=TRUE

NC_Q513_1

NO_TEST=TRUE

NC_Q513_6

NC_Q513_2 NO_TEST=TRUE

PM_PGOOD_REG_P1V05_S0

=PP3V3_S0_LED

PM_PGOOD_REG_VDDQ_S3

=PP3V3_S5_LED

PM_LED_A_PGOOD_REG_VDDQ_S3

PM_LED_K_PGOOD_REG_VDDQ_S3

LED_GND

PM_LED_K_PGOOD_REG_P1V05

LED_GND

PM_LED_A_PGOOD_REG_P1V05

PM_PGOOD_REG_CPU_P1V05_S0

LED_GND

PM_SLP_S3_L

=PP3V3_S0_LED

PM_LED_K_PGOOD_CPU_P1V05_S0

LED_GND

PM_LED_K_SLP_S3

PM_LED_A_SLP_S3

REG_CPUAXG_PGOOD

LED_GND

PM_PGOOD_REG_GPUCORE_S0

PM_LED_A_CPUAXG_PGOOD

PM_LED_K_CPUAXG_PGOOD

=PP3V3_S0_LED

LED_GND

PM_LED_K_PGOOD_REG_GPUCORE_S0

=PP3V3_S5_LED

PM_PGOOD_REG_CPUCORE_S0

PM_PGOOD_REG_FBVDDQ_S0

BLC_GOOD

LED_GND

=PP3V3_S0_LED

LED_GND

PM_LED_K_BLC_GOOD

PM_LED_A_BLC_GOOD

PM_LED_K_PGOOD_CPUCORE_S0

PM_LED_A_PGOOD_CPUCORE_S0

=PP3V3_S0_LED

LED_GND

PM_LED_K_PGOOD_REG_FBVDDQ_S0

=PP3V3_S5_LED

PM_LED_A_PGOOD_REG_FBVDDQ_S0

LED_GND

=PP3V3_S4_LED

PM_LED_A_S4

PM_LED_A_PGOOD_CPU_P1V05_S0

PM_LED_A_GPU_GOOD

PM_LED_A_ALL_SYS_PWRGD

PM_LED_A_S5

=PP3V3_S5_LED

MIN_NECK_WIDTH=0.2 MM

LED_GND

MIN_LINE_WIDTH=0.3 MM

prefsb

051-9504

7.0.0

5 OF 143

5 OF 117

1

2

K

A

6

2

1

2

K

A

1

2

K

A

3

5

4

1

2

K

A

6

2

1

2

K

A

1

2

K

A

6

2

1

2

K

A

3

5

4

13

24

5

1

2

K

A

6

2

1

2

K

A

3

5

4

1

2

K

A

6

2

1

2

K

A

3

5

4

1

2

K

A

K

A

1

2

3

5

4

6

2

1

2

K

A

3

5

4

5 6

115

5 6 5 6 5 6

115

5 6

5

5 5

5 6

5

115

5

115

5 6

5

5 6

5

5 6

5

115

5 6

5

5 6

5

5 6

115

115 115

115

5 6

5

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FILTER ADDED TO BURSTMODE_EN_L TO PASS SURGE RDAR://11059712

MLB to AC-DC Supplemental Signal Connector

MLB to AC-DC Connector

S5 Rails

On when in S5

G3 Rails

518-0389

518S0863

Always on: Keeps the PCH RTC alive

THIS IS 1.5V RAIL

S3 Rails

Enabled when system is in run or sleep

GPU Rails (S0)

Enabled when system is in run

Ground/Common

S0 Rails

Enabled when system is in run

Enabled when Thunderbolt cable is plugged in

Thunderbolt Rails (S0)

G3H Rails

On with AC/DC plugged in

Enabled when system has AC and is in run or sleep

S4 Rails

J600.5:10MM

EMC

25V

5%

402

NP0-C0G

1000PF

C603

J600.5:10MM

EMC

402

25V

5%

C602

1000PF

NP0-C0G

C601

10%

805

X5R

25V

10UF

J600.4:10MM

53

117

J601

504050-0791

M-RT-SM

SILK_PART=PWRSIG

PLACE_NEAR=J601.3:30MM

R603

402

1/16W MF-LF

10K

5%

53

117

5%

R606

PLACE_NEAR=J601.1:3MM

1/16W

402

MF-LF

1K

6.8V-100PF

402

D600

PLACE_NEAR=J601.1:3MM

48

116

MF-LF

PLACE_NEAR=J601.3:3MM

1K

402

R604

1/16W

5%

PLACE_NEAR=R604.2:3MM

C604

20%

X7R-CERM 0402

0.01UF

16V

PLACE_NEAR=J601.1:4MM

402

6.8V-100PF

D601

48 71

112

PLACE_NEAR=J601.7:3MM

R600

5%

402

1/16W

1K

MF-LF

PLACE_NEAR=J601.7:3MM

D602

6.8V-100PF

402

43045-1201

CRITICAL

M-RT-TH-1

J600

PLACE_NEAR=R606.1:3MM

X7R-CERM

16V

10%

C600

0.1UF

0402

PLACE_NEAR=R600.1:3MM

16V

0402

X7R-CERM

0.1UF

10%

C605

SYNC_MASTER=D8_DOUG

Power Connectors/Aliases

SYNC_DATE=06/20/2012

PP1V8_S0

MAKE_BASE=TRUE

=PP1V8_S0_PCH_VCC_VRM =PP1V8_S0_PCH_CLK

PP1V8_S0_REG

=PP1V8_S0_CPU_PLL =PP1V8_S0_PCH =PP1V8_S0_PCH_VCC_DFTERM

=PP1V5_S0_DP

PP1V5_S0_CPU_MEM_SNS =PP1V5_S0_CPU_MEM

=PP12V_S0_FAN

=PP12V_S0_HDD_PWR

=PP12V_S0_REG_CPU_P1V05_PWR

SMC_ACDC_ID

PP12V_S0

MAKE_BASE=TRUE

=PP12V_S0_PWRCTL

=PP12V_S0_REG_P1V05_PWR

=PP12V_S0_REG_CPU_VCCSA_PWR

=PP5V_S0_VRD

MAKE_BASE=TRUE

PP5V_S0

=PP12V_S0_REG_CPUCORE

=PP12V_S0_LCD

=PP12V_S0_REG_GPUCORE

=PP12V_S0_FBVDDQ_PWR

PP12V_S0_FET =PP12V_S0_AUDIO_SPKRAMP

PP5V_S4_REG =PP5V_S4_REG_VDDQ_S3

=PP3V3_S0_VRD

TSNS_ACDC_N TSNS_ACDC_P

PWR_BTN_R

MAKE_BASE=TRUE

PP3V3_G3

MAKE_BASE=TRUE

PP12V_G3H

MAKE_BASE=TRUE

PP3V42_G3H

SMC_ACDC_ID_R

=PP3V3_G3H_LPCPLUS

=PPVIN_G3H_SMCVREF

PP3V42_G3H_REG =PP3V3_G3H_BT

=PP12V_G3H_FET_P12V_S5

=PP3V3_G3_PCH

PP12V_ACDC

MAKE_BASE=TRUE

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_VCC_GPIO

=PP3V3_S0_PCH_VCC_ADAC

=PP3V3_S0_PCH_STRAPS

PP12V_S5_FET

=PP3V3_TBT_CLK

PPVCCSA_S0_REG

PPCPUAXG_S0_REG

PPCPUCORE_S0_REG

=PP3V3_S0_SMBUS_TCON

PP3V3_S0_SSD_SNS

=PP3V3_S0_TBTPWRCTL

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC

=PP5V_S0_HDD_PWR

=PP3V3_S0_DP =PP3V3_S0_ENET =PP3V3_S0_FAN =PP3V3_S0_GPU =PP3V3_S0_INTDPMUX =PP3V3_S0_LED

=PP3V3_S0_MEM_A_SPD

=PP3V3_S0_PCH

=PP3V3_S0_PCH_VCC

PP5V_S0_HDD_SNS =PP5V_S0_HDD

=PP3V3_S0_GPU_IFPX_PLLVDD

PP3V3_S0_FET

=PP1V05_S0_GPU_IFPEF_IOVDD =PP1V05_S0_GPU_PEX_PLLVDD

=PP1V05_S0_GPU_PEX_IOVDD

=PP1V05_S0_GPU_IFPCD_IOVDD

=PP1V05_S0_PCH_PWR =PP1V05_S0_P1V05TBTFET

PP1V05_S0_REG

=PPVCCIO_S0_CPU =PPVCCIO_S0_SMC =PPVCCIO_S0_XDP

PP1V05_S0_CPU_REG

=PPVAXG_S0_CPU

=PPVCORE_S0_CPU

=PPVCCSA_S0_CPU

PPDDRVREF_DQ_MEM_B =PPDDRVREF_DQ_MEM_B

PPDDRVREF_CA_MEM_B

=PP3V3_TBTLC_RTR

PP12V_S0_REG_CPU_P1V05_SNS

=PP1V05_S0_PCH_VCCIO_DMI

=PPDDRVREF_CA_MEM_B

PP5V_S0_FET

=PP12V_S0_REG_P1V05

=PP12V_S0_REG_VCCSA

=PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B

=PP1V5_S0_CPU_MEM_PWR

=PPVCORE_S0_GPU

=PP1V05_S0_PCH_VCCIO_USB

PPDDRVREF_DQ_MEM_A

=PP3V3_S0_MEM_B_SPD

=PP3V3_S0_AUDIO =PP3V3_S0_AUDIO_DIG

PP12V_S0_REG_CPU_VCCSA_SNS

=PP5V_S0_REG_P1V05

PP12V_S0_REG_P1V05_SNS

=PPDDRVREF_CA_MEM_A

PP1V05_S0_PCH_SNS =PP1V05_S0_PCH

=PPDDRVREF_DQ_MEM_A

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCC_DIFFCLK

=PP1V05_S0_PCH_VCC_ADPLL

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCCLKDMI

=PP1V05_S0_PCH_VCC_SSC =PP1V05_S0_PCH_V_PROC_IO

=PP1V35_S0_GPU_FBVDDQ

PPGPUCORE_S0_REG

=PP3V3_S0_PCH_PM

=PP3V3_S0_P3V3TBTFET

PP1V5R1V35_S0_GPU_REG

=PP5V_S0_REG_FBVDDQ

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCC_ASW

PP1V5_S0_FET =PP1V5_S0_AUD_DIG

=PP3V3_S0_GPU_MISC =PP3V3_S0_GPU_VDD33

PP12V_S0_FBVDDQ_SNS

=PP3V3_S0_PCH_VCC_PCI

=PP3V3_S0_SDCARD

=PP3V3_S0_RSTBUF

=PP3V3_S0_SSD_PWR

=PPDDRVTT_S0_CLAMP

=PP12V_S0_REG_FBVDDQ

=PP12V_S0_BLC

=PP12V_S0_HDD

PP12V_S0_BLC_FET

PPDDRVTT_S0_LDO

PP12V_S0_HDD_SNS

=PP12V_S0_REG_CPU_P1V05

=PP3V3_S0_PWRCTL

=PP3V3_S0_PCH_VCC_HVCMOS

=PP3V3_S0_LED_SATA

PP5V_S0_HDD

MAKE_BASE=TRUE

PPDDRVTT_S0

PPDDRVREF_DQ_MEM_A_S3

MAKE_BASE=TRUE

PP1V5_S0

MAKE_BASE=TRUE

PPVCORE_S0_GPU

MAKE_BASE=TRUE

PP12V_S0_FBVDDQ

MAKE_BASE=TRUE

PP1V05_TBTLC

MAKE_BASE=TRUE

PPFBVDDQ_S0_GPU

MAKE_BASE=TRUE

PP12V_S0_CPU_P1V05

PP12V_S0_VCCSA

MAKE_BASE=TRUE

PPDDRVREF_CA_MEM_A_S3

MAKE_BASE=TRUE

PP3V3_S0_SSD

MAKE_BASE=TRUE

PP12V_S0_BLC

MAKE_BASE=TRUE

PP12V_S0_HDD

PPDDRVREF_CA_MEM_B_S3

MAKE_BASE=TRUE

PPVAXG_S0

MAKE_BASE=TRUE

PPVCCSA_S0

PPVCORE_S0_CPU

MAKE_BASE=TRUE

PP1V05_S0_CPU

MAKE_BASE=TRUE

PP1V05_S0_PCH

MAKE_BASE=TRUE

PPDDRVREF_DQ_MEM_B_S3

MAKE_BASE=TRUE

PP1V05_S0

MAKE_BASE=TRUE

PP1V5_S0_CPU_MEM

MAKE_BASE=TRUE

PP12V_S0_P1V05

MAKE_BASE=TRUE

PP3V3_TBTLC

MAKE_BASE=TRUE

=PP3V3_TBT_PCH_GPIO

=PP3V3_S0_SENSE =PP3V3_S0_SMBUS

=PP3V3_TBTLC_FET

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP1V05_TBTLC_FET

=PP3V3_S0_BLC

=PP1V05_TBTCIO_FET

PP1V05_TBTCIO

MAKE_BASE=TRUE

PPVDDQ_S3

MAKE_BASE=TRUE

PPVDDQ_S3_DDR

MAKE_BASE=TRUE

PPDDRVTT_S3

=PP5V_S4_MEMRESET

PP3V3_S4_FET =PP3V3_S4_ALS =PP3V3_S4_AP_PWR

=PP3V3_S4_ENET =PP3V3_S4_LED =PP3V3_S4_MEMRESET

=PP3V3_S4_PWRCTL

=PP3V3_S4_PM

=PP3V3_S4_SENSE

=PP3V3_S4_SMBUS_SMC =PP3V3_S4_SMC

=PP3V3_S4_TBT

PP3V3_S4_AP_SNS =PP3V3_S4_AP

PP3V3_S4_ENET_FET

=PP3V3_S4_ENET_SYSCLK

=PP3V3_S4_ENET_FET

=PP3V3_S4_ENET_CLK

PPVDDQ_S3_REG

=PPVDDQ_S3_FET_VDDQ_S0

=PPVDDQ_S3_DDR_PWR

=PPVDDQ_S3_LDO_DDRVTT

PPVDDQ_S3_DDR_SNS =PPVDDQ_S3_DDR_VREF =PPVDDQ_S3_MEM_A =PPVDDQ_S3_MEM_B =PPVDDQ_S3_MEMRESET

PPDDRVTT_S3_LDO =PPDDRVTT_S3_VREFCA

PP3V3_G3_RTC =PP3V3_G3_PCH_RTC

=PP12V_G3H_PWR

PP12V_G3H_SNS =PP12V_G3H_P3V42

=PP12V_S5_REG_P3V3P5V_S5 =PP12V_S5_REG_VDDQ_S3

=PP5V_S0_REG_CPU_P1V05

=PP5V_S0_REG_CPUCORE

=PP5V_S0_LPCPLUS

=PP5V_S0_ISENSE

=PP5V_S0_PCH

=PP5V_S0_REG_P1V8 =PP5V_S0_REG_VCCSA

=PP5V_S0_AUDIO =PP5V_S0_BLC

BURSTMODE_EN_R_L

PPDDRVREF_CA_MEM_A

=PP3V3_S0_SSD

=PP3V3_S0_VRD

PP3V3_S0

MAKE_BASE=TRUE

PP5V_S4

PP12V_G3H_ACDC

MAKE_BASE=TRUE

PP3V3_S4_ENET

=PP3V3_S4_CAMERA

=PP5V_S4_USB

=PP5V_S4_FET_P5V_S0

=PP5V_S4_CAMERA

PP3V3_S4_AP

MAKE_BASE=TRUE

PP12V_G3H_ACDC

=PP12V_S5_PWRCTL =PPHV_SW_TBTAPWRSW

MAKE_BASE=TRUE

PP3V3_S5

=PP5V_S5_PWRCTL

PP5V_S5_LDO

=PP5V_S5_PCH

PP3V3_S5_REG =PP3V3_S5_FET_P3V3_S0 =PP3V3_S5_FET_P3V3_S4 =PP3V3_S5_SMC =PP3V3_S5_LED

=PP3V3_S5_PCH_STRAPS

=PP3V3_S5_PCH

=PP3V3_S5_PCH_VCCSUS_HDA

=PP3V3_S5_PCH_VCC_DSW

=PP3V3_S5_PCH_VCCSUS_USB

=PP3V3_S5_PWRCTL =PP3V3_S5_ROM

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S5_VRD =PP3V3_S5_XDP =PP3V3_S5_SMC_USBMUX

=PP3V3_S5_SDCARD

=PP3V3_S5_SENSE

=PPHV_SW_TBTBPWRSW =PP12V_S5_SNS

PP12V_S5

MAKE_BASE=TRUE

=PP3V3_G3H_SMC_USBMUX

=PP3V3_G3H_SMC

MAKE_BASE=TRUE

PP5V_S5

=PP3V3_G3H_RTC_D

=PP12V_G3H_FET_P12V_S0

PP12V_G3H_ACDC

PWR_BTN

BURSTMODE_EN_L

=PP3V3_S4_SMBUS

=PP3V3_S4_USB_HUB

=PP3V3_S4_TBTAPWRSW =PP3V3_S4_TBTBPWRSW

=PP3V3_S4_VREFMRGN =PP3V3_S4_AUDIO_DIG

MAKE_BASE=TRUE

PP3V3_S4

GND

MAKE_BASE=TRUE

prefsb

051-9504

7.0.0

6 OF 143

6 OF 117

2

1

2

1

2

1

8

9

4

2

3

5

6

7

1

2

12

1

2

12

2

1

2

12

1

2

1

2

3

4

5

6

12

7

8

10

11

9

2

1

2

1

106

24

26

72

13 16

19

22 24

84

51

11 13 16

54

51

55

48

116

106

65

55

72 92

106

67

87

92

51

74

58 59

71

72

6

66 69 70 72 92 95

116

106

6

116

6

116

49

48

73

35

74

18 19

106

15 19 20 38

22 24

17

15

74

26

70

17 68

67 68

50

51

38

48 51 82

50

51

85 87

39

54

78 92

84

5

29 30

18 21 24

22 24

51

52

78

74

78

51

38

95

10 11 13 16 28 66

48

25

69

13 17 51 66

13 16 51 66

13 16

34

31 32

34

15 36 37 38 50

55

22 24

31 32

74

95

70

29 30

31 32

51

51 78

22 24

34

31 32

42 56 58 59 62

60

55

95

55

29 30

51

18 29 30

22 24

17

18 22 24

18 19 22 24

22 24

78

93 94

26

38

95

110

95

22 24

74

56

78

51

22 24

41

26

51

28

95

91

52

74

72

51

69

28 74

22 24

15 44

106

110

106

38

104

106

105

104

105

104

106

104

106

15

51 52 53 55

50

38

37

38

89

38

104

106

28

74

42

55

40

5

28

65 72 74

28

51

50

48

36 37 38 86 88

55

15 35

40

26

39 40

26

72

74

51

72

51

34

29 30

31 32

28

72

34

26

115

22

51

73

71

72

69

66

49

51

24

72

70

56 63

91

34

44

6

66 69 70 72 92 95

106

6

106

42 43

45 46

74

42

106

6

64 65 74

86

106

71

24

71

74

48

5

15

19 24 26

22 24

64 65

49

22 24

71

25

45 46

41

51

88

51

106

45

47 48 50

106

26

74

6

50

27

48 86

48 88

34

60

106

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU HEATSINK MOUNTING FEATURES

(998-5013. PLATED HOLE, 3.2MM DIA, 6MM PAD TOP/BOT)

998-4640 (PLATED HOLES, 10MM DIA, 12MM PAD)

HEATPIPE MTG HOLES

WIRELESS CARD MTG HOLES

998-4938 (PLATED HOLES, 1.9MM INNER DIAMETER, 4.3MM PAD)

APN: 860-1461

860-1487 (PCB STANDOFF)

SSD STANDOFF

Rear Cover

998-5014 (PLATED HOLES, 4MM DRILL, 8.5MM TOP, 8MM BOT)

4MM PLATED HOLES (998-4158)

CPU Heatsink

ZH0700

8P5R5-NSP

OMIT

8P5R5-NSP

OMIT

ZH0701 ZH0702

8P5R5-NSP

OMIT

8P5R5-NSP

OMIT

ZH0703

STDOFF-4.5OD2.2ID-5.6H-SM

NUT0713

CRITICAL

ZH0715

STDOFF-7.14OD16.45H-TH-1.5-5.2

CRITICAL

STDOFF-7.14OD16.45H-TH-1.5-5.2

CRITICAL

ZH0718

ZH0722

CRITICAL

5P5R1P9-4P3B-NSP

CRITICAL

5P5R1P9-4P3B-NSP

ZH0721

10R12

ZH0726

6P0R3P2-NSP

CRITICAL

ZH0725

CRITICAL

6P0R3P2-NSP

ZH0724

6P0R3P2-NSP

CRITICAL

ZH0723

ZH0717

8P5R4P0-8P0B-NSP

CRITICAL

ZH0716

8P5R4P0-8P0B-NSP

CRITICAL

8P5R4P0-8P0B-NSP

ZH0714

CRITICAL

8P5R4P0-8P0B-NSP

ZH0713

CRITICAL

ZH0720

6P0R3P2-NSP

SYNC_MASTER=D8_MLB

Holes/PD parts

SYNC_DATE=03/25/2012

prefsb

051-9504

7.0.0

7 OF 143

7 OF 117

1111

1

11

1

11

1

11

1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH Clocks

PCH PCIe

PCH USB

CPU Memory

PCH PCI

PCH Unused Display

PCH Test Points

PCH SATA

PCH and CPU FDI

PCH Miscellaneous

CPU Reserved

PCH Reserved

SYNC_DATE=04/02/2012

Unused Signal Aliases

SYNC_MASTER=D8_MLB_ULTIMATE

TP_MEM_A_DQS_P<8>

TP_MEM_A_DQ_CB<7..0>

NC_DMI_MIDBUS_CLK100NX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE2_R2D_CNX

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE2_R2D_CN

TP_PCIE2_R2D_CP

TP_PCI_CLK33M_OUT2

TP_PCI_CLK33M_OUT3

TP_PCH_PWM3

TP_PCH_SST

TP_PCH_RESERVE_0

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_C_AUXNX

DP_IG_C_MLP<3..0>

NC_PCIE_CLK100M_PE5NX

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P

DMI_MIDBUS_CLK100M_N

NC_DMI_MIDBUS_CLK100PX

MAKE_BASE=TRUE

NO_TEST=TRUE

DMI_MIDBUS_CLK100M_P

TP_PCIE_CLK100M_PE0N

TP_PCIE2_D2RP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PE_TNX<3..0>

DP_IG_D_CTRL_DATA

DP_IG_D_HPD

TP_PCIE1_D2RN

TP_PCIE1_R2D_CN

TP_MEM_B_DQ_CB<7..0>

CPU_CFG<15..12>

TP_CPU_RSVD<46..19>

TP_CPU_RSVD<16..1>

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_D_D2RN

TP_SATA_E_D2RN

TP_SATA_F_R2D_CN

TP_MEM_A_DQS_N<8>

TP_PCH_PWM0

TP_HDA_SDIN2

PCH_FDI_FSYNC<1..0>

PCH_FDI_LSYNC<1..0>

PCH_FDI_INT

PCH_FDI_RX_N<7..0>

PCH_FDI_RX_P<7..0>

TP_CPU_FDI_TX_N<7..0>

TP_CPU_FDI_TX_P<7..0>

TP_SDVO_STALLP

TP_SDVO_INTN

TP_CPU_FDI_FSYNC<1..0>

TP_CPU_FDI_LSYNC<1..0>

TP_CPU_FDI_INT

TP_PCH_CL_DATA1

TP_PCH_CL_CLK1

TP_HDA_SDIN3

TP_PCH_RESERVE_8

TP_PCH_L_VDD_EN

TP_PCH_L_BKLTEN

TP_PCH_RESERVE_27

TP_PCH_RESERVE_25

DP_IG_C_MLN<3..0>

DP_IG_B_DDC_DATA

DP_IG_C_AUX_N

TP_SDVO_INTP

TP_PCH_CL_RST1

TP_PCH_PWM2

TP_PCH_PWM1

TP_PCH_RESERVE_20

TP_PCH_RESERVE_23

TP_PCH_RESERVE_7

TP_PCH_RESERVE_19

TP_PCH_RESERVE_21

TP_PCH_RESERVE_28

TP_PCH_RESERVE_24

TP_PCH_RESERVE_17

TP_PCH_RESERVE_18

TP_PCH_RESERVE_15

TP_PCH_RESERVE_16

TP_PCH_RESERVE_14

TP_PCH_RESERVE_13

TP_PCH_RESERVE_12

TP_PCH_RESERVE_10

TP_PCH_RESERVE_11

TP_PCH_RESERVE_9

TP_PCH_RESERVE_5

TP_PCH_RESERVE_6

TP_PCH_RESERVE_3

TP_PCH_RESERVE_4

TP_SDVO_TVCLKINP

DP_IG_C_AUX_P

DP_IG_C_CTRL_CLK

TP_PCH_L_BKLTCTL

TP_SDVO_STALLN

DP_IG_D_MLP<3..0>

TP_SDVO_TVCLKINN

DP_IG_D_AUXN

DP_IG_D_AUXP

DP_IG_D_MLN<3..0>

TP_SATA_F_D2RP

TP_CRT_IG_DDC_DATA

TP_CRT_IG_VSYNC

TP_CRT_IG_BLUE

TP_CRT_IG_RED

TP_CRT_IG_GREEN

TP_SATA_E_R2D_CP

TP_SATA_C_D2RN

TP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_PCH_TP20

TP_PCH_TP19

TP_PCH_TP18

TP_PCH_TP17

TP_PCH_TP16

TP_PCH_TP15

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP12

TP_PCH_TP11

TP_PCH_TP10

TP_PCH_TP9

TP_PCH_TP8

TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5

TP_PCH_TP4

TP_PCH_TP3

TP_SATA_D_D2RP

TP_PCH_TP2

TP_SATA_C_R2D_CP

TP_SATA_E_D2RP

DP_IG_C_HPD

DP_IG_D_CTRL_CLK

DP_IG_C_CTRL_DATA

TP_LPC_DREQ0_L

TP_PCH_INIT3V3_L

TP_HDA_SDIN1

TP_CRT_IG_HSYNC

TP_SATA_F_R2D_CP

TP_PCH_RESERVE_22

TP_PCH_RESERVE_26

TP_SATA_E_R2D_CN

TP_PCH_TP1

TP_SATA_F_D2RN

DP_IG_B_DDC_CLK

TP_PCI_AD<31..0>

TP_PCI_C_BE_L<3..0>

TP_PCI_PAR

TP_PCI_RESET_L

TP_PCH_PCI_GNT0_L

TP_PCH_RESERVE_2

TP_PCH_RESERVE_1

DP_IG_B_AUX_P

DP_IG_B_MLN<3..0>

DP_IG_B_MLP<3..0>TP_MEM_B_DQS_N<8>

TP_MEM_B_DQS_P<8>

DP_IG_B_HPD

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE7P

TP_PE_TX_N<3..0>

TP_PE_RX_N<3..0>

TP_PE_TX_P<3..0>

TP_PE_RX_P<3..0>

USB_PCH_4_P

USB_PCH_6_N

USB_PCH_6_P

USB_PCH_11_P

USB_PCH_12_P

USB_PCH_12_N

USB_PCH_13_P

USB_PCH_13_N

TP_PCH_CLKOUT_DPP

TP_PCIE_CLK100M_PE7N

TP_PCIE2_D2RN

TP_PCIE1_D2RP

TP_CRT_IG_DDC_CLK

TP_PCIE1_R2D_CP

DP_IG_B_AUX_N

MAKE_BASE=TRUE

NC_PCIE2_R2D_PNX

NO_TEST=TRUE

NC_PCIE1_D2RNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_DQSNX<8>

MAKE_BASE=TRUE

NC_CPU_RSVD<46..19>

NO_TEST=TRUE

NC_PCH_RESERVE_6

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_C_R2D_CNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_R2D_CNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_PWM0

NC_HDA_SDIN3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_FDI_INT

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_TVCLKINNX

MAKE_BASE=TRUE

NC_PCH_FDI_FSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_AUXPX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_FDI_LSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_RPX<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_FDI_RNX<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_FDI_TPX<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_L_BKLTEN

NC_PCH_L_VDD_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_CLK33M_OUT2

MAKE_BASE=TRUE

NC_PCH_CL_CLK1

NO_TEST=TRUE

NC_PCH_L_BKLTCTL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_CL_RST1

NO_TEST=TRUE

NC_PCH_CL_DATA1

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_SST

MAKE_BASE=TRUE

NC_PCH_PWM3

NO_TEST=TRUE

NC_PCH_PWM2

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_PWM1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_AUXNX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_MLPX<3..0>

NC_PCH_FDI_LSYNC<1..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_FDI_INT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_FDI_TNX<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_17

NO_TEST=TRUE

NC_PCH_RESERVE_18

MAKE_BASE=TRUE

NC_PCH_RESERVE_14

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_13

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_12

MAKE_BASE=TRUE

NC_PCH_RESERVE_10

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_11

NC_PCH_RESERVE_9

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_8

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_7

MAKE_BASE=TRUE

NC_PCH_RESERVE_5

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_RESERVE_4

MAKE_BASE=TRUE

NC_PCH_RESERVE_2

NO_TEST=TRUE

NC_PCH_RESERVE_0

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_1

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_STALLNX

NC_DP_IG_C_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_CTRL_CLK

MAKE_BASE=TRUE

NC_DP_IG_D_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_D_MLNX<3..0>

NO_TEST=TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_MLPX<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_MLNX<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RPX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_F_R2D_CPX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_CTRL_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_MLPX<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DP_IG_B_MLNX<3..0>

NC_CRT_IG_DDC_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_BLUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NC_CRT_IG_RED

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_GREEN

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_E_D2RNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_E_R2D_CPX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_D2RPX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_D_R2D_CPX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_C_D2RNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_C_D2RPX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP19

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP16

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP14

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP11

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP9

MAKE_BASE=TRUE

NC_PCH_TP8

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP6

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP5

MAKE_BASE=TRUE

NC_PCH_TP4

NO_TEST=TRUE

NC_PCH_TP1

MAKE_BASE=TRUE

NC_PCH_TP2

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP3

NC_CRT_IG_DDC_DATA

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_C_AUXPX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_AUXPX

NC_PCI_AD<31..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCI_PAR

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

NC_PCI_RESET_L

NO_TEST=TRUE

NC_PCI_GNT0_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LPC_DREQ0_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_INIT3V3_L

NC_HDA_SDIN1

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_HDA_SDIN2

MAKE_BASE=TRUE

NC_CPU_RSVD<16..1>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_STALLPX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_INTNX

MAKE_BASE=TRUE

NC_MEM_A_DQ_CB<7..0>

NO_TEST=TRUE

NC_MEM_B_DQ_CB<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SDVO_TVCLKINPX

MAKE_BASE=TRUE

NC_SDVO_INTPX

NO_TEST=TRUE

NC_PCH_RESERVE_27

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_16

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_15

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RPX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_F_R2D_CNX

NO_TEST=TRUE

NC_PCH_RESERVE_19

MAKE_BASE=TRUE

NC_PCH_RESERVE_20

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_21

MAKE_BASE=TRUE

NC_PCH_RESERVE_22

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_E_R2D_CNX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_23

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_24

NO_TEST=TRUE

NC_PCH_RESERVE_25

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_26

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_RESERVE_28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_TP20

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_CTRL_DATA

MAKE_BASE=TRUE

NC_MEM_A_DQSNX<8>

NO_TEST=TRUE

NC_MEM_A_DQSPX<8>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_IG_B_AUXNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_C_R2D_CPX

MAKE_BASE=TRUE

TP_CPU_CFG<15..12>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_DQSPX<8>

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4PX

NO_TEST=TRUE

NC_PCIE_CLK100M_PE4NX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5PX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6NX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE6PX

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7PX

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE7NX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PE_RNX<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PE_TPX<3..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PE_RPX<3..0>

NC_USB_PCH_4NX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_4PX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_5PX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_5NX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_6NX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_6PX

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_PCH_11PX

NC_USB_PCH_11NX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_12PX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_12NX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_13PX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_PCH_13NX

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_CLKOUT_DPNX

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE2_D2RNX

NO_TEST=TRUE

NC_PCIE2_D2RPX

MAKE_BASE=TRUE

NC_PCIE1_D2RPX

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE1_R2D_CNX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE1_R2D_CPX

TP_PCIE_CLK100M_PE5P

NC_PCH_CLKOUT_DPPX

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCH_CLKOUT_DPN

USB_PCH_4_N

USB_PCH_5_N

USB_PCH_5_P

USB_PCH_11_N

NO_TEST=TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0TP_PCH_GPIO64_CLKOUTFLEX0

PCH_CLK25M_XTALOUT

NO_TEST=TRUE

NC_PCH_CLK25M_XTALOUT

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE0PX

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_PE0NX

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE0P

prefsb

051-9504

7.0.0

8 OF 143

8 OF 117

12

18

20

21

19

18

21

18

19

18

12

10

18

12

21

18

19

10

19

10

18

19

18

19

18

21

19

18

19

18

19

18

21

18

21 18

18

19

18

19

18

19

18

19

18

21

18

19

20

19

19 12

12

19

21

10

20

18

21

18

19

18

19

18

20

18

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ALIASES (BLANK)

SYNC_MASTER=K70_MLB

SYNC_DATE=08/23/2011

Signal Aliases

prefsb

051-9504

7.0.0

9 OF 143

9 OF 117

IN

OUT

IN

OUT

IN

DMI_TX_1*

PE_TX_3*

PE_TX_3

PE_TX_2*

PE_TX_2

PE_TX_1*

PE_TX_1

PE_TX_0*

PE_TX_0

PE_RX_3*

PE_RX_3

PE_RX_2*

PE_RX_2

PE_RX_1*

PE_RX_1

PE_RX_0*

PE_RX_0

PEG_TX_15*

PEG_TX_15

PEG_TX_14*

PEG_TX_14

PEG_TX_13*

PEG_TX_13

PEG_TX_12*

PEG_TX_12

PEG_TX_11*

PEG_TX_11

PEG_TX_10*

PEG_TX_10

PEG_TX_9*

PEG_TX_9

PEG_TX_8*

PEG_TX_8

PEG_TX_7*

PEG_TX_7

PEG_TX_6

PEG_TX_5*

PEG_TX_5

PEG_TX_4*

PEG_TX_4

PEG_TX_3*

PEG_TX_3

PEG_TX_2*

PEG_TX_2

PEG_TX_1*

PEG_TX_1

PEG_TX_0*

PEG_TX_0

PEG_RX_15*

PEG_RX_15

PEG_RX_13*

PEG_RX_12

PEG_RX_11*

PEG_RX_11

PEG_RX_10

PEG_RX_9

PEG_RX_8

PEG_RX_7

PEG_RX_6

PEG_RX_5

PEG_RX_4*

PEG_RX_4

PEG_RX_3*

PEG_RX_3

PEG_RX_2

PEG_RX_1*

PEG_RX_0

FDI_TX_7*

FDI_TX_7

FDI_TX_6*

FDI_TX_6

FDI_TX_5*

FDI_TX_5

FDI_TX_4*

FDI_TX_4

FDI_TX_3*

FDI_TX_3

FDI_TX_2*

FDI_TX_2

FDI_TX_1*

FDI_TX_1

FDI_TX_0*

FDI_TX_0

FDI_LSYNC_1

FDI_LSYNC_0

FDI_FSYNC_1

FDI_FSYNC_0

DMI_TX_3*

DMI_TX_3

DMI_TX_2*

DMI_TX_2

DMI_TX_1

DMI_TX_0*

DMI_TX_0

DMI_RX_3*

DMI_RX_3

DMI_RX_2*

DMI_RX_2

DMI_RX_1

DMI_RX_0*

FDI_COMPIO FDI_ICOMPO

FDI_INT

PEG_COMPI

PEG_ICOMPO

PEG_RX_1

PEG_RX_14*

PEG_RX_12*

PEG_RX_6*

PEG_RX_13 PEG_RX_14

PEG_RCOMPO

PEG_RX_10*

PEG_RX_9*

PEG_RX_8*

PEG_RX_7*

PEG_RX_2*

PEG_RX_0*

PEG_RX_5*

PEG_TX_6*

DMI_RX_0

DMI_RX_1*

SYM 1 OF 10

FLEXIBLE DISPLAY INTERFACE

PCI EXPRESS -- GRAPHICS

DMI

PCI EXPRESS

RSVD_NCTF_AV1 RSVD_NCTF_AW2 RSVD_NCTF_AY3

RSVD_NCTF_B39

NCTF_AW38

NCTF_AU40

NCTF_D1

NCTF_C2

NCTF_A38

CFG_8

RSVD_J34

RSVD_J33

RSVD_J31

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7

CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17

RSVD_K9 RSVD_K31 RSVD_K34 RSVD_L9 RSVD_L31 RSVD_L33 RSVD_L34 RSVD_M34 RSVD_N33 RSVD_N34

RSVD_P35 RSVD_P37 RSVD_P39 RSVD_R34 RSVD_R36 RSVD_R38 RSVD_R40 RSVD_AB6

RSVD_AB7 RSVD_AD34 RSVD_AD35 RSVD_AD37

RSVD_AE6

RSVD_AF4

RSVD_AG4 RSVD_AJ11 RSVD_AJ29 RSVD_AJ30 RSVD_AJ31 RSVD_AN20 RSVD_AP20 RSVD_AT11 RSVD_AT14 RSVD_AU10 RSVD_AV34 RSVD_AW34 RSVD_AY10

RSVD_J9

RSVD_H8

RSVD_H7

RSVD_C38

RSVD_D38

RSVD_C39

SYM 5 OF 10

RESERVED

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Available for Workstation only)

CFG [6:5] PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = 1 X8, 2 X4

CFG [3] PCIE STATIC X4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [1:0] RESERVED CONFIGURATION LANE

( IVY BRIDGE EDS #473717 TABLE 6-5 )

CFG [17:7] RESERVED CONFIGURATION LANE

CFG [4] RESERVED CONFIGURATION LANE

INTEL SUGGESTS TO KEEP THESE TPS

ThermDA

ThermDC

(Unused)

ROUTE B5 TO R1010.1 AS A SEPERATE 12 MIL TRACE.

SHORT B4 & C4 TOGETHER, ROUTE AS A SINGLE 4 MIL TRACE TO R1010.1

CFG [2] PCIE STATIC X16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

19 99

75 98

402

MF-LF

24.9

1%

PLACE_NEAR=U1000.B4:12.7MM

R1010

1/16W

25 99

8

25 99

15 25 99

25 99

15 25 99

25 99

BGA-SKT-K70

IVY-BRIDGE

OMIT_TABLE

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

U1000

PLACE_NEAR=U1000.AE2:6.3MM

MF-LF

1/16W

402

5%

0

R1011

CPU DMI/PEG/FDI/RSVD

SYNC_DATE=03/23/2012

SYNC_MASTER=D8_ROSITA

CPU_FDI_COMPIO

TP_PE_TX_P<3>

TP_PE_TX_P<2>

TP_CPU_FDI_TX_N<2>

PEG_D2R_C_P<5>

CPU_PEG_COMP

PEG_D2R_C_N<1> PEG_D2R_C_N<2> PEG_D2R_C_N<3>

=PPVCCIO_S0_CPU

PEG_D2R_C_P<3>

PEG_D2R_C_N<12>

PEG_D2R_C_N<11>

PEG_D2R_C_N<5>

CPU_CFG<7>

TP_PE_RX_P<1>

TP_CPU_FDI_TX_P<7>

TP_CPU_FDI_TX_P<2>

TP_PE_RX_N<0>

TP_PE_RX_N<3>

TP_PE_RX_P<2>

PEG_R2D_P<14>

TP_CPU_FDI_TX_P<4>

PEG_D2R_C_P<14>

TP_PE_TX_P<0>

DMI_S2N_N<3>

DMI_S2N_N<0>

PEG_R2D_P<11>

PEG_R2D_P<13>

PEG_R2D_P<7>

PEG_D2R_C_N<15>

PEG_D2R_C_P<0>

DMI_S2N_P<2>

DMI_N2S_P<2>

PEG_D2R_C_N<8>

CPU_CFG<15>

PEG_D2R_C_N<4>

CPU_CFG<0>

CPU_CFG<3>

TP_CPU_RSVD<16>

PEG_D2R_C_N<14>

PEG_D2R_C_P<2>

PEG_D2R_C_N<6>

DMI_S2N_P<1>

TP_CPU_FDI_TX_N<6>

PEG_R2D_P<0>

DMI_N2S_N<0>

TP_CPU_FDI_TX_N<3>

TP_CPU_RSVD<30>

DMI_N2S_N<2>

PEG_D2R_C_N<13>

TP_CPU_FDI_FSYNC<1>

TP_PE_RX_P<0>

TP_PE_TX_N<0>

DMI_N2S_P<1>

DMI_N2S_N<1>

PEG_R2D_P<3>

PEG_R2D_P<2>

PEG_R2D_P<1>

DMI_N2S_P<3>

PEG_R2D_N<0>

PEG_D2R_C_P<7>

PEG_D2R_C_P<15>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<14>

DMI_S2N_N<1>

DMI_S2N_P<3>

TP_CPU_FDI_LSYNC<0>

TP_CPU_FDI_TX_P<5>

PEG_R2D_P<12>

PEG_R2D_N<10>

TP_CPU_FDI_TX_P<0>

TP_PE_TX_N<2>

CPU_CFG<12>

CPU_CFG<9>

CPU_CFG<6>

TP_CPU_RSVD<8>

PEG_D2R_C_P<11>

PEG_R2D_P<5>

PEG_R2D_P<8>

PEG_R2D_N<14>

TP_PE_TX_P<1>

TP_CPU_RSVD<2> TP_CPU_RSVD<3>

TP_CPU_RSVD<1>

TP_CPU_RSVD<4>

TP_CPU_RSVD<46>

TP_CPU_RSVD<40>

TP_CPU_RSVD<39>

TP_CPU_RSVD<38>

TP_CPU_RSVD<37>

TP_CPU_RSVD<35>

TP_CPU_RSVD<34>

TP_CPU_RSVD<33>

TP_CPU_RSVD<32>

TP_CPU_RSVD<31>

TP_CPU_RSVD<28>

TP_CPU_RSVD<27>

TP_CPU_RSVD<25>

TP_CPU_RSVD<24>

TP_CPU_RSVD<23>

TP_CPU_RSVD<22>

TP_CPU_RSVD<21>

TP_CPU_RSVD<20>

CPU_CFG<11>

CPU_CFG<10>

CPU_CFG<4>

TP_CPU_RSVD<7>

TP_CPU_RSVD<9>

TP_CPU_NCTF<1> TP_CPU_NCTF<2>

TP_CPU_NCTF<4>

CPU_CFG<13>

CPU_CFG<8>

TP_CPU_RSVD<15>

TP_CPU_RSVD<14>

TP_CPU_RSVD<13>

TP_CPU_RSVD<12>

TP_CPU_RSVD<10>

TP_CPU_RSVD<5> TP_CPU_RSVD<6>

TP_CPU_RSVD<26>

TP_PE_TX_N<1>

TP_CPU_FDI_TX_P<1>

DMI_S2N_P<0>

TP_CPU_RSVD<36>

TP_CPU_RSVD<43>

TP_CPU_NCTF<3>

TP_CPU_NCTF<5>

TP_CPU_RSVD<29>

PEG_R2D_P<10>

PEG_R2D_P<9>

TP_CPU_RSVD<19>

TP_CPU_RSVD<45>

TP_CPU_RSVD_NCTF<4>

TP_CPU_RSVD_NCTF<3>

TP_CPU_RSVD_NCTF<2>

TP_CPU_RSVD_NCTF<1>

TP_CPU_RSVD<44>

TP_CPU_RSVD<42>

TP_CPU_RSVD<41>

CPU_CFG<2>

CPU_CFG<1>

DMI_N2S_N<3>

TP_CPU_FDI_TX_P<3>

TP_CPU_FDI_TX_N<4>

PEG_R2D_N<1>

TP_PE_RX_P<3>

TP_CPU_FDI_INT

TP_CPU_FDI_TX_N<0> TP_CPU_FDI_TX_N<1>

PEG_D2R_C_N<9> PEG_D2R_C_N<10>

PEG_R2D_N<2>

PEG_R2D_N<15>

PEG_R2D_P<6>

TP_CPU_FDI_LSYNC<1>

TP_CPU_FDI_FSYNC<0>

TP_CPU_FDI_TX_P<6>

PEG_D2R_C_P<12>

PEG_R2D_N<5>

TP_CPU_RSVD<11>

PEG_D2R_C_N<7>

TP_CPU_FDI_TX_N<5>

PEG_D2R_C_P<4>

PEG_D2R_C_P<1>

PEG_R2D_N<4>

PEG_R2D_P<4>

TP_PE_TX_N<3>

PEG_R2D_P<15>

PEG_R2D_N<13>

PEG_R2D_N<8>

PEG_R2D_N<6>

DMI_N2S_P<0>

PEG_R2D_N<12>

PEG_R2D_N<11>

PEG_R2D_N<9>

PEG_D2R_C_P<6>

PEG_D2R_C_P<9>

PEG_D2R_C_P<8>

DMI_S2N_N<2>

PEG_R2D_N<3>

PEG_R2D_N<7>

TP_CPU_FDI_TX_N<7>

PEG_D2R_C_P<10>

PEG_D2R_C_P<13>

NC_SNS_CPU_THERMDP

NO_TEST=TRUE

NC_SNS_CPU_THERMDN

NO_TEST=TRUE

CPU_CFG<5>

PEG_D2R_C_N<0>

TP_PE_RX_N<2>

TP_PE_RX_N<1>

prefsb

051-9504

7.0.0

10 OF 143

10 OF 117

12

W8

U6

U5

R5

R6

T8

T7

P7

P8

U1

U2

T3

T4

R1

R2

P4

P3

N6

N5

L5

L6

M7

M8

J6

J5

K8

K7

G6

G5

G9

G10

F7

F8

E5

E6

D3

D7

D8

J13

J14

F11

F12

G13

G14

E13

E14

C14

C13

N2

N1

L2

K3

J2

J1

H3

G2

F4

E2

A5

C6

B7

B8

E9

E10

C10

D11

B11

AG1

AG2

AF2

AF3

AE8

AE7

AD6

AD7

AD3

AD4

AD1

AD2

AC3

AC2

AC7

AC8

AE4

AC4

AE5

AC5

AA8

AA7

Y7

Y6

W7

V6

V7

AA5

AA4

Y4

Y3

V3

W4

AE2 AE1

AG3

B4 B5

D12

M4

K4

A6

L1 M3

C4

H4

G1

F3

E1

C9

B12

C5

C3

W5

V4

AV1 AW2 AY3 B39

AW38

AU40

D1

C2

A38

J38

J34

J33

J31

H36 J36 J37 K36 L36 N35 L37 M36

L35 M38 N36 N38 N39 N37 N40 G37 G36

K9 K31 K34

L9 L31 L33 L34 M34 N33 N34

P35 P37 P39 R34 R36 R38 R40 AB6 AB7 AD34 AD35 AD37 AE6 AF4 AG4 AJ11 AJ29 AJ30 AJ31 AN20 AP20 AT11 AT14 AU10 AV34 AW34 AY10

J9

H8

H7

C38

D38

C39

1

2

99

8

98

6

11 13 16 28 66

8

BI

IN

OUT

IN

OUT

BI

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM[0]* BPM[1]* BPM[2]* BPM[3]* BPM[4]* BPM[5]* BPM[6]* BPM[7]*

TCK

PRDY*

BCLK_ITP

BCLK_0

BCLK_ITP*

BCLK_0*

UNCOREPWRGOOD

SKTOCC*

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

PROC_SEL

SYM 2 OF 10

CLOCKS

THERMAL

DDR3 MISC

PWR MGMT

JTAG & BPM

OUT

IN

OUT

IN

OUT

IN

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BASED ON INTEL MOBILE SOLUTION

FROM PCH

25 99

R1111

1/16W

5%

402

MF-LF

1K

19 28 99

21 25 28 99

34

106

34

106

28 99

15 99

19 99

48 99

47 48 66 99

21 47 48 99

R1124

1/16W

5%

402

75

PLACE_NEAR=U1000.F36:50mm

MF-LF

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

R1141

1/16W

1%

1K

402

MF-LF

R1140

1/16W

1%

402

MF-LF

1K

10% X7R-CERM

16V

0.1UF

C1140

0402

48 99

R1102

MF-LF

5%

0

1/16W

402

R1101

1/16W

5%

402

MF-LF

51

25 99

R1120

1/16W

1%

402

MF-LF

200

R1121

130

MF-LF

402

1%

1/16W

18 99

19 99

R1125

402

1/16W

5%

MF-LF

43

26 99

64 99

25 99

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

CPU CLOCK/MISC/JTAG

CPU_DDR_VREF

=PP1V5_S0_CPU_MEM

DMI_CLK100M_CPU_N

ITPCPU_CLK100M_N

DMI_CLK100M_CPU_P

ITPCPU_CLK100M_P

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_PREQ_L

=PP1V5_S0_CPU_MEM

=PPVCCIO_S0_CPU

PM_MEM_PWRGD_R

CPU_DDR_VREF

PM_MEM_PWRGD

CPU_RESET_L

CPU_DIMM_VREF_DAC_A

CPU_DIMM_VREF_DAC_B

CPU_MEM_RESET_L

PLT_RESET_LS1V05_L

PM_SYNC

CPU_PWRGD

CPU_THRMTRIP_L

CPU_PECI

CPU_CATERR_L

CPU_PROC_SEL

CPU_SKTOCC_L

CPU_PROCHOT_R_L

=PPVCCIO_S0_CPU

CPU_PROCHOT_L

prefsb

051-9504

7.0.0

11 OF 143

11 OF 117

1

2

1

2

AH4

AH1

AJ22

AW18

AJ19

E38

K40

L38 J39

L40 L39

E39

H40 H38 G38 G40 G39 F38 E40 F40

M40

K38

C40

W2

D40

W1

J40

AJ33

F36

G35

E37

J35

H34

K32

1

2

1

2

1

12

1

2

1

2

12

11

106

6

11 13 16

6

11 13 16

6

10 11 13 16 28 66

99

11

106

99

6

10 11 13 16 28 66

BI

OUT

BI

OUT

BI

OUT

BI

OUT

OUT OUT

SA_DQ_32 SA_DQ_33

SA_DQS_8*

SA_BS_2

SA_CAS*

SA_BS_1

SA_BS_0

SA_DQ_63

SA_DQ_62

SA_DQ_61

SA_DQ_60

SA_DQ_9

SA_CK_1

SA_ODT_2

SA_ODT_1

SA_ODT_0

SA_RAS* SA_WE*

SA_CK_0

SA_CK_0*

SA_CK_1*

SA_CK_2

SA_CK_2*

SA_CK_3

SA_CK_3*

SA_CKE_0

SA_CKE_1

SA_CKE_2

SA_CKE_3

SA_CS_0* SA_CS_1* SA_CS_2* SA_CS_3*

SA_DQ_0 SA_DQ_1

SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19

SA_DQ_2

SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29

SA_DQ_3

SA_DQ_30 SA_DQ_31

SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39

SA_DQ_4

SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49

SA_DQ_5

SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59

SA_DQ_6 SA_DQ_7 SA_DQ_8

SA_DQS_0

SA_DQS_0*

SA_DQS_1

SA_DQS_1*

SA_DQS_2

SA_DQS_2*

SA_DQS_3

SA_DQS_3*

SA_DQS_4

SA_DQS_4*

SA_DQS_5

SA_DQS_5*

SA_DQS_6

SA_DQS_6*

SA_DQS_7

SA_DQS_7*

SA_DQS_8

SA_ECC_CB_0 SA_ECC_CB_1 SA_ECC_CB_2 SA_ECC_CB_3 SA_ECC_CB_4 SA_ECC_CB_5 SA_ECC_CB_6 SA_ECC_CB_7

SA_MA_0 SA_MA_1

SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 SA_MA_15

SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

SA_ODT_3

SYM 3 OF 10

DDR SYSTEM MEMORY A

SB_CK_1*

SB_DQS_3*

SB_DQ_33

SB_DQS_4

SB_DQS_2

SB_DQS_8*

SB_CKE_3

SB_CS_0* SB_CS_1* SB_CS_2* SB_CS_3*

SB_CAS* SB_RAS* SB_WE*

SB_BS_0 SB_BS_1 SB_BS_2

SB_CK_0

SB_CK_0*

SB_CK_1

SB_CK_2

SB_CK_2*

SB_CK_3

SB_CK_3*

SB_CKE_0

SB_CKE_1

SB_CKE_2

SB_DQ_0 SB_DQ_1

SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19

SB_DQ_2

SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29

SB_DQ_3

SB_DQ_30 SB_DQ_31 SB_DQ_32

SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39

SB_DQ_4

SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49

SB_DQ_5

SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59

SB_DQ_6

SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_DQ_7 SB_DQ_8 SB_DQ_9

SB_DQS_0

SB_DQS_0*

SB_DQS_1

SB_DQS_1* SB_DQS_2*

SB_DQS_3

SB_DQS_4*

SB_DQS_5

SB_DQS_5*

SB_DQS_6

SB_DQS_6*

SB_DQS_7

SB_DQS_7*

SB_DQS_8

SB_ECC_CB_0 SB_ECC_CB_1 SB_ECC_CB_2 SB_ECC_CB_3 SB_ECC_CB_4 SB_ECC_CB_5 SB_ECC_CB_6 SB_ECC_CB_7

SB_MA_0 SB_MA_1

SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 SB_MA_15

SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9

SB_ODT_0 SB_ODT_1 SB_ODT_2 SB_ODT_3

SYM 4 OF 10

DDR SYSTEM MEMORY B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

33 97

29 30 97

33 97

29 30 97

29 97

33 97

31 32 97

31 97

33 97

31 32 97

30 97

32 97

29 30 97 31 32 97

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

CPU DDR3 INTERFACES

MEM_B_DQ<53>

MEM_A_CLK_P<0>

MEM_A_DQ<8>

MEM_A_DQ<6>

MEM_A_DQS_P<3>

MEM_A_DQ<11> MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_A_DQ<9>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<10>

MEM_A_ODT<3>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<1>

MEM_A_A<0>

TP_MEM_A_DQ_CB<7>

TP_MEM_A_DQ_CB<6>

TP_MEM_A_DQ_CB<5>

TP_MEM_A_DQ_CB<4>

TP_MEM_A_DQ_CB<3>

TP_MEM_A_DQ_CB<2>

TP_MEM_A_DQ_CB<1>

TP_MEM_A_DQ_CB<0>

TP_MEM_A_DQS_P<8>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQ<7>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_CS_L<3>

MEM_A_CS_L<2>

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_CLK_P<3>

MEM_A_CLK_N<0>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_ODT<0> MEM_A_ODT<1>

MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_BA<0> MEM_A_BA<1>

MEM_A_CAS_L

MEM_A_BA<2>

TP_MEM_A_DQS_N<8>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_B_ODT<3>

MEM_B_ODT<2>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<0>

TP_MEM_B_DQ_CB<7>

TP_MEM_B_DQ_CB<6>

TP_MEM_B_DQ_CB<5>

TP_MEM_B_DQ_CB<4>

TP_MEM_B_DQ_CB<3>

TP_MEM_B_DQ_CB<2>

TP_MEM_B_DQ_CB<1>

TP_MEM_B_DQ_CB<0>

TP_MEM_B_DQS_P<8>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<2>

MEM_B_DQS_P<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<6>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<5>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<4>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<3>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<2>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CAS_L

TP_MEM_B_DQS_N<8>

MEM_B_DQS_P<2>

MEM_B_DQS_P<4>

MEM_B_DQ<33>

MEM_B_DQS_N<3>

MEM_B_CLK_N<1>

MEM_B_DQ<60>

MEM_B_DQS_N<1>

MEM_A_DQ<19>

MEM_A_DQ<26>

MEM_B_CLK_P<2>

MEM_A_CLK_N<2>

MEM_A_CLK_P<2>

MEM_A_CKE<3>

MEM_A_CLK_N<3>

MEM_A_CKE<2>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_ODT<2>

MEM_B_DQ<20>

MEM_B_CS_L<3>

MEM_B_CS_L<2>

MEM_B_CS_L<1>

MEM_B_CKE<2>

MEM_B_CLK_N<3>

MEM_B_CKE<3>

MEM_B_CS_L<0>

MEM_B_CLK_P<1>

MEM_B_CKE<1>

MEM_B_CLK_N<2>

MEM_B_CLK_P<3>

prefsb

051-9504

7.0.0

12 OF 143

12 OF 117

AU35 AW37

AV12

AV20

AV30

AW28

AY29

AE40

AE39

AG38

AG39

AN4

AU24

AU30

AU32

AV31

AU28 AW29

AY25 AW25

AU25

AW27 AY27

AV26 AW26

AV19

AT19

AU18

AV18

AU29 AV32 AW30 AU33

AJ3 AJ4

AR3 AR4 AN2 AN3 AR2 AR1 AV2 AW3 AV5 AW5

AL3

AU2 AU3 AU5 AY5 AY7 AU7 AV9 AU9 AV7 AW7

AL4

AW9 AY9

AU39 AU36 AW35 AY36 AU38 AU37

AJ2

AR40 AR37 AN38 AN37 AR39 AR38 AN39 AN40 AL40 AL37

AJ1

AJ38 AJ37 AL39 AL38 AJ39 AJ40 AG40 AG37 AE38 AE37

AL2 AL1 AN1

AK3

AK2

AP3

AP2

AW4

AV4

AV8

AW8

AV37

AV36

AP38

AP39

AK38

AK39

AF38

AF39

AV13

AU12 AU14 AW13 AY13 AU13 AU11 AY12 AW12

AV27 AY24

AV28 AU21 AT21 AW32 AU20 AT20

AW24 AW23 AV23 AT24 AT23 AU22 AV22 AT22

AW33

AK20

AN12

AR29

AN29

AR8

AN15

AV15

AN25 AN26 AL25 AT26

AK25 AP24 AR25

AP23 AM24 AW17

AL21 AL22

AL20

AL23 AM22

AP21 AN21

AU16

AY15

AW15

AG7

AG8

AM10 AL10

AL6

AM6

AL9

AM9

AP7

AR7 AP10 AR10

AJ9

AP6

AR6

AP9

AR9 AM12 AM13 AR13 AP13 AL12 AL13

AJ8

AR12 AP12 AR28

AL28 AL29 AP28 AP29 AM28 AM29

AG5

AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34 AM32 AM31

AG6

AL35 AL32 AM34 AL31 AM35 AL34 AH35 AH34 AE34 AE35

AJ6

AJ35 AJ34 AF33 AF35

AJ7

AL7

AM7

AH7

AH6

AM8

AL8 AP8

AN13

AN28

AP33

AR33

AL33

AM33

AG35

AG34

AN16

AL16 AM16 AP16 AR16 AL15 AM15 AR15 AP15

AK24 AM20

AN23 AU17 AT18 AR26 AY16 AV16

AM19 AK18 AP19 AP18 AM18 AL18 AN18 AY17

AL26 AP26 AM26 AK26

8

VCCIO_31

VCCIO_44

VCCIO_SEL

VCCIO_45

VCCIO_30

VSSAXG_SENSE

VCCAXG_SENSE

VSSIO_SENSE

VCCIO_SENSE

VCC_024

VCC_038

VCCIO_42

VCCIO_29

VCCIO_28

VCCIO_09

VCC_001 VCC_002 VCC_003 VCC_004

VCCIO_27

VCC_012

VCC_015

VCC_005 VCC_006 VCC_007 VCC_008 VCC_009 VCC_010 VCC_011

VCC_013 VCC_014

VCC_016 VCC_017 VCC_018

VCC_020 VCC_021 VCC_022 VCC_023

VCC_025 VCC_026 VCC_027 VCC_028 VCC_029 VCC_030 VCC_031 VCC_032 VCC_033 VCC_034 VCC_035 VCC_036 VCC_037

VCC_039 VCC_040 VCC_041 VCC_042 VCC_043 VCC_044 VCC_045 VCC_046 VCC_047 VCC_048 VCC_049 VCC_050 VCC_051 VCC_052

VCC_057 VCC_058 VCC_059 VCC_060 VCC_061 VCC_062 VCC_063 VCC_064 VCC_065 VCC_066 VCC_067 VCC_068 VCC_069 VCC_070

VCCIO_02

VCCIO_01

VCCIO_20

VCCIO_26

VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36

VCCIO_40

VCCIO_43

VCCIO_04 VCCIO_05 VCCIO_06 VCCIO_07 VCCIO_08

VCCIO_10 VCCIO_11 VCCIO_12 VCCIO_13 VCCIO_14

VCCIO_16

VCCIO_19

VCCSA_SENSE

VIDALERT*

VIDSCLK

VIDSOUT

VSS_SENSE

VCCIO_41

VCC_SENSE

VCC_056

VCC_055

VCC_054

VCC_053

VCCIO_03

VCC_019

VCCIO_15

VCCIO_17 VCCIO_18

VCCIO_22 VCCIO_21 VCCIO_23 VCCIO_24 VCCIO_25

VCCIO_32

VCCIO_37 VCCIO_38 VCCIO_39

VCCSA_VID

SYM 6 OF 10

CPU VIDS

POWER

IO POWER

CPU CORE SUPPLY

SENSE LINES

VCCAXG_44

VCCAXG_43

VCCAXG_02 VCCAXG_03

VDDQ10

VCCPLL1

VCCPLL0

VDDQ22

VDDQ21

VDDQ20

VDDQ19

VDDQ16

VDDQ14

VDDQ13

VDDQ12

VDDQ11

VDDQ9

VDDQ8

VDDQ7

VDDQ6

VDDQ4

VDDQ3

VDDQ2

VDDQ1

VDDQ0

VCCAXG_16

VCCAXG_15

VCCAXG_14

VCCAXG_13

VCCAXG_12

VCCAXG_11

VCCAXG_10

VCCAXG_09

VCCAXG_07

VCCAXG_06

VCCAXG_05

VCCAXG_04

VCCAXG_42

VCCAXG_41

VCCAXG_40

VCCAXG_39

VCCAXG_38

VCCAXG_37

VCCAXG_36

VCCAXG_35

VCCAXG_34

VCCAXG_33

VCCAXG_32

VCCAXG_31

VCCAXG_30

VCCAXG_29

VCCAXG_28

VCCAXG_27

VCCAXG_26

VCCAXG_25

VCCAXG_24

VCCAXG_22

VCCAXG_21

VCCAXG_19

VCCAXG_18

VCCAXG_17

VCCAXG_23

VCCAXG_20

VDDQ15

VDDQ17 VDDQ18

VDDQ5

VCCAXG_01

VCCAXG_08

SYM 7 OF 10

1.8V

POWER

DDR3-1.5V RAILS

GRAPHICS

VCC_092

VSS_NCTF2 VSS_NCTF3

VCC_097

VCC_091

VCC_090

VCC_089

VCC_088

VCC_087

VCC_083

VCC_112

VCC_117

VCC_113 VCC_114 VCC_115 VCC_116

VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125

VCC_128 VCC_129 VCC_130

VCC_131 VCC_132 VCC_133 VCC_134 VCC_135 VCC_136 VCC_137 VCC_138 VCC_139 VCC_140 VCC_141 VCC_142 VCC_143 VCC_144 VCC_145 VCC_146 VCC_147 VCC_148 VCC_149 VCC_150 VCC_151 VCC_152 VCC_153

VCC_156 VCC_157 VCC_158 VCC_159 VCC_160

VCCSA0 VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6

VCCSA8 VCCSA9

VSS_NCTF1

VCC_073

VCC_072

VCC_071

VCC_155

VCC_154

VCC_084

VCC_093

VSS_NCTF0

VCC_100 VCC_101

VCC_104

VCC_106

VCC_105

VCC_096

VCC_095

VCC_094

VCC_086

VCC_085

VCCSA7

VCCSA10

VCC_107

VCC_082

VCC_077

VCC_074

VCC_076

VCC_161

VCC_126 VCC_127

VCC_111

VCC_098 VCC_099

VCC_075

VCC_081

VCC_103

VCC_102

VCC_078 VCC_079 VCC_080

VCC_108 VCC_109 VCC_110

SYM 10 OF 10

CPU CORE SUPPLY

VCCSA

CPU CORE SUPPLY

POWER

NCTF

OUT

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

U1000

IVY-BRIDGE

OMIT_TABLE

BGA-SKT-K70

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

70

104

66

105

66

105

69

104

69

104

66

105

66

105

R1311

402

5%

MF-LF

1/16W

0

R1310

44.2

MF-LF

1%

1/16W

402

R1312

402

1/16W

MF-LF

0

5%

PLACE_NEAR=U1000.A37:10mm

MF-LF

R1300

1/16W

1%

75

402

PLACE_NEAR=U1000.B37:10mm

402

R1302

110

1% 1/16W MF-LF

66

105

66

105

66

105

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

CPU POWER

CPU_VIDSOUT

CPU_VIDALERT_R_L

=PPVCORE_S0_CPU

=PPVAXG_S0_CPU

=PP1V8_S0_CPU_PLL

=PP1V5_S0_CPU_MEM

CPU_VIDSCLK

CPU_VIDSOUT_R

=PPVCCIO_S0_CPU

CPU_VIDSCLK_R

CPU_VIDALERT_L

SNS_CPU_VCORE_N

SNS_CPU_VCCSA

SNS_CPU_VAXG_P

=PPVCCSA_S0_CPU

=PPVCORE_S0_CPU

=PPVCCIO_S0_CPU

SNS_CPU_VCORE_P

SNS_CPU_VAXG_N

SNS_CPU_VCCIO_N

SNS_CPU_VCCIO_P

NO_TEST=TRUE

NC_CPU_VCCIO_VID

NC_CPU_VCCSA_VID NO_TEST=TRUE

prefsb

051-9504

7.0.0

13 OF 143

13 OF 117

L3

V8

P33

W3

J8

M32

L32

AB3

AB4

C18

D14

U4

J7

J4

AJ26

A12 A13 A14 A15

J3

B16

B25

A16 A18 A24 A25 A27 A28 B15

B18 B24

B27 B28 B30

B33 B34 C15 C16

C19 C21 C22 C24 C25 C27 C28 C30 C31 C33 C34 C36 D13

D15 D16 D18 D19 D21 D22 D24 D25 D27 D28 D30 D31 D33 D34

E18 E19 E21 E22 E24 E25 E27 E28 E30 E31 E33 E34 E35 F15

A7

A11

B9

G4

L7 M13 N3 N4

R7

U7

AB8 AF8 AG33 AJ16 AJ17

AJ28 AJ32 AK15 AK17 AK19

AK23

AK30

T2

A37

C37

B37

B36

U3

A36

E16

E15

D36

D35

AA3

B31

AK21

AK27 AK29

D6 D10 E3 E4 G3

L4

N7 R3 R4

P34

Y38

Y37

AB34 AB35

AU19

AK12

AK11

AY28

AY26

AY23

AW31

AV25

AV21

AU31

AU27

AU23

AR24

AR23

AR22

AR21

AJ24

AJ23

AJ20

AJ14

AJ13

AC40

AC39

AC38

AC37

AC36

AC35

AC34

AC33

AB39

AB38

AB37

AB36

Y36

Y35

Y34

Y33

W38

W37

W36

W35

W34

W33

U40

U39

U38

U37

U36

U35

U34

U33

T40

T38

T37

T35

T34

T33

T39

T36

AV24

AV29 AV33

AR20

AB33

AB40

G25

AV39 AY37

G32

G24

G22

G21

G19

G18

F33

H31

J18

H32 J12 J15 J16

J19 J21 J22 J24 J25 J27 J28 J30

K18 K19 K21

K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18

M22 M24 M25 M27 M28

H10 H11 H12 J10 K10 K11 L11

M10 M11

B3

F19

F18

F16

M21

M19

F34

G27

A4

H14 H15

H19

H22

H21

G31

G30

G28

G16

G15

L12

M12

H24

F32

F25

F21

F24

M30

K15 K16

H30

G33 H13

F22

F31

H18

H16

F27 F28 F30

H25 H27 H28

12

1

2

1

2

105

6

13 16 51 66

6

17 51 66

6

16

6

11 16

105

6

10 11 13 16 28 66

105

6

16

6

13 16 51 66

6

10 11 13 16 28 66

VSS_180

VSS_179

VSS_178

VSS_177

VSS_176

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_154

VSS_153

VSS_152

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_146

VSS_145

VSS_144

VSS_143

VSS_142

VSS_141

VSS_140

VSS_139

VSS_138

VSS_137

VSS_136

VSS_135

VSS_134

VSS_133

VSS_132

VSS_131

VSS_130

VSS_129

VSS_128

VSS_127

VSS_126

VSS_125

VSS_124

VSS_123

VSS_122

VSS_121

VSS_120

VSS_119

VSS_118

VSS_117

VSS_116

VSS_115

VSS_114

VSS_113

VSS_112

VSS_111

VSS_110

VSS_109

VSS_108

VSS_107

VSS_106

VSS_105

VSS_104

VSS_103

VSS_102

VSS_101

VSS_100

VSS_099

VSS_098

VSS_097

VSS_096

VSS_095

VSS_094

VSS_093

VSS_092

VSS_091

VSS_090

VSS_089

VSS_088

VSS_087

VSS_086

VSS_085

VSS_084

VSS_083

VSS_082

VSS_081

VSS_080

VSS_079

VSS_078

VSS_077

VSS_076

VSS_075

VSS_074

VSS_073

VSS_072

VSS_071

VSS_070

VSS_069

VSS_068

VSS_067

VSS_066

VSS_065

VSS_064

VSS_063

VSS_062

VSS_061

VSS_060

VSS_059

VSS_058

VSS_057

VSS_056

VSS_055

VSS_054

VSS_053

VSS_052

VSS_051

VSS_050

VSS_049

VSS_048

VSS_047

VSS_046

VSS_045

VSS_044

VSS_043

VSS_042

VSS_041

VSS_040

VSS_039

VSS_038

VSS_037

VSS_036

VSS_035

VSS_034

VSS_033

VSS_032

VSS_031

VSS_030

VSS_029

VSS_028

VSS_027

VSS_026

VSS_025

VSS_024

VSS_023

VSS_020

VSS_019

VSS_001 VSS_002 VSS_003 VSS_004 VSS_005

VSS_012

VSS_006 VSS_007 VSS_008 VSS_009 VSS_010 VSS_011

VSS_013 VSS_014 VSS_015

VSS_021 VSS_022

VSS_016 VSS_017 VSS_018

SYM 8 OF 10

VSS

VSS_360

VSS_359

VSS_358

VSS_357

VSS_356

VSS_355

VSS_354

VSS_353

VSS_352

VSS_351

VSS_350

VSS_349

VSS_348

VSS_347

VSS_346

VSS_345

VSS_344

VSS_343

VSS_342

VSS_341

VSS_340

VSS_339

VSS_338

VSS_337

VSS_336

VSS_335

VSS_334

VSS_333

VSS_332

VSS_331

VSS_330

VSS_329

VSS_328

VSS_327

VSS_326

VSS_325

VSS_324

VSS_323

VSS_322

VSS_321

VSS_320

VSS_319

VSS_318

VSS_317

VSS_316

VSS_315

VSS_314

VSS_313

VSS_312

VSS_311

VSS_310

VSS_309

VSS_308

VSS_307

VSS_306

VSS_305

VSS_304

VSS_303

VSS_302

VSS_301

VSS_300

VSS_299

VSS_298

VSS_297

VSS_296

VSS_295

VSS_294

VSS_293

VSS_292

VSS_291

VSS_290

VSS_289

VSS_288

VSS_287

VSS_286

VSS_285

VSS_284

VSS_283

VSS_282

VSS_281

VSS_280

VSS_279

VSS_278

VSS_277

VSS_276

VSS_275

VSS_274

VSS_273

VSS_272

VSS_271

VSS_270

VSS_269

VSS_268

VSS_267

VSS_266

VSS_265

VSS_264

VSS_263

VSS_262

VSS_261

VSS_260

VSS_259

VSS_258

VSS_257

VSS_256

VSS_255

VSS_254

VSS_253

VSS_252

VSS_251

VSS_250

VSS_249

VSS_248

VSS_247

VSS_246

VSS_245

VSS_244

VSS_243

VSS_242

VSS_241

VSS_240

VSS_239

VSS_238

VSS_237

VSS_236

VSS_235

VSS_234

VSS_233

VSS_232

VSS_231

VSS_230

VSS_229

VSS_228

VSS_227

VSS_226

VSS_225

VSS_224

VSS_223

VSS_222

VSS_221

VSS_220

VSS_219

VSS_218

VSS_217

VSS_216

VSS_215

VSS_214

VSS_213

VSS_212

VSS_211

VSS_210

VSS_209

VSS_208

VSS_207

VSS_206

VSS_205

VSS_204

VSS_203

VSS_202

VSS_201

VSS_196

VSS_195

VSS_194

VSS_200

VSS_199

VSS_198

VSS_197

VSS_188

VSS_193

VSS_192

VSS_191

VSS_190

VSS_189

VSS_182

VSS_187

VSS_186

VSS_181

VSS_185

VSS_184

VSS_183

SYM 9 OF 10

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

U1000

BGA-SKT-K70

OMIT_TABLE

IVY-BRIDGE

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

CPU GROUNDS

prefsb

051-9504

7.0.0

14 OF 143

14 OF 117

AV10

AU8

AU6

AU4

AU34

AU26

AU15

AU1

AT9

AT8

AT7

AT6

AT5

AT40

AT4

AT39

AT38

AT37

AT36

AT35

AT34

AT33

AT32

AT31

AT30

AT3

AT29

AT28

AT27

AT25

AT2

AT17

AT16

AT15

AT13

AT12

AT10

AT1

AR5

AR36

AR30

AR27

AR19

AR18

AR17

AR14

AR11

AP5

AP40

AP4

AP37

AP36

AP30

AP27

AP25

AP22

AP17

AP14

AP11

AP1

AN9

AN8

AN7

AN6

AN5

AN36

AN35

AN34

AN33

AN32

AN31

AN30

AN27

AN24

AN22

AN19

AN17

AN14

AN11

AN10

AM5

AM40

AM4

AM39

AM38

AM37

AM36

AM30

AM3

AM27

AM25

AM23

AM21

AM2

AM17

AM14

AM11

AM1

AL5

AL36

AL30

AL27

AL24

AL19

AL17

AL14

AL11

AK9

AK8

AK7

AK6

AK5

AK40

AK4

AK37

AK36

AK35

AK34

AK33

AK32

AK31

AK28

AK22

AK16

AK14

AK13

AK10

AK1

AJ5

AJ36

AJ27

AJ25

AJ21

AJ18

AJ15

AJ12

AH8

AH5

AH40

AH39

AH38

AH37

AH36

AH33

AH3

AH2

AG36

AF7

AF6

AF5

AF40

AF37

AF36

AF34

AF1

AE36

AE33

AE3

AD40

AD39

A17 A23 A26 A29 A35

AA6

AA33 AA34 AA35 AA36 AA37 AA38

AB5 AC1 AC6

AD5 AD8

AD33 AD36 AD38

Y8

Y5

W6

V5

V40

V39

V38

V37

V36

V35

V34

V33

V2

V1

U8

T6

T5

T1

R8

R39

R37

R35

R33

P6

P5

P40

P38

P36

P2

P1

N8

M9

M6

M5

M39

M37

M35

M33

M29

M26

M23

M20

M2

M17

M1

L8

L29

L26

L23

L20

L17

L10

K6

K5

K39

K37

K35

K33

K29

K26

K23

K20

K2

K17

K14

K13

K12

K1

J32

J29

J26

J23

J20

J17

J11

H9

H6

H5

H39

H37

H35

H33

H29

H26

H23

H20

H2

H17

H1

G8

G7

G34

G29

G26

G23

G20

G17

G12

G11

F9

F6

F5

F39

F37

F35

F29

F26

F23

F20

F2

F17

F14

F13

F10

F1

E8

E7

E36

E32

E29

E26

E23

E20

E17

E12

E11

D9

D5

D4

D39

D37

D32

D29

D26

D23

D20

D2

D17

C8

C7

C35

C32

C29

C26

C23

C20

C17

C12

C11

B6

B38

B35

B32

B29

B26

B23

B17

B14

B13

B10

AY18

AY14

AY11

AY8

AY6

AY4

AY35

AW10

AW6

AW36

AW16

AW14

AW11

AV14

AV6

AV38

AV11

AV35

AV3

AV17

OUT

S

G

D

IN

D

GS

D

GS

OUT

D

GS

D

SG

D

SG

B

Y

A

OUT

IN

D

GS

OUT

D

GS

OUT

B

Y

A

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DP_AUXIO_EN GLITCHES ON S0/S3 TRANSITIONS RDAR://11085566

D8: ISOLATION FET TO PREVENT TBT 3V3_TBTLC LEAKAGE RDAR://10885566

D7/D7I: CHECK CACTUSRIDGE POWER SEQUENCING & LEAKAGE RDAR://10739300

AP CLKREQ# ISOLATION

ISOLATION FET TO PREVENT LEAKAGE ON AP_PWR_EN AND AP_CLKREQ_L RDAR://11068662

UNUSED clock terminations for FCIM MODE

DP_AUXCH_ISOL IS ACTIVE LOW!

Inverts PCH GPIO DP_AUXCH_ISOL to drive DP_AUXIO_EN for external DP

DP_AUXIO_EN Inversion

TBT CLKREQ# ISOLATION

CFG[5:6] = Sel PCIe Cfg CFG[3]=Direct/Rev for X4 CFG[2]= Direct/Rev for x16

11 = 1x16 (default) 1 = DIR 1 = DIR 10 = 2x8 0 = REV 0 = REV

IVB PCIe Straps configuration:

00 = 1x8,2x4

TBT JTAG_TCK ISOLATION

AP PWR_EN ISOLATION

1/16W

10K

402

MF-LF

5%

R1501

10K

402

MF-LF

5%

1/16W

R1502

10K

MF-LF

5%

R1504

1/16W

402

R1509

402

5%

MF-LF

10K

1/16W

R1510

10K

MF-LF

402

5%

1/16W

5%

402

10K

MF-LF

R1511

1/16W

402

R1528

1/16W MF-LF

5%

10K

402

MF-LF

1K

5%

NOSTUFF

R1512

1/16W

PLACE_NEAR=U1000.N35:20MM

R1513

NOSTUFF

5%

402

1K

MF-LF1/16W

PLACE_NEAR=U1000.L37:20MM

PLACE_NEAR=U1000.K36:20MM

402

1K

5%

MF-LF

NOSTUFF

R1523

1/16W

PLACE_NEAR=U1000.J37:20MM

1/16W

5%

1K

402

MF-LF

R1522

5%

10K

1/16W

R1531

402

MF-LF

10K

5%

1/16W

R1534

MF-LF

402

10K

5%

1/16W

R1533

402

MF-LF

R1530

10K

5%

1/16W MF-LF

402

1/16W

10K

402

MF-LF

R1555

5%

10K

R1542

1/16W MF-LF

402

1/16W

5%

10K

MF-LF

R1505

402

5%

R1556

1/16W

10K

MF-LF

1/16W

10K

5%

R1557

MF-LF

402

1/16W

10K

5%

MF-LF

402

R1558

5%

MF-LF

10K

1/16W

402

R1517

R1520

10K

MF-LF1/16W

402

5%

1/16W MF-LF

5%

10K

R1519

402

10K

R1518

402

MF-LF

5%

1/16W

402

10K

MF-LF

5%

R1516

R1537

MF-LF

402

5%

1K

1/16W

R1536

1/16W

1K

5%

MF-LF

402

1K

5%

1/16W MF-LF

402

R1514

4.7K

R1529

1/16W

5%

402

MF-LF

402

1/16W

R1538

10K

MF-LF

5%

R1540

10K

MF-LF1/16W

402

MF-LF

R1539

1/16W

402

5%

10K

R1541

10K

5%

MF-LF

402

1/16W

10K

5%

R1508

402

MF-LF1/16W

5%

R1535

1/16W

402

MF-LF

100K

10K

5%

1/16W

R1563

402

MF-LF

20K

5%

1/16W MF-LF

R1532

402

18

101

R1552

330

5%

402

MF-LF1/16W

PLACE_NEAR=R1805.1:3MM

SOT23-3-HF

Q1500

NTR1P02L

47

117

5%

1/16W MF-LF

402

100K

R1570

5%

402

100K

1/16W MF-LF

R1571

10K

5%

1/16W

402

MF-LF

R1551

10K

5%

1/16W

R1548

MF-LF

402

PLACE_NEAR=U1800.P33:5mm

5%

1/16W MF-LF

402

R1549

10K

5%

402

MF-LF

10K

1/16W

R1550

5%

10K

1/16W

R1547

MF-LF

402

PLACE_NEAR=U1800.R33:5mm

10K

402

R1546

MF-LF1/16W

5%

PLACE_NEAR=U1800.AF55:6MM

1/16W

5%

10K

402

PLACE_NEAR=U1800.AG56:5mm

MF-LF

R1545

10K

5%

1/16W MF-LF

402

PLACE_NEAR=U1800.BD38:5mm

R1544

10K

5%

1/16W MF-LF

R1543

402

PLACE_NEAR=U1800.BF38:5mm

5%

402

1/16W

4.7K

MF-LF

R1564

1/16W MF-LF

5%

402

10K

R1590

CRITICAL

Q1509

VESM

SSM3K15AMFVAPE

10K

5%

MF-LF

R1591

402

1/16W

MF-LF

5% 1/16W

402

10K

R1592

SOD-VESM-HF

Q1510

SSM3K15FV

15 21

117

R1565

NOSTUFF

5%

1/16W

402

10K

MF-LF

402

MF-LF

5%

1/16W

R1526

10K

5%

402

10K

MF-LF

R1527

1/16W

R1594

MF-LF

10K

5% 1/16W

402

Q1530

SOD-VESM-HF

SSM3K15FV

SOT563

CRITICAL

SSM6N15AFE

Q1540

1/16W MF-LF

R1561

10K

5%

402

MF-LF

1/16W

5%

10K

R1562

CRITICAL

Q1540

SSM6N15AFE

SOT563

R1595

1/16W MF-LF

10K

5%

402

R1596

5%

MF-LF 402

10K

1/16W

R1597

10K

402

MF-LF

5% 1/16W

402

R1598

MF-LF1/16W

5%

NOSTUFF

0

1/16W

R1599

MF-LF

402

5%

NOSTUFF

402

0

NOSTUFF

5%

1/16W MF-LF

R1500

10K

5% 1/16W MF-LF 402

R1593

U1500

SOT353

74LVC1G08GW

21 99

5%

10K

MF-LF

R1521

402

1/16W

5%

NOSTUFF

0

MF-LF

402

R1584

SOD-523

BAT54XV2T1

D1521

36

MF-LF

1/16W

5%

402

R1583

10K

MF-LF

5%

1/16W

0

R1585

NOSTUFF

402

1/16W

5%

MF-LF 402

10K

R1586

MF-LF

R1587

5% 1/16W

402

10K

Q1550

SSM3K15FV

SOD-VESM-HF

15 21

112

R1588

MF-LF

5% 1/16W

402

10K

Q1560

SOD-VESM-HF

SSM3K15FV

15 20 99

SOT353

U1501

74LVC1G08GW

86 88

112

U1500.5:3MM

C1500

16V

0402

0.1UF

X7R-CERM

10%

U1501.5:3MM

0.1UF

0402

16V X7R-CERM

C1501

10%

R1524

1%

402

MF-LF1/16W

2.0K

R1525

2.0K

1%

402

MF-LF1/16W

MF-LF

402

1/16W

NOSTUFF

R1554

0

5%

1/16W

NOSTUFF

0

MF-LF

402

R1553

SYNC_MASTER=D8_MLB

STRAPS,PULL UPS,PULL DOWNS FOR PCH AND CPU

SYNC_DATE=03/29/2012

PCH_BLC_MCU_RESET_R

PCH_BLC_EXT_BOOT_R

=PP3V3_TBT_PCH_GPIO

PCH_CAM_EXT_BOOT_L

PCH_CAM_RESET

PCH_GPIO6

USB_EXTA_OC_L

=PP3V3_S4_AP

TBT_PWR_EN

TBT_PWR_EN_R

JTAG_TBT_TCK_ISOL

JTAG_TBT_TCK

=PP3V3_TBT_PCH_GPIO

TBT_CIO_PLUG_EVENT_ISOL

TBT_CIO_PLUG_EVENT

=PP3V3_S0_PCH_GPIO

=PP3V3_S5_PCH_STRAPS

PCH_GPIO1

DP_AUXCH_ISOL

SSD_CLKREQ_L

ENET_CLKREQ_L

TBT_PCH_CLKREQ_L

=PP3V3_TBT_PCH_GPIO

CPU_CFG<2>

CPU_CFG<6>

USB_EXTD_OC_EHCI_L

PCH_SATALED_L

=PP3V3_S0_LED_SATA

PCH_SMBALERT_L

USB_EXTC_OC_L

=PP3V3_S5_PCH_STRAPS

PCH_SPKR

SATARDRVR_EN

PEG_CLKREQ_L

SMC_RUNTIME_SCI_L

=PP3V3_S0_PCH_STRAPS

PCH_GPIO48

PM_SLP_S4_L

PM_SLP_S5_L

ENET_LOW_PWR_PCH

PCH_GPIO22

ENET_MEDIA_SENSE

WOL_EN

PCH_GPIO29

PCH_CLK14P3M_REFCLK

PCH_CLK100M_DMIN

=PP3V3_S0_PCH_GPIO

JTAG_TBT_TDO_ISOL

JTAG_TBT_TMS_ISOL

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDO

JTAG_TBT_TMS

JTAG_TBT_TDI_ISOL

TBT_PCH_CLKREQ_L

TBT_CLKREQ_L

HDA_SYNC

ITPXDP_CLK100M_N ITPCPU_CLK100M_N

ITPXDP_CLK100M_P ITPCPU_CLK100M_P

TBT_PWR_REQ_L

BT_PWR_RST_L

AP_PWR_EN_ISO

AP_PWR_EN

USB_EXTB_OC_EHCI_L

=PP3V3_S4_AP

=PP3V3_S5_PCH_STRAPS

SMC_WAKE_SCI_L

PCH_SUSWARN_L

PCH_GPIO72

PM_PWRBTN_L

TBT_SW_RESET_R_L

AP_CLKREQ_L

AP_PWR_EN

AP_CLKREQ_L

TBT_GO2SX_BIDIR

=PP3V3_S0_PCH_STRAPS

=PP3V3_S5_PCH_STRAPS

AP_CLKREQ_L_ISO

SPI_DESCRIPTOR_OVERRIDE_L

DP_AUXCH_ISOL

PM_PCH_PWROK

DP_AUXIO_EN

SPI_DESCRIPTOR_OVERRIDE_R

=PP3V3_S0_PCH_STRAPS

PM_SLP_S3_L

PCH_CLKIN_GND0

PCH_CLK100M_SATAP

PCH_CLK96M_DOTP

PCH_CLK96M_DOTN

PCH_CLK100M_SATAN

HDA_SDOUT_R

SDCONN_STATE_CHANGE

USB_EXTD_OC_L

=PP3V3_TBT_PCH_GPIO

=PP3V3_TBTLC_RTR

PCH_CLK100M_DMIP

PCH_CLKIN_GND1

CPU_CFG<5>

CPU_CFG<3>

USB_EXTB_OC_L

JTAG_TBT_TDI

=PP3V3_S0_PCH_GPIO

DP_AUXCH_ISOL_EN

=PP3V3_S0_PCH_GPIO

prefsb

051-9504

7.0.0

15 OF 143

15 OF 117

12

2

1

3

12

1

2

1

2

3

12

1

2

1

2

3

12

1

2

1

2

3

4

5

1

2

1

2

6

1

2

1

2

1

2

1

2

12

1

2

4

3

1

2

5

1

2

12

AK

1

2

12

1

2

1

2

1

2

3

1

2

1

2

3

4

3

1

2

5

2

1

2

1

12

21

114

21

114

6

15

21

114

21

20 45 99

6

15 35

26 36

117

36 99

21 99

6

15

6

15 19 20 38

6

15

21

15 18 99

18

117

18 40

113

15 21

117

6

15

10 25 99

20 99

18 44

6

44

18

114

20 46 99

6

15

18

18 99

18 75

114

21 47

117

6

15

21

19 47 64

115

19 47 64

115

21 26 99

21

18 39

111

21 40

117

19

18

6

15 19 20 38

6

15 19 20 38

6

15 19 20 38

36

114

36

114

6

15

21

114

18

114

36

114

38

117

18 56

101

18 25 99 11 99

20 36

117

20 35

112

35

112

15 20 99

20 99

6

15 35

6

15

21 47

117

19

114

19

19 25 47

115

21

15 21

112

21 36

6

15

6

15

35

112

15 18 99

19 26 35 43 65 89

115

101

6

15

5

19 28 40 47 48 64

115

18

20 41 99

20 46 99

6

15

6

36 37 38 50

18

10 25 99

20 45 99

21

114

6

15 19 20 38

99

6

15 19 20 38

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLL (CPU VCCSFR) DECOUPLING

Memory (CPU VCCDDR) DECOUPLING

PLACEMENT_NOTE (C1660-C1665):

PLACEMENT_NOTE (C1650-C1657):

CPU VCCIO DECOUPLING

8X 22UF 0805, 6X 10UF 0805

10x 10UF and 10x 1UF CAPACITORS

BULK CAPS ON VTT REG PAGE 77

INTEL RECOMMENDATION 9X22UF 0805,16X 0805 placeholders

PLACEMENT_NOTE (C1600-C1613):

Bulk decoupling is on VCCSA reg page 75

2x 10uF 0603. INTEL RECOMMENDATION 2X 10uF 0805

CPU VCCSA DECOUPLING

BULK CAPS ON CPU VREG PAGE 74

BULK CAPS ON CPU VREG PAGE 72

2x 47uF, 1x 22uF 0805, 1x 10uF 0603, 1x 4.7uF 0603, 1x 2.2uF 0402, 2x 1uF 0402. INTEL RECOMMENDATION 1x 10uF 0805

CPU VCORE DECOUPLING

14x 22UF,0805 INTEL RECOMMENDATION 18X 22UF 0805 (14 Inside cavity and 4 North of processor)

REPLACED WITH 603 PER RDAR://10700439

10V

10%

402

X5R

1UF

C1693

6.3V

10%

402

X5R

2.2UF

C1692 C1691

603

X5R-CERM

6.3V

10%

4.7UF

10V

20%

603

X5R

10UF

Place inside socket cavity

C1629

10V

20%

603

X5R

10UF

Place inside socket cavity

C1628

10V

20%

603

X5R

10UF

Place inside socket cavity

C1627

10V

20%

603

X5R

10UF

Place inside socket cavity

C1626

10V

20%

603

X5R

10UF

Place inside socket cavity

C1624

10V

20%

603

X5R

10UF

Place inside socket cavity

C1623

10V

20%

603

X5R

10UF

Place inside socket cavity

C1622

10V

20%

603

X5R

Place inside socket cavity

10UF

C1621

10V

20%

603

X5R

10UF

Place inside socket cavity

C1620

16V

10%

402

X5R

1UF

Place inside socket cavity

C1630

10V

20%

603

X5R

10UF

Place inside socket cavity

C1625

16V

10% X5R

1UF

Place inside socket cavity

C1631

402

16V

10% X5R

Place inside socket cavity

C1632

402

1UF

16V

Place inside socket cavity

C1633

402

X5R

10%

1UF

16V

10%

402

X5R

1UF

Place inside socket cavity

C1634

16V

10%

402

X5R

1UF

Place inside socket cavity

C1635

16V

10%

402

X5R

1UF

Place inside socket cavity

C1636

16V

10%

402

X5R

1UF

Place inside socket cavity

C1637

16V

10%

402

X5R

1UF

Place inside socket cavity

C1638

16V

10%

402

X5R

1UF

Place inside socket cavity

C1639

330UF-0.0045OHM

CRITICAL

C1670

20%

CASE-D2-SM

POLY

2V

6.3V X5R 603

10UF

20%

C1695

0201

X5R

20%

1UF

6.3V

C1682

0201

6.3V

20% X5R

1UF

C1683

6.3V

20%

0201

X5R

1UF

C1684

6.3V

20%

0201

X5R

1UF

C1685

1UF

6.3V

20%

0201

X5R

C1686

CRITICAL

CASE-D2-SM

330UF-0.0045OHM

NOSTUFF

POLY

2V

20%

C1687

6.3V 603

10uF

X5R

20%

C1667C1666

X5R 603

6.3V

20%

10uF

0603

22UF

20%

6.3V X5R-CERM2

C1600 C1601

22UF

0603

20%

6.3V X5R-CERM2 X5R-CERM2

0603

C1602

22UF

20%

6.3V

0603

22UF

20%

6.3V X5R-CERM2

C1603

0603

22UF

20%

6.3V X5R-CERM2

C1604 C1605

0603

X5R-CERM2

6.3V

20%

22UF

0603

C1606

22UF

20%

6.3V X5R-CERM2

C1607

0603

22UF

20%

6.3V X5R-CERM2

C1608

0603

22UF

20%

6.3V X5R-CERM2

C1609

0603

22UF

20%

6.3V X5R-CERM2

X5R-CERM2

6.3V

20%

22UF

0603

C1610 C1611

X5R-CERM2

6.3V

20%

22UF

0603

C1612

6.3V X5R-CERM2

20%

0603

22UF

X5R-CERM2

6.3V

20%

22UF

0603

C1613

22UF

20%

6.3V X5R-CERM2

C1650

0603 0603

C1651

X5R-CERM2

6.3V

20%

22UF

6.3V

0603

C1652

X5R-CERM2

20%

22UF

C1653

0603

22UF

20%

6.3V X5R-CERM2 X5R-CERM2

0603

C1654

6.3V

20%

22UF

0603

C1655

X5R-CERM2

6.3V

20%

22UF

0603

C1656

X5R-CERM2

6.3V

20%

22UF

0603

C1657

X5R-CERM2

6.3V

20%

22UF

X5R-CERM2

6.3V

20%

22UF

0603

C1676 C1677

22UF

0603

20%

6.3V X5R-CERM2 X5R-CERM2

C1678

0603

22UF

20%

6.3V

C1679

0603

22UF

20%

6.3V X5R-CERM2

C1680

22UF

20%

6.3V X5R-CERM2 0603

X5R-CERM2

6.3V

20%

22UF

0603

C1681

6.3V

C1690

0603

22UF

20%

X5R-CERM2

X5R

6.3V

20%

0805

47UF

C1696

X5R

20%

6.3V

0805

47UF

C1697

Place at edge of socket.

10uF

X5R 603

20%

6.3V

C1665

Place at edge of socket.

10uF

X5R 603

20%

6.3V

C1664

6.3V

10uF

C1663

20%

603

X5R

Place at edge of socket.

C1662

10uF

X5R 603

6.3V

Place at edge of socket.

20%

C1661

X5R

6.3V

20%

603

10uF

Place at edge of socket.

C1660

Place at edge of socket.

10uF

6.3V

20%

603

X5R

10V

10%

402

X5R

1UF

C1694

SYNC_MASTER=D7_MLB

CPU NON-GFX DECOUPLING

SYNC_DATE=12/20/2011

=PPVCORE_S0_CPU

=PP1V8_S0_CPU_PLL

=PPVCCIO_S0_CPU

=PPVCCSA_S0_CPU

=PP1V5_S0_CPU_MEM

=PPVCORE_S0_CPU

prefsb

051-9504

7.0.0

16 OF 143

16 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

13 16

51 66

6

13

6

10 11 13

28 66

6

13

6

11 13

6

13 16 51 66

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE (C1704-C1709):

AXG BULK CAPS

INTEL RECOMMENDATION 4X22UF 0805,3X 4.7UF

VAXG DECOUPLING

R1730

0

MF-LF

402

5%

1/16W

R1740

1/16W

5%

402

MF-LF

0

C1710

4.7UF

Place inside socket cavity

X5R-CERM 603

10%

6.3V

C1711

4.7UF

X5R-CERM

Place inside socket cavity

603

10%

6.3V

C1712

Place inside socket cavity

10%

603

X5R-CERM

6.3V

4.7UF

R1720

402

0

MF-LF

1/16W

5%

603

C1795

X5R

20%

10UF

10V

603

C1794

10V

10UF

20%

X5R

CASE-D2-SM

CRITICAL

C1793

POLY

20% 2V

330UF-0.006OHM

CASE-D2-SM

2V

C1792

330UF-0.006OHM

20%

POLY

CRITICAL

CASE-D2-SM

C1791

20% 2V POLY

330UF-0.006OHM

CRITICALCRITICAL

2V

C1790

CASE-D2-SM

POLY

20%

330UF-0.006OHM

CASE-D2-SM

330UF-0.006OHM

C1789

POLY

20% 2V

CRITICAL

330UF-0.006OHM

CASE-D2-SM

C1788

POLY

20% 2V

CRITICAL

0603

C1704

X5R-CERM2

6.3V

20%

22UF

0603

C1705

X5R-CERM2

6.3V

20%

22UF

0603

C1706

X5R-CERM2

6.3V

20%

22UF

0603

C1707

X5R-CERM2

6.3V

20%

22UF

0603

C1708

X5R-CERM2

6.3V

20%

22UF

0603

C1709

X5R-CERM2

6.3V

20%

22UF

1UF

6.3V CERM 402

10%

C1731

PLACE C1731 AT BALL U1800.AB1

1UF

10%

6.3V CERM 402

C1741

PLACE C1741 AT BALL U1800.AC2

SYNC_DATE=01/26/2012

GFX DECOUPLING & PCH PWR ALIAS

SYNC_MASTER=D8_KOSECOFF

=PP1V05_S0_PCH_VCC_ADPLL

=PP3V3_S0_PCH_VCC_ADAC

PPCPUAXG_S0_REG

=PPVAXG_S0_CPU

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLLA_F

PP3V3_S0_PCH_VCCA_DAC_F

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

prefsb

051-9504

7.0.0

17 OF 143

17 OF 117

12

2

1

2

1

2

1

12

2

1

2

11

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

68

6

13 51 66

22

115

22

115

22

115

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

IN

OUT

BI

OUT

IN

OUT

BI

OUT

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

SATA3RXP

HDA_SYNC

INTRUDER*

LDRQ1*/GPIO23

SATA1TXN

SATA3RXN

SATA1RXN

SATA1TXP

SATA0RXN

SERIRQ

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP

SATA2TXN SATA2TXP

SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

L_BKLTCTL

HDA_RST*

SPKR

HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

GPIO33 GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_MOSI

SPI_MISO

RTCX1 RTCX2

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

L_BKLTEN L_VDD_EN

FWH0/LAD0

INTVRMEN

SPI_CS1*

HDA_SDIN0

SRTCRST*

SPI_CLK

RTCRST*

HDA_BCLK

(1 OF 10)

LPC

RTC

IHDA

SATA

JTAG

SPI

CLKIN_DMI_P

PETN2

CLKOUT_PEG_A_N

CL_RST1*

CLKIN_DMI_N

PERP3

CLKOUT_PEG_B_N

CLKIN_DOT_96P

CL_DATA1

CL_CLK1

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_GND0_P

CLKOUT_ITPXDP_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

XTAL25_OUT

XTAL25_IN

CLKIN_PCILOOPBACK

REFCLK14IN

CLKIN_SATA_P

CLKIN_DOT_96N

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_PEG_A_P

SMBCLK

SMBALERT*/GPIO11

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0ALERT*/GPIO60

SML0CLK

SMBDATA

PERN3

PETP2

CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE4P

CLKOUT_PCIE5N

CLKOUT_PCIE3P

CLKOUT_PCIE4N

CLKOUT_PCIE3N

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1N CLKOUT_PCIE1P

CLKOUT_PCIE0N CLKOUT_PCIE0P

PETP8

PERP8 PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6 PETP6

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP2

CLKIN_SATA_N

CLKIN_GND0_N

CLKOUT_ITPXDP_P

CLKOUT_PEG_B_P

PETN5 PETP5

PERN6 PERP6

PERP1

PERN1

PETN1 PETP1

PERN2

FLEX

CLOCK

PCI-E*

PEG

FROM CLK BUFFER

SMBUS

(2 0F 10)

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DOES THIS NEED LENGTH MATCH???

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

PLACE THIS RESISTOR PACK CLOSE TO PCH (MIN 500MIL)

26

101

56

101

49

101

49

101

49

101

49

101

47 49

114

44

100

44

100

44

100

44

100

44

100

44

100

44

100

44

100

8

39 98

8

39 98

8

35 98

36 98

15 75

114

11 99

75 98

8

15

26

101

26

101

26

101

50

117

50

117

50

116

50

116

35 98

R1830

PLACE_NEAR=U1800.AJ53:2mm

37.4

MF-LF

1%

402

1/16W

R1820

MF-LF 402

5% 1/16W

10K

39 98

R1890

1/16W

PLACE_NEAR=U1800.AL2:2mm

MF-LF

402

1%

90.9

18

114

50

117

50

117

8

36 98

R1832

PLACE_NEAR=U1800.AC52:2mm

1/16W

750

MF-LF

1%

402

R1831

49.9

1% 1/16W

402

MF-LF

PLACE_NEAR=U1800.AE52:2mm

8

R1860

5%

402

MF-LF

33

1/16W

47 49

101

47 49

101

R1861

1/16W

33

5%

402

MF-LF

47 49

101

R1862

5%

MF-LF

402

33

1/16W

47 49

101

R1863

1/16W

33

5%

402

MF-LF

47 49 101

U1800

PANTHER-POINT

OMIT_TABLE

FCBGA

U1800

PANTHER-POINT

FCBGA

OMIT_TABLE

R1864

MF-LF

33

5%

402

1/16W

MF-LF

R1803

20K

1/16W

5%

402402

5%

MF-LF

20K

R1802

1/16W

C1803

1UF

X5R

10V

402

10%

C1802

1UF

10V

10%

402

X5R

R1801

1M

1/16W MF-LF 402

5%

402

R1800

MF-LF

5%

1/16W

390K

45

46

56

101

56

101

15 56

101

56

101

R1805

33

1/16W SM-LF

5%

402

1/16W MF-LF

0

R1851

NOSTUFF

MF-LF

1/16W

402

5%

0

R1852

15 99

R1841

SIGNAL_MODEL=EMPTY

0

5% MF

201

1/20W

R1842

SIGNAL_MODEL=EMPTY

1/20W

0

5%

201

MF

8

SYNC_MASTER=D8_MLB

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_DATE=N/A

DMI_MIDBUS_CLK100M_N

ITPXDP_CLK100M_N

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO64_CLKOUTFLEX0

PCH_CLKIN_GND1

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_CL_CLK1

TP_PCH_CL_DATA1

PCH_CLK100M_SATAP

TP_PCIE2_R2D_CP

TP_PCIE1_D2RN TP_PCIE1_D2RP TP_PCIE1_R2D_CN TP_PCIE1_R2D_CP

TP_PCIE2_R2D_CN

TP_PCIE2_D2RN TP_PCIE2_D2RP

TP_PCIE_CLK100M_PE0N TP_PCIE_CLK100M_PE0P

PCIE_AP_D2R_P

PCIE_CLK100M_AP_N

TP_SATA_D_R2D_CP

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN

XDP_PCH_TDI

TP_SATA_C_R2D_CP

TP_SATA_C_D2RP

TP_SATA_C_D2RN

SATA_SSD_R2D_N SATA_SSD_R2D_P

TP_SATA_C_R2D_CN

PCIE_CLK100M_TBT_N

PEG_CLKREQ_L

PCIE_TBT_R2D_C_P<3>

PCIE_ENET_D2R_P

HDA_RST_R_L

HDA_SDIN0

TP_HDA_SDIN3

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<2>

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_N

XDP_PCH_TMS

HDA_SYNC_R

PCH_SPKR

TP_HDA_SDIN2

ENET_MEDIA_SENSE

TP_PCH_CLKOUT_DPP

XDP_PCH_TCK

HDA_SDOUT_R

PCH_CLK14P3M_REFCLK

=PP1V05_S0_PCH

SML_PCH_0_CLK

DMI_CLK100M_CPU_P

PCH_CLK100M_DMIN

DP_AUXCH_ISOL

DP_AUXCH_ISOL_R SATARDRVR_EN_R

TP_SATA_F_R2D_CN

TP_SATA_F_D2RP

TP_PCH_L_VDD_EN

LPC_AD<1>

SPI_MOSI_R

PCH_SATA3COMP

HDA_BIT_CLK_R

HDA_SDOUT_R

SATA_SSD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

PCH_INTRUDER_L

TP_PCH_CL_RST1

PCH_CLK96M_DOTN

SML_PCH_1_DATA

TP_SATA_F_D2RN

TP_PCH_L_BKLTEN

TP_PCH_L_BKLTCTL

=PP3V3_G3_PCH

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<1>

PCH_CLK96M_DOTP

PCH_CLK100M_SATAN

HDA_SYNC_R

HDA_SYNC HDA_RST_L

PCH_CLK100M_DMIP

PCIE_AP_R2D_C_N PCIE_AP_R2D_C_P

TP_LPC_DREQ0_L TBT_PWR_EN_PCH

LPC_SERIRQ

SATA_SSD_D2R_N

PCH_CLK32K_RTCX1

SSD_CLKREQ_L

ENET_CLKREQ_L

TP_HDA_SDIN1

HDA_RST_R_L

HDA_BIT_CLK

HDA_SDOUT

SATA_HDD_R2D_C_P

SATA_HDD_D2R_N

=PP3V3_S0_PCH

PCH_CLK32K_RTCX2

LPC_FRAME_L

LFRAME_L

LPC_AD<2>

LPC_R_AD<2>

LPC_AD<0>

LPC_R_AD<0> LPC_R_AD<1>

LPC_AD<3>

LPC_R_AD<3>

SPI_MISO

HDA_BIT_CLK_R

RTC_RESET_L

PCH_SRTCRST_L

PCH_INTVRMEN

JTAG_TBT_TMS

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

PCH_SATA3RBIAS

PCH_SATAICOMP

PCIE_TBT_D2R_N<0>

PCIE_CLK100M_TBT_P

USB_EXTB_SEL_XHCI

SML_PCH_0_DATA

USB_EXTD_SEL_XHCI

SML_PCH_1_CLK

PCH_CLK33M_PCIIN

PCH_CLK25M_XTALOUT

PCH_CLKIN_GND0

=PP1V05_S0_PCH_VCCIO_PCIE

SPI_CS0_R_L

PEG_CLK100M_P

PCIE_ENET_R2D_C_P

ITPXDP_CLK100M_P

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<0> PCIE_TBT_R2D_C_P<0>

PCIE_CLK100M_AP_P

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<3>

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PCH_SMBALERT_L

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_N

SATARDRVR_EN

PCH_CLK25M_XTALIN

TP_SATA_D_D2RP

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP

PCH_SATALED_L

=PP1V05_S0_PCH_VCCIO_SATA

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

PCIE_CLKREQ5_GPIO44_L

PCIE_AP_D2R_N

PCIE_TBT_D2R_N<1>

PCIE_TBT_R2D_C_N<1>

PEG_CLK100M_N

DMI_MIDBUS_CLK100M_P

TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE4P

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE5N

PCH_INTVRMEN

PCH_INTRUDER_L

PCH_SRTCRST_L

RTC_RESET_L

NO_TEST=TRUE

NC_SPI_CS1_L

SPI_CLK_R

PCH_XCLK_RCOMP

XDP_PCH_TDO

PCIE_CLKREQ5_GPIO44_L

prefsb

051-9504

7.0.0

18 OF 143

18 OF 117

1

2

1

2

1

2

1

2

1

2

12

AE54 AE52 AC52

AN44

BP23

BM38 BA20

AG49

AN46

AA53

AG47

AC56

AV52

BJ17 BJ20 BG20

BG17

AA56

AL56 AL53

AN56 AM55

AN49 AN50 AT50 AT49

AT46

AV50 AV49

AJ53 AJ55

BF57

BC54 AY52

AG12

BC22

BE56

BF22

BJ22

BK22

BT23

BC25 BA25

BA43

BC50

BC52

BF47

AT57

AU53

AT55

BR39 BN39

AE44

AE46

AL50 AL49

AT44

AB55

BK17

AG18 AG17

BK15

BN41

AR56

BD22

BN37

AR54

BT41

BU22

R33

C22

AG8

BF49

P33

J17

AE12

BF38

BF50

BA50

P27

R27

V52

R52

BA2

AW5

BA5

AT9

AL2

AJ5

AJ3

BD15

AN8

AG56

BD38

N56 M55

R31

P31

AG9

BT47

BN49

BK46

BJ46

BR46

BM50

BU49

BT51

BR49

H17

A22

AG2

BL54

Y8

AF3

AB8

Y9

AB9

AV43

AB14

AB12

AA5

W5

AE6 AC6

D13

J10 B13

F13

H10

F15

H12

J12

A16 B15

M15

E17

N15

F18

M17

B21

P17

E21

R20

AF55

W53

N52

AE11

B17 C16

J15 L15

L20

J20

F25 F23

P20

12

1

2

1

2

1

2

1

121

2

1

2

3

4

8

7

6

5

12

15 25 99

8

15

8

25 99

8

18

101

8

25 99

18

101

15

8

15 39

111

25 99

15 18

101

6

25

99

25

99

8

100

18

101

15 18

101

18

8

6

19

18

101

8

26

117

15

117

15 40

113

8

18

101

6

21 24

101

18

101

18 26 48

116

18

114

18

15

114

8

100

8

15

6

19 22 24

15 25 99

15

114

8

15 44

6

22 24

18

114

18 26 48

116

101

25 99

18

114

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

INIT3_3V*

GPIO32

DMI2TXP

PWRBTN*

RSMRST*

SYS_RESET*

DMI3RXN

DMI2RXN

DMI2RXP DMI3RXP

DMI_ZCOMP

SUSACK*

SLP_SUS*

DSWVRMEN

DF_TVS

SLP_LAN*/GPIO29

PMSYNCH

SLP_A*

SLP_S3*

SLP_S4*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

FDI_LSYNC0

FDI_FSYNC1

FDI_INT

FDI_RXP7

FDI_RXP6

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP1

FDI_RXN7

FDI_RXN6

FDI_RXN5

FDI_RXN4

FDI_RXN3

FDI_RXN2

FDI_RXN1

FDI_RXN0

RI*

SUSWARN*/GPIO30

PWROK

SYS_PWROK

DMI_IRCOMP

DMI2RBIAS

DMI1TXN

DMI0TXN

DMI1RXP

DMI0RXP

FDI_RXP0

FDI_LSYNC1

DMI0RXN

FDI_RXP2

DMI1RXN

FDI_FSYNC0

APWROK

DMI2TXN DMI3TXN

DMI0TXP DMI1TXP

GPIO31 GPIO72

DMI3TXP

SLP_S5*/GPIO63

WAKE*

DPWROK

DRAMPWROK

DMI

FDI

(3 OF 10)

SYSTEM POWER

MANAGEMENT

DDPB_AUXN DDPB_AUXP

DDPB_0P DDPB_1N DDPB_1P

DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N

DDPD_3P

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_HPD

DDPB_0N

DDPB_2N DDPB_2P

DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_2P DDPD_3N

RESERVED

(4 OF 10)

CRT

DIGITAL DISPLAY INTERFACE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACE CLOSE TO U1800 PIN

SHORT THESE TWO PINS VERY NEAR THE PINS PLACE THE RESISTOR VERY CLOSE TO COMMON POINT

KEEPING TP, IF NEED TO USE IT LATER

10 99

8

PLACE_NEAR=U1800.E31:5MM

R1900

1/16W

1%

402

MF-LF

49.9

19 35 40 114

48

101

15 47 64

115

15 47 64

115

5

15 28 40 47 48 64

115

11 28 99

65

115

15 25 47

115

65

115

15 26 35 43 65 89

115

48 65

115

25 26 47

115

10 99

R1905

10K

402

MF-LF

1/16W

5%

11 99

26 47 49

114

R1925

MF-LF

1K

1%

1/16W

402

PLACE_NEAR=U1800.AT3:3mm

R1951

402

1K

5% 1/16W MF-LF

R1909

402

MF-LF

1/16W

10K

5%

R1915

MF-LF

1/16W

402

5%

390K

PLACE_NEAR=U1800.A32:5MM

R1920

750

1% 1/16W

402

MF-LF

R1981

1/16W MF-LF

402

2.2K

5%

R1980

402

MF-LF

1/16W

5%

4.7K

U1800

FCBGA

PANTHER-POINT

OMIT_TABLE

U1800

FCBGA

PANTHER-POINT

OMIT_TABLE

R1999

1/16W MF-LF 402

10K

5%

R1998

10K

MF-LF 402

5% 1/16W

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

PCH DMI/FDI/GRAPHICS

PCH_RI_L

PCH_DMI2RBIAS

CPU_PROC_SEL

PCIE_WAKE_L

MAKE_BASE=TRUE

PM_RSMRST_PCH_L

PCH_SUSWARN_L

PCH_GPIO31_ACPRESENT

PCH_DF_TVS

PM_SLP_S4_L

PCH_GPIO29

PCH_DSWVRMEN

PCH_FDI_FSYNC<0>

DMI_N2S_N<2>

PCH_GPIO32

LPC_PWRDWN_L

PCIE_WAKE_L

PCH_FDI_LSYNC<1>

DP_IG_D_CTRL_DATA

TP_PCH_RESERVE_6

TP_PCH_RESERVE_14

DP_IG_D_CTRL_CLK

TP_PCH_RESERVE_11

TP_PCH_RESERVE_10

TP_PCH_RESERVE_9

DP_IG_B_MLN<2>

=PP3V3_G3_PCH

TP_PM_SLP_A_L

DP_IG_C_MLP<3>

DP_IG_B_MLP<3>

PCH_DSWVRMEN

PCH_DF_TVS

TP_PCH_SUSACK_L

=PP3V3_S5_PCH

DMI_S2N_P<0>

PM_PCH_APWROK

=PP1V05_S0_PCH_VCCIO_PCIE

PM_PCH_PWROK

PM_MEM_PWRGD

PM_SYSRST_L

DMI_S2N_P<3>

PM_SLP_S5_L

DMI_S2N_N<3>

DMI_S2N_N<2>

DMI_N2S_N<1>

DMI_N2S_N<0>

DMI_N2S_P<0> DMI_N2S_P<1>

DMI_S2N_N<1>

PCH_FDI_RX_N<0>

PM_SLP_S3_L

TP_PCH_SLP_SUS_L

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_S2N_P<2>

=PP1V8_S0_PCH

DP_IG_D_MLN<3>

DP_IG_D_MLP<2>

DP_IG_D_AUXP

DP_IG_D_AUXN

DP_IG_C_MLN<3>

DP_IG_C_MLP<2>

DP_IG_C_MLN<2>

DP_IG_C_MLP<1>

DP_IG_C_MLN<1>

DP_IG_C_MLP<0>

DP_IG_B_MLP<2>

DP_IG_B_MLN<0>

DP_IG_B_DDC_DATA

DP_IG_B_DDC_CLK

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

DP_IG_D_MLP<3>

DP_IG_D_MLN<2>

DP_IG_D_MLP<1>

DP_IG_D_MLN<1>

DP_IG_D_MLP<0>

DP_IG_D_MLN<0>

DP_IG_D_HPD

DP_IG_C_MLN<0>

DP_IG_C_HPD

DP_IG_C_AUX_P

DP_IG_C_AUX_N

DP_IG_C_CTRL_DATA

DP_IG_C_CTRL_CLK

DP_IG_B_MLP<1>

DP_IG_B_AUX_P

DP_IG_B_MLP<0>

DP_IG_B_MLN<3>

DP_IG_B_MLN<1>

PM_PCH_SYS_PWROK

PCH_DMI_COMP

DMI_S2N_P<1>

DP_IG_B_HPD

DP_IG_B_AUX_N

DMI_N2S_P<2>

DMI_S2N_N<0>

TP_PCH_RESERVE_7

TP_PCH_RESERVE_5

TP_PCH_RESERVE_4

TP_PCH_RESERVE_3

TP_PCH_RESERVE_1 TP_PCH_RESERVE_2

TP_PCH_RESERVE_8

TP_PCH_RESERVE_12

TP_PCH_RESERVE_15 TP_PCH_RESERVE_16 TP_PCH_RESERVE_17

TP_PCH_RESERVE_0

TP_PCH_RESERVE_13

TP_PCH_RESERVE_20 TP_PCH_RESERVE_21

TP_PCH_RESERVE_19

TP_PCH_RESERVE_18

TP_PCH_RESERVE_26

TP_PCH_RESERVE_28

TP_PCH_RESERVE_27

TP_CRT_IG_BLUE TP_CRT_IG_GREEN

TP_CRT_IG_DDC_CLK

TP_CRT_IG_HSYNC TP_CRT_IG_VSYNC

=PP3V3_S0_PCH_GPIO

PCH_FDI_RX_N<1>

PM_SYNC

PCH_GPIO72

PM_PWRBTN_L

PM_CLK32K_SUSCLK_R

PCH_DAC_IREF

=PP3V3_S5_PCH

=TBT_WAKE_L

PCH_FDI_RX_N<5>

PCH_FDI_RX_N<4>

PCH_FDI_RX_N<3>

PCH_FDI_RX_N<2>

PCH_FDI_RX_N<6> PCH_FDI_RX_N<7>

PCH_FDI_RX_P<6>

PCH_FDI_INT

PCH_FDI_FSYNC<1>

PCH_FDI_LSYNC<0>

PCH_FDI_RX_P<7>

PCH_FDI_RX_P<2>

PCH_FDI_RX_P<0> PCH_FDI_RX_P<1>

PCH_FDI_RX_P<3>

TP_PCH_RESERVE_22 TP_PCH_RESERVE_23 TP_PCH_RESERVE_24 TP_PCH_RESERVE_25

PCH_FDI_RX_P<4> PCH_FDI_RX_P<5>

TP_PCH_INIT3V3_L

TP_CRT_IG_DDC_DATA

TP_CRT_IG_RED

prefsb

051-9504

7.0.0

19 OF 143

19 OF 117

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

BN56

BC56

J38

BT43

BK38

BE52

E37

B37

C36 F38

E31

BP45

BD43

BR42

R47

BH49

F55

BC41

BM53

BN52

BA47

BN54

E49

C52

H46

P43

H43

C49

A46

D47

F43

M43

J43

B47

B45

C46

H41

F45

C42

BJ48

BU46

BJ38

BJ53

B31

A32

P38

J36

B35

B33

B43

D51

D33

J41

A36

B51

BC46

H38 M41

H36 R38

BG43 AV46

P41

BH50

BC44

BT37

BG46

Y50

R9 R8

R14 M12 M11

M3 L5

AL12 AL14

U12 U14 N2

J3

AL9 AL8

M1

B5 D5 D7 C6 C9

E11

U43 M49 M50 R50

U44 U46 U50 R44

U49 AB44 AB49

E52

H52

F53

J55

L56

K46

AB50

L53

Y44

G56 AB46

K49

K50

M48

AM1

AN2

AN6

AW3

AW1

AR4

AR2

AT3

AM6

U9 U8

U5 W3

T3 U2

AL15 AL17

T1

R12

K8 H8

L2 G4 G2 F5 F3 E2 E4

R6 N6

B7 B11

Y41

H50

J57

1

2

1

2

114

99

11 99

19 35 40

114

15

114

19

15

19

114

8

6

18

8

19

114

19

6

19 24 26

6

18 22 24

8

6

8

99

8

6

15 20 38

8

15

6

19 24 26

36

8

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

USB3TN1

USB3TP1

USB3RN1

USB3RN2

USB3RP2

CLKOUT_PCI0 CLKOUT_PCI1

USBP13P

AD0 AD1 AD2 AD3

AD18

USBP8P

USBP8N

USBP7P

AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17

AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28

PIRQD*

REQ0*

REQ2*/GPIO52 REQ3*/GPIO54

GNT0*

GNT3*/GPIO55

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PCIRST*

SERR* PERR*

IRDY* PAR DEVSEL* FRAME*

PLOCK*

STOP* TRDY*

PME*

PLTRST*

USBP0N USBP0P

USBP1N USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N

USBP9N USBP9P

USBP10N

USBP11N USBP11P

USBP12N

USBP13N

USBRBIAS*

REQ1*/GPIO50

AD29 AD30 AD31

USBP12P

USBP10P

C/BE3*

C/BE0* C/BE1* C/BE2*

PIRQA*

GNT2*/GPIO53

GNT1*/GPIO51

PIRQC*

PIRQB*

USBRBIAS

USB3RP1

CLKOUT_PCI4

CLKOUT_PCI3

CLKOUT_PCI2

USB3TN2

USB3TP2

USB3RP3

USB3RN3

USB3TP3

USB3TN3

USB3RN4

USB3RP4

USB3TP4

USB3TN4

OC0*/GPIO59

OC2*/GPIO41

OC1*/GPIO40

OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9

OC7*/GPIO14

OC6*/GPIO10

USB

(5 OF 10)

PCI

IN

OUT

IN

OUT

IN

BI

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

UNUSED

CAMERA

INTERNAL HUB (BT,SMC12)

EHCI - EXT D

UNUSED

EHCI - EXT B

UNUSED

EXT D

EXT C

EXT B

EXT A

TIE TRACES TOGETHER CLOSE TO PINS

PLACE THE RESISTOR CLOSE TO COMMON POINT

45

102

45

102

8

45

102

45

102

45

102

45

102

45

102

45

102

45

102

45

102

45

102

45

102

46

102

46

102

46

102

46

102

46

102

46

102

46

102

OMIT_TABLE

PANTHER-POINT

FCBGA

U1800

46

102

10K

5% 1/16W MF-LF

402

NOSTUFF

R2019

60

62

15 36

117

15 35

112

15 45 99

15 46 99

15 99

15 41 99

SIGNAL_MODEL=EMPTY

201

1/20W

5% MF

0

R2001

SIGNAL_MODEL=EMPTY

0

201

1/20W

5% MF

R2002 R2003

1/20W

5% MF

0

SIGNAL_MODEL=EMPTY

201

1/20W

5%

0

MF

201

SIGNAL_MODEL=EMPTY

R2007

201

1/20W

5% MF

0

SIGNAL_MODEL=EMPTY

R2004

SIGNAL_MODEL=EMPTY

R2005

1/20W

5%

0

MF

201

SIGNAL_MODEL=EMPTY

R2006

201

1/20W

5%

0

MF

SIGNAL_MODEL=EMPTY

5% MF

1/20W

0

201

R2008

45

102

45

102

46

102

46

102

46

102

8

46

102

8

42

46

102

46

102

8

1/16W

22.6

MF-LF 402

1%

PLACE_NEAR=U1800.BM25:2mm

R2070

10K

MF-LF

4025%

1/16W

R2010

1/16W MF-LF

4025%

10K

R2011

MF-LF

402

1/16W

10K

5%

R2012

402

MF-LF

5%

1/16W

10K

R2013

10K

MF-LF

5%

1/16W

402

R2015

10K

MF-LF1/16W

4025%

R2016

10K

MF-LF

4025%

1/16W

R2017

5%

10K

1/16W

402

MF-LF

R2020

5%

10K

1/16W MF-LF

402

R2021

10K

5%

1/16W

402

MF-LF

R2022

26

114

26

101

26

101

26

101

10K

5%

1/16W

402

MF-LF

R2023

402

10K

5%

1/16W MF-LF

R2024

1/16W MF-LF

4025%

10K

R2026

402

1/16W

10K

MF-LF

5%

R2025

402

1/16W

5%

10K

MF-LF

R2027

27

102

27

102

8

MF-LF

5%

1/16W

10K

402

R2030

PCH PCI/USB

SYNC_MASTER=D7_MLB

SYNC_DATE=03/15/2012

AP_PWR_EN

USB_EXTB_OC_EHCI_L

USB_EXTC_OC_L

PCI_PERR_L

PCI_INTB_L PCI_INTC_L PCI_INTD_L

PCI_REQ0_L

USB_EXTB_OC_R_L

USB_EXTA_OC_L

SDCONN_STATE_CHANGE

USB3_EXTC_RX_F_N

USB_PCH_13_P

USB3_EXTA_TX_N

USB3_EXTD_TX_P

USB3_EXTD_TX_N

USB_EXTA_OC_R_L

USB_EXTC_OC_R_L USB_EXTD_OC_R_L USB_EXTB_OC_EHCI_R_L

AP_PWR_EN_R

USB_EXTD_OC_EHCI_L

USB3_EXTD_RX_F_P

USB3_EXTD_RX_F_N

TP_PCI_CLK33M_OUT2

PCI_DEVSEL_L

USB3_EXTB_TX_P

TP_PCI_C_BE_L<0>

TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3>

PCI_INTA_L

PCH_USB_RBIAS

TP_PCI_AD<29>

SDCONN_STATE_CHANGE_R

USB_EXTD_OC_EHCI_R_L

USB_EXTB_OC_L

TP_PCI_PME_L

USB3_EXTA_TX_P

PCH_CLK33M_PCIOUT

PCI_FRAME_L

TP_PCI_PAR

TP_PCI_AD<30> TP_PCI_AD<31>

TP_PCI_C_BE_L<1>

PCI_PLOCK_L

TP_PCI_AD<11> TP_PCI_AD<12> TP_PCI_AD<13>

USB_PCH_9_N

USB_PCH_12_N

TP_PCI_AD<2>

TP_PCI_AD<0>

TP_PCI_AD<3> TP_PCI_AD<4>

TP_PCI_RESET_L

AUD_IP_PERIPHERAL_DET

TP_PCH_PCI_GNT0_L

AUD_I2C_INT_L

LPC_CLK33M_SMC_R LPC_CLK33M_LPCPLUS_R

TBT_PWR_REQ_L

PCI_IRDY_L

PCI_TRDY_L

PCI_STOP_L

BLC_GPIO

TP_PCI_AD<6>

BT_PWR_RST_L

TP_PCH_STRP_ESI_L

TP_PCH_STRP_BBS1

JTAG_GMUX_TMS

TP_PCI_AD<28>

TP_PCI_CLK33M_OUT3

USB_PCH_11_N

USB3_EXTC_TX_P

PLT_RESET_L

USB3_EXTA_RX_F_P

USB_PCH_10_P

USB_PCH_12_P

USB_PCH_13_N

USB_PCH_11_P

USB_PCH_10_N

USB_PCH_9_P

USB_PCH_7_N

USB_PCH_6_P

USB_PCH_6_N

USB_PCH_5_P

USB_PCH_5_N

USB_PCH_4_P

USB_PCH_4_N

USB_PCH_3_P

USB_PCH_3_N

USB_PCH_2_P

USB_PCH_2_N

USB_PCH_1_P

USB_PCH_1_N

USB_PCH_0_P

USB_PCH_0_N

TP_PCI_AD<27>

TP_PCI_AD<26>

TP_PCI_AD<25>

TP_PCI_AD<24>

TP_PCI_AD<23>

TP_PCI_AD<22>

TP_PCI_AD<21>

TP_PCI_AD<20>

TP_PCI_AD<19>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<15>

TP_PCI_AD<14>

TP_PCI_AD<10>

TP_PCI_AD<9>

TP_PCI_AD<8>

TP_PCI_AD<7>

TP_PCI_AD<5>

USB_PCH_7_P

USB_PCH_8_N USB_PCH_8_P

TP_PCI_AD<18>

TP_PCI_AD<1>

USB3_EXTB_RX_F_P

USB3_EXTB_RX_F_N

USB3_EXTA_RX_F_N

PCH_STRP_TOPBLK_SWP_L

PCI_SERR_L

USB3_EXTC_TX_N

USB3_EXTC_RX_F_P

USB3_EXTB_TX_N

=PP3V3_S0_PCH_GPIO

BLC_I2C_MUX_SEL

USB_EXTD_OC_L

prefsb

051-9504

7.0.0

20 OF 143

20 OF 117

C29

E29

H31

J27

L27

AT11 AN14

BK27

BF15 BF17

BT7

BT13

BC6

BR29

BN27

BD31

BG12 BN11 BJ12

BU9

BR12

BJ3 BR9

BJ10

BM8 BF3 BN2 BE4 BE6

BG15

BT11 BA14

BL2 BC4 BL4 BC2

BM13

BA9 BF9 BA8

BP5

BG5

BK8

AV11

BA15

BE2

BN9 AV9

BT15

BR4

AV14

BR6 BM3

BF11

BH8 BH9

BC11

BA17

BC12

BC8

AV15

BK48

BF36 BD36

BC33 BA33

BM33 BM35

BT33 BU32

BR32 BT31

BN29 BM30

BK33 BJ33

BF31

BR26 BT27

BK25

BJ31 BK31

BF27

BJ27

BP25

BT5

BF8 AV17 BK12

BD27

BJ25

BP13

BN4

BP7

BG2

BK10

BU12

AV8

BM15

BJ5

BM25

J31

AT14

AT17

AT12

F28

E27

L25

J25

B27

C26

L22

J22

D25

B25

BM43

BG41

BD41

BK43 BP43 BJ41

BM45

BT45

1

2

12

1

2

12 12 12 12

12 12 12

12 12

12

12 12

12

25 99

25

99

25

99

8

102

8

25

99

25 99

8

114

8

114

6

15 19 38

OUT

IN

OUT

IN

NCTF

RSVD

GPIO

MISC

CPU

NCTF

(6 OF 10)

VSS_NCTF

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA4GP/GPIO16

PCIECLKRQ6*/GPIO45

TACH4/GPIO68

A20GATE

BMBUSY*/GPIO0 CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N CLKOUT_PCIE7P

GPIO27

GPIO28

GPIO35/NMI*

GPIO57

GPIO8

NC_5

PCIECLKRQ7*/GPIO46

PECI

PROCPWRGD

PWM0 PWM1 PWM2 PWM3

RCIN*

SATA3GP/GPIO37

SATA5GP_GPIO49

SCLOCK/GPIO22

SDATAOUT1/GPIO48

SST

STP_PCI*/GPIO34

TACH0/GPIO17

TACH1/GPIO1

TACH2/GPIO6

TACH3/GPIO7

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

THRMTRIP*

TP1

TP10

TP11

TP12

TP13

TP14

TP16

TP17

TP18

TP19

TP2

TP20

TP3

TP4

TP5

TP6

TP7

TP8

TP9

NC_1 NC_2 NC_3 NC_4

VSSADAC

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO24/PROC_MISSING

SATA2GP/GPIO36

TP15

BI

OUT

IN

OUT

IN

OUT

IN

NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RDAR://11363991 D7/D7I/D8/J35/J36: RENAME GPU/TBT MUX SELECT TO DP_TBT_SEL

Place this near the T point

X

11 25 28 99

48

115

5% 1/16W MF-LF

10K

402

R2155

402

MF-LF

1/16W

10K

5%

R2150

28 34 99

5%

100K

MF-LF

1/16W

402

R2190

49

114

NOSTUFF

0

5%

402

1/16W MF-LF

R2170

0

1/16W

5%

402

MF-LF

R2140

FCBGA

PANTHER-POINT

OMIT_TABLE

U1800

11 47 48 99

5

99

15 47

117

38

117

26 99

62 84 99

15 99

15

114

15

112

15

117

15 26 99

49

101

5%

0

201

R2106

SIGNAL_MODEL=EMPTY

1/20W

MF

SIGNAL_MODEL=EMPTY

201

5%

1/20W

MF

0

R2101

R2104

201

5% MF

1/20W

0

SIGNAL_MODEL=EMPTY

1/20W

R2107

0

5%

201

SIGNAL_MODEL=EMPTY

MF

SIGNAL_MODEL=EMPTY

0

5%

201

MF

1/20W

R2108

0

5%

1/20W

201

MF

SIGNAL_MODEL=EMPTY

R2103

MF

1/20W

5%

0

201

SIGNAL_MODEL=EMPTY

R2109

R2105

5%

201

0

1/20W

MF

SIGNAL_MODEL=EMPTY

5%

1/20W

MF

201

33

R2110

5%

1/20W

33

201

MF

R2111

43

102

43

114

MF5%

33

201

R2113

1/20W

89

114

89

114

R2112

MF

201

1/20W335%

PCH MISC

SYNC_DATE=N/A

SYNC_MASTER=D8_MLB

TP_PCH_TP20

JTAG_TBT_TCK_R

TBT_PCH_CLKREQ_L

TBT_GO2SX_BIDIR

SMC_WAKE_SCI_L

ISOLATE_CPU_MEM_R_L

JTAG_TBT_TDI

AUD_IPHS_SWITCH_EN_PCH

CPU_PWRGD

CPU_PECI

=PP3V3_S0_PCH

JTAG_TBT_TCK

=PP3V3_S0_PCH

TBT_CIO_PLUG_EVENT

DP_TBT_SEL

PCH_CAM_RESET_R

ENET_LOW_PWR_PCH

JTAG_TBT_TDO

AUD_IPHS_SWITCH_EN_PCH_R

AP_CLKREQ_L

PCH_A20GATE

TBT_CIO_PLUG_EVENT_R TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE7N TP_PCIE_CLK100M_PE7P

HDD_PWR_EN

PCH_PECI

PCH_PROCPWRGD

TP_PCH_PWM0 TP_PCH_PWM1 TP_PCH_PWM2 TP_PCH_PWM3

PCH_RCIN_L

ENET_LOW_PWR_PCH_R

PCH_GPIO22

TP_PCH_SST

TBT_SW_RESET_R_L

LPCPLUS_GPIO

PCH_GPIO1

PCH_GPIO6

SMC_RUNTIME_SCI_L

PM_THRMTRIP_L

TP_PCH_TP1

TP_PCH_TP10

TP_PCH_TP11

TP_PCH_TP12

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP16

TP_PCH_TP17

TP_PCH_TP18

TP_PCH_TP19

TP_PCH_TP2

TP_PCH_TP3

TP_PCH_TP4

TP_PCH_TP5

TP_PCH_TP6

TP_PCH_TP7

TP_PCH_TP8

TP_PCH_TP9

XDP_PIN03

WOL_EN

TP_PCH_TP15

PCH_CAM_RESET

SPIROM_USE_MLB

PCH_GPIO48

PCH_CAM_EXT_BOOT_L

PCH_BLC_MCU_RESET

PCH_BLC_EXT_BOOT_R

PCH_BLC_EXT_BOOT

ISOLATE_CPU_MEM_L

GPU_GOOD

GPU_GOOD_R

DP_TBT_SEL_R

TBT_SW_RESET_L

PCH_CAM_EXT_BOOT_R_L

PCH_BLC_MCU_RESET_R

prefsb

051-9504

7.0.0

21 OF 143

21 OF 117

1

2

1

2

1

2

12

A6

A4

BF55

BE54

AU56

AV44

BU16

BM57

B2

BB57

AW55

AB3 AA2

AE2 AF1

BJ43

BJ55

BJ57

BT53

BP51

AY20

BP55

H48

D53

BN21 BT21 BM20 BN19

BG56

BG53

BA56

BA53

AW53

BC43

BL56

BT17

BR19

BA22

BR16

BM18

BN17

BP15

E56

P22

BM46

BA27

BC49

AE49

AE41

AE50

BA36

AY36

Y14

L31

Y12

L33

M38

L36

Y18

Y17

AB18

AB17

A54 A52 F57 D57

BU54

BU6

BM1

BP1

BU4

BU52

AU2

BM55

BK50

BT2

BP57

BP53

BB55

AE43

F1

D1

12

8

25 99

15 36

15 47

117

25 99

15

114

6

18 21 24

6

18 21 24

15 99

25 99

8

52

113

114

8

114

25 99

15

8

15

8

25 99

15 40

117

8

15

114

15

114

25 99

VCCAPLLEXP

VCCCLKDMI

VCCAPLLDMI2

VCCIO

VCCADAC

VCCVRM1

VCCIO

VCC3_3_0

VCCVRM0

VCCASW

VCCCORE

VCC3_3

VCCAFDIPLL

VCCDMI

(7 OF 10)

VCCIO_DMI/CLK

VCC CORE

CRTDMI

FDI

VCCASW

VCCIO_PCIE

HVCMOS

V_PROC_IO_NCTF

VCCRTC

V5REF_SUS

VCCADPLLB

VCCSPI

VCCIO

V5REF

VCCAPLLSATA

VCC3_3

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA

DCPSST

V_PROC_IO

VCCDFTERM0 VCCDFTERM1

VCCDIFFCLKN

VCCDSW3_3

VCCIO

VCCVRM3

VCCSUSHDA

VCCVRM2

DCPRTC_NCTF

VCCSUS3_3

VCCSSC

VCC3_3

DCPSUS

SATA

PCI/GPIO/LPC

(10 OF 10)

USB

CPURTC

HDA

CLOCK AND MISCELLANEOUS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH output, for decoupling only

Max and Idle = 1mA

20mA Max, 10mA Idle

(VCCIO[1-31] total)

3.456A Max, 426mA Idle

PCH output, for decoupling only

57 mA Max, 30mA Idle

1.44 A Max, 474mA Idle

55mA Max, 5mA Idle

20mA Max, 1mA Idle

3mA Max, 1mA Idle

200 mA Max, 2mA Idle

(VCCSUS3_3 - 11 TOTAL)

Need to check layout decoupling

409 mA Max, 42mA Idle

Max and Idle = 1 MA

40mA Max, 10mA Idle

40mA Max, 5mA Idle

Max and Idle = 1mA

97mA Max, 15mA Idle

(VCCVRM 4 total)

159mA Max, 114mA Idle

105mA Max, 90mA Idle

10 mA Max, 1mA Idle

1.61A Max, 433mA Idle

(VCC3_3[1-9] total)

Max and Idle = 1mA

PLACE_NEAR=U1800.BR54:4MM

C2210

0.1UF

402

20%

CERM

10V

C2222

PLACE_NEAR=U1800.BA46:2mm

0.1UF

6.3V X5R 201

10%

0.1UF

PLACE_NEAR=U1800.BU42:2mm

C2232

402

CERM

10V

20%

C2231

CERM 402

PLACE_NEAR=U1800.BU42:2mm

10%

6.3V

1UF

U1800

OMIT_TABLE

FCBGA

PANTHER-POINT

U1800

OMIT_TABLE

FCBGA

PANTHER-POINT

SYNC_MASTER=D8_MLB

SYNC_DATE=N/A

PCH POWER

=PP3V3_G3_PCH_RTC

PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S5_PCH_V5REFSUS

=PP5V_S0_PCH_V5REF

TP_PP1V05_S0_PCH_VCCAPLL_SATA

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S5_PCH_VCCSUS_USB

TP_PP1V05_S0_PCH_FDIPLL

=PP3V3_S0_PCH_VCC_PCI

=PP1V05_S0_PCH_VCC_ASW

=PP3V3_S0_PCH_VCC_HVCMOS

=PP1V05_S0_PCH_VCC_CORE

PP1V05_S0_PCH_VCCADPLLB_F

PP1V8_S0_PCH_VCCVRM_F

TP_PP1V05_S0_PCH_VCCAPLL_EXP

TP_DCPSUS_0

=PP1V05_S0_PCH_VCC_SSC

PP1V8_S0_PCH_VCCVRM_F

=PP3V3_S5_PCH_VCC_DSW

=PP1V05_S0_PCH_VCC_DIFFCLK

=PP1V8_S0_PCH_VCC_DFTERM

PP1V05_S0_PCH_VCCADPLLA_F

=PP3V3_S5_PCH_VCC_SPI

PP1V8_S0_PCH_VCCVRM_F

PP3V3_S0_PCH_VCCA_DAC_FTP_PPVOUT_PCH_DCPSUSBYP

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S0_PCH_VCC

TP_DCPSUS_2

=PP3V3_S0_PCH_VCC_GPIO

=PP1V05_S0_PCH_VCCIO_DMI

PP1V8_S0_PCH_VCCVRM_F

=PP1V05_S0_PCH_VCCCLKDMI

TP_PP1V05_S0_PCH_VCCAPLLDMI2

=PP1V05_S0_PCH_VCCIO_PCIE

=PP3V3_S5_PCH_VCCSUS_HDA

TP_DCPSUS_1

=PP1V05_S0_PCH_V_PROC_IO

PPVOUT_G3_PCH_DCPRTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm

=PP1V05_S0_PCH_VCCIO_USB

TP_PP1V05_S0_PCH_VCC_A_CLK

prefsb

051-9504

7.0.0

22 OF 143

22 OF 117

2

1

2

1

2

1

2

1

AG26 AG28 AJ24

AN34

AL34

AJ28

AJ26

B53

AJ20

A19

AN32

AC32

Y26

V33

AA36

Y20 Y22 Y24

Y28 V22 V25 V27 F20

AT1

R56

B41

Y30 Y32

Y34

Y36

V36 V31 F30

AF57

AJ1

AU32 AV36 AU34 AG24

AL24 AL28 AN22 AN24 AN26 AN28 AR24 AR26 AR28 AR30 AR36 AR38 AU30 AU36

AC24 AC26 AC28 AC30

AE24 AE28 AE30 AE32 AE34 AE36

AJ32 AJ34 AJ36 AL32

AR32 AR34

BC17 BD17 BD20

C54

E41

AG32 AG34

AA34

B56

BU42

BT25

AC2

AN52

AG40 AG38 AG41 BA38 AN40 AN41

BF1

U56

AV20

AU20

A12

AN38

AV41

AL5

BR54

AB1

BA46

AT41

AU22

D55

T55 T57

AE15 AE17 AG15

AV40

AY25 AY27 AV24 AV26

AV30 AV32 AY31 AY33 BJ36 BK36 BM36 AT40 AU38 BT35

AJ38 AE40

AL40

R2

AV28

R54

BT56

U31

AC20 AE20

AL38

AA32

A39

6

24

6

18 24

6

24

6

24

6

24

6

24

6

24

17

115

22 24

115

6

24

22 24

115

6

24

6

24

6

24

17

115

6

24

22 24

115

17

115

6

24

6

24

6

24

6

24

22 24

115

6

24

6

18 19 24

6

24

6

24

6

24

VSS

(8 OF 10)

VSS

(9 OF 10)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

U1800

OMIT_TABLE

PANTHER-POINT

FCBGA

U1800

OMIT_TABLE

PANTHER-POINT

FCBGA

SYNC_MASTER=D7_MLB

SYNC_DATE=03/15/2012

PCH GROUNDS

prefsb

051-9504

7.0.0

23 OF 143

23 OF 117

AE56 BR36

AB15

AB43

AA28

AN11

AM57

AM52

AM3

AL47

AL46

AL41

AL36

AL30

AL26

AL22

AL20

AL18

AL11

AJ22 AJ30

AK6

AK52

AJ57

AG5 AG50 AG53 AH52

AH6

AG30 AG36 AG43 AG44 AG46

AF6 AG11 AG14 AG20 AG22

AF52

AE4 AE47

AE8

AE9

AE38

AE14 AE18 AE22 AE26

AC54

AC34 AC36

AC4

AC22

AB47 AB52 AB57

AB6

AB11

AA38

AB40 AB41

AA30

AA26

AA24

AA22

AA20

A9

A49

A42

A26

BG33 BG36

BG31

BF25 BF33 BF41 BF43 BF46 BF52 BF6 BG22 BG25 BG27

BC27 BC31 BC36 BC38 BC47 BC9 BD25 BD33 BF12 BF20

BA41 BA44 BA49 BB1 BB3 BB52 BB6 BC14 BC15 BC20

BA31

AV47 AV6 AW57 AY38 AY6 B23 BA11 BA12

AV34

AT52 AT6 AT8 AU24 AU26 AU28 AU5 AV12 AV18 AV22

AN54 AN9 AR20 AR22 AR52 AR6 AT15 AT18 AT43 AT47

AN12 AN15 AN17 AN18 AN20 AN30 AN36 AN4 AN43 AN47

AC38

AV38

A29

AY22

C12

J46 J48 J5 J53 K52 K6 K9 L12 L17 L38 L41 L43 M20 M22 M25 M27 M31 M33 M36 M46 M52 M57 M6 M8 M9 N4 N54 R11 R15 R17 R22 R4 R41 R43 R46 R49

T6 U11 U15 U17 U20 U22 U25 U27 U33 U36 U38 U41 U47 U53 V20 V38 V6 W1 W55 W57 Y11 Y15 Y38 Y40 Y43 Y46 Y47 Y49 Y52 Y6 AL43 AL44 R36 P36 R25 P25

BH52

BH6

BJ1 BJ15 BK20 BK41 BK52

BK6 BM10 BM12 BM16 BM22 BM23 BM26 BM28 BM32 BM40 BM42 BM48

BN47

BN6

BP3 BP33 BP35 BR22 BR52 BU19 BU26 BU29 BU36 BU39

C19

C32

C39

C4 D15 D23

D3 D35 D43 D45 E19 E39 E54

E6

E9 F10 F12 F16 F22 F26 F32 F33 F35 F36 F40 F42 F46 F48 F50

F8 G54 H15 H20 H22 H25 H27 H33

H6

J1 J33

T52

BN31

BM5

BG38

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

1 mA S0-S5

PLACEMENT_NOTE:

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

<1 MA

PCH V5REF_SUS Filter & Follower (PCH Reference for 5V Tolerance on USB)

<1 MA S0-S5

PLACEMENT_NOTEs:

(PCH PCI 3.3V PWR)

PCH VCC3_3 BYPASS

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PLACEMENT_NOTEs:

1 mA

(PCH DMI 1.05V PWR)

PCH VCCIO BYPASS

INTEL PDG: 1X 0.1UF

PLACEMENT_NOTE:

INTEL PDG: 2X 1UF

PLACEMENT_NOTES:

PCH VCCIO BYPASS (PCH USB 1.05V PWR)

PLACEMENT_NOTEs:

(PCH HD Audio 3.3V/1.5V PWR)

PLACEMENT_NOTE:

INTEL PDG: 1X 0.1UF

PLACEMENT_NOTEs:

INTEL PDG: 4X 1UF AND 2X 10UF

FOR PCH_VCC_DIFFCLK AND PCH_VCC_CORE

(PCH 1.05V CORE PWR)

PLACEMENT_NOTEs:

PCH VCCCORE BYPASS

PCH VCCSUS3_3 BYPASS

PLACEMENT_NOTEs:

(PCH Reference for 5V Tolerance on PCI)

INTEL PDG: 1X 1UF

INTEL PDG: 2X 0.1UF AND 1X 2.2UF

PLACEMENT_NOTEs:

PCH VCCSUSHDA BYPASS

(PCH SUSPEND USB 3.3V PWR)

PLACEMENT_NOTE:

INTEL PDG: 2X 0.1UF AND 1X 4.7UF

PLACEMENT_NOTEs (all 3):

PLACEMENT_NOTEs:

PLACEMENT_NOTE:

PCH V5REF Filter & Follower

1UF

402

10V

10%

X5R

C2439

PLACE C2439 AT BALL BF1

100

5%

402

1/16W MF-LF

R2405

2

1

20%

402

CERM

0.1UF

10V

C2438

PLACE C2438 AT BALL BT25

SOT-363

BAT54DW-X-G

D2400

402

5%

MF-LF

1/16W

10

2

1

R2404

BAT54DW-X-G

SOT-363

D2400

MF-LF

R2400

0

1/16W

5%

402

PLACE C2440 AT BALL T55

C2440

0.1UF

402

20%

CERM

10V

0.1UF

20%

CERM 402

10V

C2441

PLACE C2441 AT BALL AV28

PLACE C2450 AT BALL AV26

1UF

CERM 402

10%

6.3V

C2450

PLACE C2419 AT BALL B41

402

10%

1UF

6.3V CERM

C2419

C2422

PLACE C2422 AT BALL AU20

402

CERM

1UF

6.3V

10%

PLACE C2449 AT BALL AY27

CERM 402

1UF

10%

6.3V

C2449

PLACE C2416 AT BALL D55

C2416

4.7UF

6.3V

20%

402

X5R

PLACE C2485 AT BALL AL38

X5R

10% 25V

0.1UF

402

C2485

PLACE C2410 AT BALL Y20

10UF

C2410

CERM

20%

6.3V

805-1

PLACE C2463 AT BALL V25

402

1UF

10%

6.3V CERM

C2463

PLACE C2480 AT BALL AC20

6.3V CERM

20%

805-1

C2480

10UF

PLACE C2475 AT BALL AE20

402

CERM

6.3V

C2475

1UF

10%

PLACE C2437 AT BALL AE15

10UF

CERM

20%

6.3V

805-1

C2437

PLACE C2435 AT BALL AE17

CERM

1UF

10%

6.3V

402

C2435

PLACE C2434 AT BALL AE15

1UF

6.3V

402

CERM

10%

C2434

PLACE C2471 AT BALL AA34

805-1

10UF

20%

6.3V CERM

C2471

PLACE C2469 AT BALL V36

10%

CERM

6.3V

402

C2469

1UF

PLACE C2414 AT BALL Y26

C2414

1UF

402

10%

6.3V CERM

PLACE C2401 AT BALL V22

C2401

20%

6.3V CERM

10UF

805

PLACE C2487 AT BALL E41

10%

402

CERM

6.3V

C2487

1UF

PLACE C2452 AT BALL AG38

1UF

CERM

6.3V

402

10%

C2452

PLACE C2453 AT BALL AJ38

C2453

1UF

CERM

6.3V

402

10%

2.2UF

C2412

402

X5R

6.3V

10%

PLACE C2412 AT BALL AT40

PLACE C2499 AT BALL AV40

402

20%

CERM

10V

0.1UF

C2499

CERM

10%

1UF

402

C2442

6.3V

PLACE C2442 AT BALL AN52

C2445

10UF

PLACE C2445 AT BALL R2

805-1

CERM

6.3V

20%

C2443

PLACE C2443 AT BALL AJ1

6.3V

402

1UF

10%

CERM

402

CERM

6.3V

C2436

10%

1UF

PLACE C2436 AT BALL R54

X5R

PLACE C2486 AT BALL AU22

0.1UF

10%

402

25V

C2486

PLACE C2444 AT BALL BA38

10%

402

6.3V CERM

1UF

C2444

PLACE C2446 AT BALL AY25

1UF

402

CERM

6.3V

10%

C2446

805-1

20%

CERM

6.3V

C2472

PLACE C2472 AT BALL V31

10UF

1UF

402

10%

PLACE C2470 AT BALL Y32

6.3V CERM

C2470

CERM

6.3V

10UF

805-1

PLACE C2473 AT BALL F30

20%

C2473

10%

402

6.3V

1UF

PLACE C2425 AT BALL BD20

CERM

C2425

10%

402

6.3V

PLACE C2427 AT BALL BD17

CERM

1UF

C2427

C2461

805-1

CERM

20%

10UF

6.3V

PLACE C2461 AT BALL AR32

C2460

PLACE C2460 AT BALL AJ34

6.3V

10UF

CERM

805-1

20%

PLACE C2482 AT BALL AC24

C2482

CERM

10%

1UF

6.3V

402

PLACE C2481 AT BALL AC32

6.3V

402

1UF

10%

CERM

C2481

CERM

C2483

6.3V

1UF

10%

402

PLACE C2483 AT BALL AL34

PLACE C2407 AT BALL Y28

402

CERM

6.3V

1UF

10%

C2407

PLACE C2415 AT BALL F20

10UF

20%

CERM

805-1

C2415

6.3V

402

C2429

PLACE C2429 AT BALL Y24

10%

1UF

6.3V CERM

PLACE C2428 AT BALL AJ24

10UF

6.3V CERM

20%

805-1

C2428

PLACE C2420 AT BALL AU32

6.3V

20%

CERM

10UF

805-1

C2420

PLACE C2418 AT BALL AN22

C2418

CERM

6.3V

20%

10UF

805-1

PLACE C2498 AT BALL AR24

CERM

6.3V

10%

1UF

402

C2498

PLACE C2496 AT BALL AR36

C2496

1UF

6.3V

10%

CERM 402

6.3V

C2456

PLACE C2456 AT BALL AG28

CERM 402

1UF

10%

PLACE C2426 AT BALL AU30

C2426

1UF

402

CERM

6.3V

10%

C2411

10%

X5R

16V

402

1UF

PLACE C2411 AT BALL AJ20

2.2UF

10%

X5R

6.3V

PLACE C2412 AT BALL AV30

C2455

402

C2490

0.1UF

10% 16V X7R-CERM 0402

C2413

0.1UF

10% 16V X7R-CERM 0402

C2484

0.1UF

10% 16V X7R-CERM 0402

C2430

0402

X7R-CERM

16V

10%

0.1UF

C2417

X7R-CERM

0.1UF

10% 16V

0402

C2421

0.1UF

10% 16V X7R-CERM 0402

C2423

0402

X7R-CERM

16V

0.1UF

10%

C2424

0.1UF

0402

X7R-CERM

16V

10%

C2447

X7R-CERM

10%

0402

16V

0.1UF

SYNC_DATE=N/A

SYNC_MASTER=D8_MLB

PCH DECOUPLING

PP1V8_S0_PCH_VCCVRM_F

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM

PP5V_S5_PCH_V5REFSUS

MAKE_BASE=TRUE

=PP3V3_S0_PCH_VCC_HVCMOS

=PP3V3_S0_PCH_VCC

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3_S0_PCH_VCC_PCI

=PP3V3_S5_PCH_VCCSUS_USB

=PP5V_S0_PCH

=PP5V_S0_PCH_V5REF

=PP1V05_S0_PCH_VCC_ASW

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO_DMI

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCC_DIFFCLK

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_S5_PCH_VCCSUS_HDA

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S5_PCH_VCC_DSW

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S0_PCH

=PP1V05_S0_PCH_VCC_SSC

=PP3V3_S5_PCH =PP5V_S5_PCH

=PP1V8_S0_PCH_VCC_VRM

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S0_PCH_VCC_GPIO

=PP1V05_S0_PCH_VCCCLKDMI

=PP5V_S5_PCH_V5REFSUS

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

prefsb

051-9504

7.0.0

24 OF 143

24 OF 117

2

1

2

1

6

1

5

3

4

2

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

22

115

6

22

6

22

6

22

6

22

6

22

6

22

6

22

6

22

6

22

6

18 19 22

6

22

6

22

6

22

6

18 22

6

22

6

22

6

18 21

6

22

6

19 26

6

22

6

22

6

22

6

22

115

BI

IN

NC

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

BI

IN

OUT

IN

OUT

IN

NC NC

NC

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- Unused GPIOs 0 & 15 not isolated.

be replaced with aliases. Otherwise these R’s must

and path to non-XDP signal destination.

Pull-up to 3.3V on csa 26 (PCH Support)

1K series resistor on csa 26 (PCH Support)

Connects to PCH XDP Conn

- For isolated GPIOs:

- MXM_GOOD not isolated as only LED is affected.

needs to split between route from PCH to J2550

- ’Output’ PCH/XDP signals require pulls.

PCH Signals

oc7#/gpio14

xdp_present#

obsdata_c1

sata2gp/gpio36 sata3gp/gpio37

gpio15

PCH Micro2-XDP

1K series resistor on csa 26 (PCH Support)

obsdata_b0

obsdata_c2 obsdata_c3

obsen_d1

obsen_c0

obsdata_c2

obsen_d0

obsdata_c1

obsdata_a2

trstn

itpclk/hook4

obsen_a1

obsdata_d3

itpclk#/hook5

reset#/hook6

obsdata_c3

obsen_d1

tms

tdi

tdo

dbr#/hook7

vcc_obs_cd

obsen_c0

obsen_d0

obsdata_c0

obsen_c1

itpclk/hook4

tdo

tdi tms

obsdata_a2 obsdata_a3

obsen_b0

vcc_obs_ab

pwrgd/hook0

scl

sda

hook3

hook1

obsdata_b2

obsen_b1

hook2

obsdata_b0

tck0

tck1

scl

sda

vcc_obs_ab hook2 hook3

hook1

pwrgd/hook0

obsdata_b3

obsdata_b2

obsdata_b1

obsdata_a1

obsdata_a0

obsen_a1

obsen_a0

obsdata_b1

obsdata_b3

CPU Micro2-XDP

obsdata_a1

PCH/XDP Signal Isolation Notes:

events while using PCH XDP.

obsdata_d0 obsdata_d1

obsdata_d2

obsdata_c0

obsen_c1

obsen_a0

XDP Signals

- ’Output’ non-XDP signals require pulls.

If PCH XDP not implemented, all of R2524-R2537 can

connect to appropriate non-XDP signals on PCB.

obsen_b1

obsen_b0

oc3#/gpio42

oc2#/gpio41

oc0#/gpio59

oc6#/gpio10

oc5#/gpio9

sata1gp/gpio19

sata0gp/gpio21

gpio0

gpio35

sata5gp/gpio49

sata4gp/gpio16

mgpio7/gpio28

xdp_present#

trstn

dbr#/hook7

itpclk#/hook5

obsdata_d2

obsdata_d1

obsdata_d0

oc4#/gpio43

oc1#/gpio40

obsdata_a3

obsdata_d3

vcc_obs_cd reset#/hook6

be stuffed even in production so that PCH pins

R2524-R2537 should be placed where signal path

- USB OC#’s not isolated, avoid USB port overcurrent

tck0

tck1

998-2516

11 99

10 99

25 50

11 25 99

10 99

10 25 99

10 15 99

10 99

10 15 99

10 99

10 15 99

10 99

26 99

11 25 99

SW2600.2:350MM

0

R2506

XDP

1/16W

5%

MF-LF

402

19 26 47

115

R1553.1:5MM

402

MF-LF

0

R2505

5%

XDP

1/16W

R1554.1:5MM

0

XDP

1/16W

402

5%

R2504

MF-LF

15 18 99

11 99

U1000.J40:25MM

XDP

R2500

1/16W5%402

MF-LF

1K

MF-LF

U4900.D10:350MM

0

R2501

402

1/16W

XDP

5%

MF-LF

U1000.H36:25MM

1K

5%

1/16W

402

XDP

R2502

5%

XDP

1/16W

402

MF-LF

0

R2503

J2500.47:10MM

5

65 66

115

10 25 99

15 19 25 47

115

11 21 28 99

J2500.52:10MM

402

1/16W

51

MF-LF

5%

XDP

R2510

MF-LF

U1000.L40:10MM

402

1/16W

5%

51

XDP

R2511

U1000.L38:10MM

402

MF-LF

1/16W

5%

51

XDP

R2512

U1000.J39:10MM

402

MF-LF

1/16W

5%

51

XDP

R2513

U1000.M40:10MM

402

MF-LF

1/16W

5%

51

XDP

R2514

25 99

26 99

18 25 99

25 99

25 50

18 25 99

25 99

15 19 25 47

115

J2550.30:10MM

XDP

402

MF-LF

1/16W

5%

1K

R2550

6

25

402

5%

U1800.BC50:10MM

200

1/16W MF-LF

XDP

R2562

MF-LF

5% 1/16W

402

200

U1800.BC52:10MM

XDP

R2561

51

5%

402

1/16W MF-LF

U1800.BA43:10MM

XDP

R2566

J2500.52:121MM

XDP

MF-LF

5%

200

1/16W

R2560

402

20 99

21 99

18 99

21 99

CRITICAL

M-ST-SM

XDP_CONN

DF40RC-60DP-0.4V

J2500

CRITICAL

DF40RC-60DP-0.4V

XDP_CONN

M-ST-SM

J2550

NOSTUFF

R2567

402

0

5%

MF-LF

1/16W

1/16W MF-LF 402

5%

100

U1800.BA43:10MM

XDP

R2565

1/16W

5%

402

MF-LF

100

U1800.BA43:10MM

XDP

R2564

J2500.52:121MM

R2563

XDP

100

1/16W MF-LF 402

5%

R2520

5%

402

MF-LF

1/16W

33

5%

402

MF-LF

33

1/16W

R2521

5%

MF-LF

33

402

1/16W

R2522

MF-LF

402

1/16W

5%

33

R2523 R2524

1/16W

5%

402

MF-LF

33

5%

1/16W

402

MF-LF

33

R2525

4025%1/16W

MF-LF

33

R2526

5%

1/16W

MF-LF

33

402

R2527

402

1/16W

MF-LF

33

5%

R2537

1/16W

33

402

MF-LF

R2528

5%

33

402

MF-LF

1/16W

5%

R2529

33

MF-LF

4025%1/16W

R2530

1/16W

5%33MF-LF

402

R2533

402

MF-LF335%

1/16W

R2534

402

MF-LF

5%

33

1/16W

R2535

MF-LF

1/16W

5%

33

402

R2536

21 99

MF-LF

33

402

1/16W

5%

R2531

402

MF-LF

1/16W

5%

33

R2532

11 25 99

U4900.D10:117MM

XDP

R2551

0

1/16W

MF-LF

402

5%

0402

XDP

X7R-CERM

C2500

0.1UF

10% 16V

X7R-CERM

16V

10%

0402

0.1UF

C2501

XDP

C2551

X7R-CERM

16V

10%

0402

0.1UF

XDP

C2550

0.1UF

0402

XDP

X7R-CERM

10% 16V

CPU and PCH XDP

SYNC_MASTER=D7_MLB

SYNC_DATE=01/26/2012

=PP3V3_S5_XDP

=PPVCCIO_S0_XDP

=SMBUS_XDP_SCL

XDP_CPU_PWRGD XDP_CPU_PWRBTN_L

XDP_CPU_TMS

=PP3V3_S5_XDP

XDP_CPU_TDI

VOLTAGE=3.3V

PP3V3_S5_XDP_R

MAX_NECK_LENGTH=3MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

ISOLATE_CPU_MEM_R_L

XDP_PIN03

XDP_DA3_USB_EXTD_OC_L

USB_EXTD_OC_R_L USB_EXTB_OC_EHCI_R_L USB_EXTD_OC_EHCI_R_L

USB_EXTA_OC_R_L USB_EXTB_OC_R_L USB_EXTC_OC_R_L

PM_PWRBTN_L

=PP3V3_S5_XDP

XDP_PCH_PWRGD

CPU_CFG<2>

CPU_CFG<7>

XDP_FC0_PCH_GPIO15 XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_DD3_ENET_LOW_PWR_PCH

XDP_DB2_AP_PWR_EN

CPU_CFG<3>

CPU_CFG<8> CPU_CFG<9>

XDP_CPU_TDO

XDP_DBRESET_L

XDP_PCH_TCK

XDP_DA1_USB_EXTB_OC_L

XDP_FC0_PCH_GPIO15

GPU_GOOD_R

DP_TBT_SEL_R

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA2_USB_EXTC_OC_L

XDP_DA1_USB_EXTB_OC_L

SDCONN_STATE_CHANGE_R

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_CPU_PLTRST_L

XDP_DA0_USB_EXTA_OC_L

XDP_DD3_ENET_LOW_PWR_PCH

XDP_DC1_GPU_GOOD

XDP_PCH_PLTRST_L

XDP_PCH_TMS

XDP_DB1_USB_EXTD_OC_EHCI_L

=SMBUS_XDP_SDA

XDP_PCH_TCK

XDP_DB2_AP_PWR_EN XDP_DB3_SDCONN_STATE_CHANGE

CPU_CFG<1>

CPU_CFG<17>

CPU_CFG<0>

XDP_BPM_L<0> XDP_BPM_L<1>

XDP_BPM_L<2>

CPU_CFG<4>

XDP_CPU_PRDY_L

CPU_CFG<10> CPU_CFG<11>

=SMBUS_XDP_SDA

XDP_CPU_TCK

XDP_BPM_L<3>

XDP_CPU_PREQ_L

=PPVCCIO_S0_XDP

ITPXDP_CLK100M_P

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_TDI XDP_CPU_TMS XDP_CPU_TCK

XDP_CPU_CFG<0>

PM_SYSRST_L

CPU_CFG<16>

XDP_DD2_AUD_IPHS_SWITCH_EN_PCH

XDP_DD1_JTAG_TBT_TCK

XDP_DD0_DP_TBT_SEL

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DD1_JTAG_TBT_TCK

TBT_CIO_PLUG_EVENT_R

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_PCH_TDI

XDP_DC3_SATARDRVR_EN

XDP_DC2_DP_AUXCH_ISOL

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_PCH_TDI

XDP_PCH_TDO

XDP_DC2_DP_AUXCH_ISOL

XDP_DC1_GPU_GOOD

XDP_DA3_USB_EXTD_OC_L

AUD_IPHS_SWITCH_EN_PCH_R ENET_LOW_PWR_PCH_R

PM_PGOOD_REG_CPUCORE_S0

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_PCH_TDO

=SMBUS_XDP_SCL

XDP_PCH_PWRBTN_L

AP_PWR_EN_R

XDP_DD0_DP_TBT_SEL

XDP_DA2_USB_EXTC_OC_L

XDP_BPM_L<6>

CPU_CFG<0>

XDP_PCH_TMS

XDP_DD2_AUD_IPHS_SWITCH_EN_PCH

XDP_DC3_SATARDRVR_EN

ITPXDP_CLK100M_N

CPU_CFG<6>

CPU_CFG<5>

SATARDRVR_EN_R

CPU_PWRGD

JTAG_TBT_TCK_R

XDP_VR_READY

XDP_CPU_TRST_L

XDP_DBRESET_L

XDP_CPU_CLK100M_N

XDP_CPU_CLK100M_P

DP_AUXCH_ISOL_R

PM_PWRBTN_L

prefsb

051-9504

7.0.0

25 OF 143

25 OF 117

12

1

2

1

2

1

2

1

2

1

2

12

1

2

1

2

1

2

1

2

53

51

43

41

35

29

23

19

17

15

11

7

5

9

3

2

13

10

12

14

16

8

1

21

27

33

37

39

45

47

49

57

55

59

6

20

22

24

26

32

30

38

42

44

48

46

50

52

54

58

56

60

28

40

18

4

34

36

25

31

61

62

6364

53

51

43

41

35

29

23

19

17

15

11

7

5

9

3

2

13

10

12

14

16

8

1

21

27

33

37

39

45

47

49

57

55

59

6

20

22

24

26

32

30

38

42

44

48

46

50

52

54

58

56

60

28

40

18

4

34

36

25

31

61

62

6364

12

1

2

1

2

1

2

12

2

1

2

1

2

1

2

1

6

25

6

25

99

6

25

115

99

25 99

18 25 99

25 99

6

25

11 25 99

99

25 99

18 25 99

25 99

99

25 99

18 25 99

25 99

99

OUT

NCNC

OUT

IN

OUT

IN

NCNC

OUT

IN

OUT

IN

OUT

NC

OUT

NC

OUT

GND

VDD

25MHZ_A

VDDIO_B

VDDIO_A

VDDIO_C

25MHZ_B 25MHZ_C

THRM

XIN

XOUT

PAD

NC

OUT

Y

A

B

08

OUT

Y

A

B

08

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MAY NEED TO MOVE LONGER TRACE ONES TO BUFFERED

PCH RTC Crystal

Reset Button

OPEN-DRAIN BUFFER

System 25MHz Clock Generator

PCH 25MHZ CLOCK

From GreenClk @ 1.8V

To PCH @ 1.1V

Ethernet XTAL Power SB XTAL Power TBT XTAL Power

Unbuffered

Platform Reset Connections

Buffered

ENET > S0 > TBT, so ENET is used here.

VDD must be powered if any VDDIO is.

GreenClk 25MHz Power

VTT VOLTAGE DIVIDER AND PU ON CPU PAGE

Clock series termination

511-0054

RDAR://11218892 TESTPOINT TO RESET RTC FOR APPLE CARE

GPIO Isolation to prevent glitches on critical core well GPIOs

Coin-Cell Holder

RTC Power Sources

NOTE: 30 PPM crystal required

19 25 47

115

1

1K

402

2

MF-LF

5%

1/16W

R2602

BAT54DW-X-G

SOT-363

D2600

33

MF-LF

402

5%

1/16W

R2681

MF-LF

R2690

1/16W

5%

402

33

49

112

75 82

113

18

101

18

101

20

114

PLACE_NEAR=U1800.AN14:10mm

MF-LF

33

5%

1/16W

402

R2626

PLACE_NEAR=U1800.AT11:10mm

MF-LF

402

33

5%

1/16W

R2625

20

101

49

101

47

101

20

101

18

101

R2627

PLACE_NEAR=U1800.AT14:10mm

33

402

1/16W

5%

MF-LF

20

101

20%

C2680

0.1UF

10V

CERM

402

MF-LF

5%

100K

1/16W

402

R2680

J2600

SM

BB10201-C1403-7H

MF-LF

402

10M

1/16W

5%

R2611

MC74VHC1G08

SOT23-5-HF

U2680

0.1UF

20% 10V

CERM

402

C2690

402

MF-LF

0

R2610

1/16W

5%

25 99

402

1K

XDP

MF-LF

R2699

5%

1/16W

35

112

1/16W

5%

402

MF-LF

33

R2688

1/16W

5%

402

MF-LF

33

R2655

SC70

U2690

74LVC1G07

XDP

R2698

1/16W MF-LF

5%

1K

402

25 99

41

113

402

MF-LF

5%

1/16W

33

R2692

18

101

36

101

CERM

10V

20%

402

0.1UF

C2620

402

CERM

20%

0.1UF

10V

C2622C2624

0.1UF

402

20%

10V

CERM

0

5%

MF-LF

1/16W

R2605

402

NO STUFF

5%

MF-LF 402

1M

R2606

1/16W

39

101

PLACE_NEAR=U2600.4:10MM

MF-LF

1/16W

402

5%

33

R2628

CERM

6.3V

10%

1UF

402

C2602

U2600

CRITICAL

TDFN

SLG3NB146V

CRITICAL

32.768K-12.5PF

SM-HF

Y2610

SILK_PART=SYS RESET

0

5%

MF-LF 402

1/16W

R2696

NOSTUFF

47

116

R2694

VREFMRGN:EXT

33

5% 1/16W MF-LF

402

28 34

114

11 99

38

15 36

117

PLACE_NEAR=U2650.8:2MM

C2650

20%

0.1UF

CERM 402

10V

74LVC2G08GT

U2650

8

4

CRITICAL

SOT833

60

PLACE_NEAR=U2660.5:2MM

C2660

20% 10V CERM

0.1UF

402

SOT833

74LVC2G08GT

8

4

CRITICAL

U2650

U2660

SOT23-5-HF

MC74VHC1G08

39 41

113

MF-LF 402

5% 1/16W

4.7K

R2697

1/16W

402

MF-LF

140

1%

R2672

1%

402

MF-LF

1/16W

40.2

R2671

SW2600

NTC020AA1JB260T

SM

SILK_PART=SYS RESET

DEVELOPMENT

R2691

1/16W MF-LF

5%

402

33

C2605

12PF

5%

50V

0402

C0G-CERM

0402

C0G-CERM

50V

5%

12PF

C2606

12PF

5%

50V

C0G-CERM

0402

C2610

PLACE_NEAR=Y2610.3:7MM

C2611

5%

50V

C0G-CERM

0402

PLACE_NEAR=Y2610.1:2MM

12PF

TP2601

1.97X2.02MM-NSP

OMIT

SMT-PAD

TP2603

1.4-SQ-NSP

SM-PAD

OMIT

SMT-PAD

OMIT

TP2600

1.97X2.02MM-NSP

TP2602

1.4-SQ-NSP

OMIT

SM-PAD

CRITICAL

3.2X2.5MM-SM

25.000MHZ-20PPM-12PF-85C

Y2605

SYNC_DATE=N/A

CHIPSET SUPPORT

SYNC_MASTER=D8_MLB

=PP3V3_S5_PCH

AUD_IPHS_SWITCH_EN

LPC_CLK33M_LPCPLUS

LPC_CLK33M_LPCPLUS_R

SYSCLK_CLK25M_X2

PCH_CLK32K_RTCX1

PM_PCH_PWROK

SYSCLK_CLK25M_X1

=PP3V3_G3H_RTC_D

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVBATT_G3_RTC_R

PP3V3_G3_RTC

MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6MM

RTC_RESET_L

VOLTAGE=3.3V

PPVBATT_G3_RTC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 MM

PCH_CLK33M_PCIOUT

ENET_LOW_PWR

PLT_RESET_L

MAKE_BASE=TRUE

TBT_PLT_RST_L

MAKE_BASE=TRUE

SMC_LRESET_L

=PP3V3_S0_RSTBUF

PLT_RST_BUF_L

=TBT_RESET_L

AP_RESET_L

ENET_SD_RESET_L

=PP3V3_S5_PCH

LPC_PWRDWN_L

LPC_CLK33M_SMC_R

=PP1V8_S0_PCH_CLK =PP3V3_TBT_CLK

SYSCLK_CLK25M_X2_R

GPU_RESET_L

DEBUG_RESET_L

LPC_CLK33M_SMC

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_ENET

SYSCLK_CLK25M_TBT

AUD_IPHS_SWITCH_EN_PCH

PM_PCH_PWROK

ENET_LOW_PWR_PCH

PCH_CLK25M_XTALIN

TBT_PWR_EN

=PP3V3_S5_PCH

TBT_PWR_EN_PCH

SYSCLK_CLK25M_SB

XDP_PCH_PLTRST_L

=PP3V3_S4_ENET_SYSCLK

SYSCLK_CLK25M_SB

PCH_CLK33M_PCIIN

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_PM

=PP3V3_S4_ENET_CLK

SYSCLK_CLK25M_ENET_R

CPU_RESET_L

PM_SYSRST_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX2_R

XDP_CPU_PLTRST_L

PCA9557D_RESET_L

prefsb

051-9504

7.0.0

26 OF 143

26 OF 117

3

6

2

4

1

5

12

2

1

2

1

2

1

2

5

1

2

3

4

2

1

12

4

13

2

5

12

2

1

2

1

2

1

12

1

2

12

2

1

9

2

5

367

4 8

11

1

10

41

1

2

12

2

1

7

2

1

2

1

3

6

5

1

2

3

4

1

2

1

2

12

132

4

12

1

42

13

6

19 24 26

101

15 19 26 35 43 65 89

115

101

6

116

6

115

18 48

116

6

26

114

6

19 24 26

19 47 49

114

6

101

26

101

21 99

15 19 26 35 43 65 89

115

15 21 99

6

19 24 26

18

117

26

101

6

26

101

6

26

6

26

101

BI

NC NC

TEST1

USBDM_DN1

USBDP_DN1

VBUS_DET

USBDP_DN2 USBDM_DN2

SUSP_IND/NON_REM0

VDD33

NC

XTALOUT

XTALIN/CLKIN

TEST

RESET*

HS_IND

NON_REM1

PLLFILT

CRFILT

VDD33

USBDM_UP

USBDP_UP

PRTPWR1 PRTPWR2

OCS1* OCS2*

RBIAS

VDD33

EPAD

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NON_REM 0 and 1 are used to indicate whether the downstream ports are removable or captive

NON_REM[1:0] = 1x ---> ports 1 and 2 are non-removable

via array to GND

NON_REM[1:0] = 01 ---> port 1 is non-removable

ePad needs a minimum of 3x3

NON_REM[1:0] = 00 ---> ports 1 and 2 are removable

155S0220

338S1076

50mV P-P spec @ 100k-1MHz

PLACE_NEAR=U2700.26:2MM

1%

402

1/16W

12K

R2707

MF

20

102

20

102

35

102

35

102

R2705

1/16W

5%

402

MF-LF

100K

R2708

402

100K

MF-LF

5% 1/16W

5%

10K

MF-LF

1/16W

402

R2703

C2705

6.3V

603

4.7UF

10%

X5R-CERM

1UF

10%

C2708

X5R

16V

402

MF-LF

5%

1M

1/16W

R2706

R2711

201

5%

1/20W

MF

4.7K

1/16W

402

R2704

100K

5%

MF-LF

USB2412-DZK

QFN

CRITICAL

U2700

MF-LF

0

5%

402

R2709

1/16W

35 64 74

115

5%

1/20W

R2710

MF

201

4.7K

0402

L2700

FERR-120-OHM-1.5A

50V

C2701

0402

C0G-CERM

5%

18PF

0402

50V

C0G-CERM

5%

C2702

MF-LF

5%

1K

402

R2712

1/16W

10%

0.01UF

402

C2712

16V CERM

CRITICAL

Y2700

5X3.2X1.5-SM

24.000M-50PPM-16PF

X7R-CERM

16V

10%

0.1UF

0402

C2709

X7R-CERM

16V

10%

0.1UF

0402

C2710

X7R-CERM

16V

10%

0.1UF

0402

C2711

C2703

10%

0.1UF

0402

16V X7R-CERM

10%

0.1UF

0402

16V X7R-CERM

C2704

C2707

X7R-CERM

16V

10%

0.1UF

0402 0402

0.1UF

10% 16V X7R-CERM

C2706

SYNC_DATE=03/23/2012

SYNC_MASTER=D8_ROSITA

USB 2.0 HUB (BT/SMC)

MIN_NECK_WIDTH=0.25MM MAX_NECK_LENGTH=3MM

PP3V3_S4_USB_HUB_VDD

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

MAX_NECK_LENGTH=3MM

VOLTAGE=1.2V

PP1V2_USB_HUB_PLLFILT

MIN_LINE_WIDTH=0.4MM

PP1V2_USB_HUB_CRFILT

VOLTAGE=1.2V

MAX_NECK_LENGTH=3MM

MIN_NECK_WIDTH=0.2MM

USB_HUB_XTAL2_R

USB_HUB_XTAL1

PM_PGOOD_P3V3_S4_FET

USB_HUB_RESET_L

USB_HUB_NON_REM1

USB_HUB_XTAL2

USB_HUB_NON_REM0

USB_PCH_7_P

USB_HUB_RBIAS

USB_HUB_2N

USB_BT_P

=PP3V3_S4_USB_HUB

USB_PCH_7_N

USB_BT_N

=PP3V3_S4_USB_HUB

USB_HUB_HS_IND

USB_HUB_VBUS_DET

USB_HUB_2P

prefsb

051-9504

7.0.0

27 OF 143

27 OF 117

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

15

28

1

18

3 2

19

14

5

23

24

6

17

16

13

25

92027

10

21

22

7

11

8

12

26

4

29

12

1

2

21

12

2

1

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

115

102

6

27

6

27

6

27

6

27

102

OUT

IN

G

D

S

OUT

D

SG

D

SG

D

SG

D

SG

NC

IN

D

S

G

D

S

G

D

S

OUT

IN

AY

NC NC

VCC

GND

NCNC

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MEMVTT_EN = CPU_PWRGD * PM_SLP_S3_L (VTT is enabled when PCH tells CPU to enable VCCORE)

MEMVTT Clamp actively holds MEMVTT rail low until MEMVTT is enabled.

Clamping MEMVTT will keep the MEM_CKE low until CPU actively controls it.

CPU does not drive MEM_CKE until VCCORE activated but CPU 1V5 (VDDQ) leaks into it.

MEMVTT_EN Generator

Enables MEMVTT when PCH drives CPU PWRGD.

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L (Block CPU from driving MEM_RESET_L in S3)

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuits below handle MEMVTT power during S0->S3->S0 transitions, as well

WHEN LOW: MEM_RESET_L IS ISOLATED.

0

1

1 1

0 (*)

X

CPU_MEM_RESET_L

MEMVTT_EN

1

0

1

1 1

0

1

0

1

1 1

1

0

7

6

5

4

3

2

1

0

PM_SLP_S3_L

ISOLATE_CPU_MEM_L

Step

Rails will power-up as if from S3, but MEM_RESET_L now needs to be asserted in S0. Software

S0

to

S0

to

NOTE: On a S5->S0 transition, ISOLATE_CPU_MEM_L will default low.

must de-assert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

Ensures CKE signals are held low in S3 and in S0 before CPU PWRGD

75mA max load @ 0.75V 60mW max power

MEMVTT Clamp

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

With optional delay from 1V5 S0 PGOOD

1V5 S0 "PGOOD" for CPU

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behaviour of signals. WHEN HIGH: MEM_RESET_L NOT ISOLATED.

MEM_RESET_L Generator

rdar://11117167

S3

PLT_RESET_L equivalent

Open-drain buffer

CPU_PWRGD

CPU_MEM_RESET_L

1

MEM_RESET_L

0

Vih = 0.65 * Vcc = 0.65 * 1.05 = 0.68V

MF-LF

5%

1/16W

402

10K

R2802

28 64

114

28 64

114

100K

MF-LF

402

5%

1/16W

R2851

MF-LF

1/10W

10

603

5%

R2850

MF-LF

402

1/16W

R2820

5%

10K

CRITICAL

Q2820

SOT-563

DMB53D0UV

10K

MF-LF

5%

402

1/16W

R2822

SOT-563

DMB53D0UV

Q2820

CRITICAL

11 19 99

MF-LF 402

5%

10K

1/16W

R2810

Q2810

CRITICAL

SOT563

SSM6N15AFE

CRITICAL

Q2850

SSM6N15AFE

SOT563

Q2850

CRITICAL

SSM6N15AFE

SOT563

Q2810

SOT563

SSM6N15AFE

CRITICAL

74LVC1G07

SC70

U2820

64 74

115

R2985

402

MF-LF

5% 1/16W

20K

50V

C2899

402

10%

CERM

0.0022UF

Q2899

2N7002

SOT23-HF1

5%

1/16W

402

MF-LF

20K

R2897

Q2898

2N7002DW-X-G

SOT-363

R2898

20K

5% 1/16W

402

MF-LF

R2899

1/16W

5%

402

MF-LF

20K

Q2898

SOT-363

2N7002DW-X-G

29 30 31 32 97

21 34 99

11 99

C2821

X7R-CERM

16V

0402

20%

0.01UF

0.001UF

20%

0402

NOSTUFF

C2820

50V CERM

C2851

0.001UF

20%

0402

NOSTUFF

74AUP1G07GF

U2830

SOT891

CRITICAL

C2830

0.01UF

0402

X7R-CERM

16V

20%

402

5%

MF-LF

1/16W

0

R2831

402

0

1/16W MF-LF

5%

NOSTUFF

R2832

R2830

1/16W MF-LF

402

10K

5%

5

15 19 40 47 48 64

115

26 34

114

11 21 25 99

MF-LF

1/16W

0

5%

402

R2833

20%

0.01UF

16V

C2831

NOSTUFF

X7R-CERM 0402

SYNC_DATE=04/23/2012

CPU Memory S3 Support

SYNC_MASTER=D8_MARK

PM_PGOOD_REG_ALL_P1V05_S0_R

=PPVCCIO_S0_CPU

CPU_PWRGD

MEMVTT_EN

PCA9557D_RESET_L

CPU_PWRGD_3V3_R

PM_SLP_S3_L

=PPDDRVTT_S0_CLAMP

ISOLATE_CPU_MEM_5V

ISOLATE_CPU_MEM_L

CPU_MEM_RESET_L

MEM_RESET_L

=PP5V_S4_MEMRESET

=PPVDDQ_S3_MEMRESET

=PP3V3_S4_MEMRESET

=PP3V3_S4_PM

PM_MEM_PWRGD_L

PM_MEM_PWRGD

PM_PGOOD_FET_VDDQ_S0

MEMVTT_EN

PGOOD_P1V5_S0_DLY

=PP3V3_S0_PWRCTL

VTTCLAMP_EN

=PP3V3_S0_PWRCTL

=PP3V3_S4_MEMRESET

MIN_NECK_WIDTH=0.25mm MIN_LINE_WIDTH=0.25mm

VTTCLAMP_L

CPU_PWRGD_1V05_R

ISOLATE_CPU_MEM_5V_L

CPU_PWRGD_3V3

MEMVTT_EN_L

prefsb

051-9504

7.0.0

28 OF 143

28 OF 117

1

2

1

2

1

2

1

2

4

5

3

1

2

6

2

1

2

3

4

5

6

1

2

3

4

5

6

1

2

4

13

2

5

1

2

1

32

1

2

3

5

4

1

2

1

2

6

2

1

2

1

2

1

2

1

2

4

1

5

63

2

1

12

1

2

12

2

1

64

115

6

10 11 13 16 66

112

6

114

6 6 6

28

6

115

114

6

28 74

117

6

28 74

6

28

117

114

112

114

BI

BIBI

BI

IN

BI

IN

BI

IN

BI

IN

BI

OUT

BI

IN

BI

NC

BI

DQ0

VREFDQ VSS_1

VSS_3 DM0

VSS_12 DQ16

VSS_14

DQ18

VSS_21

VSS_24

DQ27

EVENT*

DQS7*

DQS6*

DQS5*

DQS4*

S1*

CAS*

S0*WE*

RAS*

CK1*CK0*

DQS3*

DQS2*

RESET*

DQS1*

DQS0*

DQ31

VDD_0 NC_0 BA2 VDD_2 A12/BC* A9

A8

VSS_50

VTT_0

VDDSPD SA1

SA0

DQ59

VSS_48 DQ58

DM7

VSS_47

DQ57

DQ56

VSS_45

DQ50 DQ51

DQ49 VSS_40

DQS6 VSS_43

DQ48

VSS_36 DQ42 DQ43 VSS_38

DM5

DQ40

VSS_35

VSS_33

DQ41

DQ35

VSS_28

DQS4 VSS_31 DQ34

DQ32

TEST

VDD_16

VSS_26

DQ33

VDD_10

VDD_6

A1 VDD_8 CK0

VDD_4

A5

CKE0

VSS_22

DM3

DQ26

VSS_19

DQ19

DQ25

DQ24

VSS_17

DQS2

DQ17

DQ10 DQ11

VSS_10

DQS1

VSS_8

DQ9

DQ8

VSS_6

DQ3

DQ2

SCL

SDA

VSS_49

DQ62 DQ63

VSS_51

DQS7

VTT_1

DM6

DQ53

VSS_41

VSS_42

DQ60 DQ61

VSS_46

DQ52

DQ45

VSS_34

VSS_39

DQS5

VSS_37

DQ46

DQ44

DQ47

VSS_32

DM4

VDD_17 VREFCA VSS_27

DQ36 DQ37

VSS_29

VSS_30

DQ38 DQ39

BA1

VDD_11

VDD_13

ODT0

VDD_15

ODT1 NC_1

CK1

A0

A2

A6 A4

A11

A7

VDD_7

VDD_5

VDD_9

VDD_3

A14

A15

CKE1

VDD_1

VSS_25

DQ30

DQS3

VSS_23

DM2

DQ29

VSS_20

DQ28

DQ23

VSS_18

VSS_16

DQ22

VSS_15

DQ21

DM1

DQ13

VSS_9

VSS_11

DQ14 DQ15

VSS_13

DQ20

DQ12

VSS_7

VSS_4

DQ1

DQ7

DQ6

DQ4 DQ5

DQS0

VSS_5

VSS_2

VSS_0

VSS_44

DQ55

DQ54

A3

A10_AP BA0 VDD_12

VDD_14 A13

KEY

SYM 1 OF 2

SYM 2 OF 2

MTG HOLE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

P/N: 516S1030

Power aliases required by this page:

- =PPDDRVTT_S0_MEM_A

- =I2C_SODIMMA_SDA

BOM options provided by this page:

- =PPVDDQ_S3_MEM_A

- =PP1V5_S0_MEM_A

(NONE)

Page Notes

- =I2C_SODIMMA_SCL

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

30 33

10V CERM

C2931

20%

0.1UF

402

CERM

20%

402-LF

2.2UF

C2930

6.3V

30 33

12 97

30 33

28 30 31 32 97

30 33

12 30 97

12 97

12 30 97

12 97

30 33

12 97

30 33

10V

20%

402

CERM

0.1UF

C2936

6.3V

C2935

20%

402-LF

CERM

2.2UF

30 33

30 31 32 47 48

114

30 50

12 97

12 30 97

12 97

12 30 97

12 97

30 33

10K

5%

R2941

MF-LF 402

1/16W

10K

R2940

1/16W

5%

402

MF-LF

20%

6.3V CERM 402-LF

C2940

2.2UF

C2900

6.3V

20%

603

X5R

10UF

C2901

6.3V 603

X5R

10UF

20%

C2910

0.1UF

CERM

20% 10V

402

C2911

0.1UF

402

20% 10V CERM

C2912

10V

20%

402

CERM

0.1UF

C2913

0.1UF

CERM 402

20% 10V 10V

20%

C2914

CERM 402

0.1UF

C2915

10V

20%

402

CERM

0.1UF

20%

C2916

10V 402

CERM

0.1UF

CERM

C2917

0.1UF

402

20% 10V

C2918

10V

20%

402

CERM

0.1UF

C2919

10V

20%

402

CERM

0.1UF

10V

20%

402

CERM

0.1UF

C2920 C2921

402

20% 10V CERM

0.1UF

C2922

10V

20%

402

CERM

0.1UF

C2923

20%

402

CERM

0.1UF

10V

1UF

X5R 402

10% 10V

C2953C2952

10V

10%

402

X5R

1UF

C2951

1UF

X5R 402

10% 10V

C2950

10V

10%

402

X5R

1UF

30 33

F-ANG-SM-2

J2900

SODIMM-P0.60-D8

F-ANG-SM-2

J2900

SODIMM-P0.60-D8

SYNC_MASTER=D8_KOSECOFF

DDR3 SO-DIMM Connector A Slot0

SYNC_DATE=03/19/2012

=MEM_A_DQ<4>

MEM_A_CKE<0>

=PPVDDQ_S3_MEM_A

MEM_A_WE_L

=MEM_A_DQ<0>

=PPDDRVREF_DQ_MEM_A

=MEM_A_DQ<16>

=MEM_A_DQ<18>

=MEM_A_DQ<27>

MEM_EVENT_L

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_CS_L<0>

MEM_A_RAS_L

MEM_A_CLK_N<1>MEM_A_CLK_N<0>

=MEM_A_DQS_N<3>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<0>

=MEM_A_DQ<31>

MEM_A_BA<2>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

=PPDDRVTT_S0_MEM_A

=PP3V3_S0_MEM_A_SPD MEM_DIMM0_SA<1>

MEM_DIMM0_SA<0>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

=MEM_A_DQ<57>

=MEM_A_DQ<56>

=MEM_A_DQ<50> =MEM_A_DQ<51>

=MEM_A_DQ<49>

=MEM_A_DQS_P<6>

=MEM_A_DQ<48>

=MEM_A_DQ<42> =MEM_A_DQ<43>

=MEM_A_DQ<40> =MEM_A_DQ<41>

=MEM_A_DQ<35>

=MEM_A_DQS_P<4>

=MEM_A_DQ<34>

=MEM_A_DQ<32> =MEM_A_DQ<33>

MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_A<5>

=MEM_A_DQ<26>

=MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<24>

=MEM_A_DQS_P<2>

=MEM_A_DQ<17>

=MEM_A_DQ<10> =MEM_A_DQ<11>

=MEM_A_DQS_P<1>

=MEM_A_DQ<8>

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=MEM_A_DQ<62> =MEM_A_DQ<63>

=MEM_A_DQS_P<7>

=PPDDRVTT_S0_MEM_A

=MEM_A_DQ<53>

=MEM_A_DQ<60> =MEM_A_DQ<61>

=MEM_A_DQ<52>

=MEM_A_DQ<45>

=MEM_A_DQS_P<5>

=MEM_A_DQ<46>

=MEM_A_DQ<44>

=MEM_A_DQ<47>

=PPVDDQ_S3_MEM_A

=PPDDRVREF_CA_MEM_A

=MEM_A_DQ<36> =MEM_A_DQ<37>

=MEM_A_DQ<38> =MEM_A_DQ<39>

MEM_A_BA<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<6> MEM_A_A<4>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=MEM_A_DQ<30>

=MEM_A_DQS_P<3>

=MEM_A_DQ<29>

=MEM_A_DQ<28>

=MEM_A_DQ<23>

=MEM_A_DQ<22>

=MEM_A_DQ<21>

=MEM_A_DQ<13>

=MEM_A_DQ<14>

=MEM_A_DQ<20>

=MEM_A_DQ<12>

=MEM_A_DQ<1>

=MEM_A_DQ<7>

=MEM_A_DQ<6>

=MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<55>

=MEM_A_DQ<54>

MEM_A_A<3>

MEM_A_A<10> MEM_A_BA<0>

MEM_A_A<13>

MEM_DIMM0_SA<0>

=PP3V3_S0_MEM_A_SPD

MEM_DIMM0_SA<1>

MEM_RESET_L

=MEM_A_DQ<15>

=MEM_A_DQS_N<1>

=MEM_A_DQ<9>

=MEM_A_DQ<2> =MEM_A_DQ<3>

prefsb

051-9504

7.0.0

29 OF 143

29 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

5

1 3

9

11

37 39

43

51

61

71

69

198

186

169

152

135

121

115

114113

110

104103

62

45

30

27

10

70

75 77 79 81 83 85

89

195

203

199 201

197

193

189 191

187

185

183

181

179

175 177

165 167

171 173

163

155 157 159 161

153

147

151

145

149

143

133

137 139 141

129

125

123

127

131

105

93

97 99

101

87

91

73

65

63

67

55

53

59

57

49

47

41

33 35

31

29

25

23

21

19

17

15

202

200

190 192 194 196

188

204

170

166 168

172

180 182 184

164

148 150

162

154 156 158

146

160

144

136

124 126 128 130 132 134

138 140 142

108

106

112

116 118 120 122

102

98

96

90 92

84 86

94

88

100

82

80

78

74 76

72

68

64 66

46

58 60

56

52 54

48 50

44

42

28

24 26

32 34 36 38 40

22

20

13

7

18

16

4 6

12 14

8

2

178

176

174

95

107 109 111

117 119

205 206 207 208 209

6

29 30

6

30

6

29 30

6

29 30

29

6

29 30

6

29 30

6

30

29

6

29 30

29

BI

BIBI

BI

IN

BI

IN

BI

IN

BI

IN

BI

OUT

BI

IN

BI

NC

BI

DQ0

VREFDQ VSS_1

VSS_3 DM0

VSS_12 DQ16

VSS_14

DQ18

VSS_21

VSS_24

DQ27

EVENT*

DQS7*

DQS6*

DQS5*

DQS4*

S1*

CAS*

S0*WE*

RAS*

CK1*CK0*

DQS3*

DQS2*

RESET*

DQS1*

DQS0*

DQ31

VDD_0 NC_0 BA2 VDD_2 A12/BC* A9

A8

VSS_50

VTT_0

VDDSPD SA1

SA0

DQ59

VSS_48 DQ58

DM7

VSS_47

DQ57

DQ56

VSS_45

DQ50 DQ51

DQ49 VSS_40

DQS6 VSS_43

DQ48

VSS_36 DQ42 DQ43 VSS_38

DM5

DQ40

VSS_35

VSS_33

DQ41

DQ35

VSS_28

DQS4 VSS_31 DQ34

DQ32

TEST

VDD_16

VSS_26

DQ33

VDD_10

VDD_6

A1 VDD_8 CK0

VDD_4

A5

CKE0

VSS_22

DM3

DQ26

VSS_19

DQ19

DQ25

DQ24

VSS_17

DQS2

DQ17

DQ10 DQ11

VSS_10

DQS1

VSS_8

DQ9

DQ8

VSS_6

DQ3

DQ2

SCL

SDA

VSS_49

DQ62 DQ63

VSS_51

DQS7

VTT_1

DM6

DQ53

VSS_41

VSS_42

DQ60 DQ61

VSS_46

DQ52

DQ45

VSS_34

VSS_39

DQS5

VSS_37

DQ46

DQ44

DQ47

VSS_32

DM4

VDD_17 VREFCA VSS_27

DQ36 DQ37

VSS_29

VSS_30

DQ38 DQ39

BA1

VDD_11

VDD_13

ODT0

VDD_15

ODT1 NC_1

CK1

A0

A2

A6 A4

A11

A7

VDD_7

VDD_5

VDD_9

VDD_3

A14

A15

CKE1

VDD_1

VSS_25

DQ30

DQS3

VSS_23

DM2

DQ29

VSS_20

DQ28

DQ23

VSS_18

VSS_16

DQ22

VSS_15

DQ21

DM1

DQ13

VSS_9

VSS_11

DQ14 DQ15

VSS_13

DQ20

DQ12

VSS_7

VSS_4

DQ1

DQ7

DQ6

DQ4 DQ5

DQS0

VSS_5

VSS_2

VSS_0

VSS_44

DQ55

DQ54

A3

A10_AP BA0 VDD_12

VDD_14 A13

KEY

SYM 1 OF 2

SYM 2 OF 2

MTG HOLE

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- =I2C_SODIMMA_SDA

- =PPDDRVTT_S0_MEM_A

Page Notes

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =I2C_SODIMMA_SCL

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

- =PPVDDQ_S3_MEM_A

Power aliases required by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

P/N: 516S1030

29 33

402

CERM

C3031

20% 10V

0.1UF

CERM

2.2UF

402-LF

20%

6.3V

C3030

29 33

12 97

29 33

28 29 31 32 97

29 33

12 29 97

12 97

12 29 97

12 97

29 33

12 97

29 33

C3036

0.1UF

CERM 402

20% 10V

402-LF

CERM

C3035

2.2UF

20%

6.3V

29 33

29 31 32 47 48

114

29 50

12 97

12 29 97

12 97

12 29 97

12 97

29 33

R3041

10K

MF-LF 402

5% 1/16W

1/16W

R3040

10K

MF-LF

5%

402

C3040

6.3V

20%

402-LF

CERM

2.2UF

C3000

6.3V

20%

603

X5R

10UF

C3001

6.3V

20%

603

X5R

10UF

C3010

0.1UF

CERM 402

20% 10V

C3011

0.1UF

CERM 402

20% 10V

C3012

0.1UF

CERM 402

20% 10V

C3013

0.1UF

CERM 402

20% 10V

C3014

0.1UF

CERM 402

20% 10V

C3015

0.1UF

CERM 402

20% 10V

C3016

0.1UF

10V

20%

402

CERM

C3017

0.1UF

20% 10V CERM 402

C3018

CERM 402

10V

20%

0.1UF 0.1UF

CERM

10V

C3019

20%

402

C3020

402

CERM

10V

20%

0.1UF

C3021

10V

20%

402

CERM

0.1UF

C3022

10V

20%

402

CERM

0.1UF 0.1UF

C3023

10V

20%

402

CERM

C3053

10V

10%

1UF

X5R 402

C3052

10V

10%

402

X5R

1UF1UF

C3051

10V

10% X5R

402402

C3050

1UF

10% X5R

10V

29 33

F-ANG-SM-2

J3000

SODIMM-P0.60-D8

F-ANG-SM-2

J3000

SODIMM-P0.60-D8

SYNC_DATE=03/19/2012

DDR3 SO-DIMM Connector A Slot1

SYNC_MASTER=D8_KOSECOFF

=PP3V3_S0_MEM_A_SPD

MEM_DIMM1_SA<0>

MEM_DIMM1_SA<1>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_A<10>

MEM_A_A<3>

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQS_P<0>

=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<1>

=MEM_A_DQ<12>

=MEM_A_DQ<20>

=MEM_A_DQ<15>

=MEM_A_DQ<14>

=MEM_A_DQ<13>

=MEM_A_DQ<21>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<28> =MEM_A_DQ<29>

=MEM_A_DQS_P<3>

=MEM_A_DQ<30>

MEM_A_CKE<3>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<2> MEM_A_A<0>

MEM_A_CLK_P<3>

MEM_A_ODT<3>

MEM_A_ODT<2>

MEM_A_BA<1>

=MEM_A_DQ<39>

=MEM_A_DQ<38>

=MEM_A_DQ<37>

=MEM_A_DQ<36>

=PPDDRVREF_CA_MEM_A

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=PPDDRVTT_S0_MEM_A

=MEM_A_DQS_P<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

=I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

=MEM_A_DQ<2> =MEM_A_DQ<3>

=MEM_A_DQ<8> =MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQ<11>

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_P<2>

=MEM_A_DQ<24> =MEM_A_DQ<25>

=MEM_A_DQ<19>

=MEM_A_DQ<26>

MEM_A_CKE<2>

MEM_A_A<5>

MEM_A_CLK_P<2>

MEM_A_A<1>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>

=MEM_A_DQ<41>

=MEM_A_DQ<40>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQ<50>

=MEM_A_DQ<56> =MEM_A_DQ<57>

=MEM_A_DQ<58> =MEM_A_DQ<59>

MEM_DIMM1_SA<0>

MEM_DIMM1_SA<1>

=PP3V3_S0_MEM_A_SPD

=PPDDRVTT_S0_MEM_A

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

=PPVDDQ_S3_MEM_A

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

MEM_RESET_L

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

MEM_A_CLK_N<2> MEM_A_CLK_N<3>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CS_L<2>

MEM_A_CAS_L

MEM_A_CS_L<3>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

MEM_EVENT_L

=MEM_A_DQ<27>

=MEM_A_DQ<18>

=MEM_A_DQ<16>

=PPDDRVREF_DQ_MEM_A

=MEM_A_DQ<0>

prefsb

051-9504

7.0.0

30 OF 143

30 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

5

1 3

9

11

37 39

43

51

61

71

69

198

186

169

152

135

121

115

114113

110

104103

62

45

30

27

10

70

75 77 79 81 83 85

89

195

203

199 201

197

193

189 191

187

185

183

181

179

175 177

165 167

171 173

163

155 157 159 161

153

147

151

145

149

143

133

137 139 141

129

125

123

127

131

105

93

97 99

101

87

91

73

65

63

67

55

53

59

57

49

47

41

33 35

31

29

25

23

21

19

17

15

202

200

190 192 194 196

188

204

170

166 168

172

180 182 184

164

148 150

162

154 156 158

146

160

144

136

124 126 128 130 132 134

138 140 142

108

106

112

116 118 120 122

102

98

96

90 92

84 86

94

88

100

82

80

78

74 76

72

68

64 66

46

58 60

56

52 54

48 50

44

42

28

24 26

32 34 36 38 40

22

20

13

7

18

16

4 6

12 14

8

2

178

176

174

95

107 109 111

117 119

205 206 207 208 209

6

29 30

6

29 30

30

6

29

6

29 30

6

29 30

30

6

29 30

6

29 30

6

29 30

6

29

IN

NC

BI

IN

BI

IN

BI

IN

BI

NC

DQ0

VREFDQ VSS_1

VSS_3 DM0

VSS_12 DQ16

VSS_14

DQ18

VSS_21

VSS_24

DQ27

EVENT*

DQS7*

DQS6*

DQS5*

DQS4*

S1*

CAS*

S0*WE*

RAS*

CK1*CK0*

DQS3*

DQS2*

RESET*

DQS1*

DQS0*

DQ31

VDD_0 NC_0 BA2 VDD_2 A12/BC* A9

A8

VSS_50

VTT_0

VDDSPD SA1

SA0

DQ59

VSS_48 DQ58

DM7

VSS_47

DQ57

DQ56

VSS_45

DQ50 DQ51

DQ49 VSS_40

DQS6 VSS_43

DQ48

VSS_36 DQ42 DQ43 VSS_38

DM5

DQ40

VSS_35

VSS_33

DQ41

DQ35

VSS_28

DQS4 VSS_31 DQ34

DQ32

TEST

VDD_16

VSS_26

DQ33

VDD_10

VDD_6

A1 VDD_8 CK0

VDD_4

A5

CKE0

VSS_22

DM3

DQ26

VSS_19

DQ19

DQ25

DQ24

VSS_17

DQS2

DQ17

DQ10 DQ11

VSS_10

DQS1

VSS_8

DQ9

DQ8

VSS_6

DQ3

DQ2

SCL

SDA

VSS_49

DQ62 DQ63

VSS_51

DQS7

VTT_1

DM6

DQ53

VSS_41

VSS_42

DQ60 DQ61

VSS_46

DQ52

DQ45

VSS_34

VSS_39

DQS5

VSS_37

DQ46

DQ44

DQ47

VSS_32

DM4

VDD_17 VREFCA VSS_27

DQ36 DQ37

VSS_29

VSS_30

DQ38 DQ39

BA1

VDD_11

VDD_13

ODT0

VDD_15

ODT1 NC_1

CK1

A0

A2

A6 A4

A11

A7

VDD_7

VDD_5

VDD_9

VDD_3

A14

A15

CKE1

VDD_1

VSS_25

DQ30

DQS3

VSS_23

DM2

DQ29

VSS_20

DQ28

DQ23

VSS_18

VSS_16

DQ22

VSS_15

DQ21

DM1

DQ13

VSS_9

VSS_11

DQ14 DQ15

VSS_13

DQ20

DQ12

VSS_7

VSS_4

DQ1

DQ7

DQ6

DQ4 DQ5

DQS0

VSS_5

VSS_2

VSS_0

VSS_44

DQ55

DQ54

A3

A10_AP BA0 VDD_12

VDD_14 A13

KEY

SYM 1 OF 2

SYM 2 OF 2

MTG HOLE

NC

BI

OUT

IN

BI

IN

BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

- =PPVDDQ_S3_MEM_B

- =PPDDRVTT_S0_MEM_B

- =PP1V5_S0_MEM_B

Signal aliases required by this page:

BOM options provided by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

(NONE)

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Power aliases required by this page:

Page Notes

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

P/N: 516S1030

C3153

X5R

10V 402

10%

1UF

32 50

12 97

12 32 97

12 97

12 32 97

32 33

C3131

10V 402

20% CERM

0.1UF

12 32 97

32 33

20% CERM

6.3V 402-LF

2.2UF

C3130

32 33

12 97

32 33

12 97

12 32 97

12 97

0.1UF

CERM

10V 402

20%

C3117

12 32 97

12 97

C3123

10V

20%

402

CERM

0.1UF

20%

C3116

0.1UF

CERM 402

10V

12 97

10V 402

C3115

0.1UF

CERM

20%

CERM

C3114

402

20% 10V

0.1UF

10V

C3113

CERM 402

20%

0.1UF

C3122

10V

20%

402

CERM

0.1UF

C3121

10V

0.1UF

CERM 402

20%

0.1UF

C3120

CERM 402

10V

20%

C3119

10V 402

CERM

0.1UF

20%

10V

C3112

20%

402

CERM

0.1UF

C3111

CERM 402

20% 10V

0.1UF

C3110

10V 402

CERM

0.1UF

20%

32 33

C3118

0.1UF

CERM 402

20% 10V

C3101

X5R 603

20%

6.3V

10UF

C3100

10UF

X5R 603

20%

6.3V

SODIMM-P0.60-D8

F-ANG-SM-2

J3100

F-ANG-SM-2

J3100

SODIMM-P0.60-D8

32 33

C3136

20%

402

10V

0.1UF

CERM

32 33

C3135

2.2UF

CERM 402-LF

20%

6.3V

29 30 32 47 48

114

12 32 97

12 97

32 33

C3152

1UF

10V X5R

10%

402

32 33

C3151

X5R 402

10% 10V

1UF

32 33

R3141

1/16W

5% MF-LF

10K

402

R3140

1/16W

5%

402

MF-LF

10K

C3140

6.3V

20%

402-LF

CERM

2.2UF

32 33

C3150

1UF

X5R 402

10% 10V

32 33

28 29 30 32 97

32 33

32 50

32 33

12 32 97

SYNC_DATE=03/19/2012

DDR3 SO-DIMM CONNECTOR B SLOT0

SYNC_MASTER=D8_KOSECOFF

=MEM_B_DQ<6>

=PP3V3_S0_MEM_B_SPD

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_A<10>

MEM_B_A<3>

=MEM_B_DQ<54> =MEM_B_DQ<55>

=MEM_B_DQS_P<0>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<7>

=MEM_B_DQ<1>

=MEM_B_DQ<12> =MEM_B_DQ<13>

=MEM_B_DQ<22> =MEM_B_DQ<23>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_B_DQS_P<3>

=MEM_B_DQ<30>

MEM_B_CKE<1>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<2> MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_BA<1>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=PPDDRVREF_CA_MEM_B

=PPVDDQ_S3_MEM_B

=MEM_B_DQ<47>

=MEM_B_DQ<44>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQ<45>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<53>

=PPDDRVTT_S0_MEM_B

=MEM_B_DQS_P<7>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

=MEM_B_DQ<2> =MEM_B_DQ<3>

=MEM_B_DQ<8> =MEM_B_DQ<9>

=MEM_B_DQ<11>

=MEM_B_DQ<10>

=MEM_B_DQ<17>

=MEM_B_DQS_P<2>

=MEM_B_DQ<24> =MEM_B_DQ<25>

=MEM_B_DQ<19>

=MEM_B_DQ<26>

MEM_B_CKE<0>

MEM_B_A<5>

MEM_B_CLK_P<0>

MEM_B_A<1>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

=MEM_B_DQ<35>

=MEM_B_DQ<41>

=MEM_B_DQ<40>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<48>

=MEM_B_DQS_P<6>

=MEM_B_DQ<49>

=MEM_B_DQ<51>

=MEM_B_DQ<50>

=MEM_B_DQ<56> =MEM_B_DQ<57>

=MEM_B_DQ<58> =MEM_B_DQ<59>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

=PP3V3_S0_MEM_B_SPD

=PPDDRVTT_S0_MEM_B

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_BA<2>

=PPVDDQ_S3_MEM_B

=MEM_B_DQ<31>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<1>

MEM_RESET_L

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<3>

MEM_B_CLK_N<0> MEM_B_CLK_N<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

MEM_B_CAS_L

MEM_B_CS_L<1>

=MEM_B_DQS_N<4>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<7>

MEM_EVENT_L

=MEM_B_DQ<27>

=MEM_B_DQ<18>

=MEM_B_DQ<16>

=PPDDRVREF_DQ_MEM_B

=MEM_B_DQ<0>

=MEM_B_DQ<20>

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<21>

=MEM_B_DQS_P<1>

prefsb

051-9504

7.0.0

31 OF 143

31 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

5

1 3

9

11

37 39

43

51

61

71

69

198

186

169

152

135

121

115

114113

110

104103

62

45

30

27

10

70

75 77 79 81 83 85

89

195

203

199 201

197

193

189 191

187

185

183

181

179

175 177

165 167

171 173

163

155 157 159 161

153

147

151

145

149

143

133

137 139 141

129

125

123

127

131

105

93

97 99

101

87

91

73

65

63

67

55

53

59

57

49

47

41

33 35

31

29

25

23

21

19

17

15

202

200

190 192 194 196

188

204

170

166 168

172

180 182 184

164

148 150

162

154 156 158

146

160

144

136

124 126 128 130 132 134

138 140 142

108

106

112

116 118 120 122

102

98

96

90 92

84 86

94

88

100

82

80

78

74 76

72

68

64 66

46

58 60

56

52 54

48 50

44

42

28

24 26

32 34 36 38 40

22

20

13

7

18

16

4 6

12 14

8

2

178

176

174

95

107 109 111

117 119

205 206 207 208 209

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

31 32

6

31 32

31

6

32

6

31 32

6

31 32

31

6

31 32

6

31 32

6

31 32

6

32

IN

NC

BI

IN

BI

IN

BI

IN

BI

NC

DQ0

VREFDQ VSS_1

VSS_3 DM0

VSS_12 DQ16

VSS_14

DQ18

VSS_21

VSS_24

DQ27

EVENT*

DQS7*

DQS6*

DQS5*

DQS4*

S1*

CAS*

S0*WE*

RAS*

CK1*CK0*

DQS3*

DQS2*

RESET*

DQS1*

DQS0*

DQ31

VDD_0 NC_0 BA2 VDD_2 A12/BC* A9

A8

VSS_50

VTT_0

VDDSPD SA1

SA0

DQ59

VSS_48 DQ58

DM7

VSS_47

DQ57

DQ56

VSS_45

DQ50 DQ51

DQ49 VSS_40

DQS6 VSS_43

DQ48

VSS_36 DQ42 DQ43 VSS_38

DM5

DQ40

VSS_35

VSS_33

DQ41

DQ35

VSS_28

DQS4 VSS_31 DQ34

DQ32

TEST

VDD_16

VSS_26

DQ33

VDD_10

VDD_6

A1 VDD_8 CK0

VDD_4

A5

CKE0

VSS_22

DM3

DQ26

VSS_19

DQ19

DQ25

DQ24

VSS_17

DQS2

DQ17

DQ10 DQ11

VSS_10

DQS1

VSS_8

DQ9

DQ8

VSS_6

DQ3

DQ2

SCL

SDA

VSS_49

DQ62 DQ63

VSS_51

DQS7

VTT_1

DM6

DQ53

VSS_41

VSS_42

DQ60 DQ61

VSS_46

DQ52

DQ45

VSS_34

VSS_39

DQS5

VSS_37

DQ46

DQ44

DQ47

VSS_32

DM4

VDD_17 VREFCA VSS_27

DQ36 DQ37

VSS_29

VSS_30

DQ38 DQ39

BA1

VDD_11

VDD_13

ODT0

VDD_15

ODT1 NC_1

CK1

A0

A2

A6 A4

A11

A7

VDD_7

VDD_5

VDD_9

VDD_3

A14

A15

CKE1

VDD_1

VSS_25

DQ30

DQS3

VSS_23

DM2

DQ29

VSS_20

DQ28

DQ23

VSS_18

VSS_16

DQ22

VSS_15

DQ21

DM1

DQ13

VSS_9

VSS_11

DQ14 DQ15

VSS_13

DQ20

DQ12

VSS_7

VSS_4

DQ1

DQ7

DQ6

DQ4 DQ5

DQS0

VSS_5

VSS_2

VSS_0

VSS_44

DQ55

DQ54

A3

A10_AP BA0 VDD_12

VDD_14 A13

KEY

SYM 1 OF 2

SYM 2 OF 2

MTG HOLE

NC

BI

OUT

IN

BI

IN

BI

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

P/N: 516S1030

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

- =PPDDRVTT_S0_MEM_B

- =PPVDDQ_S3_MEM_B

- =I2C_SODIMMA_SCL

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMA_SDA

BOM options provided by this page:

(NONE)

- =PP1V5_S0_MEM_B

Power aliases required by this page:

Signal aliases required by this page:

Page Notes

C3253

10V

10%

402

X5R

1UF

31 50

12 97

12 31 97

12 97

12 31 97

31 33

402

CERM

10V

20%

C3231

0.1UF

12 31 97

31 33

6.3V 402-LF

CERM

20%

2.2UF

C3230

31 33

12 97

31 33

12 97

12 31 97

12 97

C3217

10V

20%

402

CERM

0.1UF

12 31 97

12 97

10V

20%

402

CERM

0.1UF

C3223

C3216

10V

20%

402

CERM

0.1UF

12 97

C3215

10V

20%

402

CERM

0.1UF

C3214

10V

20%

402

CERM

0.1UF

C3213

10V

20%

402

CERM

0.1UF

C3222

10V

20%

402

CERM

0.1UF

C3221

0.1UF

CERM

10V

20%

402

C3220

20% 10V

402

CERM

0.1UF

C3219

10V

20%

402

CERM

0.1UF

C3212

0.1UF

CERM 402

20% 10V

C3211

0.1UF

CERM 402

20% 10V

0.1UF

C3210

CERM 402

20% 10V

31 33

C3218

0.1UF

CERM 402

20% 10V

C3201

6.3V

20%

10UF

603

X5R

C3200

10UF

X5R 603

20%

6.3V

SODIMM-P0.60-D8

J3200

F-ANG-SM-2

SODIMM-P0.60-D8

F-ANG-SM-2

J3200

31 33

C3236

0.1UF

10V

20%

402

CERM

31 33

C3235

6.3V

20%

402-LF

CERM

2.2UF

29 30 31 47 48

114

12 31 97

12 97

31 33

C3252

10V

10%

402

X5R

1UF

31 33

C3251

10V

10%

402

X5R

1UF

31 33

10K

R3241

MF-LF 402

5% 1/16W

R3240

10K

MF-LF 402

5% 1/16W

C3240

2.2UF

6.3V

20%

402-LF

CERM

31 33

C3250

1UF

10V

10%

402

X5R

31 33

28 29 30 31 97

31 33

31 50

31 33

12 31 97

SYNC_DATE=03/19/2012

DDR3 SO-DIMM CONNECTOR B SLOT1

SYNC_MASTER=D8_KOSECOFF

MEM_B_A<4>

MEM_B_A<2>

MEM_B_CKE<3>

=MEM_B_DQ<13>

=MEM_B_DQ<0>

=PPDDRVREF_DQ_MEM_B

=MEM_B_DQ<18>

=MEM_B_DQ<27>

MEM_EVENT_L

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<4>

MEM_B_CS_L<3>

MEM_B_CAS_L

MEM_B_CS_L<2>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CLK_N<3>MEM_B_CLK_N<2>

=MEM_B_DQS_N<3>

=MEM_B_DQS_N<2>

MEM_RESET_L

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

=PPVDDQ_S3_MEM_B

MEM_B_BA<2>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8>

=PPDDRVTT_S0_MEM_B

=PP3V3_S0_MEM_B_SPD MEM_DIMM3_SA<1>

MEM_DIMM3_SA<0>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<50> =MEM_B_DQ<51>

=MEM_B_DQ<49>

=MEM_B_DQS_P<6>

=MEM_B_DQ<48>

=MEM_B_DQ<42> =MEM_B_DQ<43>

=MEM_B_DQ<40> =MEM_B_DQ<41>

=MEM_B_DQ<35>

=MEM_B_DQS_P<4>

=MEM_B_DQ<34>

=MEM_B_DQ<32> =MEM_B_DQ<33>

MEM_B_A<1>

MEM_B_CLK_P<2>

MEM_B_A<5>

MEM_B_CKE<2>

=MEM_B_DQ<26>

=MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQS_P<2>

=MEM_B_DQ<17>

=MEM_B_DQ<10> =MEM_B_DQ<11>

=MEM_B_DQS_P<1>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

=MEM_B_DQ<62> =MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=PPDDRVTT_S0_MEM_B

=MEM_B_DQ<53>

=MEM_B_DQ<60> =MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DQ<46>

=MEM_B_DQ<44>

=MEM_B_DQ<47>

=PPVDDQ_S3_MEM_B

=PPDDRVREF_CA_MEM_B

=MEM_B_DQ<36> =MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

MEM_B_BA<1>

MEM_B_ODT<2>

MEM_B_ODT<3>

MEM_B_CLK_P<3>

MEM_B_A<0>

MEM_B_A<6>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<15>

=MEM_B_DQ<30>

=MEM_B_DQS_P<3>

=MEM_B_DQ<29>

=MEM_B_DQ<28>

=MEM_B_DQ<23>

=MEM_B_DQ<22>

=MEM_B_DQ<21>

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<1>

=MEM_B_DQ<7>

=MEM_B_DQ<5>

=MEM_B_DQS_P<0>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

MEM_B_A<3>

MEM_B_A<10> MEM_B_BA<0>

MEM_B_A<13>

MEM_DIMM3_SA<0>

=PP3V3_S0_MEM_B_SPD

MEM_DIMM3_SA<1>

=PP3V3_S0_MEM_B_SPD

=MEM_B_DQ<6>

=MEM_B_DQ<16>

=MEM_B_DQ<4>

prefsb

051-9504

7.0.0

32 OF 143

32 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

5

1 3

9

11

37 39

43

51

61

71

69

198

186

169

152

135

121

115

114113

110

104103

62

45

30

27

10

70

75 77 79 81 83 85

89

195

203

199 201

197

193

189 191

187

185

183

181

179

175 177

165 167

171 173

163

155 157 159 161

153

147

151

145

149

143

133

137 139 141

129

125

123

127

131

105

93

97 99

101

87

91

73

65

63

67

55

53

59

57

49

47

41

33 35

31

29

25

23

21

19

17

15

202

200

190 192 194 196

188

204

170

166 168

172

180 182 184

164

148 150

162

154 156 158

146

160

144

136

124 126 128 130 132 134

138 140 142

108

106

112

116 118 120 122

102

98

96

90 92

84 86

94

88

100

82

80

78

74 76

72

68

64 66

46

58 60

56

52 54

48 50

44

42

28

24 26

32 34 36 38 40

22

20

13

7

18

16

4 6

12 14

8

2

178

176

174

95

107 109 111

117 119

205 206 207 208 209

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

31

6

31 32

6

31 32

6

31 32

32

6

31 32

6

31 32

6

31

32

6

31 32

32

6

31 32

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_DATE=03/19/2012

DDR3 ALIASES AND BITSWAPS

SYNC_MASTER=D8_KOSECOFF

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MEM_B_DQ<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MEM_A_DQ<40>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<5>

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MAKE_BASE=TRUE

MEM_A_DQ<26>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MEM_A_DQ<54>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQ<16>

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MEM_A_DQ<18>

MAKE_BASE=TRUE

MEM_A_DQS_P<0>

MAKE_BASE=TRUE

MEM_A_DQ<23>

MEM_A_DQS_N<2>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<5>

MAKE_BASE=TRUE

MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQ<47>

MAKE_BASE=TRUE

MEM_B_DQ<41>

MAKE_BASE=TRUE

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUE

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MEM_B_DQ<22>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<21>

MEM_B_DQ<9>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<8>

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MAKE_BASE=TRUE

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<4> MEM_B_DQ<3>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MEM_B_DQ<12>

MAKE_BASE=TRUE

MEM_B_DQ<11>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_A_DQ<17>

MEM_B_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<4> MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<38>

MEM_A_DQ<41>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MEM_A_DQS_P<7>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MAKE_BASE=TRUE

MEM_A_DQ<50>

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_A_DQ<62>

MAKE_BASE=TRUE

=MEM_A_DQ<61>

=MEM_A_DQ<58>

=MEM_B_DQ<48>

=MEM_B_DQS_N<7>

=MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<59> =MEM_B_DQ<62>

=MEM_B_DQS_P<1>

=MEM_A_DQ<8>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQS_P<2>

=MEM_A_DQ<22>

=MEM_A_DQS_N<3>

=MEM_A_DQ<32>

=MEM_A_DQS_P<1>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<14>

=MEM_A_DQ<54>

=MEM_A_DQ<57> =MEM_A_DQ<56>

=MEM_A_DQ<2>

=MEM_A_DQ<63> =MEM_A_DQ<59>

=MEM_A_DQ<0>

=MEM_A_DQS_P<0>

=MEM_A_DQS_N<0>

=MEM_A_DQ<28>

=MEM_A_DQ<42>

=MEM_A_DQ<37> =MEM_A_DQ<35> =MEM_A_DQ<34>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<33>

=MEM_A_DQ<60>

=MEM_A_DQ<17> =MEM_A_DQ<16>

=MEM_A_DQ<15>

=MEM_B_DQ<56> =MEM_B_DQ<57>

=MEM_B_DQ<39> =MEM_B_DQ<38> =MEM_B_DQ<37> =MEM_B_DQ<36> =MEM_B_DQ<35> =MEM_B_DQ<34> =MEM_B_DQ<33> =MEM_B_DQ<32>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

=MEM_B_DQ<47> =MEM_B_DQ<46> =MEM_B_DQ<45> =MEM_B_DQ<44> =MEM_B_DQ<43> =MEM_B_DQ<42> =MEM_B_DQ<41> =MEM_B_DQ<40>

=MEM_B_DQS_N<6>

=MEM_B_DQ<49>

=MEM_B_DQ<58>

=MEM_B_DQ<50>

=MEM_B_DQ<15>

=MEM_B_DQ<12>

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<7>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<6>

=MEM_B_DQ<3>

=MEM_B_DQ<9>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<18>

=MEM_B_DQ<22>

=MEM_B_DQS_N<2>

=MEM_B_DQ<25>

=MEM_B_DQ<27>

=MEM_B_DQS_N<4> =MEM_B_DQS_P<4>

=MEM_B_DQS_N<1>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<0>

=MEM_B_DQ<26>

=MEM_B_DQ<24>

=MEM_A_DQ<7> =MEM_A_DQ<6> =MEM_A_DQ<4> =MEM_A_DQ<1> =MEM_A_DQ<3>

=MEM_A_DQ<9>

=MEM_A_DQ<19>

=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQS_P<3>

=MEM_B_DQ<14> =MEM_B_DQ<8>

=MEM_B_DQ<63>

=MEM_B_DQS_P<7>

=MEM_B_DQS_P<6>

=MEM_B_DQ<51>

=MEM_B_DQ<55> =MEM_B_DQ<54> =MEM_B_DQ<52> =MEM_B_DQ<53>

=MEM_B_DQ<19>

=MEM_B_DQ<23>

=MEM_B_DQS_P<2>

=MEM_B_DQ<13>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_A_DQS_N<2>

=MEM_A_DQ<41> =MEM_A_DQ<40>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<1>

=MEM_A_DQ<5>

=MEM_A_DQ<23>

=MEM_A_DQ<21> =MEM_A_DQ<20> =MEM_A_DQ<18>

=MEM_A_DQ<29>

=MEM_A_DQ<36>

=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>

=MEM_A_DQ<45>

=MEM_A_DQ<43>

=MEM_A_DQ<53>

=MEM_A_DQ<49>

=MEM_A_DQ<51>

=MEM_A_DQS_N<6>

=MEM_A_DQ<55>

=MEM_A_DQ<52>

=MEM_A_DQ<50>

=MEM_A_DQ<48>

=MEM_A_DQS_P<7>

=MEM_A_DQ<62>

=MEM_A_DQS_N<7>

prefsb

051-9504

7.0.0

33 OF 143

33 OF 117

12 97

12 97 12 97

29 30

31 32

29 30

31 32

29 30

31 32

29 30

V-

V+

V-

V+

IN

D

SG

D

SG

NC NC

NC

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

TABLE_5_ITEM

CRITICAL

BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Addr=0x98(WR)/0x99(RD)

NOTE: CPU DAC output step sizes:

VRef DQ

Driven by CPU

DAC Channel: PCA9557D Pin:

DAC range: VRef current: DAC step size:

Margined target:

MEM A VREF CA

0.75V (DAC: 0x3A)

7.69mV / step @ output

0.300V - 1.200V (+/- 450mV)

+3.4mA - -3.4mA (- = sourced)

MEM B VREF CA

MEM VREG

8.59mV / step @ output

+61uA - -61uA (- = sourced)

1.5V (DAC: 0x3A)

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74)

GPU Frame Buffer (1.8V, 70% VRef)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)

0.000V - 3.300V (0x00 - 0xFF)

1.267V (DAC: 0x8B)

1.51mV / step @ output

0.000V - 1.501V (0x00 - 0x74)

CC D D 34 5 6

soft-resets and sleep/wake cycles.

a DAC output, cannot enable

NOTE: MEMVREG and FRAMEBUF share

RST* on ’platform reset’ so that system watchdog will disable margining.

Addr=0x30(WR)/0x31(RD)

(OD)

NOTE: Margining will be disabled across all

both at the same time!

Nominal value

DDR3 (1.5V) 7.70mV per step

C3402

0.1UF

20% 10V

CERM

402

VREFMRGN:EXT

UCSP

B4

U3402

B1

CRITICAL

MAX4253

VREFMRGN:EXT

B1

B4

UCSP

CRITICAL

MAX4253

U3402

402

OMIT

NONE

NONE NONE

SHORT

R3418

OMIT

NONE

402

R3419

NONE

SHORT

26 28

114

R3422

1%

1K

402

1/16W MF-LF

PLACE_NEAR=R3421.2:2MM

1%

402

1K

MF-LF

1/16W

R3442

PLACE_NEAR=R3441.2:4MM

1% 1/16W

PLACE_NEAR=Q3420.6:64MM

402

R3421

MF-LF

1K

PLACE_NEAR=Q3420.3:70MM

R3441

1/16W MF-LF 402

1%

1K

VREFMRGN:EXT

MF-LF

402

200

1%

R3403

1/16W

1%

133

402

1/16W MF-LF

VREFMRGN:EXT

R3404

VREFMRGN:EXT

MF-LF

1/16W

133

1%

402

R3406

VREFMRGN:EXT

MF-LF

402

200

R3405

1/16W

1%

CRITICAL

Q3420

SSM6N15AFE

SOT563

SSM6N15AFE

CRITICAL

SOT563

Q3420

MF-LF

5%

402

1/16W

R3480

0

NOSTUFF

5%

0

R3481

402

MF-LF

1/16W

PLACE_NEAR=Q3420.3:70MM

X7R-CERM 0402

C3440

0.1UF

10% 16V

X7R-CERM 0402

0.1UF

10% 16V

C3441

16V

10%

0.1UF

0402

X7R-CERM

C3420

16V

10%

0.1UF

0402

X7R-CERM

C3421

VREFMRGN:EXT

R3402

MF-LF 402

5%

100K

1/16W

MF-LF

VREFMRGN:EXT

R3401

100K

5% 1/16W

2

1

402

CRITICAL

QFN

PCA9557

U3401

VREFMRGN:EXT

50

DAC5574

MSOP

U3400

VREFMRGN:EXT

CRITICAL

50

402

20%

C3401

0.1UF

10V CERM

VREFMRGN:EXT

6.3V CERM

402-LF

20%

VREFMRGN:EXT

2.2UF

C3400

402

20% 10V

C3403

CERM

0.1UF

VREFMRGN:EXT

SYNC_MASTER=D8_KOSECOFF

DDR3/FRAMEBUF VREF MARGINING

SYNC_DATE=03/19/2012

116S0004

2

R3403,R3405

RES,MTL FLM,0,5%,402,SM,LF

VREFMRGN:N

CPU_DIMM_VREF_DAC_A

PPDDRVREF_DQ_MEM_A

PLACE_NEAR=Q3420.6:2mm

=PPVDDQ_S3_DDR_VREF

PPDDRVREF_DQ_MEM_B

=PPVDDQ_S3_DDR_VREF

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S4_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP3V3_S4_VREFMRGN_DAC

VREFMRGN_SODIMMS_CA_MEM_B_R

=PP3V3_S4_VREFMRGN

=I2C_VREFDACS_SCL

PCA9557D_RESET_L

=I2C_PCA9557D_SCL

=PPDDRVTT_S3_VREFCA

PPDDRVREF_CA_MEM_A

ISOLATE_CPU_MEM_L

CPU_DIMM_VREF_DAC_B

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_SODIMMS_CA_MEM_A

VREFMRGN_CA_SODIMMB_EN

=PP3V3_S4_VREFMRGN

VREFMRGN_CA_SODIMMB_BUF

PPDDRVREF_CA_MEM_B

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_SODIMMS_CA_MEM_B

prefsb

051-9504

7.0.0

34 OF 143

34 OF 117

2

1

C4

C1

C3

C2

A4

A1

A3

A2

12

1

2

1

2

1

2

1

2

12

6

1

2

3

4

5

12

1

2

1

2

1

2

1

2

1

2

15

3 4 5

1 2

6 7 9

12 13 14

16

10 11

17

8

3

5

4

2

16

7

9

10

2

1

2

1

2

1

11

106

6

34

6

34

106

6

34

6

21 28 34 99

11

106

117

6

34

6

117

IN

OUT

IN

BI

D

GS

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

BI

IN

D

GS

OUT

NC

D

S

G

S

D

P-CH

N-CH

IN

VINONVOUT

GND

VINONVOUT

GND

IN

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SUPERVISOR & CLKREG # ISOLATION

DELAY = 130 MS +/- 20%

514S0335

AIRPORT

BLUETOOTH

WI-FI POWER CONSUMPTION: RDAR://10174119

26

112

15 35

112

15

112

402

C3530

0.1uF

20% 10V CERM

R3531

MF-LF

1/16W

232K

402

1%

R3532

402

1/16W MF-LF

100K

1%

MF-LF

1/16W

1%

100K

402

R3530

35

112

6.3V

603

X5R

C3508

20%

10UF

18 98

CRITICAL

F-RT-SM1

SSD-K99

J3500

35

112

18 98

10%

C3505

0.1UF

201

6.3V

X5R

C3506

10%

201

6.3V

0.1UF

X5R

18 98

47 48

112

603

X5R

20%

10UF

C3504

6.3V

MF-LF

1/16W

402

10K

5%

R3570

SOD-VESM-HF

Q3570

SSM3K15FV

CRITICAL

SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

DFN

CRITICAL

USB3740

U3501

27

102

27

102

27 64 74

115

Q3501

SOD-VESM-HF

CRITICAL

SSM3K15FV

47 48

116

R3599

1/20W

15K

1%

201

MF

0.1uF

10V

20%

402

CERM

C3531

R3542

402

MF-LF

5%

10K

1/16W

Q3543

DMC2400UV

SOT563

15 20

112

R3543

10K

MF-LF

5%

402

1/16W

CSP

U3503

CRITICAL

TPS22924B

CSP

U3502

CRITICAL

15 35

112

TDFN

U3530

SLG4AP041V

L3502

CRITICAL

FERR-220-OHM-2.5A

0603

FERR-220-OHM-2.5A

0603

L3501

CRITICAL

X7R-CERM

16V

10%

0.1UF

C3502

0402

X7R-CERM

16V

10%

0.1UF

0402

C3503

X7R-CERM 0402

C3507

0.1UF

16V

10%

SYNC_MASTER=D8_FIYIN SYNC_DATE=07/02/2012

AIRPORT/BT

PP3V3_G3H_BT_FLT

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

NET_PHYSICAL_TYPE=POWER_PHY

PP3V3_S4_AP_FLT

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=3.3V

PP3V3_G3H_BT_FET

BT_PWR_EN

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S4_AP_FET

BT_PWR_RST_L

PM_PCH_PWROK

P3V3AP_VMON

AP_RESET_CONN_L

AP_CLKREQ_Q_L

PCIE_WAKE_L

AP_WAKE_L

SMC_PME_S4_WAKE_L

USB_ACT_DET

USB_BT_MUX_N

=PP3V3_S4_AP_FET

USB_BT_P

USB_BT_MUX_N

AP_RESET_CONN_L

AP_WAKE_L

AP_CLKREQ_Q_L

USB_BT_MUX_P

PM_PGOOD_P3V3_S4_FET

USB_BT_N

=PP3V3_G3H_BT

SMC_S4_WAKESRC_EN

BT_PWR_RST_L_Q

PCIE_AP_R2D_C_N

AP_EVENT_L

PCIE_AP_R2D_N

PCIE_CLK100M_AP_N

PCIE_AP_D2R_N

PCIE_AP_R2D_P

PCIE_CLK100M_AP_P

USB_BT_MUX_P

=PP3V3_S4_AP_FET

=PP3V3_G3H_BT

AP_CLKREQ_L_ISO

AP_PWR_EN_ISO

AP_RESET_L

=PP3V3_S4_AP

=PP3V3_S4_AP_FET

=PP3V3_S4_AP

AP_PWR_EN_ISO

prefsb

051-9504

7.0.0

35 OF 143

35 OF 117

2

1

2

1

2

1

2

1

18

21

19

20

10

11

12

13

16

15

14

17

9

1

2

3

4

5

6

7

8

12

2

1

2

1

2

3

58

9

10

3

4

2

1

7

6

1

2

3

1

2

1

2

6

1

2

5

4

3

1

2

A2 B2

C2

B1

A1

C1

A2 B2

C2

B1

A1

C1

8

6

3

5

9

7

1

2

4

21

2

1

2

1

2

1

115

112

115

15 19 26 43 65 89

115

114

35

112

35

112

19 40

114

35

112

35

102

35 48

35

102

35

112

35

102

6

35

47 48

117

35

112

35 112

98

35

102

6

35

6

15 35 35 48

6

15 35

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

BI

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

IN

OUT

PETN_3

PETN_2

PETP_2

PETP_1 PETN_1

PETP_0 PETN_0

MONOBS_N

MONDC0 MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0 PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI EE_DO EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS TCK

TEST_EN TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

OUT

IN

BI

IN

D

C

Q

S*

W*

HOLD*

PAD

VSS

THM

VCC

IN

OUT

BI

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: The following pins require testpoints:

5 - PCIE_RST_1_N

2 - GPIO_2

SNK0 AC Coupling

SNK1 AC Coupling

R3681 for CYA, allows separation of GPIO_2/GPIO_9 if necessary.

(FORCE_PWR)

(TBT_EN_CIO_PWR_L)

(TBT_SPI_MISO)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

Use AA8 GND ball for THERM_DN

(TBT_SPI_MOSI)

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

8 - GPIO_15 9 - GPIO_11 10 - GPIO_14 11 - GPIO_0 12 - GPIO_12 13 - GPIO_10 14 - PB_LSTX 15 - PB_LSRX

1 - GPIO_1

0 - GPIO_13

4 - GPIO_5

6 - PCIE_RST_2_N

Divides 3.3V to 1.8V

Stuff one of R3861/2.

DEBUG: For monitoring current/voltage

7 - PCIE_RST_3_N

3 - GPIO_3

Not used in host mode.

DEBUG: For monitoring clock

R3690

3.3K

402

1/16W

5%

MF-LF

82

107

82

107

R3625

0

5% 1/16W MF-LF

402

R3632

100K

5% 1/16W

402

MF-LF

86

107

86

107

86

107

86

107

86

107

86

107

86

107

86

107

86

107

86

107

88

107

88

107

88

107

88

107

88

107

88

107

88

107

88

107

88

107

88

107

R3630

100K

402

MF-LF

1/16W

5%

MF-LF

100K

402

1/16W

R3631

86

107

86

107

R3629

MF-LF

5%

0

402

1/16W

R3693

3.3K

5%

402

MF-LF

1/16W

C3629

16V10%

X5R-CERM

0.1UF

0201

75

107

75

107

81

107

81

107

81

107

81

107

81

107

81

107

81

107

81

107

C3628

10% 16V X5R-CERM

0.1UF

0201

C3627

16V10%

X5R-CERM

0.1UF

0201

C3626

10% 16V X5R-CERM

0.1UF

0201

C3625

16V10%

X5R-CERM

0.1UF

0201

C3624

10% 16V X5R-CERM

0.1UF

0201

C3623

16V10%

X5R-CERM

0.1UF

0201

C3622

10% 16V X5R-CERM

0.1UF

0201

R3655

1%

1K

MF

1/20W

201

C3621

16V

0.1UF

X5R-CERM

10%

0201

C3620

16V10%

X5R-CERM

0.1UF

0201

C3630

16V10%

X5R-CERM

0.1UF

0201

C3631

16V10%

X5R-CERM

0.1UF

0201

C3632

16V10%

X5R-CERM

0.1UF

0201

C3633

16V10%

X5R-CERM

0.1UF

0201

C3634

16V10%

X5R-CERM

0.1UF

0201

C3635

16V10%

X5R-CERM

0.1UF

0201

C3636

16V10%

X5R-CERM

0.1UF

0201

C3637

16V10%

X5R-CERM

0.1UF

0201

C3638

16V10%

X5R-CERM

0.1UF

0201

C3639

16V10%

X5R-CERM

0.1UF

0201

81

107

81

107

81

107

81

107

81

107

81

107

81

107

81

107

C3690

402

CERM

10%

1UF

6.3V

75

107

75

107

86

107

86

107

88

107

88

107

38

88

107

88

107

88

107

88

107

88

107

88

107

88

112

15

114

15

114

15 99

15

114

86

107

86

107

86

107

86

107

86

112

36 86

117

86

36 86

36 88

117

88

36 88

38

117

19

U3600

CACTUSRIDGE4C

CRITICAL

OMIT_TABLE

FCBGA

38

26

101

R3698

5%

10K

402

MF-LF

1/16W

R3695

1/16W MF-LF

1%

806

402

R3696

1K

402

5% 1/16W MF-LF

R3699

10K

5%

1/16W

NO STUFF

MF-LF

402

18 98

38

117

50

107

50

107

38

117

U3690

OMIT_TABLE

M95256-RMC6XG

MLP

CRITICAL

R3697

100K

MF-LF

1/16W

5%

402

OMIT

R3615

NONE

NOSTUFF

NONE

402

NONE

R3688

10K

5% 1/16W MF-LF

402

R3687

10K

5% 1/16W

402

MF-LF

R3686

10K

1/16W

402

MF-LF

5%

R3685

10K

5%

402

MF-LF

1/16W

R3680

10K

5% 1/16W

402

MF-LF

R3682

10K

5% 1/16W

402

MF-LF

NO STUFF

15 26

117

36 85

117

NO STUFF

C3610

X5R

16V

0.1UF

402

10%

R3610

47K

5%

1/16W

402

MF-LF

15

15 20

117

R3683

10K

5% 1/16W

402

MF-LF

R3681

402

1/16W

5%

0

MF-LF

15 21 36

X5R-CERM

0201

C3601

10% 16V

0.1UF

C3600

0.1UF

10% 16V

X5R-CERM

0201

10%

0201

C3602

16V

X5R-CERM

0.1UF

C3603

10% 16V

X5R-CERM

0.1UF

0201

R3692

MF-LF

1/16W

402

5%

3.3K

0.1UF

X5R-CERM

0201

C3604

10% 16V

X5R-CERM

C3605

16V10%

0.1UF

0201

C3606

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

C3607

X5R-CERM

0.1UF

0201

0.1UF

C3640

X5R-CERM

10%

0201

16V

16V10%

C3641

X5R-CERM

0.1UF

0201

C3642

10% 16V

X5R-CERM

0.1UF

0201

R3691

3.3K

402

MF-LF

5% 1/16W

X5R-CERM

C3643

10% 16V

0.1UF

0201

16V

C3645

0.1UF

X5R-CERM

10%

0201

0.1UF

C3644

10% 16V

X5R-CERM

0201

C3646

16V10%

X5R-CERM

0.1UF

0201

C3647

0201

X5R-CERM

16V

0.1UF

10%

18 98

Thunderbolt Host (1 of 2)

SYNC_DATE=N/A

SYNC_MASTER=D8_MLB

TBT_A_D2R_P<0>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_C_N<2>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CP<0> TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CN

DP_TBTSRC_HPD

TBT_GO2SX_BIDIR

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_P<3>

TBT_CIO_PLUG_EVENT_ISOL

TBT_PWR_EN

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CP<3>

SYSCLK_CLK25M_TBT_R

TP_TBT_MONDC0

TBT_MONOBSN

PCIE_TBT_R2D_N<0>

TBT_SPI_CLK

=TBT_WAKE_L

TP_DP_TBTSRC_AUXCH_CP

JTAG_TBT_TDI_ISOL

JTAG_TBT_TCK_ISOL

TBT_SPI_MOSI

JTAG_TBT_TMS_ISOL

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2> DP_TBTSNK0_ML_N<2>

TP_TBT_PCIE_RESET0_L TP_TBT_PCIE_RESET1_L TP_TBT_PCIE_RESET2_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_P<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_N<0>

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<2>

PCIE_TBT_D2R_C_P<2>

TBT_PCIE_RESET_L

TBT_EN_LC_PWR

=TBT_CLKREQ_L

TBT_TMU_CLK_IN

TBT_TMU_CLK_OUT

SYSCLK_CLK25M_TBT

TBT_SPI_CS_L

DP_TBTSNK0_AUXCH_N

TP_DP_TBTSRC_ML_CN<3>

TBT_GPIO_9

TBT_DDC_XBAR_EN_L

=PP3V3_TBTLC_RTR

TBT_B_D2R_P<0>

DP_TBTPB_HPD

DP_TBTSNK0_ML_P<3>

TBT_SPI_MISO

=PP3V3_S4_TBT

=PP3V3_TBTLC_RTR

TBT_GPIO_14

=PP3V3_S4_TBT

DP_TBTSNK1_ML_N<0>

TBT_B_R2D_C_P<0>

TBT_A_HV_EN TBT_A_CIO_SEL TBT_A_DP_PWRDN

TBTROM_HOLD_L

TBTROM_WP_L

TP_TBT_MONDC1

TBT_A_CONFIG1_BUF

TP_TBT_PCIE_RESET3_L

PCIE_TBT_R2D_C_P<3>

DP_TBTSNK0_HPD

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK1_ML_P<0>

I2C_TBTRTR_SCL

TP_TBT_XTAL25OUT

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_C_N<2>

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_ML_C_N<3>

DP_TBTPB_AUXCH_C_P

TBT_A_D2R_N<0>

DP_TBTPA_ML_C_N<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<1>

TBT_RSENSE

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

TP_TBT_THERM_DP

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

TBT_A_CONFIG2_RC

TBT_A_R2D_C_P<1> TBT_A_R2D_C_N<1>

TBT_A_D2R_P<1> TBT_A_D2R_N<1>

TBT_A_LSTX TBT_A_LSRX

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

DP_TBTSNK1_HPD

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<3>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CP<2>

TBT_B_R2D_C_N<0>

TBT_B_D2R_N<0>

TBT_B_CONFIG2_RC

TBT_B_R2D_C_P<1> TBT_B_R2D_C_N<1>

TBT_B_D2R_P<1> TBT_B_D2R_N<1>

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<3>

DP_TBTPB_AUXCH_C_N

TBT_B_HV_EN TBT_B_CIO_SEL TBT_B_DP_PWRDN

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

TBT_B_CONFIG1_BUF

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<3>

DP_TBTPA_AUXCH_C_N

=PP3V3_TBTLC_RTR

PCIE_TBT_R2D_C_N<2>

PCIE_CLK100M_TBT_N

TBT_DDC_XBAR_EN_L

TBT_GPIO_9

I2C_TBTRTR_SDA

TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

TBT_A_HV_EN TBT_B_HV_EN

TBT_GPIO_14

PCIE_CLK100M_TBT_P

TBT_PWR_REQ_L

DP_TBTSNK0_ML_P<1>

DP_TBTSNK1_ML_N<3>

TBT_GO2SX_BIDIR

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_N<1>

TBT_RBIAS

TBT_MONOBSP

PCIE_TBT_R2D_C_N<0>

TBT_TEST_EN TBT_TEST_PWR_GOOD

JTAG_TBT_TDO_ISOL

MAKE_BASE=TRUE

TBT_EN_CIO_PWR_L

prefsb

051-9504

7.0.0

36 OF 143

36 OF 117

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

12

2

1

AD19

AD15

AD13

AD9

AD11

AD5

AD7

W16

AD23

AC24

AB19

AA18

AA16

AB15

AB13

AA12

AB9

AA10

W18

Y3

AA4

A14

A12

B15

A10

B13

B11

A8

C2

B9

V3

D3

Y1

V5

M5

T3

P3

AC2

AB1

AA2

J4

W2

U24

H5

N22

P1

R22

R24

N24

W24

B23

B21

A20

G6

U22

L6

W22

A22

L2

L4

M1

K3

E2

D1

Y7

R4

P5

AD3

V1

W4

R2

E16

D13

E18

D15

E20

D17

A6

D19

U6

B5

D5

E6

D7

E8

D9

E10

D11

E12

B3

A4

T5

E24

G24

E22

G22

G4

K1

J24

L24

J22

L22

J6

N2

B17

A16

B19

A18

F3

H1

F1

M3

G2

H3

AD17

U20

AB21

AD21

AA24

AB23

AB3

AA6

N4

AB5

E14

J2

R6

U4

W20

N6

T1

U2

Y5

W6

K5

1

2

12

121

2

94

5

6

2

1

3

7

8

1

2

1

2

121

2

121

2

1

2

1

2

1

2

1

2

1

2

12

1

2

12

1

2

12

36

107

84

107

36

107

36

107

84

101

98

107

84

107

36

107

36

107

36

107

98

98 98

107

36

107

84

36

36 85

117

6

15 36 37 38 50

36

107

6

36 37 38 86 88

6

15 36 37 38 50

36

6

36 37 38 86 88

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

84

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

6

15 36 37 38 50

36

36 88

36 86

117

36 88

117

36

107

36

107

15 21 36

98

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE VSSPE VSSPE

VSSPE VSSPE

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0_PE

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VCC1P0 VCC1P0

VCC3P3_DP VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3

VCC1P0

VCC1P0 VCC1P0

VCC1P0

VCC1P0_ON

VCC3P3

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCCGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP current / power consumption figures from CR DG v0.57, IBL doc #472455.

EDP: 1000 mA

250 mW (Dual Port)

??? mW (Single Port)

???? mW (Single-Port) 2700 mW (Dual-Port) EDP: 3000 mA

250 mW (Dual-Port) EDP: 240 mA

??? mW (Single-Port)

EDP: 10 mA

C3745

6.3V

1UF

X5R

0201

20%

C3716

6.3V

1UF

X5R 0201

20%

C3705

6.3V

20%

10UF

CERM-X5R 0402-1

C3773

6.3V

1UF

X5R

0201

20%

C3774

6.3V

1UF

X5R

0201

20%

C3717

1UF

6.3V X5R 0201

20%

C3713

1UF

6.3V X5R 0201

20%

C3700

10UF

6.3V

20%

CERM-X5R

0402-1

C3701

20%

6.3V

10UF

CERM-X5R

0402-1

C3714

6.3V

1UF

X5R 0201

20%

C3715

1UF

6.3V X5R 0201

20%

U3600

CRITICAL

FCBGA

CACTUSRIDGE4C

OMIT_TABLE

C3760

20%

10UF

6.3V CERM-X5R 0402-1

C3772

6.3V

1UF

X5R

0201

20%

C3771

1UF

6.3V X5R

0201

20%

C3710

1UF

6.3V X5R 0201

20%

C3770

1UF

6.3V X5R

0201

20%

C3790

6.3V

1UF

X5R

0201

20%

C3711

6.3V

1UF

X5R 0201

20%

C3712

6.3V

1UF

X5R 0201

20%

C3744

1UF

6.3V X5R

0201

20%

C3743

1UF

6.3V X5R

0201

20%

C3742

1UF

6.3V X5R

0201

20%

C3741

6.3V

1UF

X5R

0201

20%

C3740

1UF

6.3V X5R

0201

20%

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

Thunderbolt Host (2 of 2)

=PP3V3_S4_TBT

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP3V3_TBTLC_RTR

prefsb

051-9504

7.0.0

37 OF 143

37 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

212

1

2

1

C18

C20

C14

C16

C12

C10

B7

B1

AC8

AC6

AC4

AC22

AC18

AC20

AC16

AC14

AC12

AB7

AB17

AC10

AA8

AB11

AA14

AA20

AA22

A2

A24

U8

V9

U12

U16

T9

T13

T17

R8

R16

R12

P9

P17

P13

N16

N8

M9

N12

M17

L8

M13

L16

L12

K13

AD1

K9

H9

G8

K7

Y9

G10

G12

G14

G16

H19

G18

K19

M19

P19

T19

V15

V19

W12

W14

K11

K15

H13

H15

H11

R18

N18

L18

P7

M7

W10

V11

U10

T11

R14

R10

P15

N14

P11

N10

M15

M11

L14

L10

W8

T15

V7

U14

K17

J8

J16

J14

J12

J10

T7

C22

C24

C4

C6

C8

D21

E4

D23

F11

F13

F15

F17

F21

F19

F23

F5

F7

G20

F9

H21

H23

J18

J20

K21

K23

L20

M23

M21

N20

P21

P23

R20

T21

T23

U18

V17

V13

V21

V23

Y11

Y13

Y15

Y17

Y19

Y23

Y21

H17

H7

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

36 38 86 88

6

15 36 38 50

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

VOUT

GND

ON

VIN

GND

VOUT

ON

VIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

OUT

IN

D

SG

IN

D

SG

OUT

D

GS

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM options provided by this page:

- =TBT_CLKREQ_L

Signal aliases required by this page:

- =PP1V05_TBT_FET (1.05V FET Output)

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_FET (3.3V FET Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

DLY = 60 ms +/- 20%

1.05V TBT "CIO" Switch

Delay = 27.3ms

TPS3808G25

(IPU)

Max Current = 4A (85C)

Vt = 2.33V +/- 2%

Pull-up: R3610

@ 1.05V

R(on)

Type

Part

Load Switch

11.5 mOhm Max

8 mOhm Typ

U3820

TPS22920

- =PPVIN_SW_TBTBST (8-13V Boost Input)

TBTBST:Y - Stuffs 15V boost circuitry.

- =PP15V_TBT_REG (15V Boost Output)

Power aliases required by this page:

- =TBT_RESET_L

Page Notes

Intel investigating whether RC is sufficient.

TBT "POC" Power-up Reset

Supervisor & CLKREQ# Isolation

Platform(PCIe) Reset

TPS22924C

18.5 mOhm Typ

Load Switch

U3810

25.8 mOhm Max

3.3V TBT "LC" Switch

Part

R(on) @ 2.5V

Type

Max Current = 2A (85C)

20.3 mOhm Typ

28.6 mOhm Max

Load Switch

TPS22924C

U3815

@ 1.0V

R(on)

Part

Type

Max Current = 2A (85C)

1.05V TBT "LC" Switch

Pull-up provided by SB page.

CRITICAL

CSP

TPS22924

U3810

36

C3800

25V X5R

0.1UF

10%

402

26

36

402

1UF

10%

CERM

6.3V

C3810

1UF

C3815

10%

6.3V CERM

402

U3800

TDFN

SLG4AP016V

CRITICAL

402

MF-LF

100K

5% 1/16W

R3807

NOSTUFF

C3816

10%

6.3V CERM

402

1UF

5%

0

402

MF-LF

1/16W

R3816

U3820

CSP

CRITICAL

TPS22920

U3815

CSP

CRITICAL

TPS22924

C3820

402

CERM

6.3V

10%

1UF

U3830

CRITICAL

QFN

TPS3808

C3830

0.1UF

10%

X5R

25V

402

36

117

C3831

CERM

0.0047UF

25V

10%

0402

21

117

Q3825

SOT563

SSM6N37FEAPE

36

117

R3820

5%

402

1/16W MF-LF

100K

Q3825

SSM6N37FEAPE

SOT563

R3830

100K

MF-LF

1/16W

402

5%

15

117

Q3840

VESM

SSM3K15AMFVAPE

36

117

MF-LF

5%

402

10K

R3840

1/16W

0402

X7R-CERM

10% 50V

330PF

C3825

47 48 65

116

1UF

CERM

6.3V

10%

C3811

402

1%

36.5K

R3811

1/16W MF-LF

Thunderbolt Power Support

SYNC_MASTER=D7_MLB

SYNC_DATE=03/15/2012

=PP1V05_S0_P1V05TBTFET

=TBT_RESET_L

=PP3V3_S0_P3V3TBTFET

TBT_EN_LC_RC1V05

=PP1V05_TBTLC_FET

=TBT_CLKREQ_L

TBT_EN_LC_RC3V3

=PP3V3_TBTLC_FET

TBT_CLKREQ_ISOL_L

MAKE_BASE=TRUE

TBT_CLKREQ_L

=PP3V3_S0_TBTPWRCTL

TBT_EN_LC_PWR

SMC_DELAYED_PWRGD

=PP3V3_S0_PCH_GPIO

TBTPOCRST_MR_L

=PP3V3_TBTLC_RTR

=PP3V3_S4_TBT

=PP1V05_S0_P1V05TBTFET

TBT_PWR_ON_POC_RST_L

TBTPOCRST_CT

TBT_EN_CIO_PWR

TBT_EN_CIO_PWR_L

TBT_PCIE_RESET_L

PP1V05_TBTLC

TBT_SW_RESET_L

=PP1V05_TBTCIO_FET

TBT_EN_LC_ISOL

38 OF 117

38 OF 143

7.0.0

051-9504

prefsb

C1

A1

B1

C2

B2

A2

2

1

2

1

2

1

4

8

6

3

5

9

7

1

2

1

2

1

12

A1

D1

D2

A2

B2

C2

B1

C1

A1

B1

C2

B2

A2

2

1

2

7

6

3

5

4

1

2

1

2

1

6

1

2

1

2

3

4

5

1

2

1

2

3

1

2

1

2

1

12

6

38

6

117

6

15 19 20

6

15 36 37 38 50

6

15 36 37 38 50

6

36 37 86 88

6

38

117

6

104

6

117

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

VDDC

SR_LX

PCIE_PLLVDDL

SR_VFB

SR_VDDP

SR_VDD

SCLK SI/LINKLED*

CS*

SO

SPD100LED*/SERIAL_DO TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

TRD2_P

TRD3_N

TRD3_P

GPIO_1/CR_BUS_PWR

GPIO_0

RE*/GPIO_2

VMAIN_PRSNT

PCIE_TXD_N PCIE_TXD_P

PCIE_RXD_N

PCIE_RXD_P

PCIE_REFCLK_N

PCIE_REFCLK_P

PERST*

CLKREQ*

WAKE*

LOW_PWR

SD_DETECT/WE*

CR_CMD/CLE

CR_CLK/RY_BY*

CR_DATA0 CR_DATA1

CR_DATA3

CR_DATA2

CR_DATA4 CR_DATA5 CR_DATA6

CE*/MS_INS*

CR_DATA7

CR_LED/ALE

XD_DETECT

THRM_PAD

XTALI XTALO

RDAC

GPHY_PLLVDDL

AVDDH

VDDO

XTALVDDH

BIASVDDH

AVDDL

SMD_DATA

SMB_CLK

CR_WP*/XD_WP*

OUT

IN

OUT

IN

OUT

BI

IN

BI

NC

RESET*

CS*

SCK

SO

WP*

SI

GND

VCC

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VDD for Card Reader I/O

Special Star routing needed on these pins. Decoupling on Pg 37.

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

(IPx-ENET)

(IPU-ENET)

Connect only to U3900 pin 20.

No MS (Memory Stick) Insert feature needed. Control signal to light LED or control SD bus power.

ENET supports both active-levels for WP.

(OD)

IF ENET SWITCHING REGULATOR IS USED, THIS PIN SHOULD HAVE A 1K PD TO GND

(IPD-ENET)

(IPU)

SD_DETECT can only be used active low due to errata.

281mA (1000base-T max power, Caesar IV)

(OD)

(IPU-ENET)

(OD)

o

PHY Non-Volatile Memory

NOTE: Pull-down on SO plus internal pull-ups on

=ENET_WAKE_L to PCIE_WAKE_L.

info as well as code for Bonjour proxy.

(Required ROM size 1 Mbit)

Avoids need for EFI to program at startup.

is powered-down in S3/S5. Standard

Must isolate from PCIe WAKE# if PHY

WAKE#

If PHY is always powered then alias

Resistor

Limiting

396mA (1000base-T, Caesar II)

(IPD)

N-channel FET isolation suggested.

(See note)

(IPD-ENETM)

Current

(IPD)

Internal 1.2V Switching Regulator pins.

ROM contains MAC address, PCIe config

other 3 SPI pins configures ENET for the

ROM is used then the straps must change. NOTE: ENETM requires SI pull-down instead of SO.

Atmel AT45DB011D (1Mbit) ROM. If a different

NOTE: "IPx" == Programmable pull-up/down

(IPU-ENET)

the card reader on-chip I/O.

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

(NO IPU OR IPD-ENET)

(IPU-ENET)

ENET_SR_DISABLE

ENET_CR Signals

BCM requests SD CR[0:7], CMD, CLK termination.

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

10UF

6.3V X5R 603

C3935

20%

4.7UF

X5R-CERM1

6.3V

20%

402

C3925

FERR-600-OHM-0.5A

CRITICAL

L3925

SM

402

4.7UF

X5R-CERM1

6.3V

20%

C3920

R3942

1/16W

1K

402

MF-LF

5%

18 98

40

26 41

113

1.24K

MF-LF

R3965

1/16W

1%

402

18 98

40

111

40

111

40

111

40

111

40

111

40

111

40

111

40

111

402

MF-LF

4.7K

R3941

5% 1/16W

4.7K

R3940

402

5%

MF-LF

1/16W

41

111

41

111

41

111

41

111

41

111

MF-LF

R3990

4.7K

1/16W

5%

402

NOSTUFF

41

111

41

111

15 18

111

4.7K

R3910

MF-LF

402

5%

1/16W

U3900

QFN-8X8

BCM57765

OMIT_TABLE

40

39

111

39

111

39

111

39

111

41

113

39

111

39

111

39

111

39

111

41

111

41

111

41

111

41

111

41

111

1K

5%

R3981

MF-LF

402

1/16W

SOIC-8S1

AT45DB011D

OMIT_TABLE

U3990

41

113

26

101

R3961

PLACE_NEAR=U3900.26:5MM

2015% MF

1/20W

33

C3905

0201

X5R-CERM

16V

10%

0.1UF

16V

10%

0201

C3910

0.1UF

X5R-CERM

0.1UF

C3911

0201

16V

10% X5R-CERM

0.1UF

C3916

16V 0201

X5R-CERM

10%

X5R-CERM

0201

0.1UF

10% 16V

C3921

C3926

16V

10%

0.1UF

X5R-CERM

0201

X5R-CERM

16V

10%

0.1UF

C3931

0201

C3936

0.1UF

10% 16V

0201

X5R-CERM

C3950

0.1UF

X5R-CERM

0201

10% 16V

0.1UF

C3951

0201

16V

X5R-CERM

10%

C3955

0201

10% 16V

0.1UF

X5R-CERM

C3956

0.1UF

10%

0201

X5R-CERM

16V

X5R-CERM

C3990

0.1UF

16V

10%

0201

PLACE_NEAR=U3900.21:5MM

2015% MF

1/20W

33

R3979

PLACE_NEAR=U3900.25:5MM

201

1/20W

5% MF

33

R3971

PLACE_NEAR=U3900.24:5MM

5% 201MF

1/20W

33

R3972

PLACE_NEAR=U3900.23:5MM

5%

1/20W

201MF

33

R3973

PLACE_NEAR=U3900.22:5MM

201

1/20W

5% MF

33

R3974

PLACE_NEAR=U3900.52:5MM

R3975

33

201

1/20W

MF5%

PLACE_NEAR=U3900.53:5MM

5%

R3976

1/20W

MF33201

PLACE_NEAR=U3900.54:5MM

5% 201

33

1/20W

MF

R3977 R3978

PLACE_NEAR=U3900.55:5MM

1/20W

2015%

33

MF

FERR-600-OHM-300MA-0.85OHM

CRITICAL

L3900

0402

CRITICAL

L3905

FERR-600-OHM-300MA-0.85OHM

L3910

0402

CRITICAL

FERR-600-OHM-300MA-0.85OHM

CRITICAL

L3920

0402

FERR-600-OHM-300MA-0.85OHM

0402

CRITICAL

L3930

X5R-CERM

0201

10%

C3996

0.1UF

16V 16V

0.1UF

C3997

0201

10%

X5R-CERM

10% 16V

0.1UF

0201

C3998

X5R-CERM

C3999

X5R-CERM 0201

0.1UF

10% 16V

402

1/16W

0

R3901

5%

MF-LF

C3979

X5R-CERM1

4.7UF

402

20%

6.3V

C3912

1.0UF

X5R-CERM

10%

6.3V

0201

C3913

10%

1.0UF

6.3V X5R-CERM

40

113

C3900

10%

0.1UF

X5R-CERM

16V

0201

C3930

402

X5R-CERM1

20%

6.3V

4.7UF

C3915

X5R-CERM1

4.7UF

402

20%

6.3V

R3997

4.7K

1/16W MF-LF 402

5%

ETHERNET PHY (CAESAR IV+)

SYNC_MASTER=D8_FIYIN SYNC_DATE=07/02/2012

PCIE_ENET_D2R_C_P

PCIE_ENET_R2D_N

PCIE_CLK100M_ENET_N

ENET_RESET_L

ENET_CLKREQ_L_Q

ENET_MOSI

ENET_MISO

ENETCONN_MDI_N<0>

ENETCONN_MDI_P<2>

ENETCONN_MDI_P<1>

=PP3V3R1V8_CR_IOPWR_OUT

ENET_CR_DATA<4>

=ENET_WAKE_L

ENET_LOW_PWR

SDCONN_DATA<7>

PCIE_ENET_D2R_P

=PP3V3_S0_ENET

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

ENET_SR_VFB

ENET_CS_L

PCIE_ENET_D2R_C_N

ENET_SR_LX

ENET_CR_PWREN

PCIE_ENET_R2D_P

ENET_VMAIN_PRSNT

ENET_CR_DATA<3>

ENET_SR_DISABLE

ENET_CR_DATA<7>

ENETCONN_MDI_P<3>

ENETCONN_MDI_N<1>

=PP3V3_S4_ENET_FET

ENET_CS_L

ENET_SCLK

ENET_MISO

ENET_SCLK

SMB_ENET_SDA

SMB_ENET_SCL

PCIE_CLK100M_ENET_P

=PP3V3_S4_ENET_FET

ENET_MOSI

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S4_ENET_FET_AVDDH

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.2V

PP1V2_S4_ENET_PHY_GPHYPLL

NC_ENET_CE_L_MS_INS_L

NO_TEST=TRUE

SDCONN_WP

SDCONN_CLK

SDCONN_CMD

SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6>

ENET_CR_DATA<1>

PP3V3_S4_ENET_FET_BIASVDDH

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_S4_ENET_PHY_AVDDL

PP1V2_S4_ENET_PHY_PCIEPLL

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

ENETCONN_MDI_N<3>

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_S4_ENET_FET_SRVDD

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S4_ENET_FET_XTALVDDH

ENET_SD_DETECT_L

=PP3V3R1V8_CR_IOPWR_OUT

=PP1V2_S4_ENET_PHY

ENETCONN_MDI_N<2>

SYSCLK_CLK25M_ENET

TP_ENET_CR_3V3_EN_L ENET_TRAFFICLED_L

ENET_RDAC

ENET_CR_DATA<6>

ENET_CR_DATA<5>

ENET_CR_DATA<2>

ENET_CR_DATA<0>

ENET_SD_CLK

ENET_SD_CMD

ENET_MEDIA_SENSE

PP3V3R1V8_ENET_LR_OUT_REG

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MAKE_BASE=TRUE

TP_ENET_CR_1V8_EN

ENETCONN_MDI_P<0>

39 OF 143

prefsb

051-9504

7.0.0

39 OF 117

2

1

2

1

21

2

1

2

1

2

121

2

1

2

1

2

62

35

16

29

51

45

13

15

14

66 64

63

65

2

67

40

44

41

43

47

46

49

50

8

5

9

58

27 28

34

33

30

31

11

12

3

4

1

26

21

25 24

22

23

52 53 54

59

55

60

68

69

18 19

38

61

36

32

48

42

20567

17

37

39

10

6

57

12

7

6

3

4

2

8

5

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

2

1

12

12 12 12 12 12 12 12 12

21

2

1

2

1

2

1

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

98

39 40

111

6

40

98

40

113

98

111

113

111

6

39 40

6

39 40

115

111

115

39 40

40

111

115

BI

G

DS

IN

G

D

S

G

D

S

IN

D

GS

NBC

BI

D

GS

OUT

BI

TX

RX

TX

RX

BI

ENET_MDI_TRAN2+ ENET_MDI_TRAN1+

ENET_MDI_TRAN3-

SHIELD

ENET_MDI_TRAN0ENET_MDI_TRAN0+

ENET_MDI_TRAN2-

ENET_MDI_TRAN1-

ENET_MDI_TRAN3+

ENET_MDI

PINS

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAESAR IV 1.2V INT.VR CMPTS

157S0058

SILKSCREEN:ENET ACT

CAESAR IV WAKE# ISOLATION

"ENET" = "S0" || ("S&& "WOL_EN")

CAESAR IV ACTIVITY LED

Power decoupling

3.3V ENET FET

ENET Enable Generation

Feedback loop

40

111

40

111

40

111

40

111

40

111

40

111

SOT-23-HF

NTR4101P

Q4020

CRITICAL

10% 16V X5R 402

C4020

0.033UF

R4021

100K

402

MF-LF

5%

1/16W

10K

5%

1/16W

R4020

402

MF-LF

15 21

117

Q4021

2N7002DW-X-G

CRITICAL

SOT-363

Q4021

SOT-363

2N7002DW-X-G

5

15 19 28 47 48 64

115

4.7UF

20%

6.3V

C4010

402

X5R-CERM1

MF-LF

5%

402

R4070

10K

1/16W

Q4070

SSM3K15FV

SOD-VESM-HF

CRITICAL

R4050

402

MF-LF

1/16W

5%

330

DEVELOPMENT

2.0X1.25MM-SM

GREEN-3.6MCD

DEVELOPMENT

LED4050

L4010

CRITICAL

4.7UH-0.8A

PCAA031B-SM

20%

603

X5R

10UF

6.3V

C4012

40

111

40

111

1/16W

402

75

5%

MF-LF

R4003

402

5%

MF-LF

75

1/16W

R4002

75

5%

402

MF-LF

1/16W

R4001

402

5% 1/16W MF-LF

R4000

75

1206

1000PF

CERM

2KV

10%

C4000

NOSTUFF

C4004

0.1UF

CERM

20% 10V

402

0.1UF

402

20%

CERM

10V

C4003C4002

10V

402

20%

0.1UF

CERM

402

0.1UF

20% 10V CERM

C4001

X5R-CERM

10%

0201

0.1UF

C4014

16V

0.1UF

10% X5R-CERM

0201

16V

C4015

0.1UF

10% 16V

C4016

0201

X5R-CERM

0201

X5R-CERM

C4017

16V

10%

0.1UF

X5R-CERM

16V 0201

10%

0.1UF

C4018

X5R-CERM

10%

0.1UF

16V

C4019

0201

MF-LF

5%

402

10K

R4071

1/16W

SOD-VESM-HF

SSM3K15FV

Q4071

CRITICAL

15 18

113

40

111

LFE8904CF

SM

T4000

T4010

SM

LFE8904CF

39

111

39

111

40

111

40

111

40

111

40

111

40

111

40

111

39

111

39

111

39

111

39

111

39

111

39

111

C4024

0.1UF

16V

10%

0201

X5R-CERM

16V

0.1UF

C4023

0201

10% X5R-CERM

6.3V

20%

4.7UF

X5R-CERM1 402

C4022

0402

X7R-CERM

50V

10%

0.01UF

C4021

F-ANG-TH

RCPT-RJ45-D8

J4000

CRITICAL

40

111

NOSTUFF

C4025

4.7UF

402

X5R-CERM1

20%

6.3V

0402

X7R-CERM

16V

10%

0.1UF

C4011

SYNC_MASTER=D8_FIYIN

Ethernet Support & Connector

SYNC_DATE=07/02/2012

=PP3V3_S4_ENET_FET

ENETCONN_MDI_N<1>

=PP3V3R1V8_CR_IOPWR_OUT

ESD_HOT=TRUE

ENETCONN_MDI_T_P<0>

ENETCONN_MDI_T_N<1>

ESD_HOT=TRUE

ENETCONN_MDI_T_P<2>

ESD_HOT=TRUE

ENETCONN_MDI_T_N<0>

ESD_HOT=TRUE

ENETCONN_MDI_T_P<1>

ESD_HOT=TRUE

ENETCONN_MDI_T_N<2>

ESD_HOT=TRUE

ENETCONN_MDI_T_P<3>

ESD_HOT=TRUE

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_N<2>

ENETCONN_MCT0

ENET_PWR_EN_L_R

PP3V3_S4_ENET_FET

=PP3V3_S4_ENET

ENETCONN_MDI_T_P<0>

=PP1V2_S4_ENET_PHY

ENET_PWR_EN_L

ENETCONN_MDI_P<1>

ENETCONN_MDI_T_P<3>

ENET_TRAFFICLED_L

=PP3V3_S4_ENET_FET

PM_SLP_S3_L

WOL_EN

ENET_CLKREQ_L

PCIE_WAKE_L

=ENET_WAKE_L

ENET_CLKREQ_L_Q

=PP3V3_S4_ENET_FET

ENETCONN_MDI_P<0>

ENETCONN_MDI_N<3>

ENETCONN_MDI_P<3>

ENETCONN_MCT2

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_P<2>

ENETCONN_MDI_T_N<2>

ENET_ACT

=PP3V3_S4_ENET_FET

ENETCONN_MCT3

ENET_SR_VFB

ENETCONN_MDI_T_N<3>

ENETCONN_MCT1

MIN_LINE_WIDTH=0.4 MM

ENETCONN_MCT_BS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6MM

SWITCH_NODE=TRUE

ENET_SR_LX

MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

DIDT=TRUE

MAKE_BASE=TRUE

ENET_WAKE_L

PP1V2_ENET_INTREG

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP1V2_ENET_INTREG

VOLTAGE=1.2V

MAKE_BASE=TRUE

ENETCONN_MDI_P<2>

ENETCONN_MDI_N<0>

ENETCONN_TCT

prefsb

051-9504

7.0.0

40 OF 143

40 OF 117

32

1

2

1

12

1

2

6

2

1

3

5

4

2

1

2

1

2

3

1

2

K

A

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

10

6

5

7

8

9

11

12

4

3

2

1

10

6

5

7

8

9

11

12

4

3

2

1

2

1

2

1

2

1

12

4 3

8

9

2 1

10 11 12 13 14

5

6

7

2

1

2

1

6

39 40

39

111

113

6 6

39

113

39

6

39 40

19 35

114

39

113

6

39 40

111

113

6

39 40

111

39

111

39

113

40

115

40

115

113

OUT

IN

LOW_PWR

GND

THRM

VDD

RST_OUT*

DET_OUT

DET_CHNGD*

DET_LVL

DET_IN

RST_IN*

DET_CH_EN*

DLY

RST

LOGIC

XOR

(IPU)

XOR

(OD)

PAD

THRML

OUT

GND

FAULT*

ILIM

EN

IN

PAD

BI

OUT

IN

OUT

BI

SHLD_PIN

CRD_DETECT_SWITCH

SHLD_PIN

DAT6

DAT5

DAT7

DAT2

DAT1

DAT0

DAT4

VSS

CMD

CLK

VDD

VSS

CD/DAT3

WRITE_PROTECT_SWITCH

SHLD_PIN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

512-0038

DLY block is 20ms nominal

regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

FROM SD CONN ->

SD CARD 3.3V OVERCURRENT PROTECTION

-> TO ENET CHIP

-> TO PCH GPIO

When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.

39

113

R4114

402

1/16W MF-LF

0

5%

15 20 99

39

111

C4110

402-1

X5R

10V

10%

1UF

26 39

113

1/16W MF-LF

402

5%

NOSTUFF

10K

R4110

5%

402

MF-LF

1/16W

0

R4111

26

113

R4112

5%

0

MF-LF

1/16W

402

NOSTUFF

CRITICAL

U4111

SLG4AP026V

TDFN

SON

U4100

TPS2553

10UF

C4102

X5R 603

20%

6.3V

5%

47K

R4100

402

MF-LF

1/16W

402

R4101

1/16W MF-LF

100K

5%

MF-LF 1/16W

5%

402

R4108

0

R4116

0

MF-LF

5%

402

1/16W

402

R4109

MF-LF

5%

0

R4117

1/16W

402

5%

MF-LF

0

39

111

39

111

39

111

39

111

39

111

15PF

NOSTUFF

C4170

5%

CERM 402

50V

R4107

MF-LF 1/16W

0

402

5%

1/16WMF-LF

402

0

R4105

5%

402

1/16W

5%

R4104

0

MF-LF

R4106

1/16W

5%

MF-LF

402

0

MF-LF

402

1/16W

R4103

0

5%

39

111

39

111

39

111

39

111

39

111

39

111

R4115

MF

1/20W

5%

10K

201

6.3V

22UF

20%

X5R

C4100

0603

10%

0.1UF

X7R-CERM

16V

C4101

0402

C4103

10%

0.1UF

X7R-CERM

16V

0402

NOSTUFF

C4171

50V CERM

22PF

5%

0402

L4102

47NH-1.3OHM

F-ANG-TH1

J4100

SD-CARD-D8

MF-LF

1/16W

1%

13K

402

R4113

402

MF-LF

1/16W

1%

13K

R4118

SYNC_DATE=07/02/2012

SD READER CONNECTOR

SYNC_MASTER=D8_FIYIN

=PP3V3_S0_SW_SD_PWR

SDCONN_DETECT

SDCONN_DATA_R<6>

ESD_HOT=TRUE

SDCONN_DATA_R<5>

ESD_HOT=TRUE

SDCONN_DATA_R<7>

ESD_HOT=TRUE

SDCONN_DATA_R<2>

ESD_HOT=TRUE

SDCONN_DATA_R<1>

ESD_HOT=TRUE

SDCONN_DATA_R<0>

ESD_HOT=TRUE

SDCONN_DATA_R<4>

ESD_HOT=TRUE

SDCONN_CMD_R

ESD_HOT=TRUE

SDCONN_CLK_R

SDCONN_WP

SDCONN_CMD

SDCONN_DATA<3>

SDCONN_DATA<6>

SDCONN_CLK

SDCONN_DATA<0>

SDCONN_DATA<4>

SDCONN_DATA<7>

SDCONN_DATA<2>

SDCONN_DATA<1>

SLG_ENET_RESET_R_L

=PP3V3_S0_SDCARD

ENET_SD_RESET_L

SDCONN_DATA<5>

ENET_LOW_PWR

=PP3V3_S0_SW_SD_PWR

=PP3V3_S0_SDCARD

ENET_SD_DETECT_L

SDCONN_STATE_CHANGE

SDCONN_DETECT

=PP3V3_S5_SDCARD

SD_DETECT_LVL

SLG_ENET_RESET_L

ENET_CR_PWREN

ENET_RESET_L

SDCONN_DATA_R<3>

ESD_HOT=TRUE

SDCONN_ILIM

SDCONN_OC_L

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_S0_SW_SD_PWR

MAKE_BASE=TRUE

VOLTAGE=3.3V

SDCONN_ILIM_R

prefsb

051-9504

7.0.0

41 OF 143

41 OF 117

12

2

1

2

12

2

5

11

10

4

8

9

1

7

3

6

715

3

2

4

6

2

1

2

1

2

12

2

1

12

1

2

1

2

1

2

1

2

1

21

27

26

25

24

22

21

20

23

14

19

18

17

12

11

13

9

8

7

10

6

2

5

4

3

1

15

16

1

2

1

2

41

116

111

116

6

41

6

41

116

6

116

39

113

111

116

115

NC

HOLD*

SCLK

WP*

CS*

VCC

THRM

GND

SO/SIO1

SI/SIO0

PAD

OVDD2

OVDD1

USB_VDDA0

MAVSS

DVSS6

DVSS4

USB_VSSA0

GPIO0 GPIO1 GPIO3 GPIO9

MRXDATAINP

MRXCLKINP MRXCLKINN

CLKIN

MRXDATAINN

SF_DOUT

SF_DIN

CS_PWDB

SF_CLK

MIPI_RESISTOR

USB_VSDL0

OVSS2

CS_SCK

USB_PADM

USB_PADP

LED_FIXED

CS_SDA

SF_CS*

VSSA_PLL

DVDD4

DVDD6

VDDA_PLL

CS_CLK

CS_RSTB

TEST

USB_VRES

RST*

UART1_RX UART1_TX

THRM

SF_WP*

OVSS1

DVSS3

USB_VDDL0

CLKOUT

NC

MAVDD33

DVDD3

PAD

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPIO3 CAN BE CONFIGED AS GENERAL

USB CAMERA CONTROLLER

SERIAL FLASH

STITCH THERMAL PAD TO INNER GROUND

335S0852

UART1_TX IS STRAP FOR SELECTION

SPI CLOCK DURING POWER-ON. ’1’ = POSITIVE EDGE ’0’ = NEGATIVE EDGE

518S0856

USE 100 OHMS AND 150PF FOR 10MHZ FILTER

(SMIA_DATA_P)

(SMIA_CLK_P)

(SMIA_CLK_N)

CAMERA/ALS/DMIC CONNECTOR

(SMIA_DATA_N)

OF POS/NEG EDGE SAMPLING OF

197S0478

CRYSTAL

’1’= EXT FW

GPIO AFTER POWER ON

’0’= INT FW

GPIO3: EXT/IN FIRMWARE BOOT SEL

337S4151

X5R

C4218

0.1UF

6.3V

10%

201

0201-MUR

C4216

1.0UF

6.3V X5R

20%

X5R

1.0UF

C4221

0201-MUR

6.3V

PLACE_NEAR=U4200.33:5mm

R4204

1/20W MF

1%

24K

201

47

1/20W MF

1%

201

R4216

PLACE_NEAR=U4200.24:5mm

R4213

MF

8.2K

201

1/20W

1%

0201-MUR

C4222

6.3V

20%

X5R

1.0UF

SHORT-0201

XW4202

SHORT-0201

XW4203

X5R

10%

0.1UF

201

C4223

6.3V

PLACE_NEAR=U4200.24:5mm

C4226

0.1UF

201

X5R

10%

6.3V

C4219

201

0.1UF

10%

6.3V X5R

X5R 201

0.1UF

10%

6.3V

C4215

C4224

6.3V

201

10%

X5R

0.1UF

6.3V

201

C4217

X5R

10%

0.1UF0.1UF

6.3V X5R

10%

201

C4214

C4213

X5R 201

6.3V

10%

0.1UF

201

1K

MF

1/20W

R42181%R4219

1% 1/20W MF

1K

201

CRITICAL

F-RT-SM

J4200

20455-020E-32

FERR-1000-OHM

0402

L4200

0

R4260

R4264

0

201

MF

1%

1M

1/20W

R4214

MF

201

1/20W

1%

47

R4215

201

0.1UF

6.3V

C4228

10%

X5R

201

1/20W

10K

1%

MF

R4211

10K

201

1%

MF

1/20W

R4210

L4220

FERR-600-OHM-300MA-0.85OHM

0402

0.1UF

C4220

201

6.3V

10%

X5R

FERR-1000-OHM

0402

L4210

MF5%

201

10

R4220

1/20W

402

10% 16V X5R

1UF

C4262

L4202

0402

FERR-1000-OHM

C4264

1UF

X5R

16V

402

10%

FERR-1000-OHM

0402

L4204

L4206

FERR-1000-OHM

0402

C4266

1UF

402

X5R

16V

10%

201

R4267

0

1/20W

MF

5%

NOSTUFF

402

C4267

150PF

CERM

50V

5%

R4268

201

5%

MF

1/20W

0

C4268

150PF

NOSTUFF

402

CERM

50V

5%

U4202

OMIT_TABLE

CRITICAL

1MBIT-104MHZ

USON

MX25L1006EZUI-10G

10K

201

MF

1% 1/20W

R4206

MF

PLACE_NEAR=U4200.6:5mm

33

R4203

1%

1/20W

201

PLACE_NEAR=U4200.5:5mm

R4205

MF

33

1%

201

1/20W

PLACE_NEAR=U4202.2:5mm

MF

201

R4209

33

1%

1/20W

R4207

10K

1% 1/20W

201

MF

1/20W

201

MF

5%

4.7K

R4208

402

C4265

1UF

X5R

16V

10%

NP0-C0G-CERM

C4227

0201

25V

5%

18PF

5%

NP0-C0G-CERM

18PF

0201

25V

C4225

NOSTUFF

1/20W MF

1%

100

201

R4250

R4255

1/20W

100

MF 201

1%

NOSTUFF

CRITICAL

Y4200

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

U4200

CRITICAL

FQFN

VC0359

SYNC_MASTER=D8_ROSITA

Camera Controller

SYNC_DATE=03/23/2012

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V

PP3V3_S4_CAMFILT

PP1V2_S4_CAMERA

=PP3V3_S4_CAMERA

PP1V8_S4_CAMERA

PP1V2_S4_CAMERA

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM

PP1V2_S4_CAMFILT

I2C_CAMSENSOR_SCL

USB_PCH_8_P

MAKE_BASE=TRUE

USB_CAMERA_N

CAM_AGND

TP_CAM_GPIO1

CAM_EXT_BOOT

SMIA_DATA_P

SMIA_CLK_P SMIA_CLK_N

CAM_XTAL_INSMIA_DATA_N

CAM_SF_DOUT

CAM_SF_DIN

TP_CS_PWD_L

CAM_SF_CLK

MIPI_RESISTOR

USB_CAMERA_P

MAKE_BASE=TRUE

TP_CAM_LED_PWM

I2C_CAMSENSOR_SDA

CAM_SF_CS_L

CAM_PLLGND

TP_ISM_CLK TP_ISM_RST_L

CAM_TEST

CAM_USB_VRES

CAM_PROC_RESET_L

CAM_RX CAM_TX

CAM_SF_WP_L

CAM_XTAL_OUT

CAM_XTAL_IN

CAM_XTAL_OUT_R

SMIA_DATA_N

SMIA_DATA_P

=PP3V3_S4_ALS

=SMB_ALS_SCL

PP1V8_S4_CAMERA

=PP5V_S4_CAMERA

=SMB_ALS_SDA

AUD_DMIC_CLK

AUD_DMIC_SDA1

PP3V3_S4_ALS_F

AUD_DMIC_SDA1_CONN

AUD_DMIC_CLK_CONN

PP1V8_S4_CAMERA_F

SMB_ALS_F_SDA

I2C_CAMSENSOR_SDA I2C_CAMSENSOR_SCL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4MM

PP3V3_DMIC_CONN MIN_NECK_WIDTH=0.15MM

SMB_ALS_F_SCL

PP5V_S4_CAMERA_F

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM VOLTAGE=3.3V

PP3V3_S4_ALS_F

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

PP1V8_S4_CAMERA_F

MIN_NECK_WIDTH=0.15 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM

PP5V_S4_CAMERA_F

SMIA_CLK_P

SMIA_CLK_N

SMB_ALS_F_SCL

SMB_ALS_F_SDA

GND_AUDIO_DMIC

CAM_PLLGND

CAM_AGND

USB_PCH_8_N

=PP3V3_S4_CAMERA

CAM_SF_DOUT

CAM_SF_DIN_R

CAM_SF_DIN

CAM_SF_DOUT_R

CAM_SF_CLK

CAM_XTAL_OUT

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM

PP1V2_S4_F_R

VOLTAGE=1.2V

=PP3V3_S0_AUDIO

=PP3V3_S4_CAMERA

CAM_SF_WP_L CAM_SF_HOLD_L

CAM_SF_CLK_R

CAM_SF_CS_L

CAM_AGND

prefsb

051-9504

7.0.0

42 OF 143

42 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

9

10

6

3

4

5

2

1

21

22

12

13

20

8

7

11

14

19

18

17

16

15

23

24

21

12

1

2

12

2

1

2

1

2

21

2

1

21

12

2

1

21

2

1

21

2

1

12

2

1

12

2

1

7

6

3

1

8

9

4

2

5

1

2

12 12

12

1

2

1

2

1

12

1

2

1

2

42

13

40

7

23

31

443522

48 47 46 12

28

30 29

927

4

5

37

6

33

18

39

41

21

20

17

42

3

25

34

43

26

38 36

11

24

1

14 13

49

2

8

15

19

10

45

32

16

42 43

6

42 43

42

102

20

102

42

102

43

112

42

102

42

102

42

102

42

102

42

102

42

102

42

102

42

102

42

102

42

102

42

102

43

112

42

102

42

102

42

102

42

102

42

102

6

50

42 43

6

50

56

42

115

42

102

42

102

42

102

115

42

102

42

115

42

102

42

102

42

102

42

102

56

42

102

42

102

20

6

42 43

42

102

42

102

42

102

42

102

6

56 58 59 62

6

42 43

42

102

42

102

42

102

NC

EN

NC

VO

VIN

GND

NC

EN

NC

VO

VIN

GND

D

GS

Y

A

B

08

Y

A

B

08

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Camera Processor Reset

Camera Processor ExtBoot Cntl

PP1V2_S4_CAMERA VregPP1V8_S4_CAMERA Vreg

0.1UF

6.3V X5R 201

10%

C4300

402

X5R-CERM1

20%

6.3V

4.7UF

C4314

402

10%

X5R

16V

1UF

C4310

U4310

ISL9021AIRUCZ-T

CRITICAL

DFN

402

20%

4.7UF

X5R-CERM1

6.3V

C4324

ISL9021AIRUWZ-T

DFN

CRITICAL

U4320

10%

1UF

16V X5R 402

C4320

51K

MF

1/20W

201

5%

R4300

402

2.2UF

20%

X5R-CERM

10V

C4301

SSM3K15AMFVAPE

VESM

CRITICAL

Q4300

CRITICAL

SOT902

74LVC2G08

U4300

4

8

CRITICAL

74LVC2G08

SOT902

U4300

4

8

SSM3K15AMFVAPE

CRITICAL

VESM

Q4302

1/20W MF 201

10K

5%

R4302

10V

10%

1UF

X5R-CERM 0402

C4312

1/20W

201

5%

MF

4.7K

R4310

MF

1/20W

5%

201

4.7K

R4320

1UF

0402

X5R-CERM

10V

10%

C4322

MMDT3904-X-G

SOT-363-LF

Q4310

MMDT3904-X-G

SOT-363-LF

Q4310

5% 1/20W

10K

201

MF

R4306

201

MF

1/20W

5%

1K

R4304

Camera Controller Support

SYNC_DATE=03/15/2012

SYNC_MASTER=D7_MLB

PM_PCH_PWROK

=PP3V3_S4_CAMERA

PCH_CAM_RESET_R

PM_PCH_PWROK

=PP3V3_S4_CAMERA

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.2V

PP1V2_S4_CAMERA

VOLTAGE=1.8V

PP1V8_S4_CAMERA

MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.6 MM

P1V2_S4_EN

CAM_EXT_BOOT

CAM_EXT_BOOT_L

=PP3V3_S4_CAMERA

PP1V8_S4_CAMERA

CAM_P1V2_RST_HOLDOFF_L

CAM_PROC_RESET

CAM_P1V2_RST_HOLDOFF

PP1V2_S4_CAMERA

P1V8_S4_EN

=PP3V3_S4_CAMERA

PCH_CAM_EXT_BOOT_R_L

CAM_PROC_RESET_L

prefsb

051-9504

7.0.0

43 OF 143

43 OF 117

2

1

2

1

2

1

3

5

2

6

1

4

2

1

3

5

2

6

1

4

2

1

2

1

2

3

5

2

3

1

6

7

1

2

3

1

2

1

2

1

2

1

6

2

4

3

5

1

2

1

2

15 19

26

35

43

65

89

115

6

42 43

21

114

15 19 26 35 43 65 89

115

6

42 43

42 43 42 43

114

42

112

102

6

42 43

102

112

102

42 43

114

6

42 43

6

42 43

21 102

42

112

IN

OUT OUT

IN IN

IN

OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

D8:CONSIDER CHANGING SMC_OOB2_RX/TX_L PULL-UP TO 100K (FROM 10K) RDAR://10817697

155S0397 20mOHM

518S0865

HDD POWER

GUMSTICK2

HDD DATA

518S0251

AC CAP O S12 SIDE

514S0411

POR USE

AC CAP O S12 SIDE

CLK_REQ RESET_L

SATA Activity LED

CRITICAL

L4500

0603

PLACE_NEAR=J4500.1:3MM

FERR-70-OHM-4A

20% CERM

C4501

402

0.1UF

10V

20%

0.1UF

CERM

402

10V

C4500

48

116

18

100

18

100

18

100

18

100

L4530

0402

FERR-220-OHM

SILK_PART=HDD

CRITICAL

EP00-081-91

J4520

GND_VOID=TRUE

M-ST-SM

GND_VOID=TRUE

C4521

0.01UF

25V X7R

40210%

X7R

10%

25V

402

C4522

GND_VOID=TRUE

0.01UF

C4523

GND_VOID=TRUE

X7R25V

40210%

C4524

0.01UF

GND_VOID=TRUE

10% 402

25V X7R

18

100

18

100

18

100

18

100

52

116

10UF

10V

603

X5R

20%

C4532

1206-1

C4531

X5R

25V

10%

10UF

48

116

GND_VOID=TRUE

J4500

CRITICAL

F-RT-SM1

SSD-K70

SILK_PART=GS2 SSD

78047-0773

J4530

CRITICAL

SILK_PART=PWR

M-ST-SM-1

1/16W

402

R4521

100K

MF-LF

5%

100K

5% 1/16W

R4522

402

MF-LF

330

1/10W MF-LF

5%

DEVELOPMENT

603

R4599

DEVELOPMENT

GREEN-3.6MCD

2.0X1.25MM-SM

D4599

SILK_PART=SATA

SATA Connectors

SYNC_DATE=01/31/2012

SYNC_MASTER=D8_JERRY

NO_TEST=TRUE

SATA_SSD_R2D_N

=PP3V3_S0_SSD

SMC_OOB2_RX_L SMC_OOB2_TX_L

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=3.3V

PP3V3_S0_SSD_FLT

MAKE_BASE=TRUE

SATALED_L

NO_TEST=TRUE

SATA_HDD_D2R_P

SATA_HDD_R2D_N

NO_TEST=TRUE NO_TEST=TRUE

SATA_HDD_R2D_C_N

SATA_HDD_R2D_P

NO_TEST=TRUE

SATA_HDD_D2R_N

SATA_HDD_D2R_C_N

NO_TEST=TRUE

SATA_HDD_D2R_C_P

NO_TEST=TRUE

SATA_SSD_R2D_P

NO_TEST=TRUE

SATA_SSD_D2R_N

NO_TEST=TRUE

SATA_SSD_D2R_P

PCH_SATALED_L

=PP3V3_S0_LED_SATA

SATALED_R_L

=PP3V3_S0_SSD

SMC_OOB1_RX_FILT

NO_TEST=TRUE

SATA_HDD_R2D_C_P

PP12V_S0_HDD_FET

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=12V

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP5V_S0_HDD_FET

SMC_OOB1_RX_CN

prefsb

051-9504

7.0.0

45 OF 143

44 OF 117

21

2

1

2

1

21

1

2

3

5

4

6

7

12

2

1

2

1

2

24

26

25

31

27 28

18

1

7

6

3 4

8

23

22

20

5

10 11

9

13

12

15 16

14

17

21

19

29 30

32 33 34 35

37 38

40

39

36

7

6

5

4

3

2

1

2

1

2

12

K

A

6

44

115

116

100

15 18

6

15

6

44

52

115

52

115

116

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

BI

L2

L1

L2

L1

SYM_VER-1

IN

SYM_VER-1

BI

L2

L1

L2

L1

OUT

IN

BI

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

BI

IN

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

IN

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

NC

GND

VBUS

IO

NC

GND

VBUS

IO

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

377S0126

155S0367

377S0126

377S0104

353S3052

44 mOHM

=> 2.19A MIN

2x ILIM resistors rdar://11104691

3ms Rise Time

EHCI

=> 2.63A MAX

23.2K (1%)

514-0840

514-0839

BLM18S121: 25 mOHM

USB/SMC DEBUG MUX

SEL: 0 MOJO SEL: 1 USB

155S0430

155S0367

155S0721

377S0104

155S0430

353S3603

BLM18S121: 25 mOHM

155S0721

377S0104377S0104

377S0104

353S3603

155S0721

377S0104 377S0104

EXT PORT B

155S0721

377S0104

EXT PORT A

PCH GPIO60

XHCI

CRITICAL

SON

TPS2561DR

U4600

20

102

0504

CRITICAL

GND_VOID=TRUE

L4603

80OHM-25%-100MA

CRITICAL

GND_VOID=TRUE

0504

L4604

120-OHM-90MA

DLP0NS

L4602

CRITICAL

X5R

0.1UF

20110%

C4608

GND_VOID=TRUE

6.3V

10%

X5R

0.1UF

6.3V 201

C4609

GND_VOID=TRUE

10V

20%

C4606

402

0.1UF

CERM

10V

402

C4607

0.1UF

20%

CERM

46 64

115

FERR-120-OHM-3A

0603

L4611

CRITICAL

120-OHM-90MA

DLP0NS

L4612

0.1UF

CERM

20%

C4617

10V

402

10K

402

1/16W

5%

R4615

MF-LF

C4616

402

0.1UF

20% 10V CERM

20

102

20

102

20

102

80OHM-25%-100MA

GND_VOID=TRUE

0504

L4613

CRITICAL

L4614

80OHM-25%-100MA

0504

GND_VOID=TRUE

20

102

20

102

C4618

GND_VOID=TRUE

X5R

6.3V 201

0.1UF

10%

201

C4619

10%

X5R

0.1UF

6.3V

GND_VOID=TRUE

20

102

20

102

PLACE_NEAR=U4600.2:2MM

CERM

20% 10V

0.1UF

C4601

402

C4602

330UF-25MOHM

CASE-D2E

20%

6.3V TANT

NOSTUFF

10UF

X5R 603

20% 10V

C4613

NOSTUFF

C4603

10UF

X5R

10V

603

20%

R4604

1/16W

0

5%

402

MF-LF

20

102

SIGNAL_MODEL=SWI_USB3740_DFN_USB3740_MOJO

CRITICAL

USB3740

U4610

DFN

20

102

47 48

114

47

CRITICAL

DFN

USB3740

U4630

18

D4604

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

D4605

ESD0P2RF-02LS

TSSLP-2-1

D4602

CRITICAL

D4603

TSSLP-2-1

ESD0P2RF-02LS

CRITICAL

D4613

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

D4612

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

D4615

TSSLP-2-1

CRITICAL

D4614

ESD0P2RF-02LS

CRITICAL

J4600

F-ANG-TH

USB-NO1-T86-D8

USB-NO2-T86-D8

F-ANG-TH

J4610

CRITICAL

C4605

0402

20%

0.01UF

16V X7R-CERM

C4615

X7R-CERM

16V

0.01UF

20%

0402

402

1%

PLACE_NEAR=R4602.2:2MM

MF-LF

1/16W

11.5K

R4603

CRITICAL

NOSTUFF

RCLAMP0582N

D4601

SLP1210N6

RCLAMP0582N

NOSTUFF

CRITICAL

D4611

15 20 99

20

102

20

102

20

102

20

102

FERR-120-OHM-3A

L4601

0603

1/16W

R4605

10K

5%

402

MF-LF

402

1/16W

1%

MF-LF

R4602

11.5K

PLACE_NEAR=U4600.7:2MM

47 48

114

15 20 99

SYNC_MASTER=D8_ROSITA

EXTERNAL USB PORTS A & B

SYNC_DATE=03/23/2012

MIN_LINE_WIDTH=0.6MM

PP5V_S4_EXTB

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

USB_EXTAB_ILIM

USB_EXTAB_ILIM_R

USB_EXTB_OC_L

USB_PCH_1_P

USB_PCH_9_P

USB_DEBUGPRT_EN_L

NO_TEST=TRUE

USB3_EXTB_TX_F_P

NO_TEST=TRUE

USB3_EXTA_RX_F_P

NO_TEST=TRUE

USB3_EXTA_RX_P

USB3_EXTA_TX_F_N

NO_TEST=TRUE

USB2_EXTA_MUXED_N

NO_TEST=TRUE

USB3_EXTB_RX_N

PP3V3_G3H_SMC_USBMUX_R

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

NO_TEST=TRUE

USB3_EXTB_RX_F_P

NO_TEST=TRUE

USB3_EXTA_TX_P

NO_TEST=TRUE

USB3_EXTA_TX_N

USB3_EXTA_RX_F_N

NO_TEST=TRUE

USB3_EXTB_TX_N

NO_TEST=TRUE

USB3_EXTB_TX_P

NO_TEST=TRUE

USB3_EXTB_RX_F_N

USB3_EXTB_TX_C_N

NO_TEST=TRUE

USB2_EXTB_MUXED_P

USB3_EXTB_RX_P

NO_TEST=TRUE

USB3_EXTB_TX_F_N

NO_TEST=TRUE

USB2_EXTB_MUXED_N

USB_PCH_0_N

MOJO_TX_L

MOJO_RX_L

=PP3V3_G3H_SMC_USBMUX

USB_PCH_1_N

USB_EXTB_SEL_XHCI

USB_PCH_0_P

NO_TEST=TRUE

USB3_EXTA_TX_F_P

NO_TEST=TRUE

USB3_EXTA_RX_N

=PP3V3_S5_SMC_USBMUX

PM_EN_USB_PWR

=PP5V_S4_USB

USB_EXTA_OC_L

USB_PCH_9_N

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM

PP5V_S4_EXTA

USB3_EXTA_TX_C_P

NO_TEST=TRUE

USB3_EXTA_TX_C_N

NO_TEST=TRUE

USB3_EXTB_TX_C_P

NO_TEST=TRUE

USB2_EXTB_MUXED_F_P

NO_TEST=TRUE

USB2_EXTB_MUXED_F_N

PP5V_S4_EXTB_F

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

NO_TEST=TRUE

USB2_EXTA_MUXED_P

PP5V_S4_EXTA_F

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

USB2_EXTA_MUXED_F_P

NO_TEST=TRUE

USB2_EXTA_MUXED_F_N

prefsb

051-9504

7.0.0

46 OF 143

45 OF 117

1

11

8

9

7

2 3

5

10

6

4

3

2

1

4

3

2

1

43

12

2

1

2

1

21

43

12

2

1

2

1

4

3

2

1

4

3

2

1

12

2

11

2

1

2

1

12

58

9

10

3

4

2

1

7

6

58

9

10

3

4

2

1

7

6

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

2

1

2

1

2

32

1

6

5

4

32

1

6

5

4

21

1

2

1

2

115

102

115

102

6

102

6

46

6

46

115

102

115

102

115

102

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

L2

L1

L2

L1

SYM_VER-1

IN

SYM_VER-1

BI

L2

L1

L2

L1

OUT

IN

BI

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

IN

BI

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

STDA_SSTX+

STDA_SSTX-

STDA_SSRX+

GND

DD+

GND_DRAIN

VBUS

STDA_SSRX-

SHIELD

NC

GND

VBUS

IO

NC

GND

VBUS

IO

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

2x ILIM resistors rdar://11104691

23.2K (1%)

PCH GPIO74

353S3052

XHCI

EHCI

=> 2.19A MIN => 2.63A MAX

BLM18S121: 25 mOHM

377S0104

155S0367

155S0721

377S0104 377S0104

44 mOHM

155S0430

155S0367

353S3603

155S0721

377S0104

377S0104377S0104

3ms Rise Time

155S0430

EXT PORT D

377S0104377S0104

EXT PORT C

514-0842

514-0841

377S0126

TPS2561DR

U4700

SON

CRITICAL

80OHM-25%-100MA

GND_VOID=TRUE

0504

L4703

CRITICAL

L4704

GND_VOID=TRUE

0504

CRITICAL

80OHM-25%-100MA

L4702

120-OHM-90MA

DLP0NS

CRITICAL

201

X5R 10%

C4708

0.1UF

6.3V

GND_VOID=TRUE

X5R

0.1UF

201

GND_VOID=TRUE

C4709

6.3V

10%

402

C4707

0.1UF

CERM

10V

20%

45 64

115

0603

L4711

FERR-120-OHM-3A

DLP0NS

120-OHM-90MA

CRITICAL

L4712

C4717

10V

0.1UF

20%

CERM 402

R4715

5%

1/16W

402

MF-LF

10K

10V

0.1UF

C4716

CERM

20%

402

20

102

20

102

20

102

CRITICAL

L4713

0504

GND_VOID=TRUE

80OHM-25%-100MA

0504

80OHM-25%-100MA

L4714

CRITICAL

GND_VOID=TRUE

20

102

20

102

10%

0.1UF

201

6.3V

X5R

C4718

GND_VOID=TRUE

6.3V 201

0.1UF

X5R 10%

C4719

20

102

20

102

10V

C4701

20%

0.1UF

402

CERM

PLACE_NEAR=U4700.2:2MM

TANT

CASE-D2E

6.3V

20%

C4702

330UF-25MOHM

10V

C4713

NOSTUFF

603

X5R

10UF

20%

C4703

10V

10UF

20%

X5R 603

NOSTUFF

20

102

U4730

DFN

CRITICAL

USB3740

18

D4704

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

D4705

TSSLP-2-1

CRITICAL

D4702

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

ESD0P2RF-02LS

CRITICAL

D4703

TSSLP-2-1

CRITICAL

TSSLP-2-1

D4713

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

D4712

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D4715

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

D4714

20

102

20

102

F-ANG-TH

CRITICAL

J4700

USB-NO3-T86-D8

CRITICAL

J4710

USB-NO4-T86-D8

F-ANG-TH

X7R-CERM 0402

16V

0.01UF

20%

C4705

C4715

X7R-CERM 0402

16V

0.01UF

20%

MF-LF

402

1%

1/16W

11.5K

PLACE_NEAR=U4700.7:2MM

R4702

1/16W MF-LF

1%

11.5K

402

R4703

PLACE_NEAR=R4702.2:2MM

D4711

NOSTUFF

RCLAMP0582N

SLP1210N6

CRITICAL

RCLAMP0582N

SLP1210N6

CRITICAL

D4701

15 20 99

20

102

20

102

20

102

20

102

L4701

0603

FERR-120-OHM-3A

15 20 99

SYNC_DATE=03/23/2012

EXTERNAL USB PORTS C & D

SYNC_MASTER=D8_ROSITA

USB2_EXTD_MUXED_F_N

NO_TEST=TRUE

USB2_EXTD_MUXED_F_P

NO_TEST=TRUE

PP5V_S4_EXTD_F

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

USB2_EXTC_F_N

NO_TEST=TRUE

USB2_EXTC_F_P

NO_TEST=TRUE

PP5V_S4_EXTC_F

MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM

PP5V_S4_EXTC

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

USB3_EXTC_TX_F_N

NO_TEST=TRUE NO_TEST=TRUE

USB3_EXTC_TX_F_P

USB3_EXTC_TX_N

NO_TEST=TRUE

USB3_EXTC_TX_C_N

NO_TEST=TRUE

USB3_EXTD_TX_C_P

USB3_EXTC_RX_N

NO_TEST=TRUE

USB3_EXTD_TX_F_P

NO_TEST=TRUE

USB3_EXTC_RX_P

NO_TEST=TRUE

USB3_EXTD_TX_N

NO_TEST=TRUE

USB3_EXTD_TX_P

NO_TEST=TRUE

USB3_EXTD_RX_F_P

NO_TEST=TRUE

USB3_EXTD_RX_F_N

NO_TEST=TRUE

USB3_EXTD_TX_C_N

NO_TEST=TRUE

USB3_EXTC_TX_C_P

NO_TEST=TRUE

USB3_EXTC_RX_F_N

USB3_EXTC_RX_F_P

NO_TEST=TRUE

USB3_EXTC_TX_P

NO_TEST=TRUE

USB3_EXTD_RX_N

NO_TEST=TRUE

USB3_EXTD_RX_P

NO_TEST=TRUE

USB3_EXTD_TX_F_N

USB2_EXTD_MUXED_P

NO_TEST=TRUE

USB2_EXTD_MUXED_N

NO_TEST=TRUE

USB_PCH_10_N

USB_PCH_10_P

USB_PCH_3_N

USB_PCH_3_P

USB_EXTD_SEL_XHCI

PM_EN_USB_PWR

USB_EXTC_OC_L

USB_EXTD_OC_L

=PP3V3_S5_SMC_USBMUX

USB_PCH_2_P

USB_PCH_2_N

USB_EXTCD_ILIM_R

USB_EXTCD_ILIM

PP5V_S4_EXTD

MIN_LINE_WIDTH=0.6MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

=PP5V_S4_USB

prefsb

051-9504

7.0.0

47 OF 143

46 OF 117

1

11

8

9

7

2 3

5

10

6

4

3

2

1

4

3

2

1

43

12

2

1

21

43

12

2

1

2

1

4

3

2

1

4

3

2

1

12

2

11

2

1

2

1

58

9

10

3

4

2

1

7

6

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

9

8

6

4

14 15 16

2 3

11 12 13

17

21

7

1

5

22

10

18 19 20

2

1

2

1

2

1

2

32

1

6

5

4

32

1

6

5

4

21

102

115

102

115 115

102

6

45

115

6

45

LPC0AD3 LPC0CLK LPC0FRAME*

LPC0AD1 LPC0AD2

AIN08

AIN07 LPC0CLKRUN* LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119 PP4/IRQ120

C0-

WT2CCP0/PH0 WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2 SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127 PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4 PF5

T1CCP0/PJ0

T2CCP0/PJ2 T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

BI

IN

BI

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

NC

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

proj

arch

arch arch

od

proj proj

arch

proj

arch

od

analog

od

arch

od

analog

arch

int

arch

od

arch arch

arch arch arch

arch arch

arch

proj

arch

proj proj

od

proj

int

analog

arch

proj

proj proj

arch arch

arch

analog

proj

analog

int

arch

od

arch

od

analog

arch

proj

analog

proj

analog

proj

analog

proj

analog

proj

analog analog

analog

proj

analog

proj

analog

arch

pwm

proj

arch

od

arch

proj

od

proj

int

arch

proj

int

arch

proj

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating,

proj

arch

proj

arch

proj

analog

proj

analog

od

analog

arch

int

proj

arch

proj

arch

analog

those designated as inputs require pull-ups.

(OD)

proj

arch

arch arch arch

arch

proj

analog

arch

LM4FSXAH5BB

BGA

OMIT_TABLE

U4900

LM4FSXAH5BB

OMIT_TABLE

BGA

U4900

PLACE_NEAR=U4900.A1:4MM

SM

XW4900

48 49

116

48

101

201

5% 1/20W MF

1M

R4902

18 49

101

18 49

101

18 49

101

18 49

101

26

101

18 49

101

26

116

18 49

114

48 49

114

19 26 49

114

15 21

117

50

116

50

116

50

116

50

116

50

116

50

116

50

116

50

116

48 50

116

48 50

116

48 50

116

48 50

116

48

48 74

116

48 65

114

38 48 65

116

48

116

45 48

114

45 48

114

48

101

48

101

48

101

48

101

45

48 82

116

5

65

112

48

117

15 19 25

115

19 25 26

115

29 30 31 32 48

114

15 21

117

11 21 48 99

48

116

48 49

117

48 49

117

48

54

48

54

116

54

116

48

116

35 48

116

48

113

5

15 19 28 40 48 64

115

15 19 64

115

15 19 64

115

48

116

48

35 48

117

48

35 48

112

48

113

82

116

65

116

15

117

0402

30-OHM-1.7A

L4901

11 48 66 99

52

116

48

116

48

65

0.1UF

201

10%

6.3V X5R

C4917

X5R

0.1UF

201

10%

6.3V

C4913

6.3V

0.1UF

201

10%

X5R

C4914

X5R

6.3V

10%

201

0.1UF

C4915

0.1UF

201

10%

6.3V X5R

C4916

201

10%

6.3V X5R

0.1UF

C4903

0.1UF

201

10%

6.3V X5R

C4904

0.1UF

201

10%

6.3V X5R

C4905

6.3V

201

0.1UF

10%

X5R

C4906

0.1UF

201

10%

6.3V X5R

C4909

0.1UF

10%

6.3V X5R 201

C4908

10%

201

X5R

6.3V

0.1UF

C4907

X5R

6.3V

10%

201

0.1UF

C4901

48

112

48

116

48

116

48

PLACE_NEAR=U4900.D2:4mm

0201

X5R-CERM

10V

10%

0.01UF

C4921

PLACE_NEAR=U4900.D1:4mm

1UF

0201

20%

X5R

6.3V

C4920

1UF

10%

6.3V CERM 402

C4910

1UF

10%

6.3V CERM 402

C4911

1UF

10%

6.3V CERM 402

C4912

10V

1UF

C4902

X5R-CERM 0603-1

20%

SYNC_MASTER=D8_MARK

SYNC_DATE=03/22/2012

SMC

LPC_AD<1>

LPC_AD<0>

LPC_FRAME_L

PP3V3_G3H_SMC_VDDA

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 MM VOLTAGE=3.3V

SMC_ADC5

SMC_PP5

SMC_TCK

SMC_TDO

CPU_PROCHOT_L

SMBUS_SMC_3_SCL

SMC_TDI

SMBUS_SMC_5_G3H_SCL

SMC_ADC16

SMC_ADC18

SMC_ADC23

SMC_CPU_CATERR_L

MOJO_RX_L

SMC_PROCHOT

SMC_DELAYED_PWRGD

SMC_PP6

SMC_RX_L SMC_TX_L

SMC_FAN_1_CTL

SMC_ADC7

SMC_ADC9

SMC_ADC12

SMC_ADC19

SMC_GFX_THROTTLE_L

SMC_RESET_L

SMC_TMS

SMC_S4_WAKESRC_EN

SMC_WAKE_L

SMC_XTAL

NO_TEST=TRUE

NC_SMC_XOSC1

SMC_EXTAL

AP_EVENT_L

SMC_CLK32K

NO_TEST=TRUE

NC_SMC_HIB_L

SPI_SMC_MOSI

MOJO_TX_L

SMC_ADC0

SMC_ADC21 SMC_ADC22

CPU_THRMTRIP_3V3

SMC_PM_G2_EN

SMC_PN7

SMC_DP_HPD_L

ENET_ASF_GPIO

SMC_BC_ACOK G3_POWERON_L

SMC_PJ3

SMC_BATLOW_L

SMC_PJ2

SMC_OOB1_RX_L

LPC_SERIRQ PM_CLKRUN_L LPC_PWRDWN_L

SMC_PME_S4_WAKE_L

SMBUS_SMC_5_G3H_SDA

USB_SMC_N

PM_SLP_S4_L

SMC_PP7

SMC_ADC11

SMC_ADC8

PM_SLP_S3_L

USB_SMC_P

SMBUS_SMC_1_S0_SDA

LPC_AD<2>

SMC_LRESET_L

SMC_RUNTIME_SCI_L

SMBUS_SMC_4_ASF_SDA

SMBUS_SMC_0_S0_SCL

SMC_PN6

SMBUS_SMC_0_S0_SDA

SMC_WAKE_SCI_L

SMC_VCCIO_CPU_DIV2

SMC_ADC10

SMC_ADC6

SMC_ADC15

SMC_ADC20

SMBUS_SMC_2_S4_SCL

SMS_INT_L

PM_SLP_S5_L SMC_ONOFF_L

SMC_FAN_0_TACH

SMC_SYS_LED

PM_PWRBTN_L

SMC_THRMTRIP

ALL_SYS_PWRGD

SMC_GFX_OVERTEMP

PM_DSW_PWRGD

SPI_DESCRIPTOR_OVERRIDE_L

SMC_ADC17

SMC_S5_PWRGD_VIN

SMC_PM_PCH_SYS_PWROK

SMC_PP0

CPU_PECI

SMC_OOB1_TX_L

SMC_PH7

MEM_EVENT_L

PM_SYSRST_L

USB_DEBUGPRT_EN_L

S5_PWRGD

SPI_SMC_CS_L

SPI_SMC_CLK

SPI_SMC_MISO

SMC_PME_S4_DARK_L

SMC_PH2

SMC_PN2

SMBUS_SMC_3_SDA SMBUS_SMC_4_ASF_SCL

SMC_PECI_L

SMC_PH3

SMC_PN5

SMC_PN4

SMC_PN3

SMC_FAN_1_TACH

SMC_FAN_0_CTL

SMBUS_SMC_2_S4_SDA

SMBUS_SMC_1_S0_SCL

LPC_AD<3> LPC_CLK33M_SMC

SMC_ADC2

SMC_ADC14

SMC_ADC13

SMC_ADC1

SMC_ADC3 SMC_ADC4

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.1 MM

PP1V2_G3H_SMC_VDDC

GND_SMC_AVSS

PP3V3_G3H_AVREF_SMC

=PP3V3_G3H_SMC

prefsb

051-9504

7.0.0

49 OF 143

47 OF 117

D11 H12 D12

A13 C12

B5

A4 G11 F13

C2

B1

L13

H11

B3

L2

M8

A3

A5

A6

A7

A8

A12

B2

B4

B6

B7

B8

B9

B12

B13

C1

C4 C6

C11

C13

D4

D8

D10

D13

E1

E2

E4

E10

E11

E12

E13

F1

F2

F3

F4

F5

F11

F12

G1

G2

G3

G4

H1

H2

H3

H4

H10

H13

J2

J3

J4

J12

J13

K2

K3

K4

K5

K6

K7

K8

K10

L1

L3

L4

L5

L6

L7

L8

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M9

M11

M13

N1

N2

N3

N5

N6

N7

N8

N9

N11

N12

N4

D5

C5

L9

K9

C9

A9

C8

K1

K13

J1

J9

J7

F10

D1

C7

A11 B10

G10

M12

N13

M10

D2

D3

C3

B11

A1

A2

E3

E5 F9

G12

H5 H9 J5

E6 E8

D9

J10

E9

N10

J8

C10 A10

G13

K12

D7

K11

J11

D6

J6

12

1

2

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

48 49 117

117

48

117

48

116

115

48 51 55

113

48

115

6

48 50

D

SG

IN

OUT

NC

IN

OUT

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

NC NC

OUT

IN

BI

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

D

SG

IN

D

SG

IN

BI

IN

OUT

IN

D

GS

D

GS

D

GS

OUT

IN

D

SG

D

SG

VDD

GND

DM

DP

OE*

S

DP_1

DM_1

DM_2

DP_2

IN

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RDAR://10107203

Note: Previously SMC_NMI. Matt card pulls low.

Note: IPU are pulled to VIN rail

Remove USB hookup from SMC (not needed)

SMC Crystal

SMC 32KHz Clock

(ipu)

SMC Supervisor and AVREF Supply

rdar://11180279 SMC_RESET_L workaround

Level-shifter that allows SMC to drive PROCHOT

SMC samples on power on to enter recovery flasher mode.

Arch Pull Up/Down

PCH and CPU PM signals to SMC

AC/DC from oscillating in and out.

PECI Support

radar://11033060

Serial/JTAG Interface Pull-ups

If power high (i.e. charging iPad)

SMC to monitor 12V G3H power in S3

Pull-down needed for SMC SSI signals

TP for access if ZPB re-instated

case when SMC is initializing in S5, and chip is not yet configured.

rdar://10506970

rdar://10196882

SMC SPI Support

ADC Channel Aliases

Enable S4 Wake Sources

Power Button

Unused Project-specific

To absorb current from discharging RTC Reset Cap

enable BURSTMODE to avoid the

SMC Controlled RTC Reset

To let SMC log if a CATERR or SYS_PWROK abruptly occurs

Note:

Level-shifter that allows unidir SMC to drive bidir PECI

RDAR://11158919 D8:DETERMINE VALUE AND STUFF SERIES R FOR SPI BUS

Project-specific Aliases

197S0472

RDAR://10350663 SMC CRYSTAL SELECTION

PLACEMENT_NOTE: Place this circuit near the Tee point to minimize reflections

PROCHOT Support

Platform Thermal Control

Allow either GFX_OVERTEMP, SMC-driven THRMTRIP or

For a debug ability to communicate to BLC MCU through SMC

Connect BLC Serial through Mojo Mux

CPU-driven THRMTRIP to drive PCH PM_THRMTRIP

SEE

(RADAR://PROBLEM/11724870)

THIS CIRCUIT WILL NOT WORK

SECOND STAGE FET WILL NOT FIX THIS S0 COLLAPSES BEFORE SIGNAL REACHES 3.3 SOLUTION WILL REQUIRE LATCHING OF TT

Note:

Comparator VCCIO Reference

AC/DC Burst Mode Enable

and ACDC_BURST_EN_L could be floating.

Open-drain stage on S4 to account

SSM6N15AFE

CRITICAL

SOT563

Q5024

45 47 48

114

45 47 48

114

C5060

X7R-CERM

0402

0.01UF

10% 16V

402

5%

MF-LF

1/16W

0

NOSTUFF

R5059

402

5%

1/16W

0

MF-LF

NOSTUFF

R5058

R5026

5%

201

1/20W

MF

10K

89

116

89

116

5X3.2X1.2-SM

12.000MHZ-50PPM-8PF-100OHM

Y5065

CRITICAL

SOT-363-LF

Q5027

CRITICAL

MMDT3904-X-G

CRITICAL

MMDT3904-X-G

Q5027

SOT-363-LF

10% 10V

0201

C5040

X5R-CERM

0.01UF

C5031

X7R-CERM

16V

10%

0.1UF

0402

PLACE_NEAR=U4900.K1:4MM

VREF-3.3V-VDET-3.0V

CRITICAL

DFN

U5000

6.3V

CERM-X5R

0.47UF

10%

C5000

402

20%

C5005

1UF

10V

X5R-CERM

0603-1

47 49

116

R5005

100K

1/16W

5%

402

MF-LF

47

116

1/16W MF-LF

5%

0

402

R5065

47

116

11 47 66 99

100K

5%

201

1/20W

MF

R5078

MF-LF

402

1/16W

5%

0

R5035

47

116

402

NOSTUFF

OMIT

NONE NONE

NONE

R5036 R5037

402

330

1/16W MF-LF

5%

11 21 47 99

MF-LF

1%

402

1/16W

10K

R5030

PLACE_NEAR=U4900.K1:6MM

PLACE_NEAR=U4900.K1:5MM

R5031

MF-LF

1/16W

1%

402

10K

47

10K

1/20W

MF5%201

R5085

47

101

49

101

49

101

47

101

49

101

47

101

49

101

47

101

5% MF

201

1/20W

10K

R5075

10K

1/20W

201

MF

5%

R5080

47

101

1/16W

R5060

22

MF-LF

402

5%

PLACE_NEAR=U1800.BA47:6MM

19

101

10K

1/20W MF 201

5%

R5020

100K

201

5%MF1/20W

R5077

6

86 86

MF5%201

1/20W

100K

R5079

R5090

201

1/20W

10K

5% MF

R5091

1/20W

201

MF

5%

100K

MF

10K

201

5%

1/20W

R5095 R5096

201

MF

10K

1/20W

5%

10K

1/20W

201

5% MF

R5097

5%

201

1/20W

10K

MF

R5098

1/20W

MF5%201

100K

R5093

1/20W

MF

201

10K

5%

R5092

MF

1/20W

5%

201

100K

R5087

10K

5%

201

1/20W

MF

R5076

88

201

MF

1/20W

5%

0

R5048

19 65

115

47

116

47

116

R5049

201

1/20W

MF

5%

0

11 99

SOT563

CRITICAL

Q5023

SSM6N15AFE

47 82

116

Q5023

SOT563

CRITICAL

SSM6N15AFE

49

117

47

117

201

R5025

1/20W

MF

1K

5%

21

115

5%

201

MF

1/20W

10K

R5040

48

112

R5041

5%

MF

10K

1/20W

201

6

71

112

5%

MF-LF

1/16W

402

43

R5038

R5023

1/20W

5%

MF

201

51

1/20W

5%

3.3K

R5027

201

MF

11 99

5%

MF

3.3K

1/20W

R5028

201

Q5035

CRITICAL

VESM

SSM3K15AMFVAPE

VESM

SSM3K15AMFVAPE

Q5025

CRITICAL

Q5099

CRITICAL

SSM3K15AMFVAPE

VESM

18 26

116

10K

MF-LF

402

R5099

1/16W

5%

20%

X5R-CERM 0402

6.3V

1.0UF

NOSTUFF

C5099

402

330

1/16W

R5094

5%

MF-LF

R5024

10K

5%

201

1/20W

MF

201

1/20W

5%

10K

R5070

201

MF

1/20W

5%

10K

R5071

NOSTUFF

R5066

MF-LF

1M

5%

1/16W

402

1/16W

MF-LF

5%

100K

R5084

MF-LF

402

1/16W

5%

100K

R5086

47

112

MF-LF

402

1/16W

5%

100K

R5017

MF

1/20W

5%

201

10K

R5081

6

88

SILK_PART=PWR BTN

SM

NTC020AA1JB260T

S5000

SM

S5020

SILK_PART=PWR BTN

NTC020AA1JB260T

6

116

5% MF

NOSTUFF

10K

201

1/20W

R5072

C0G-CERM 0402

50V

12PF

C5065

5%

C0G-CERM 0402

50V

12PF

C5066

C5001

0.01UF

X7R-CERM

10%

0402

16V

0402

10% 16V

C5006

0.01UF

X7R-CERM

SOT563

Q5040

SSM6N15AFE

Q5040

SOT563

1%

24.9

1/16W MF-LF

402

R5050

1%

15

1/16W MF-LF

402

R5051

402

MF-LF

1/16W

15

1%

R5052

1%

15

1/16W MF-LF

402

R5053

402

MF-LF

1/16W

5%

47

R5009

0603

25V X5R-CERM

10%

4.7UF

C5009

DFN

USB3740

CRITICAL

U5060

48 89

112

48 89

112

Q5024

SSM6N15AFE

CRITICAL

SOT563

SMC Support

SYNC_MASTER=D8_DOUG

SYNC_DATE=07/19/2012

SMC_VCCIO_CPU_DIV2

BURSTMODE_EN_L

ACDC_BURST_EN

=PP3V3_S4_SMC

SMC_TO_BLC_TX_L

BLC_EXT_BOOT

SMBUS_SMC_4_ASF_SCL

SMCISNS_P3V3S0_SSD

MAKE_BASE=TRUE

SMCISNS_P12VS0_CPU_P1V05

MAKE_BASE=TRUE

SMCISNS_P12VS0_CPU_VCCSA

SMBUS_SMC_5_G3H_SDA

SMC_OOB1_TX_L

SMC_GFX_OVERTEMP

SMC_ADC20

PM_THRMTRIP_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMB_OOB1_TX_L

SMC_PN3

SMC_ADC23

=PPVCCIO_S0_SMC

SMC_XTAL_R

SPI_SMC_MISO

SMC_PH3

NC_USB_SMC_N

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PN3

SMC_PN6

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PP6

MAKE_BASE=TRUE

SMC_ONOFF_L

SMC_PECI_L_R

SMC_PECI_L

SMC_RX_L

SMC_TCK

MOJO_RX_L

SMC_TMS

SMC_BLC_MUX_TX_L

SMC_BLC_MUX_RX_L

BLC_EXT_BOOT

NC_SMBUS_SMC_5_G3H_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_SMC_PH7

GND_SMC_AVSS

SMC_CPU_PECI

=PPVCCIO_S0_SMC

SMC_PN2

NC_SMC_PN6

MAKE_BASE=TRUE

NO_TEST=TRUE

=PP3V3_G3H_SMC

SMC_ADC4

SMCISNS_P1V5S0_CPU_MEM

MAKE_BASE=TRUE

SMCVSNS_PVDDQS3_DDR

MAKE_BASE=TRUE

SMCISNS_P5VS0_HDD

MAKE_BASE=TRUE

SMC_ADC19

=PP3V3_S4_TBTBPWRSW

=PP3V3_S4_TBTAPWRSW

=TBTBPWRSW_EN

=TBTAPWRSW_EN

=PP3V3_G3H_SMC

SMC_ADC18

=PP3V3_G3H_SMC

SPI_MLB_CS_LSPI_SMC_CS_L

SPI_MLB_CLKSPI_SMC_CLK

SPI_MLB_MOSISPI_SMC_MOSI

SPI_MLB_MISO

ACDC_BURST_EN_L

NO_TEST=TRUE

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

SMC_PP5

SMC_PP6

SMC_PP7

SMCVSNS_P1V05S0_PCH

MAKE_BASE=TRUE

SMC_PN5

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_SMC_P

=PP3V3_S5_SMC

SMC_ADC21

SMCVSNS_P3V3S0

MAKE_BASE=TRUE

SMCISNS_P3V3S4_AP

MAKE_BASE=TRUE

SMCISNS_P1V05S0_PCH

SMC_PN7

SMBUS_SMC_5_G3H_SCL

SMC_PH7

USB_SMC_P

SMC_PJ3

MAKE_BASE=TRUE

SMC_ASSERT_RTCRST

SMC_BLC_FAULT

MAKE_BASE=TRUE

SMS_INT_L

AP_EVENT_L

ENET_ASF_GPIO

SMC_BC_ACOK

=PP3V3_S4_AP_FET

SMCISNS_P12VS0_FBVDDQ

MAKE_BASE=TRUE

SMCVSNS_CPUCORE

MAKE_BASE=TRUE

=PP3V3_G3H_SMC

RTC_RESET_L

RTC_RESET_L_R

SMC_ADC6

SMC_ADC2

SMC_ADC5

SMC_ADC8

SMC_ADC13

SMC_ADC16

SMC_ADC1

SMC_ADC3

SMC_ADC7

SMC_ADC9

SMC_ADC10

SMC_ADC11

SMC_ADC12

G3_POWERON_L SMC_BATLOW_L

SMC_DELAYED_PWRGD PM_DSW_PWRGD

SMC_TX_L

SMC_TDI

MOJO_TX_L

SMC_PME_S4_WAKE_L

SMC_SYS_LED

SMC_S4_WAKESRC_EN

SMC_ADC15

MEM_EVENT_L

PM_CLKRUN_L

=PP3V3_S0_SMC

SMC_BLC_FAULT

SMC_XTAL

MAKE_BASE=TRUE

SMCISNS_P12VS0_P1V05

MAKE_BASE=TRUE

SMC_OOB2_RX_L

ACDC_BURST_EN_L

MAKE_BASE=TRUE

SMCVSNS_P1V5S0_CPU_MEM

MAKE_BASE=TRUE

SMCISNS_GPUCORE

MAKE_BASE=TRUE

SMC_OOB2_TX_L

MAKE_BASE=TRUE

BDV_BKL_PWM

MAKE_BASE=TRUE

SMCISNS_P12VS0_HDD

MAKE_BASE=TRUE

SMC_ACDC_ID

SMCVSNS_P5VS0_HDD

MAKE_BASE=TRUE

SMCISNS_PVDDQS3_DDR

SMCVSNS_CPUAXG

MAKE_BASE=TRUE

SMCISNS_CPUCORE

MAKE_BASE=TRUE

SMCISNS_CPUAXG

SMC_PJ2

SMC_PP0

SMCVSNS_GPUCORE

MAKE_BASE=TRUE

SMCVSNS_P12VG3H

SMC_ADC0

SMC_PN4

MAKE_BASE=TRUE

SMCISNS_P12VG3H

SMC_PM_G2_EN

NC_SMC_PN2

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_SMC_N

SMC_PH2

SMC_TDO

PM_SLP_S3_L

SMC_RESET_L

CPU_PROCHOT_L

SMC_PROCHOT

CPU_PECI

=PP3V3_S0_SMC

MOJO_RX_L

SMC_PM_PCH_SYS_PWROK

SMC_CPU_CATERR_L

PM_PCH_SYS_PWROK

CPU_CATERR_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM

PP3V3_G3H_AVREF_SMC

MIN_LINE_WIDTH=0.4MM

=PPVIN_G3H_SMCVREF

PP3V42_G3H_SMC_SPVSR

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.42V

SMC_MANUAL_RST_L

MIN_LINE_WIDTH=0.4MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.1MM

GND_SMC_AVSS

PWR_BTN

SMC_ASSERT_RTCRST

SMC_CLK32K

PM_CLK32K_SUSCLK_R

MAKE_BASE=TRUE

NC_SMC_PN7

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PP5

SMC_ADC17

CPU_THRMTRIP_L

SMC_ADC14

NC_SMC_PP7

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_EXTAL

SMBUS_SMC_4_ASF_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

SMC_ADC22

SMC_TO_BLC_RX_L

SMC_ROMBOOT

SMC_THRMTRIP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMBUS_SMC_4_ASF_SCL

=PPVCCIO_S0_SMC

MOJO_TX_L

NC_SMBUS_SMC_5_G3H_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_PME_S4_DARK_L

SMC_DP_HPD_L

CPU_THRMTRIP_R_L

=PP3V3_S0_SMC

CPU_THRMTRIP_3V3

prefsb

051-9504

7.0.0

50 OF 143

48 OF 117

6

1

2

1

12

1

2

21

4

3

5

1

6

2

1

2

1

8

6

9

2

5

4

7

3

1

2

1

2

1

2

12

1

2

1

2

1

2

1

2

1

2

12

1

2

12

6

1

2

3

4

5

12

1

2

1

2

12

1

2

12

1

2

1

2

3

1

2

3

1

2

3

1

2

1

12

1

2

12

1

2

12

132

4

132

4

12

2

1

2

1

2

1

2

1

3

4

5

6

1

2

12

2

1

58

9

10

3

4

2

1

7

6

3

4

5

112

6

117

47 50

116

51

116

55 116

47 50

116

47

116

47

6

48

117

47

116

47 49

117

47 49

117

45 47 48

114

47 49

117

47 48 51 55

113

116

6

48

47

6

47 48 50

47

51

116

51

116

51

116

47

6

47 48 50

47

6

47 48 50

47

51

116

47

6

47

51

116

55

116

51

116

47

47 50

116

47

48

116

48

47

35 47

112

47

113

47

35

51

116

51

116

6

47 48 50

116

47

113

47

38 47 65

116

47 65

114

47 49

117

47 49

117

45 47 48

114

35 47

116

47

35 47

117

47

29 30 31 32 47

114

47 49

114

6

48 51 82

48

47

117

55

116

44

116

48

112

51

116

51

116

44

116

84

107

51

116

6

116

51

116

51

116

51

116

51

116

51

116

47

51

116

51

116

47

51

116

47 74

116

47

47 49

117

5

15 19 28 40 47 64

115

6

48 51 82

47

115

6

116

47 48 51 55

113

48

116

47

116

47 50

116

47

117

6

48

47

116

112

6

48 51 82

IN

OUT

IN

OUT

BI

IN

OUT

IN

BI

IN

OUT

IN

OUT

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

IN

OUT

IN

OUT

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

998-4235

LPC+SPI Connector

MATT CONNECTOR

RDAR://11158919 D8:DETERMINE VALUE AND STUFF SERIES R FOR SPI BUS

SPI BootROM

RDAR://11364047 D8: CHANGE R5112 TO 100K FOR SPIROM_USE_MLB

RDAR://11379703 D8: MOVE MATT CARD POWER TO G3H

SPI Series Termination

47 48

117

47 48

117

26

112

21

114

18 47

101

26

101

47 48

117

47 48

117

48

117

47 48

116

47 48

117

47 48

117

19 26 47

114

18 47

114

49

101

49

101

47 48

114

49

101

48 49

101

48 49

101

C5110

6.3V CERM

402

10%

1UF

U5110

SST25VF064C

CRITICAL

SOIC

OMIT_TABLE

64MBIT

R5111

5%

3.3K

402

1/16W MF-LF

48 49

101

48 49

101

MF-LF 402

24

5%

PLACE_NEAR=J5100.11:5mm

1/16W

R5123

18

101

18

101

48 49

101

48 49

101

48 49

101

48 49

101

5%

402

MF-LF

15

1/16W

PLACE_NEAR=U1800.AR54:7MM

R5121

R5122

402

MF-LF

5%

1/16W

15

PLACE_NEAR=U1800.AU53:6MM

21 49

101

18

101

5%

MF-LF

402

1/16W

PLACE_NEAR=U1800.AT57:5mm

R5120

15

18

101

J5100

DF40C-30DP-0.4V

M-ST-SM

LPCPLUS CRITICAL

18 47

101

18 47

101

18 47

101

49

101

21 49

101

18 47

101

R5125

43

402

5%

MF-LF

1/16W

PLACE_NEAR=J5100.12:5mm

R5126

43

5%

PLACE_NEAR=J5100.14:5mm

1/16W MF-LF 402

5%

MF-LF

1/16W

43

R5127

PLACE_NEAR=R5126.2:5mm

402

R5128

1/16W

5%

402

PLACE_NEAR=R5125.2:5mm

MF-LF

43

24

5%

MF-LF

1/16W

402

R5130

PLACE_NEAR=U5110.2:5MM

1/16W MF-LF

402

R5129

54.9

PLACE_NEAR=R5124.2:5mm

1%

402

1/16W

1%

54.9

R5124

MF-LF

PLACE_NEAR=J5100.11:5mm

402

MF-LF

100K

R5112

1/16W

5%

SPI and Debug Connector

SYNC_MASTER=D8_MLB

SYNC_DATE=N/A

SPI_MLB_MISO

SPI_CS0_R_L

SPI_CLK_R

SPI_MOSI_R

SPI_MOSI

SPI_CS0_L

SPI_CLK

SPI_MISO

=PP3V3_G3H_LPCPLUS =PP5V_S0_LPCPLUS

LPC_CLK33M_LPCPLUS LPC_AD<0>

LPC_AD<2>

=PP3V3_S5_ROM

SPIROM_USE_MLB

SPI_MLB_MOSI

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_ALT_MISO

SPI_ALT_CLK

SPI_ALT_MOSI

SPI_WP_L

LPC_SERIRQ

SMC_TCK

LPC_FRAME_L SPIROM_USE_MLB

SPI_ALT_MOSI

LPC_AD<3>

LPC_AD<1>

SMC_TX_L

DEBUG_RESET_L SMC_TDO

LPCPLUS_GPIO

TP_SMC_TRST_L TP_SMC_MD1

SPI_ALT_MISO

PM_CLKRUN_L SPI_ALT_CLK SPI_ALT_CS_L

LPC_PWRDWN_L SMC_TDI

SMC_RESET_L SMC_ROMBOOT SMC_RX_L SMC_TMS

SPI_MLB_MISO

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_MLB_MOSI

SPI_ALT_CS_L

prefsb

051-9504

7.0.0

51 OF 143

49 OF 117

2

1

4

7

8

5

1

3

2

6

1

2

1

2

12

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

3

1

5

9

7

15

11

13

17

19

21

23

25

27

29

31

32

33

34

1

2

1

2

12

1

2

1

2

101

6

49

101

49

101

49

101

49

101

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC (SMBus 3)

J2900 & J3000

radar://11669665

0x73 Read

TBT I2C will not be used in D8 0-ohm not stuffed and pullups stuffed

EMC1414-1:

I2C can be used as alternative to JTAG

Thunderbolt Router

U3600

addresses in 0b11111XXX are "reserved"

0xFF Write 0xFE Read

U6551

Mikey

UJ6500

U3401

Vref Control

0x76 Write 0x77 Read

U9700

0x30 Write 0x31 Read

U1800

PCH (SMBus)

U3400

VRef DACs

Memory Channel B

Memory Channel A

J3100 & J3200

0x99 Read

0xA0 Write

0xA2 Write

DIMM 0: 0xA1 Read

DIMM 2: 0xA3 Read

0xA4 Write

0xA6 Write 0xA7 Read

DIMM 1: 0xA5 Read

DIMM 3:

0x98 Write

Backlight Controller

PCH (SMLink 0)

U1800

PCH SMLink 0 is unused

0x6E Write 0x6F Read

SMC SMBus 4 is unused (reserved for ethernet LOM)

SMC (SMBus 5)

Temp Sensors "T2"

SMC SMBus 3 is reserved for SMC/PCH multi-master experiment

0x53 Read

D8 TCon has 2.2K pullup

K62 TCon has 4.7K pullup

Ambient Light Sensor

GK107:U8000 / GK104:UA000

0x6F Read

0x6E Write

J4200

Display TCon master

J9500 U9700

Backlight Controller

U4900

LCD remote IR temp

0x88 Write

0x93 Read

SMC SMBus 5 is unused

0x8A Write 0x8B Read

U5550

PCH PECI sensor data

PCH (SMLink 1)

U1800

J9500

0x98 Write

U5500

0x99 Read

U5500U4900

0x89 Read

GPU die temp

U4900

U5550

TMP421: 0x9F Read

0x1A Write 0x1B Read

0x9E Write

Panel/Vendor ID:

0x52 Write

SMC (SMBus 2)

U4900

0x9F Read

U5590

0x9E Write

SMC (SMBus 4)

0x92 Write

EMC1428-7:

Temp Sensors "T1"

SMC (SMBus 0)

SMC (SMBus 1)

0x95 Read

0x94 Write

J2500 & J2550

radar://11710650

XDP disconnected from I2C bus to reduce load

XDP

Display TCon slave

0x72 Write

China Headset

MF-LF 402

5%

R5261

1/16W

2.2K

5% 1/16W MF-LF

402

2.2K

R5260

1/16W

5%

8.2K

402

MF-LF

R5271R5270

5%

MF-LF

1/16W

402

8.2K

R5201

MF-LF

1/16W

402

5%

2.2K

1/16W

402

MF-LF

5%

2.2K

R5200

R5211

MF-LF

5% 1/16W

402

2.2K

402

MF-LF

5%

1/16W

R5210

2.2K

R5221

MF-LF

1/16W

5%

402

R5220

2.2K

5% 1/16W MF-LF

402

4.7K

MF-LF

5%

402

1/16W

NOSTUFF

R5241

MF-LF

5%

4.7K

402

NOSTUFF

R5240

1/16W

402

5%

R5281

MF-LF

2.2K

R5280

1/16W

5%

402

2.2K

MF-LF

1/16W

402

4.7K

NOSTUFF

R5231

MF-LF

5%5%

MF-LF

1/16W

402

4.7K

R5230

NOSTUFF

MF-LF

1/16W

402

5%

R5251

4.7K

NOSTUFF

1/16W MF-LF

402

4.7K

5%

NOSTUFF

R5250

NOSTUFF

R5264

402

MF-LF

1/16W

0

5%

R5265

MF-LF 402

0

5% 1/16W

NOSTUFF

MF-LF

1/16W

R5203

5%

402

0

402

MF-LF

1/16W

0

R5202

5%

R5262

MF-LF

0

5%

1/16W

402

R5263

0

MF-LF5%1/16W

402

5%

MF-LF01/16W

R5282

402

R5283

1/16W

5%

MF-LF

0

5%

402

MF-LF01/16W

R5233

NOSTUFF

0

1/16W

5%

MF-LF

402

R5232

NOSTUFF

1/16W

402

MF-LF

R5266

0

5%

NOSTUFF

402

1/16W

5%

MF-LF

R5267

0

NOSTUFF

MF-LF 402

5% 1/16W

R5269

3.3K

402

MF-LF

5%

R5268

1/16W

3.3K

NOSTUFF

MF-LF 402

5% 1/16W

2.2K

R5275R5274

5% 1/16W MF-LF

402

2.2K

NOSTUFF

SMBus Connections

SYNC_MASTER=D8_TAVYS SYNC_DATE=06/22/2012

=I2C_CHS_SCL

=I2C_CHS_SDA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_CLK

MAKE_BASE=TRUE

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

SMBUS_PCH_CLK_R

MAKE_BASE=TRUE

SMBUS_PCH_DATA_R

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_2_S4_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_S4_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

=SMB_SNS2_SCL

=PP3V3_S0_SMBUS_SMC

=SMB_SNS3_SCL

GPU_SMB_DAT_R

=PP3V3_S4_SMBUS_SMC

=SMB_ALS_SDA

=SMB_ALS_SCL

=SMB_SNS1_SCL

GPU_SMB_CLK_R

=PP3V3_S0_SMBUS_SMC

=I2C_TCON_SLA_SDA

=I2C_TCON_SLA_SCL

=SMB_SNS2_SDA

=SMB_SNS3_SDA

SML_PCH_1_DATA

SML_PCH_1_CLK

=PP3V3_S0_SMBUS_TCON

I2C_TCON_MAS_SCL SMB_TCON_BLC_SCL

SMB_TCON_BLC_SDA

=PP3V3_S0_SMBUS_SMC

I2C_TCON_MAS_SDA

SMBUS_SMC_3_SDA

SMBUS_SMC_3_SCL

SMBUS_SMC_4_ASF_SDA

SMBUS_SMC_4_ASF_SCL

=PP3V3_G3H_SMC

SMBUS_SMC_5_G3H_SDA

SMBUS_SMC_5_G3H_SCL

=SMB_SNS1_SDA

SML_PCH_0_CLK

=PP3V3_S4_SMBUS

=I2C_SODIMMA_SDA

=I2C_SODIMMA_SCL

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

SMB_PCH_BLC_SCL

SMB_PCH_BLC_SDA

=I2C_MIKEY_SCL

=I2C_MIKEY_SDA

=PP3V3_TBTLC_RTR

I2C_TBTRTR_SCL

I2C_TBTRTR_SDA

SML_PCH_0_DATA

prefsb

051-9504

7.0.0

52 OF 143

50 OF 117

121

2

121

2

121

2

121

2

121

2

121

2

121

2

121

2

121

2

121

2

121

2

12

121

2

121

2

60

18 116

25

116

6

50

6

50

47

116

47

116

47

116

47

116

47

116

47

116

53

6

50

53

82 108

6

42

53

82 108

6

50

6

50

87

53

18 117

6

87 113

89 109

6

50

87 113

47

116

47

116

47 48 116

6

47 48

47 48 116

53

18 117

6

29 30

31 32

34

89 109

60

6

15 36 37 38

36

107

36

107

18 117

OUT

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN+

IN-

OUT

GND

IN+

IN-

OUT

IN

OUT

IN-

IN+ REF

V+

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ADC 0/1 12V G3H (ID2R/VD2R)

AC/DC CURRENT SENSOR TO 100V/V: RDAR://10645440

CPU VDD (DDR3) lowside sense

GK104:

ADC12/13 CPUAXG IMON S0 (VC0G/IC0G)

PEAK: 35.0 A

OpAmp Gain = 3.1 V/V

ADC 4/5 CPU DDR3 S0 (IC0M/VC0M)

SCALE:141 A

PEAK: 4.75 A SCALE:6.60 A

SCALE:141 A

ADC 6/7 SODIMM DDR3 S3 (IM0R/VM0R)

TDP: 10.0 A

SCALE:41.4 A

AC/DC lowside sense (System total)

Gain: 500 V/V

ADC20/21 SSD 3.3V S0 (IH1R/VR3R)

ADC 16/17 PCH 1.05V S0 (IN1R/VN1R)

OpAmp Gain = 3.1 V/V

(radar://problem/1056794)

SCALE:8.25 A

PEAK: 2.0 A

PEAK: 1.2 A

Gain: 200 V/V

353S2073

GK107:

353S2216

PEAK: 5.93 A TDP: 4.45 A

353S3597

SCALE:3.3 A

TDP: 0.5 A

TDP: 1.25 A

Gain: 200 V/VGain: 500 V/V

353S2073 Gain: 200 V/V

PEAK: 3.0A

TDP: 63 A

DIMM 1.5V lowside sense

353S2216

PCH Vcc 1.05V lowside sense

SCALE:3.3 A

TDP: 25.0 A

PEAK: 11.3 A

NOTE, MUST KEEP 5V OUT BELOW 3.3V

VMAX = 0.9V @ 120 A

PEAK: 120 A TDP: 95 A

PEAK: 30 A TDP: 24 A

HIGHSIDE SENSE FOR HDD 12V

353S2073

Current sense of SSD 3.3V FET

Voltage sense of 3.3V S0

SCALE:3.3 A

TDP: 0.8 A

GPU Core

PEAK: 112 A

TDP: 2.1 A

CPU VCCore

353S2073 Gain: 200 V/V

Gain: 200 V/V

VMax = 0.9V @ 35A

VR IMON SCALE TENTATIVE

SCALE:13.2 A

GAIN: 100 V/V

353S2208

OpAmp Gain = 3.1 V/V

Highside sense for HDD 5V

CPU VCCAXG

SCALE:142 A

ADC 10/11 CPUCORE IMON S0 (VC0C/IC0C)

TDP: 1.76 A

PEAK: 2.35 A

GPU FB highside sense

ADC 2/3 GPUCORE IMON S0 (IG0C/VG0C)

SCALE:33 A

TDP: 25 A

VMax = 0.9V @ 120A

SCALE:3.30 A

ADC 9 FBVDDQ 12V S0 (IG0F)

ADC14/15 HDD 5V S0 (VH05/IH05)

ADC18 HDD 12V S0 (IH02/VH02)

48

116

402

20%

C5302

10V CERM

0.1UF

U4900.E2:10mm

48

116

U4900.E1:10mm

20%

402

0.22UF

X5R

6.3V

C5303

10K

U4900.E2:10mm

402

R5301

MF-LF

1%

1/16W

6

U4900.E1:10mm

4.53K

R5303

1/16W

402

1%

MF-LF

C5300

6.3V

0.22UF

X5R 402

20%

U4900.E2:10mm

402

1% 1/16W

3.32K

MF-LF

R5302

CRITICAL

SC70-5

OPA348

U5325

402

MF-LF

21K

1%

1/16W

R5327

R5325

10K

1/16W MF-LF

1%

402

5.1K

U4900.A6:10mm

R5329

1/16W MF-LF

5%

R5326

1%

402

1/16W

10K

MF-LF

48

116

66

105

48

116

U4900.B6:10mm

0.22UF

C5328

6.3V

402

X5R

20%

MF-LF

U4900.B6:10mm

R5328

1/16W

1%

4.53K

402

48

116

48

116

C5333

20%

X5R

0.22UF

U4900.C1:10mm

6.3V

402

U4900.C1:10mm

R5333

402

MF-LF

1%

1/16W

4.53K

U4900.C2:10mm

MF-LF

1/16W

5%

5.1K

R5334

402

21K

R5332

1% 1/16W MF-LF

402

R5330

MF-LF

1%

1/16W

402

10K

U5330

OPA348

CRITICAL

SC70-5

402

1% 1/16W

10K

MF-LF

R5331

66

105

48

116

402

MF-LF

1%

1/16W

4.53K

R5312

U4900.B3:10mm

0.22UF

C5312

U4900.B3:10mm

20%

X5R 402

6.3V

402

4.53K

R5313

MF-LF

1%

U4900.A3:10mm

1/16W

20%

C5313

0.22UF

402

6.3V X5R

U4900.A3:10mm

C5310

6.3V X5R

20%

402

0.22UF

48

116

48

116

C5337

6.3V X5R 402

20%

0.22UF

U4900.B1:10MM

R5337

1%

MF-LF 402

1/16W

6.65K

U4900.B1:10MM

R5338

4.53K

MF-LF

1/16W

402

1%

U4900.B2:10MM

4.53K

R5336

1/16W

402

MF-LF

1%

U4900.B1:10MM

6

C5338

X5R 402

6.3V

0.22UF

20%

U4900.B2:10MM

6

0612

0.001

1W

MF-1

1%

R5310

48

116

6.3V

20%

X5R 402

0.22UF

C5317

U4900.B4:10MM

4.53K

402

MF-LF

1%

1/16W

R5317

U4900.B4:10MM

6

48

116

C5318

0.22UF

U4900.A4:10MM

20%

402

X5R

6.3V

1/16W

402

1%

MF-LF

4.53K

R5318

U4900.A4:10MM

C5315

402

X5R

20%

6.3V

0.22UF

1% 1W

0612

MF

0.0005

R5315

48 116

4.53K

MF-LF

402

1/16W

U4900.A5:10MM

R5323

1%

6

X5R 402

0.22UF

C5320

20%

6.3V

U4900.A5:10MM

402

0.22UF

C5323

X5R

6.3V

20%

INA210

SC70

U5320

48

116

402

6.3V

20%

0.22UF

C5342

X5R

U4900.G2:10MM

4.53K

402

MF-LF

1%

1/16W

U4900.G2:10MM

R5342

6

48

116

U4900.G1:10MM

0.22UF

C5343

X5R 402

6.3V

20%

R5343

4.53K

1%

402

1/16W MF-LF

U4900.G1:10MM

0.22UF

C5340

X5R 402

6.3V

20%

0612

0.002

1%

MF-1

1W

R5340

U5340

SC70

INA210

48

116

20%

0.22UF

6.3V

402

X5R

C5348

U4900.H1:10MM

1/16W

U4900.H1:10MM

1%

402

MF-LF

4.53K

R5348

6

0.22UF

C5345

6.3V

402

X5R

20%

INA210

U5345

SC70

48

116

U4900.B7:10MM

R5351

4.53K

1/16W

402

MF-LF

1%

48

116

6.3V

0.22UF

20%

402

X5R

U4900.B7:10MM

C5352

X5R 402

6.3V

0.22UF

20%

C5353

U4900.A7:10MM

R5353

4.53K

1/16W MF-LF

402

1%

6

1W

0612

R5350

1%

MF

0.002

U5310

SC70

INA211

U5315

SC70

INA211

INA216A4YFFX

U5350

WCSP-4

INA216A4YFFX

U5335

WCSP-4

402

MF-LF

5%

1/16W

0

R5316

402

MF-LF

1/16W

R5319

0

5%

NOSTUFF

4.53K

MF-LF

U4900.F2:10mm

1/16W

R5308

1%

402

48

116

48

116

0.22UF

U4900.F2:10mm

X5R

6.3V

C5308

20%

402

U4900.F1:10mm

R5309

MF-LF

402

5%

5.1K

1/16W

U5305

OPA348 SC70-5

CRITICAL

R5305

10K

402

1%

MF-LF

1/16W

402

1%

MF-LF

R5307

21K

R5306

MF-LF

10K

1/16W

402

1%

92

110

SC70

U5300

INA214

C5309

0.22UF

10%

6.3V X5R-CERM 0402

U4900.F1:10mm

0402

X5R-CERM

6.3V

10%

0.22UF

C5329

U4900.A6:10MM

0.22UF

U4900.C2:10MM

C5334

10%

6.3V X5R-CERM 0402

16V X7R-CERM

C5305

0402

0.01UF

20%

0402

16V X7R-CERM

0.01UF

20%

C5325

20%

0.01UF

X7R-CERM

16V

C5330

0402

0.005

MF

1W

1%

R5320

0612-2

R5335

0.005

MF

1W

1%

0612-2

R5345

0.005

MF

1W

1%

0612-2

R5300

0.001

0612

1% 1W

MF-1

SYNC_DATE=06/20/2012

SYNC_MASTER=D8_DOUG

I and V Sense 1

ISNSA_P12VS0_HDD_N

ISNSA_P12VS0_HDD_P

PP12V_S0_HDD_SNS

=PP12V_S0_HDD_PWR

ISNSA_P1V05S0_PCH_P

ISNSA_P12VS0_FBVDDQ_P

ISNSA_P5VS0_HDD_N

ISNSA_P5VS0_HDD_P

PP5V_S0_HDD_SNS

=PP5V_S0_HDD_PWR

ISNSA_P12VS0_FBVDDQ_N

PP12V_S0_FBVDDQ_SNS

=PP12V_S0_FBVDDQ_PWR

=PP12V_S5_SNS

SMCVSNS_P12VG3H

=PP5V_S0_ISENSE

ISNS_GPUCORE_FB

GND_SMC_AVSS

ISNS_CPUCORE_FB

GND_SMC_AVSS

ISNS_CPUAXG_FB

=PPVCORE_S0_GPU

=PP3V3_S5_SENSE

ISNS_P12VG3H_R

PPVDDQ_S3_DDR_SNS

SMCVSNS_P1V5S0_CPU_MEM

=PP3V3_S0_SENSE

ISNS_P12VS0_FBVDDQ_R

=PP3V3_S0_SMC

ISNS_P12VS0_HDD_R

GND_SMC_AVSS

ISNS_P3V3S0_SSD_R

ISNSA_P3V3S0_SSD_N

GND_SMC_AVSS

=PP3V3_S0_SSD_PWR

ISNSA_P3V3S0_SSD_P

GND_SMC_AVSS

SMCVSNS_GPUCORE

=PP3V3_S4_SENSE

ISNSA_PVDDQS3_DDR_N

ISNS_PVDDQS3_DDR_R

SMCVSNS_PVDDQS3_DDR

=PP3V3_S0_SENSE

SMCISNS_P12VS0_FBVDDQ

SMCVSNS_P1V05S0_PCH

SMCISNS_P1V05S0_PCH

SMCISNS_PVDDQS3_DDR

SMCISNS_P1V5S0_CPU_MEM

GND_SMC_AVSS

VR_GPU_IMON

ISNSA_P1V5S0_CPU_MEM_N

ISNSA_P1V05S0_PCH_N

=PP1V05_S0_PCH_PWR

ISNS_CPUCORE_N

ISNSA_P1V5S0_CPU_MEM_P

ISNS_GPUCORE_P ISNS_CPUCORE_P

REG_CPUCORE_IMON

PP1V05_S0_PCH_SNS

GND_SMC_AVSS

SMCISNS_P12VS0_HDD

SMCVSNS_P3V3S0

=PP3V3_S0_SENSE

ISNS_CPUAXG_P

SMCISNS_P5VS0_HDD

ISNS_P5VS0_HDD_R

=PPVDDQ_S3_DDR_PWR

GND_SMC_AVSS

=PP3V3_S0_SENSE

ISNS_P1V05S0_PCH_R

=PP3V3_S0_SENSE

GND_SMC_AVSS

SMCISNS_P3V3S0_SSD

GND_SMC_AVSS

=PP1V5_S0_CPU_MEM_PWR

GND_SMC_AVSS

PP3V3_S0_SSD_SNS

SMCISNS_P12VG3H

GND_SMC_AVSS

REG_CPUAXG_IMON

ISNS_CPUAXG_N

GND_SMC_AVSS

ISNSA_PVDDQS3_DDR_P

ISNS_P1V5S0_CPU_MEM_R

GND_SMC_AVSS

SMCVSNS_P5VS0_HDD

SMCVSNS_CPUCORE=PPVCORE_S0_CPU

PP1V5_S0_CPU_MEM_SNS

ISNS_GPUCORE_N

=PPVAXG_S0_CPU

SMCISNS_GPUCORE

SMCVSNS_CPUAXG

SMCISNS_CPUCORE

SMCISNS_CPUAXG

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_PVDDQS3_ISNS

=PP12V_G3H_PWR

PP12V_G3H_SNS

ISNSA_P12VG3H_P

ISNSA_P12VG3H_N

prefsb

051-9504

7.0.0

53 OF 143

51 OF 117

2

1

2

1

12

2

1

2

4

1

3

5

2

12

1

2

1

12

2

1

12

4

1

3

5

2

1

2

12

2

1

12

2

1

2

1

2

1

2

12

2

1

43

21

2

1

12

2

1

12

2

1

43

21

12

2

1

2

1

2

3

14

5

6

2

1

12

2

1

12

2

1

43

21

2

3

14

5

6

2

1

12

2

1

2

3

14

5

6

12

2

1

2

1

12

43

21

2

3

14

5

6

2

3

14

5

6

B2

B1

A1

A2

B2

B1

A1

A2

12

2

1

12

4

1

3

5

2

12

1

2

6

5

41

3

2

1

2

1

2

1

2

1

2

1

2

1

43

21

43

21

43

21

43

21

113

6

113 113

113

6

113

6 6

6

51

6

51

6

51

114

47 48 51 55

113

114

47 48 51 55 113

114

6

78

6

114

6

51 52

53 55

114

6

48 82

114

47 48 51 55 113

114

113

47 48 51 55

113

47 48 51 55

113

6

113

47 48 51 55

113

6

113

114

6

51 52

53 55

47 48 51 55

113

6

114

113

114 114

47 48 51 55 113

47 48 51 55

113

47 48 51 55

113

6

51 52

53 55

114

6

47 48 51 55

113

6

51 52

53 55

114

6

51 52

53 55

47 48 51 55

113

47 48 51 55

113

47 48 51 55

113

47 48 51 55 113

6

47 48 51 55

113

47 48 51 55

113

114

47 48 51 55

113

114

47 48 51 55 113

6

13 16 66

114

6

13 17 66

47 48 51 55 113

6

113

G

D

S

OUT

NC

VCC+

GND

IN

D

SG

D

SG

GND

VDD

D

SON

CAP

IN

OUT

NC

THRM

GND

PG

ON

NC

D1

D2

G

VCC

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(max 2.8A,ave 0.6A)

HDD Out-of-Band Temp Sensing

353S3672

REMOVE R5413 AND SHORT R5412 AFTER HDD_PWR_EN WORKS

(PULL UP TO 3V3_S5 INSIDE PCH)

for Test Only

4AMP,

Input: 2.4V to 5.5V

12mOhm

376S0910

HDD 12V_S0 FET

(max 0.7A,ave 0.3A)

353S3098

4nF = 2.3V/ms Ramp Rate

Drive asleep: HDD drives HDD_OOB_TEMP low

Drive active: Valid signal protocol

Notes:

From drive:

0.0V to 0.3V

1.2V to 2.0V

Low: High:

Node is at 1.5V

R5413 is no stuff

HDD 5V_S0 FET

Drive disconnected: Pulled high

Trip is 1.0V

Temperature read from SATA power connecter pin 11

C5420

16V

20%

CERM

0.1UF

603

PQFN

IRFH3702TRPBF

Q5410

CRITICAL

44

115

402

MF-LF

1/16W

5%

0

R5412

SC70-5

CRITICAL

U5400

LMV331

402

232K

1% 1/16W MF-LF

R5400

402

100K

1% 1/16W MF-LF

R5401

21

113

402

1%

MF-LF

1/16W

100K

NOSTUFF

R5413

CRITICAL

SOT563

SSM6N15AFE

Q5420

R5421

10K

5%

1/16WMF-LF

402

Q5420

SSM6N15AFE

SOT563

CRITICAL

TDFN

U5420

SLG5AP304V

0.0047UF

C5421

0402

25V CERM

10%

C5400

0.1UF

10% 16V X7R-CERM 0402

16V

C5401

0.1UF

10%

X7R-CERM 0402

5%

MF-LF

1/16W

3.3K

402

R5403

402

5%

MF-LF

1/16W

180K

R5402

150K

5% 1/16W MF-LF

402

R5404

402

R5405

1K

5% 1/16W MF-LF

44

116

47

116

44

115

16V

603

10%

X5R

1UF

C5410

CRITICAL

TDFN

SLG5AP026

U5410

R5410

603

100

5% 1/10W MF-LF

SYNC_DATE=02/25/2012SYNC_MASTER=D8_JERRY

HDD/SSD Temp Sense

=PP3V3_S0_SENSE

HDD_OOB_1V00_REF

SMC_OOB1_RX_L

=PP5V_S0_HDD

HDD_PWR_EN_R

HDD_PWR_EN_L

SMC_OOB1_RX_FILT

SMC_OOB1_RX_R

PP12V_S0_HDD_FET

FET_HDD_SLGSW

HDD_12V_S0_GATE

=PP12V_S0_HDD

HDD_PWR_EN

=PP3V3_S0_SENSE

PP5V_S0_HDD_FET

HDD_PWR_EN_R

HDD5V_RAMP_CAP

prefsb

051-9504

7.0.0

54 OF 143

52 OF 117

2

1

5

1

4

12

5

4

2

3

1

2

1

2

1

2

6

1

2

1

2

3

4

5

81

3

52

7

2

1

2

1

2

1

12

1

2

1

2

1

2

1

9

4

8

2

3

5

6

7

1

12

6

51 52 53 55

113

6

52

113

113 116

113

6

51 52 53 55

IN

BI

NC

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

AGNDDGND

SCL

SDA

ADR0 ADR1

DRDY*

V+

IN

BI

IN

VDD

DP6/DN7 DN6/DP7

DN4/DP5

DP2/DN3 DN2/DP3

DP4/DN5

DN1

DP1

THRM_PAD

GND

NC

TRIP/SET

SMDATA

SMCLK

SYS_SHND*

ALERT*

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Temperature Sensor T1 EMC1414: Near PSU Conn

Make sure these caps are OK with U5500 Vendor!

NOTE - Follow TI layout guide(SBOU108.pdf) for this part!!!

Temperature Sensor T3: LCD Remote Sensor(Dev4Now)

I2C Address (TMP006):

SNS T2: TEMP SENSOR IC

MLB Prox 2 (Tm1p)

EMC1428-7: 6.8K PULL UP: I2C ADDRESS: WRITE: 0x92, READ: 0x93

AC/DC

Via connector to diode inside PSU

Temperature Sensor T2 EMC1428: Near GPU VR

will be used as MLB sensor.

AC/DC (Tp2p)

LCD Skim (TL2p)

CPU Prox (TC0p)

BLC Proximity

0x8A (Write) 0x8B (Read)

I2C Address (EMC1414-1):

0x98 (Write) 0x99 (Read)

Internal sensor of the EMC 1414

Note:

518S0698

Skin

Skin Temp (TS0p)

MLB Prox 1 (Tm0p)

CPU Proximity

Ambient

GPU Proximity

Set trip point to 125 C.

SO-DIMM Proximity 1

SO-DIMM Proximity 2

SO-DIMM Proximity 3

SO-DIMM Proximity 4

Ambient (TA0p)

GPU Prox (TG0p)

SoDIMM Prox 1 (TM0p)

SoDIMM Prox 3 (TM2p)

BLC PROX (Tb0p)

SoDIMM Prox 2 (TM1p)

SoDIMM Prox 4 (TM3p)

50V C0G-CERM 402

2.2PF

+/-0.25PF

C5550

Q5550.3:2MM

C5500

402-1

10% 10V X5R

1UF

C5510

402

0.0022UF

CERM

50V

10%

L5510.2:2MM

0402

FERR-220-OHM

L5510

J601.3:21MM

J601.4:20MM

L5511

0402

FERR-220-OHM

6

117

6

117

C5570

402

50V

+/-0.25PF

SIGNAL_MODEL=EMPTY

C0G-CERM

2.2PF

Q5570.3:2MM

SIGNAL_MODEL=EMPTY

50V

402

Q5505.3:2MM

2.2PF

C5505

+/-0.25PF

C0G-CERM

10K

5%

MF-LF 402

R5500

1/16W

50

PLACEMENT_NOTE=Place Q5550 near GPU and GDDR5

BC846BLP

DFN1006H4-3

Q5550

10% 50V

402

CERM

SIGNAL_MODEL=EMPTY

C5501

0.0022UF

L5500.2:2MM

TEMPSNSDEV

L5500

FERR-220-OHM

0402

J5500.1:15MM

TEMPSNSDEV

L5501

FERR-220-OHM

0402

J5500.2:15MM

TEMPSNSDEV

J5500

M-RT-SM

53780-8602

CRITICAL

SILK_PART=SkinTemp

TEMPSNSDEV

402

+/-0.25PF

C0G-CERM

50V

C5560

Q5560.3:2MM

2.2PF

PLACEMENT_NOTE=Place Q5560 near BLC VR

Q5560

DFN1006H4-3

BC846BLP

PLACEMENT_NOTE=Place Q5570 near SO-DIMM connectors (top left)

DFN1006H4-3

BC846BLP

Q5570

BC846BLP

DFN1006H4-3

PLACEMENT_NOTE=PLACE Q5505 NEAR CPU

Q5505

J601.4:30MM

MSOP

EMC1414-1-AIZL

PLACEMENT_NOTE=PLACE U5500 NEAR PSU CONNECTOR

U5500

U5590

WCSP

TMP0006AIYZER

TEMPSNSDEV

50

5% 1/16W

402

MF-LF

R5590

10K

TEMPSNSDEV

U5500.5:2MM

C5503

NOSTUFF

47PF

5% 50V CERM 402

C5502

50V

CERM

5%

NOSTUFF

U5500.4:2MM

402

47PF

R5552

402

5%

20K

MF-LF

1/16W

402

R5551

1/16W MF-LF

10K

5%

50

R5550

MF-LF

1/16W

402

6.81K

1%

C5559

10%

1UF

10V

402-1

X5R

QFN

CRITICAL

U5550

EMC1428-7

PLACEMENT_NOTE=PLACE U5550 NEAR GPU VR TO GET GPU VR PROX TEMP

SM

XW5505

OMIT

XW5504

OMIT

SM

XW5503

OMIT

SM

XW5502

OMIT

XW5501

SM

XW5500

SM

OMIT

Q5555.3:2MM

+/-0.25PF

402

C0G-CERM

50V

C5555

2.2PF

PLACEMENT_NOTE=Place Q5555 near bottom of board

Q5555

BC846BLP

DFN1006H4-3

C5575

402

+/-0.25PF

C0G-CERM

50V

2.2PF

SIGNAL_MODEL=EMPTY

Q5575.3:2MM

DFN1006H4-3

BC846BLP

Q5575

PLACEMENT_NOTE=Place Q5575 near SO-DIMM connectors (top right)

C5580

2.2PF

+/-0.25PF 50V

402

C0G-CERM

Q5580.3:2MM

SIGNAL_MODEL=EMPTY

PLACEMENT_NOTE=Place Q5580 near SO-DIMM connectors (bottom left)

DFN1006H4-3

BC846BLP

Q5580

402

+/-0.25PF

C0G-CERM

2.2PF

50V

Q5585.3:2MM

SIGNAL_MODEL=EMPTY

C5585

DFN1006H4-3

BC846BLP

Q5585

PLACEMENT_NOTE=Place Q5585 near SO-DIMM connectors (bottom right)

10% 16V

0402

TEMPSNSDEV

C5590

0.01UF

X7R-CERM

U5550.15:10MM

402

10% 50V

CERM

C5552

0.0022UF

SIGNAL_MODEL=EMPTY

U5550.10:10MM

402

0.0022UF

CERM

50V

10%

SIGNAL_MODEL=EMPTY

C5554

402

10% 50V

CERM

0.0022UF

C5556

SIGNAL_MODEL=EMPTY

U5550.10:5MM

372S0186 372S0185

Alternate Temp Diode

ALL

SYNC_DATE=06/07/2012

Temperature Sensors

SYNC_MASTER=D8_DOUG

TSNS_2_2_N

TSNS_2_5_P

TSNS_2_5_N

TSNS_2_7_P

TSNS_2_7_N

TSNS_2_7_P

TSNS_2_6_P

TSNS_2_5_N

TSNS_2_5_P

TSNS_2_4_P

TSNS_2_4_N

TSNS_2_3_P

TSNS_2_3_N

TSNS_2_2_P

TSNS_2_1_P

TSNS_2_1_N

MAKE_BASE=TRUE

TSNS_1_2_N

TSNS_1_2_P

TSNS_1_3_P

=SMB_SNS2_SDA

TSNS_2_ALERT_L

TSNS_1_ALERT_L

=SMB_SNS1_SDA

TSNS_1_1_N

TSNS_1_1_P

TSNS_3_DRDY_L

TSNS_SKIN_P

TSNS_1_1_P

=SMB_SNS3_SDA

TSNS_1_1_N

TSNS_1_3_N

TSNS_1_3_P

TSNS_ACDC_N

TSNS_1_3_N

=SMB_SNS1_SCL

TSNS_2_ADDR

=SMB_SNS2_SCL

TSNS_2_TRIPSET

TSNS_ACDC_P

TSNS_1_2_N

MAKE_BASE=TRUE

TSNS_1_2_P

TSNS_2_3_N TSNS_2_3_P

=PP3V3_S0_SENSE

TSNS_2_4_P

TSNS_2_6_N

TSNS_2_4_N

TSNS_2_2_N

TSNS_2_2_P

TSNS_2_1_N

TSNS_2_1_P

TSNS_SKIN_N

TSNS_2_6_N

=PP3V3_S0_SENSE

=SMB_SNS3_SCL

=PP3V3_S0_SENSE

TSNS_2_6_P

prefsb

051-9504

7.0.0

55 OF 143

53 OF 117

2

1

2

1

2

1

21

2

1

2

1

2

3

2

1

2

1

21

4

2

1

3

2

1

3

2

1

3

2

1

3

2

1

8

72

10

9

1

3

4

5

6

A2

A1

B3

C3 C1

B1

C2

A3

1

2

1

2

1

2

1

2

1

2

1

16

15 14

9

3 4

10

2

1

17

8

13

5

11

12

6

7

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3

2

1

2

1

3

2

1

2

1

3

2

1

2

1

3

2

1

2

1

12

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

6

51 52 53 55

53

117

53

117

53

117

53

117

53

117

53

117

53

117

53

117

6

51 52 53 55

6

51 52 53 55

53

117

IN

OUT

D

GS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

12V DC

Otherwise, this is simply a pass-FET.

FET input.

there is a pull-up, going to a Hi-Z

See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors).

when Q5610 is on.

Note:

It is assumed there is a pull-up to

The circuit for the PWM input to

level-shifter to protect the SMC.

This resembles an open-drain if

at common and the SMC sinks current

definition, the drain of Q5610 is

present on the SMC pin! Then by

the fan acts as a non-inverting

turns on, there would be 5V/12V

when the SMC PWM goes low and Q5610

5V/12V inside the fan, otherwise

Tach GND

518S0730

SMC Fan 0 (System)

SMC Fan 1 (Unused)

L5600

CRITICAL

220-OHM-1.4A

0603

C5601

0.01UF

16V

20%

X7R-CERM 0402

C5600

4.7UF

20%

CERM 1206-1

16V

47

116

J5600

CRITICAL

53780-8604

M-RT-SM

47

CRITICAL

L5620

0402

FERR-220-OHM

L5610

CRITICAL

0402

FERR-220-OHM

C5610

CERM

50V

5%

100PF

0402

R5626

MF-LF

1/16W

5%

402

47K

5%

MF-LF

1/16W

47K

402

R5625

47

116

R5610

10K

1/16W MF-LF

5%

402

Q5610

CRITICAL

SSM3K15AMFVAPE

VESM

10%

C5690

1000PF

U4900.L13:5MM

16V

X7R-CERM

0201

0402

5% 50V CERM

100PF

C5620

SYNC_DATE=07/19/2012

System Fan

SYNC_MASTER=D8_DOUG

SMC_FAN_0_TACH FAN_0_TACH_FET

VOLTAGE=12V MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP12V_S0_FAN_0_FILT

FAN_0_PWM_FET

=PP12V_S0_FAN

SMC_FAN_1_CTL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_1_CTL

SMC_FAN_1_TACH

=PP3V3_S0_FAN

SMC_FAN_0_CTL

=PP3V3_S0_FAN

MIN_NECK_WIDTH=0.25MM

FAN_0_PWM_FILT

MIN_LINE_WIDTH=0.5MM

FAN_0_TACH_FILT

prefsb

051-9504

7.0.0

56 OF 143

54 OF 117

21

2

1

2

1

5

1

2

4

6

3

21

2

1

2

12

1

2

1

2

3

2

1

2

1

113

115

113

6

54

6

54

113

OUTOUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

OUT

V+

REFIN+

IN-

OUT

GND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_HEAD

QTY

DESCRIPTION

PART#

ADC23 CPU VCCIO 12V S0 (IC0I)

SCALE:3.30 A

PEAK: 0.83 A

TDP: 0.15 A

TDP: 0.83 A

353S2073 Gain: 200 V/V

Gain: 200 V/V

353S2073 Gain: 200 V/V

TDP: 0.15 A

SCALE:1.65 A

PEAK: 0.46 A

ADC8 PCH/GPU/TBT 1V05 12V S0 (IR1R)

Gain: 200 V/V

353S2073

ADC19 AP 3.3V S4 (IW0R)

SCALE:1.65 A

PEAK: 1.0 A

PEAK: 0.86 A

Current sense of AP 3.3V FET

ADC22 CPU VCCSA 12V S0 (IC0S)

SCALE:1.65 A

TDP: 0.4 A

48

116

OMIT_TABLE

20%

6.3V

402

X5R

0.22UF

C5904

U4900.H2:10MM

1%

MF-LF

4.53K

1/16W

402

DEVELOPMENT

U4900.H2:10MM

R5904

6

0.22UF

20%

6.3V

402

X5R

C5900

DEVELOPMENT

INA210

DEVELOPMENT

U5900

SC70

48

116

U4900.A8:10MM

C5914

20%

0.22UF

6.3V

402

X5R

U4900.A8:10MM

R5914

1%

402

MF-LF

1/16W

4.53K

C5910

X5R

20%

6.3V

0.22UF

402

SC70

U5910

INA210

6

48

116

U4900.B8:10MM

C5909

20%

0.22UF

6.3V

402

X5R

1%

402

MF-LF

1/16W

4.53K

U4900.B8:10MM

R5909

6

20%

0.22UF

C5905

6.3V X5R 402

U5905

INA210

SC70

48

116

U4900.A5:10MM

1/16W

R5919

4.53K

MF-LF

1%

402

6

U4900.A5:10MM

C5919

402

X5R

0.22UF

20%

6.3V

C5915

0.22UF

X5R 402

20%

6.3V

U5915

SC70

INA210

R5915

1%

0.010

1/2W

MF

1206-1

0.010

1206-1

1%

1/2W

MF

R5900

R5905

1%

0.010

1/2W

MF

1206-1

0.005

1% 1W MF

0612-2

R5910

DEVELOPMENT

C5904

CAP,0.22UF,402

1

132S0080

PRODUCTION

C5904

116S0004

RES,0,OHM,402

1

SYNC_MASTER=D8_MARK

I and V Sense 2

SYNC_DATE=04/23/2012

PP12V_S0_REG_CPU_VCCSA_SNS

ISNS_P3V3S4_AP_R

GND_SMC_AVSS

SMCISNS_P3V3S4_AP

PP3V3_S4_AP_SNS

=PP3V3_S0_SENSE

ISNSA_P3V3S4_AP_N

ISNSA_P12VS0_CPU_VCCSA_N

ISNSA_P12VS0_CPU_VCCSA_P

=PP12V_S0_REG_CPU_VCCSA_PWR

ISNSA_P3V3S4_AP_P

=PP3V3_S4_AP_PWR

ISNSA_P12VS0_P1V05_N

ISNSA_P12VS0_P1V05_P

PP12V_S0_REG_P1V05_SNS

=PP12V_S0_REG_P1V05_PWR

=PP3V3_S0_SENSE

ISNS_P12VS0_P1V05_R

ISNS_P12VS0_CPU_P1V05_R

GND_SMC_AVSS

SMCISNS_P12VS0_P1V05

SMCISNS_P12VS0_CPU_VCCSA

=PP3V3_S0_SENSE

GND_SMC_AVSS

SMCISNS_P12VS0_CPU_P1V05

GND_SMC_AVSS

=PP3V3_S0_SENSE

ISNS_P12VS0_CPU_VCCSA_R

=PP12V_S0_REG_CPU_P1V05_PWR

PP12V_S0_REG_CPU_P1V05_SNS

ISNSA_P12VS0_CPU_P1V05_P

ISNSA_P12VS0_CPU_P1V05_N

prefsb

051-9504

7.0.0

59 OF 143

55 OF 117

2

1

12

2

1

2

3

14

5

6

2

1

12

2

1

2

3

14

5

6

2

1

12

2

1

2

3

14

5

6

12

2

1

2

1

2

3

14

5

6

43

21

43

21

43

21

43

21

114

47 48 51 55

113

6

51 52

53 55

113

6

113

6

113

6

51 52

53 55

114

47 48 51 55

113

6

51 52

53 55

47 48 51 55

113

47 48 51 55

113

6

51 52

53 55

114

6

113

OUT

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

OUT

IN

OUT

NC NC

OUT

G

D

S

P-CHN

D

S

G

N-CHN

G

D

S

P-CHN

NC NC

D

S

G

N-CHN

IN

OUT

IN

OUT

NR/FB

NC

IN

EN

GND

IN

OUT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TWEETERS

NC

DMICS 1 & 2

HP AMP CNTRL

MAC SPKR AMP CNTRL

NC

SE FSINPUT= 1.22VRMS

PLACE XW6110 BENEATH U6101, BETWEEN PINS 2 & 5

WIN SPKR AMP CNTRL

DMICS SHOULD HAVE OWN GND ON CONNECTOR SHARED WITH CAMERA

PLACE TP FOR ALL HDA SIGNALS NEAR CODEC

NC NC

WOOFERS

HP AMP/LINE OUT

RESERVE SPACE FOR POSSIBLE LATCH CIRCUIT

DAC2/3 FSOUTPUTSE= 1.34VRMS

DAC2/3 FSOUTPUTDIFF= 2.67VRMS

DAC1 FSOUTPUT= 1.34VRMS

DIFF FSINPUT= 2.45VRMS

NC

PLACE C6200 AS CLOSE TO PIN 9 AS POSSIBLE

4.5V POWER SUPPLY FOR CODEC

VD MUST BE LESS THAN OR EQUAL TO VL_HD

APPLE P/N 353S2592

AUDIO CODEC

APPLE P/N 353S2456

60

101

56 58

U6101

CS4206B

CRITICAL

QFN

C6101

20%

4.7UF

402

4V

X5R-1

57

42

R6104

22

5%

402

MF-LF

1/16W

56 58

42

D6100

BAT54XV2T1

SOD-523

XW6110

SM

R6171

DEVEL_AUDIO

5%

0

402

1/16W MF-LF

C6107

10UF

CRITICAL

10V X5R-CERM 0402-1

20%

XW6100

SM

42

Q6170

DEVEL_AUDIO

DMC2400UV

CRITICAL

SOT563

R6170

DEVEL_AUDIO

5% 1/16W MF-LF 402

0

Q6170

DEVEL_AUDIO

SOT563

DMC2400UV

CRITICAL

Q6171

SOT563

CRITICAL

DMC2400UV

DEVEL_AUDIO

R6172

0

402

MF-LF

1/16W

5%

DEVEL_AUDIO

R6173

MF-LF

1/16W

402

0

5%

DEVEL_AUDIO

R6102

MF-LF

5%

1/16W

402

22

Q6171

CRITICAL

SOT563

DEVEL_AUDIO

DMC2400UV

C6123

10%

0.1UF

0402

X7R-CERM

16V

C6100

0.47UF

10V

10%

0402

X5R

C6102

0.47UF

10V X5R

0402

10%

R6101

5%

MF-LF

402

1/16W

22

C6106

0.47UF

10% 10V X5R

0402

C6115

10% 10V

0.47UF

X5R

0402

C6104

10%

0.47UF

0402

X5R

10V

R6103

100K

402

1%

MF-LF

1/16W

C6111

402-LF

6.3V

20%

CERM

2.2UF

18

101

C6112

2.2UF

402-LF

20%

CERM

6.3V

56 60 62

115

R6100

1/16W

1%

2.67K

MF-LF 402

C6109

20%

6.3V

2.2UF

402-LF

CERM

C6110

20%

6.3V CERM

2.2UF

402-LF

C6108

POLY-TANT

CASE-B2-SM

10UF

20% 16V

C6113

1UF

CRITICAL

CASE-P3-HF

TANT

10% 20V

18

101

C6114

CASE-B2-SM

POLY-TANT

16V

20%

10UF

CRITICAL

60 63

87

107

59 63

58 63

57 59 63

57 58 63

C6103

10UF

CASE-B2-SM

20% 16V POLY-TANT

18

101

C6105

1UF

10%

X5R

10V

402-1

57 58 63

R6105

5% 1/16W

0

MF-LF 402

15 18

101

56 60 62

115

6

42 56 58 59 62

56 57

115

6

42 56 58 59 62

6

63

18

101

R6120

MF-LF

0

1/16W

5%

402

XW6111

SM

C6122

402-1

X5R

10V

10%

1UF

VR6101

TPS71745

SON

CRITICAL

L6110

FERR-220-OHM

0402

L6111

FERR-220-OHM

0402

C6124

X5R 402-1

1UF

10% 10V

62 63

56 57

115

56 60 62

115

58

SYNC_DATE=06/13/2012SYNC_MASTER=D8_DAVID

AUDIO: CODEC/REGULATORS

THAILAND ALTERNATE

127S0134 127S0111

C6113

NO_TEST=TRUE

NC_AUD_MIC_INN_R

NO_TEST=TRUE

NC_AUD_MIC_INP_R

AUD_LO2_R_N

AUD_LO2_R_P

AUD_LO1_L_N

MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM

TP_AUD_HP_L

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

PP5V_AUDIO_HPAMP

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_CODEC_MICBIAS

NO_TEST=TRUE

NC_AUD_LI_P_L

AUD_MIC_INL_P

NO_TEST=TRUE

NC_AUD_LI_P_R

AUD_LO2_L_N

AUD_LO2_L_P

AUD_LO1_R_N

=PP1V5_S0_AUD_DIG

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.1MM

TP_AUD_HP_R

MIN_LINE_WIDTH=0.1MM

PP5V_AUDIO_HPAMP

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM VOLTAGE=5V

AUD_GPIO_3

GND_AUDIO_CODEC

AUD_DMIC_SDA1 TP_AUD_GPIO_1 AUD_GPIO_2

HDA_BIT_CLK

DP_INT_SPDIF_AUDIO

AUD_SPDIF_CHIP

CS4206_VREF_ADC

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_MIC_INL_N

NO_TEST=TRUE

NC_AUD_LI_COM

AUD_LO1_R_P

MIN_NECK_WIDTH=0.1MM

CS4206_HPREF

MIN_LINE_WIDTH=0.2MM

HDA_SYNC

AUD_SPDIF_OUT

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.40MM

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

4V5_NR

MIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.5MM VOLTAGE=0V

PP4V5_AUDIO_ANALOG

AUD_SENSE_A

CS4206_FLYN

AUD_CODEC_MICBIAS

HDA_SDOUT HDA_RST_L

AUD_SDI_RHDA_SDIN0

AUD_LO1_L_P

=PP3V3_S0_AUDIO

CS4206_FN

CS4206_FP

VBIAS_DAC

GND_AUDIO_HPAMP

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

AUD_DMIC_CLK

CS4206_FLYP CS4206_FLYC

MIN_NECK_WIDTH=0.15MM VOLTAGE=0V

MIN_LINE_WIDTH=0.20MM

GND_AUDIO_DMIC

VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

4V5_REG_IN

4V5_REG_EN

CS4206_VCOM

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_DMIC_SCL

Q6171_P_S

Q6171_P_G

Q6171_N_G

Q6171_N_S

Q6170_N_S

Q6170_N_G

Q6170_P_G

Q6170_P_S

=PP5V_S0_AUDIO

prefsb

051-9504

7.0.0

61 OF 143

56 OF 117

3

13

12

2

44

14

11

34

29

45

24

9

15

41

37

36

33

48

22

43 42

47

35

49

46

40

39

28

26

25

23

21

18 17

16

10

7

4

38

8 5

1

6

20

19

27

31 30 32

2

1

12

AK

2

1

2

1

2

1

34

5

1

2

1

2

6

34

5

1

2

1

2

12

1

2

6

2

1

2

1

2

1

12

2

1

2

1

2

1

2

212

1

2

212

1

2

1

2

1

2

1

2

1

2

12

2

1

2

1

3

5

2

6

4

21

2

1

56 60 62 63

6

56 60 62 63

101

56 60 62 63

101

57

112

PGND

SGND

PVSS

THM_PAD

PVDD

SVDD

BIAS

OUTL

OUTR

C1P C1N

SVDD2

INLINL+

INR-

INR+

SHDN*

IN

OUT

G

D

S

IN

OUT

G

D

S

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

NCNC

R & L CHANNELS SWAPPED TO MAKE LAYOUT MORE LOGICAL

C6252

402-1

X5R

1UF

10% 10V

C6256

402-1

10V

10%

1UF

X5R

U6250

CRITICAL

MAX97220AETE

TQFN

56 59 63

56 58 63

57 63

57 60

57 63

57 60

C6253

X5R

1UF

10V

10%

402-1

CASE-A

CRITICAL

33UF

6.3V

20%

TANT

C6261

C6263

CASE-A

20%

33UF

TANT

6.3V

CRITICAL

C6273

33UF

CRITICAL

CASE-A

TANT

6.3V

20%

CASE-A

33UF

20%

6.3V TANT

C6271

CRITICAL

R6252

MF-LF

33

5% 1/16W

402

R6251

5% 1/16W MF-LF

402

33

C6251

10V X5R-CERM 0402-1

20%

10UF

Q6251

MMBFJ201

SOT23

CRITICAL

NOSTUFF

L6250

FERR-220-OHM

0402

R6250

5%

402

MF-LF

100K

1/16W

56

57

R6253

2.0K

5% 1/16W MF-LF

402

R6254

5%

MF-LF 402

2.0K

1/16W

Q6250

MMBFJ201

SOT23

CRITICAL

NOSTUFF

R6255

5%

402

0

MF-LF

1/16W

NOSTUFF

R6256

1/16W MF-LF

402

5%

0

NOSTUFF

R6272

1/16W MF-LF

SIGNAL_MODEL=EMPTY

19.6K

1%

402

R6274

19.6K

1%

MF-LF

1/16W

402

SIGNAL_MODEL=EMPTY

19.6K

1/16W MF-LF

1%

R6264

402

SIGNAL_MODEL=EMPTY

R6262

SIGNAL_MODEL=EMPTY

402

1/16W

1%

19.6K

MF-LF

C6274

SIGNAL_MODEL=EMPTY

100PF

5% 50V CERM 0402

C6264

50V CERM

5%

SIGNAL_MODEL=EMPTY

100PF

0402

C6262

SIGNAL_MODEL=EMPTY

100PF

0402

CERM

50V

5%

C6272

5%

50V CERM 0402

100PF

SIGNAL_MODEL=EMPTY

C6250

10%

0.1UF

0402

X7R-CERM

16V

C6257

16V

X7R-CERM

0402

0.1UF

10%

C6258

10%

0.1UF

0402

X7R-CERM

16V

1%

26.1K

1/16W MF-LF

R6261

402

R6263

1%

MF-LF

1/16W

26.1K

402

26.1K

1%

1/16W

R6273

402

MF-LF

1/16W

26.1K

1%

R6271

402

C6254

0402-1

2.2UF

25V X5R-CERM

20%

C6255

0402-1

2.2UF

20% 25V X5R-CERM

SYNC_MASTER=D8_DAVID SYNC_DATE=06/13/2012

AUDIO: HEADPHONE AMP

THAILAND ALTERNATE

127S0135 127S0120

C6271

THAILAND ALTERNATE

127S0120

C6261

127S0135

THAILAND ALTERNATE

C6263

127S0135 127S0120

THAILAND ALTERNATE

C6273

127S0135 127S0120

MAX97220_C1N

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MAX97220_C1P

GND_AUDIO_HPAMP

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MAX97220_PVSS

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.2MM

MAX97220_BIAS

MIN_LINE_WIDTH=0.4MM

MAX97220_OUTL

MIN_NECK_WIDTH=0.2MM

AUD_LO1_L_C_P

AUD_LO1_L_C_N

MAX97220_INL_N

MAX97220_INL_P

AUD_LO1_R_C_N

MAX97220_INR_N

AUD_LO1_R_C_P

MAX97220_INR_P

MAX97220_PVSS

MAX97220_INR_N

MAX97220_INL_N

MAX97220_INR_P

MAX97220_SHDN_LAUD_GPIO_2

AUD_LO1_R_N

AUD_LO1_L_P

AUD_LO1_L_N

GND_AUDIO_HPAMP

HPOUT_JFET_G

PP5V_AUDIO_HPAMP

AUD_HP_PORT_REF

MAX97220_OUTR

MAX97220_INL_P

MAX97220_SHDN_L

MAX97220_OUTL_ZOBEL MAX97220_OUTR_ZOBEL

MIN_NECK_WIDTH=0.2MM

MAX97220_OUTR

MIN_LINE_WIDTH=0.4MM

GND_AUDIO_HPAMP

PP5V_AUDIO_HPAMP

MAX97220_OUTL

AUD_LO1_R_P

prefsb

051-9504

7.0.0

62 OF 143

57 OF 117

2

1

2

1

365

17

1

13

11

12

10

2

4

9

14 15

8

7

16

2

1

12

1

2

1

2

1

2

3

21

1

2

121

2

1

2

3

12

1

2

1

2

12

2

1

2

1

12

2

1

2

1

2

1

12

2

1

2

1

56 57

57

63

57

56 57

115

60

56 57

115

IN

OUT

REGEN

VREG/AVDD

PGND

THRM_PAD

PVDD

THERM

NC

AGND

EDGEINL-

INR+

GAIN

INL+

BOOTL-

INR-

MONO

OUTR-

OUTL+

BOOTR+

OUTL-

SDNR*

OUTR+

BOOTR-

BOOTL+

TEST

SDNL*

OUT OUT OUT

IN

OUT

NC NC

OUT

IN

SYM_VER-2

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

FC_HPF, WOOFERS = ~4 HZ (1.0 UF)

ONLY WOOFERS ON UNDER WINDOWS

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

MAKE LAYOUT MORE LOGICAL

OUTPUT POLARITY FLIP TO

FC_HPF, TWEETERS = ~847 HZ (4700 PF)

SPEAKER AMP GAIN = +9 DB

EDGE RATE

NC

SHOULD BE TIED TO GND

SPEAKER AMP RIN = 40K NOMINAL

APPLE P/N 353S3163

LEFT CH SPEAKER AMP

PINS 14 & 15 ARE TEST PINS AND

WOOFERS & TWEETERS ON UNDER MAC OS

AUD_RAMP_MONO NET:

LOW = STEREO OPERATION

HIGH = MONO OPERATION

+9 DB NOSTUFF 0 OHM

+18 DB 47 KOHM NOSTUFF

+12 DB NOSTUFF 47 KOHM

GAIN R6306 R6307

+15 DB NOSTUFF NOSTUFF

+24 DB 0 OHM NOSTUFF

OFF NOSTUFF 0 OHM

ON 0 OHM NOSTUFF

CONTROL R6304 R6305

C6311

4700PF

0805

50V

5%

NPO-C0G-CERM

C6308

10% 25V X5R

0402

1UF

C6309

10% 25V X5R

0402

1UF

C6317

20% 10V

X5R-CERM

402

2.2UF

58

6

59

C6300

10%

X5R

25V

805

10UF

C6301

X5R

25V

805

10%

10UF

C6316

X5R

25V

20%

603

0.22UF

58

C6315

25V

0.22UF

20%

X5R 603

C6314

X5R

25V

603

20%

0.22UF

C6313

X5R

0.22UF

25V

603

20%

C6319

NP0-C0G

SIGNAL_MODEL=EMPTY

25V

402

1000PF

5%

CRITICAL

C6320

CRITICAL

5%

1000PF

SIGNAL_MODEL=EMPTY

25V

402

NP0-C0G

C6321

1000PF

CRITICAL

SIGNAL_MODEL=EMPTY

402

5% 25V NP0-C0G

C6322

402

NP0-C0G

25V

5%

1000PF

CRITICAL

SIGNAL_MODEL=EMPTY

C6302

0.1UF

10%

402

25V X5R

C6303

25V X5R

10%

603-1

1UF

C6304

10%

X5R

0.1UF

25V

402

61 63

C6305

25V

10%

603-1

1UF

X5R

U6300

SSM3302

LFCSP

CRITICAL

R6305

5%

0

402

1/16W MF-LF

NOSTUFF

R6304

1/16W

0

402

5%

MF-LF

58

R6303

MF-LF

5%

0

402

1/16W

58

R6306

402

0

5%

MF-LF

NOSTUFF

1/16W

58

56

R6308

0

MF-LF

402

5%

1/16W

56

R6309

MF-LF

1/16W

5%

402

100K

C6318

NOSTUFF

5%

CERM 402

100PF

50V

58 59

R6301

5%

MF-LF

402

100K

1/16W

C6312

CERM

50V

100PF

402

NOSTUFF

5%

58 59

C6323

5% 25V

402

1000PF

NP0-C0G

SIGNAL_MODEL=EMPTY CRITICAL

C6324

1000PF

5% 25V

402

NP0-C0G

CRITICAL

SIGNAL_MODEL=EMPTY

58

L6308

0402

FERR-1000-OHM

L6305

CRITICAL

110-OHM-3A

DLY5ATN111SQ2

SIGNAL_MODEL=EMPTY

L6307

CRITICAL

SIGNAL_MODEL=EMPTY

110-OHM-3A

DLY5ATN111SQ2

56 57 63

56 63

L6303

0402

FERR-1000-OHM

L6302

FERR-1000-OHM

0402

L6301

0402

FERR-1000-OHM

56 63

L6300

0402

FERR-1000-OHM

58 59

58

58 59

C6306

20% 16V ELEC

CRITICAL

SM-CASE-C1-HF

220UF

C6307

CRITICAL

20% 16V

220UF

ELEC SM-CASE-C1-HF

R6307

402

MF-LF

1/16W

5%

47K

C6310

4700PF

0805

NPO-C0G-CERM

50V

5%

SYNC_DATE=06/13/2012

AUDIO: LEFT SPKR AMP

SYNC_MASTER=D8_DAVID

AUD_LAMP_LINC_N

AUD_LAMP_LINC_P

=PP3V3_S0_AUDIO

AUD_LAMP_AVDD

AUD_LAMP_GAIN

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTNR

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTNL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_LAMP_OUTPL

AUD_LAMP_BOOTRN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

AUD_LAMP_OUTPR

AUD_LAMP_OUTNR

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKRAMP_WIN_SHDN_L

AUD_LAMP_MONO

AUD_SPKRAMP_MAC_SHDN_L

AUD_LO2_L_N

AUD_LO1_L_P

AUD_LO1_L_N

AUD_LO2_L_P

AUD_LAMP_BOOTLP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BOOTLN

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.15MM

AUD_LAMP_AVDD

TP_AUD_LAMP_THERM

AUD_LAMP_EDGE

AUD_SPKRAMP_WIN_SHDN_L

AUD_GPIO_3

AUD_LAMP_MONO

AUD_CODEC_MICBIAS

AUD_SPKRAMP_MAC_SHDN_L

AUD_LAMP_GAIN

MIN_LINE_WIDTH=0.20MM

AUD_LAMP_BOOTRP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AUD_LAMP_OUTPR

AUD_LAMP_LIN_P

AUD_LAMP_LIN_N

AUD_LAMP_RINC_P

AUD_LAMP_RIN_N

AUD_LAMP_RINC_N

AUD_LAMP_RIN_P

=PP12V_S0_AUDIO_SPKRAMP

prefsb

051-9504

7.0.0

63 OF 143

58 OF 117

12

2

1

2

1

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

394038

33

23

8

31

41

37

35

34

32

24

17

13

7

10

36

12

20

21

11

6

19

3

16

27

2

30

5

22

28

26

4

29

25

1

18

15

14

9

1

2

1

2

1

2

1

2

12

1

2

1

2

1

2

1

2

1

21

43

12

43

12

21

1

2

1

2

1

2

12

63

6

42 56 59 62

58

63

63 63

63

IN

REGEN

VREG/AVDD

PGND

THRM_PAD

PVDD

THERM

NC

AGND

EDGEINL-

INR+

GAIN

INL+

BOOTL-

INR-

MONO

OUTR-

OUTL+

BOOTR+

OUTL-

SDNR*

OUTR+

BOOTR-

BOOTL+

TEST

SDNL*

IN

OUT OUT OUT

IN

NC NC

IN

OUT

IN

OUT

SYM_VER-2

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GAIN R6406 R6407

+24 DB 0 OHM NOSTUFF

+15 DB NOSTUFF NOSTUFF

+12 DB NOSTUFF 47 KOHM

+18 DB 47 KOHM NOSTUFF

+9 DB NOSTUFF 0 OHM

NC

RIGHT CH SPEAKER AMP

APPLE P/N 353S3163

SPEAKER AMP GAIN = +9 DB SPEAKER AMP RIN = 40K NOMINAL FC_HPF, TWEETERS = ~847 HZ (4700 PF)

EDGE RATE

ON 0 OHM NOSTUFF OFF NOSTUFF 0 OHM

LOW = STEREO OPERATION

PINS 14 & 15 ARE TEST PINS AND SHOULD BE TIED TO GND

CONTROL R6404 R6405

OUTPUT POLARITY FLIP TO MAKE LAYOUT MORE LOGICAL

HIGH = MONO OPERATION

AUD_RAMP_MONO NET:

ONLY WOOFERS ON UNDER WINDOWS

INPUT POLARITY FLIP OK -- TRUE DIFF INPUTS

FC_HPF, WOOFERS = ~4 HZ (1.0 UF)

WOOFERS & TWEETERS ON UNDER MAC OS

6

58

C6421

NP0-C0G

25V

5%

1000PF

402

SIGNAL_MODEL=EMPTY

CRITICAL

C6419

SIGNAL_MODEL=EMPTY

5%

1000PF

402

NP0-C0G

25V

CRITICAL

C6420

1000PF

SIGNAL_MODEL=EMPTY

25V

402

5%

NP0-C0G

CRITICAL

C6422

SIGNAL_MODEL=EMPTY

CRITICAL

402

NP0-C0G

25V

5%

1000PF

C6415

X5R

25V

0.22UF

20%

603

56 57 63

56 63

C6416

603

X5R

0.22UF

25V

20%

C6413

0.22UF

603

25V

20%

X5R

C6414

603

20% 25V

0.22UF

X5R

U6400

LFCSP

SSM3302

CRITICAL

59

C6417

2.2UF

402

X5R-CERM

10V

20%

58

C6401

X5R

10%

805

25V

10UF

R6404

5%

MF-LF 402

0

1/16W

R6405

NOSTUFF

MF-LF

1/16W

402

0

5%

59 59

R6403

1/16W

402

0

5%

MF-LF

59

R6406

1/16W

NOSTUFF

402

MF-LF

5%

0

59

C6400

10UF

805

25V X5R

10%

59

C6423

1000PF

NP0-C0G

25V

5%

402

CRITICAL

SIGNAL_MODEL=EMPTY

C6424

SIGNAL_MODEL=EMPTY

402

1000PF

CRITICAL

NP0-C0G

25V

5%

C6406

CRITICAL

16V

POLY

SM

470UF

20%

59

L6405

DLY5ATN111SQ2

110-OHM-3A

CRITICAL

SIGNAL_MODEL=EMPTY

L6407

110-OHM-3A

SIGNAL_MODEL=EMPTY

CRITICAL

DLY5ATN111SQ2

R6407

47K

402

MF-LF

1/16W

5%

C6410

NPO-C0G-CERM

4700PF

5%

50V

0805

C6411

4700PF

0805

NPO-C0G-CERM

50V

5%

C6408

1UF

0402

25V

10%

X5R

C6409

1UF

0402

X5R

25V

10%

L6400

0402

FERR-1000-OHM

C6404

25V

402

X5R

10%

0.1UF

L6401

FERR-1000-OHM

0402

L6402

0402

FERR-1000-OHM

L6403

FERR-1000-OHM

0402

C6402

0.1UF

10% 25V

402

X5R

C6403

1UF

10%

X5R

25V

603-1

C6405

1UF

X5R 603-1

10% 25V

56 63

56 57 63

61 63

AUDIO: RIGHT SPKR AMP

SYNC_MASTER=D8_DAVID SYNC_DATE=06/13/2012

AUD_RAMP_OUTPL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AUD_RAMP_RINC_N

AUD_RAMP_RIN_N

AUD_RAMP_RINC_P

AUD_RAMP_RIN_P

AUD_RAMP_LIN_P

AUD_RAMP_GAIN

AUD_RAMP_LINC_N

AUD_RAMP_LIN_N

AUD_RAMP_LINC_P

AUD_LO2_R_P

AUD_RAMP_MONO

=PP12V_S0_AUDIO_SPKRAMP

AUD_LO2_R_N

AUD_RAMP_AVDD

AUD_RAMP_MONOAUD_RAMP_EDGE

TP_AUD_RAMP_THERM

AUD_RAMP_EDGE

AUD_SPKRAMP_WIN_SHDN_L

AUD_SPKRAMP_MAC_SHDN_L

AUD_LO1_R_N

AUD_LO1_R_P

=PP3V3_S0_AUDIO

AUD_SPKR_RWFR_OUT_N

AUD_RAMP_OUTPR

AUD_SPKR_RWFR_OUT_P

AUD_RAMP_OUTNR

AUD_SPKR_RTWT_OUT_N

AUD_SPKR_RTWT_OUT_P

AUD_RAMP_BOOTLN

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_OUTPR

MIN_NECK_WIDTH=0.25MM

AUD_RAMP_OUTNR

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_BOOTLP

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_BOOTRN

MIN_NECK_WIDTH=0.15MM

AUD_RAMP_BOOTRP

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_AVDD

VOLTAGE=5V

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_RAMP_OUTNL

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM

AUD_RAMP_GAIN

prefsb

051-9504

7.0.0

64 OF 143

59 OF 117

2

1

2

1

2

1

2

1

12

394038

33

23

8

31

41

37

35

34

32

24

17

13

7

10

36

12

20

21

11

6

19

3

16

27

2

30

5

22

28

26

4

29

25

1

18

15

14

9

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

43

12

43

12

1

2

12

21

2

1

21

2

1

2

1

2

1

63 63

63

63 63

63

59

6

42 56 58 62

59

OUT

IN

BI

OUT

IN

CS

HDET

ENABLE

INT*

SDA

SCL

AGND

MICBIAS

DETECT

BYPASS

AVDD

DGND

OUT

IN

OUT

IN

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOISE ISSUE SEEN ON EARLY HEADSETS (SEE RADAR <RDAR://PROBLEM/6210118>)

R/C6750 FILTER TO ADDRESS OUT-OF-BAND

MIKEY RECEIVER CKT

WRITE: 0X72 READ: 0X73

APN 353S3231

I2C PULLUPS ON SOUTHBRIDGE PAGE

ON: INPUT LOOKS LIKE 1M PULL-UP TO 3V

HDET FUNCTION:

OFF: INPUT LOOKS LIKE 1M PULL-DOWN TO GND

APPLE P/N 518S0687

I2C ADDRESSES

MIKEY U6551 READ 0111 0011 0X73 MIKEY U6551 WRITE 0111 0010 0X72

INTENTIONALLY

OPPOSIDE

POLARITY

56 63

50

20

26

62

NOSTUFF

1/16W

5%

MF-LF

47K

402

R6561

CD3285A0

CRITICAL

MQFN-RSV

U6551

R6556

201

1/20W

MF

100K

5%

2.2K

402

5%

MF-LF

1/16W

R6550

1/16W

SIGNAL_MODEL=EMPTY

MF-LF

402

5%

1K

R6554

0.01UF

X7R

10% 25V

402

C6556

4.7UF

0402

10V

X5R-CERM

20%

CRITICAL

C6555

60

60 63

0402

L6505

FERR-1000-OHM

56 60 62 63

62

L6501

FERR-1000-OHM

0402

FERR-1000-OHM

L6500

62

60 63

FERR-1000-OHM

0402

L6510

62

402

1/16W

5%

MF-LF

R6551

0

NOSTUFF

1/16W MF-LF

SIGNAL_MODEL=EMPTY

5%

1K

R6553

402

SIGNAL_MODEL=EMPTY

F-ST-SM

54722-0224

J6500

L6507

0402

FERR-120-OHM-2.0A

CRITICAL

56 101

FERR-1000-OHM

L6502

0402

CRITICAL

L6509

FERR-120-OHM-2.0A

0402

57

50

CRITICAL

0402

L6504

FERR-120-OHM-2.0A

NOSTUFF

L6503

0402

CRITICAL

FERR-120-OHM-2.0A

50

57

60

60 63

0

MF-LF

1/16W

402

5%

R6506

5%

10K

1/20W

MF

201

R6562

100K

5%

1/20W

MF

201

R6555

L6508

0402

CRITICAL

FERR-120-OHM-2.0A

0.1UF

0402

X7R-CERM

16V

10%

C6552

0.1UF

0402

16V

10%

C6553

X7R-CERM

10%

0.1UF

0402

X7R-CERM

16V

C6560

CRITICAL

50V CERM 0402-1

27PF

5%

C6558

0402

CRITICAL

25V X7R-CERM

0.0082UF

10%

C6550

DZ6500

SOD882

ESDALC5-1BM2

DZ6501

ESDALC5-1BM2

SOD882

DZ6502

ESDALC5-1BM2

SOD882

DZ6503

ESDALC5-1BM2

DZ6504

ESDALC5-1BM2

SOD882

DZ6505

ESDALC5-1BM2

SOD882

CRITICAL

L6511

FERR-120-OHM-2.0A

0402

AUDIO: Jack, Mikey, CHS Switch

SYNC_MASTER=D8_DIRK

SYNC_DATE=06/29/2012

=PP3V3_S4_AUDIO_DIG

AUD_J1_MIC_N

AUD_J1_TIPDET1_R

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_HP_OUTR

GND_AUDIO_CODEC

=I2C_MIKEY_SDA

AUD_TIPDET1_R

MAX97220_OUTR

AUD_HP_PORT_REF

MAX97220_OUTL

AUD_SPDIF_OUT

=I2C_CHS_SCL

GND_AUDIO_CODEC

AUD_TIPDET2_R

MIN_NECK_WIDTH=0.20MM

HS_MIC_BIAS

MIN_LINE_WIDTH=0.25MM

=I2C_MIKEY_SCL

AUD_PORTD_DET_L

PP4V5_AUDIO_ANALOG

AUD_HS_MIC_N

AUD_MIC_INL_N

AUD_MIC_INL_P

HS_HDET

=PP3V3_S0_AUDIO_DIG

HS_SW_DET

HS_RX_BP

AUD_HS_MIC_RC_N

AUD_IPHS_SWITCH_EN

=I2C_CHS_SDA

AUD_TYPEDET_R

HS_MIC_BIAS

=PP3V3_S0_AUDIO_DIG

AUD_HS_MIC_P

AUD_HS_MIC_N

AUD_J1_TYPEDET_R

AUD_HS_MIC_RC_P

AUD_HS_MIC_P

GND_AUDIO_CODEC

AUD_I2C_INT_L

AUD_J1_MIC_P

AUD_J1_MIC_BIAS

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM

AUD_J1_TIPDET2_R

MIN_NECK_WIDTH=0.20MM VOLTAGE=0V

MIN_LINE_WIDTH=0.50MM

AUD_J1_GND_ANALOG

AUD_J1_HP_PORT_REF

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_HP_OUTL

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.25MM

AUD_J1_PP3V3_S0

prefsb

051-9504

7.0.0

65 OF 143

60 OF 117

12

16

13

1

4

2

3

678

12

10

11

9

15

14

5

1

2

12

1

2

1

2

1

21

12

1

2

1

3

7

5

9

11

13

15

19

17

21

2

4

6

8

14

10

12

18

16

20

22

21

12

1

2

1

2

21

12

2

1

2

1

2

1

12

21

6

63

56 60 62 63

56 62

115

6

60

63

6

60

63

56 60 62 63

63

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APPLE P/N 518S0862

SPEAKER CABLE CONNECTORS

TWEETER (FR)

WOOFER (BR)WOOFER (BL)

TWEETER (FL)

63

58 63

63

59 63

58 63

J6603

504050-0691

M-RT-SM

CRITICAL

J6602

504050-0691

M-RT-SM

CRITICAL

Audio: Spkr/Mic Conn.

SYNC_MASTER=D8_DAVID SYNC_DATE=06/13/2012

AUD_SPKR_LTWT_OUT_N

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_VENDOR_ID_L

AUD_SPKR_LWFR_OUT_N

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_RTWT_OUT_N

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_VENDOR_ID_R

AUD_SPKR_RWFR_OUT_N

AUD_SPKR_RWFR_OUT_P

prefsb

051-9504

7.0.0

66 OF 143

61 OF 117

1

2

4

3

5

6

8

7

1

2

4

3

5

6

8

7

OUT

IN

NC

IN

OUT

IN

OUT

IN

OUT

D

SG

D

SG

D

SG

D

SG

D

S

G

N-CHN

G

D

S

P-CHN

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APN:376S1032

IPHS HS Detect Debounce CKT

LI Insert Detect

(DETECT A)

NC

AUDIO CONNECTOR DETECT STATES

NC

PLACE C6700 CLOSE TO Q6700 PIN 4

PORT D DETECT (HEADPHONES)

NOTHING SPDIF HEADPHONE

PORT B DETECT(SPDIF DELEGATE)

AUD_OUTJACK_INSERT 0 1 1

AUD_TYPEDET_R 1 1 0 AUD_TIPDET*_R 0 1 1

AUD_SENSE_A 1 20K/2.67K RDIV 5.11K/2.67K RDIV

TBT/DP Audio Enable

20

5%

1/16W

402

MF-LF

0

R6745

NOSTUFF

10%

0.1UF

16V

402

X5R

C6741

56 62 63

402

100K

1/16W MF-LF

5%

R6744

0402

FERR-1000-OHM

L6743

60

56 62 63

1/16W MF-LF

402

5%

47K

R6792

10V 402

0.1UF

20% CERM

C6791

1% 1/16W

20.0K

402

MF-LF

R6796

402

5%

MF-LF

1/16W

10K

R6730

L6732

0402

FERR-1000-OHM

21 84 99

60

1%

MF-LF 402

1/16W

5.11K

R6795

1/16W

402

MF-LF

39.2K

1%

R6731

402

MF-LF

1/16W

5%

47K

R6742

100K

402

MF-LF

5%

1/16W

R6791

60

402

MF-LF

1/16W

5%

47K

R6741

62

SOT563

SSM6N15AFE

Q6797

SOT563

SSM6N15AFE

Q6796

SOT563

SSM6N15AFE

Q6741

SOT563

SSM6N15AFE

Q6741

SOT563

DMC2400UV

Q6700

DMC2400UV

SOT563

Q6700

60

402

MF-LF

1/16W

5%

270K

R6701

100K

5% 1/16W MF-LF

402

R6702

402

MF-LF

1/16W

5%

100K

R6703

SOT563

SSM6N15AFE

Q6797

47K

5%

1/16W

402

MF-LF

R6743

SSM6N15AFE

SOT563

Q6796

SSM6N15AFE

SOT563

Q6800

SOT-563-HF

NTZD3152P

Q6740

SOT-563-HF

NTZD3152P

Q6740

16V

X7R-CERM

0402

0.1UF

10%

C6700

SYNC_DATE=06/13/2012SYNC_MASTER=D8_DAVID

AUDIO: Detects/Grounding

DP_TBT_SEL

AUD_LI_TIPDET

AUD_SENSE_A

AUD_TYPEDET_OD_INV

AUD_OUTJACK_INSERT

GND_AUDIO_CODEC

AUD_TYPEDET_OD

PP4V5_AUDIO_ANALOG

AUD_PORTD_DET_L

AUD_OUTJACK_INSERT_L

AUD_TIPDET1_R

AUD_TIPDET2_R

AUD_TIPDET_INV

AUD_PORTA_DET_L

GND_AUDIO_CODEC

AUD_PORTB_DET_L

AUD_J1_DET_RC

AUD_TYPEDET_R

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_IP_PERIPHERAL_DET

AUD_SENSE_A

AUD_IP_PERPH_DET_DB

AUD_J1_DET_RC

AUD_IP_PERPH_DET_R

GND_AUDIO_CODEC

prefsb

051-9504

7.0.0

67 OF 143

62 OF 117

12

2

1

2

21

12

2

1

2

1

2

21

1

2

1

2

1

2

1

2

1

2

3

4

5

3

4

5

3

4

5

6

1

2

1

2

6

34

5

1

2

1

2

1

2

6

1

2

1

2

6

1

2

3

4

5

1

6

2

4

3

5

2

1

56 60 62 63

56 60 62

115

56 60 62

115

56 60 62 63

6

42 56 58 59

56 60 62 63

OUT

IN IN

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

CIRCUIT THEORY OF OPERATION AVAILABLE IN <RDAR://PROBLEM/9776522>

PORT C DETECT(SPEAKER MISMATCH)

CODEC OUTPUT SIGNAL PATHS

FUNCTION

PRIMARY SPKRS (WFR) SECONDARY SPKRS (TWT)

PIN COMPLEX

0X0E (14,LEFT & RIGHT)

0x10 (16)

PIN COMPLEX

0X0A (DET D)GPIO_2

MAC SHDN

0X03 (3)

DET ASSIGNMENT

0X09 (DET A)

DET ASSIGNMENT

PANTHER POINT GPIO 3 (PERIPH DET)

0X0D (DET B)

0X0D (13,V22,B,LEFT)

CONVERTER

ENABLE/CONTROL

0X0C (DET C)

PANTHER POINT GPIO 5 (RCVR INT)

N/A

ENABLE/CONTROL

N/A

DET ASSIGNMENT

CONVERTER

0X0B (11)

WIN SHDN

0X12 (18,LEFT)

0X06 (6)

N/A

MICBIAS

0X0A (10,D)

PIN COMPLEX

PANTHER POINT GPIO 16

GPIO_2

N/A

MICBIAS

N/A N/A

0X05 (5) 0X06 (6)

0x0F (15)

0X0A (10,V24)

0X03 (3)

GPIO_3

0X04 (4)

CODEC INPUT SIGNAL PATHS

0X08 (8)

0X03 (3)0X03 (3)

SPDIF OUT

HP/LINE OUT

MULTIPLE SPKR VENDORS

FUNCTION

N/A

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

N/A

FUNCTION

INTERNAL MIC ARRAY

SPDIF IN

N/A

CONVERTER

EXTERNAL MIC

OTHER DETECT

0X07 (7)

N/A

0X04 (4)

VOLUME/MUTE

N/A

NC

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I254

I255

I263

I264

100K

1% 1/16W MF-LF

402

SPEAKERID

R6812

SPEAKERID

100K

1%

402

1/16W MF-LF

R6813

MF-LF

402

100K

1%

SPEAKERID

1/16W

R6810

402

SPEAKERID

MF-LF

1/16W

100K

1%

R6811

1%

402

MF-LF

SPEAKERID

100K

1/16W

R6816

56 62

MAX9119EXK-T

CRITICAL

SC70-5

SPEAKERID

U6800

61 61

SPEAKERID

0402

FERR-1000-OHM

L6802

402

MF-LF

33

1/16W

5%

SPEAKERID

R6820

SPEAKERID

MF-LF

402

10K

1/16W

1%

R6894

10%

2.2UF

805

X7R-CERM

16V

SPEAKERID

C6811

402

MF-LF

1/16W

1%

75K

SPEAKERID

R6815

1%

37.4K

402

1/16W MF-LF

SPEAKERID

R6817

402

MF-LF

1/16W

1%

226K

SPEAKERID

R6814

I324

I325

I326

I327

I328

I329

SOT563

SSM6N15AFE

Q6800

SPEAKERID

16V X7R-CERM 0402

0.1UF

10%

C6810

*

Y

10 MM

0.2 MM

0.25 MM

0.6 MM

0.2 MM

SPKROUTDIFF

AUDIODIFF

Y

*

0.1 MM

10 MM

0.1 MM

0.1 MM0.1 MM

SPKROUTDIFF

*

SPKROUTDIFF

?

*

0.1 MM

AUDIO

0.2 MM

SPKROUT

*

?

AUDIODIFF

*

AUDIODIFF

SYNC_MASTER=D8_DAVID SYNC_DATE=06/13/2012

AUDIO: Speaker ID

AUD_PORTC_DET_L

GND_AUDIO_CODEC

AUD_SPKR_VENDOR_ID_L

MAX9119_NEG

=PP5V_S0_AUDIO

SPKR_MATCH_DRV_R

AUD_SENSE_A

SPKR_MATCH_DRV

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_MIC_INL_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_HS_MIC_RC_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_HS_MIC_N

AUDIO

AUDIO_DIFFPAIR

AUD_HS_MIC_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_HS_MIC_RC_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_J1_MIC_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_J1_MIC_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_MIC_INL_N

AUD_SPKR_LWFR_OUT_N

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

AUD_SPKR_RTWT_OUT_N

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

SPKROUT

AUD_SPKR_LTWT_OUT_P

SPKROUTDIFF

AUD_SPKR_LTWT_OUT_N

SPKROUT_DIFFPAIR

SPKROUT

SPKROUTDIFF

AUD_SPKR_LWFR_OUT_P

SPKROUT

SPKROUTDIFF

SPKROUT_DIFFPAIR

SPKROUT

AUD_SPKR_RTWT_OUT_P

SPKROUTDIFF

SPKROUT_DIFFPAIR

SPKROUT

AUD_SPKR_RWFR_OUT_N

SPKROUTDIFF

SPKROUT_DIFFPAIR

SPKROUT

SPKROUTDIFF

AUD_SPKR_RWFR_OUT_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

MAX97220_INR_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

MAX97220_INL_P

AUDIO

AUD_LAMP_LIN_N

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LAMP_RIN_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LAMP_RINC_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LAMP_RINC_P

AUDIODIFF

AUDIO

AUD_LAMP_LINC_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_RIN_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_RAMP_RIN_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LIN_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LIN_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_RINC_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

MAX97220_INR_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LINC_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_LINC_N

AUDIO

AUD_LAMP_RIN_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO2_R_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO2_R_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO2_L_N

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO2_L_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_C_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_L_N

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_L_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_C_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_R_N

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_LO1_R_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_LO1_L_C_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO1_L_C_P

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

AUD_RAMP_RINC_P

AUDIO

AUD_LAMP_LIN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_LAMP_LINC_N

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUDIODIFF

MAX97220_INL_N

=PP5V_S0_AUDIO

MAX9119_POS

MAX9119_OUT

=PP5V_S0_AUDIO

AUD_SPKR_VENDOR_ID_R

prefsb

051-9504

7.0.0

68 OF 143

63 OF 117

1

2

1

2

1

2

1

2

12

3

1

2

4

5

21

12

1

2

1

2

12

1

2

6

1

2

1

56 60 62

6

56 63

56 60

60

56 60

58 61

59 61

58 61

59 61

57

58

59

57

59

58

56 59

56 58

57

56 57 58

57

56 57 59

57

59

58

57

6

56 63

6

56 63

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

D

GS

OUT

IN

OUT

IN

OUT

IN

OUT

IN

08

Y1

Y2

GND

B2

VCC

A1 B1 A2

IN

OUT

IN

08

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RADR://11753451 ADD PP3V3_S4 TO PWR SEQUENCE

GPU Sequencing

S3 1V5 Reg (S0/S3) Enable

S0 Platform Parallel Sequence Enable

Parallel Enable PGOOD combinator

S0 5V and TBT Enable

S4 3V3 Enable

S4 USB Enable

CPU/PCH Sequencing

CPUCORE

S5 3V3 Soft Enable

S0 12V Enable

0.0

Rail definitions

PCH/GPU/TBT 1V05

8. All rails must be powered off within 10 ms from first rail powering off

7. The ramp time for any rail must be more than 40 uS

5. PEX_VDD (our GPU_1V05) after FBVDDQ

4. FBVDDQ (our GPU_VDDQ) after NVVDD

2. IFPA/B_IOVDD (1.8 V) with or after 3V3_S0 (unused in our implementation)

2. SMC guarantees timing on PCH DPWROK and PWROK

1. No hard specification on platform rails

Notes on sequencing requirements

3. CPU VDDQ must ramp before MEMVTT and vice versa on power down. It has no relationship to any other rails.

VccSA, VDDQ, VccA (1.8 V), VccIO (VccSA, VccA, and VccIO must ramp within 50 ms of each other)

S4 5V Enable

6. IFPC/D/E/F_IOVDD (1.05V) wit or after PEX_VDD

1. VDD33 (our 3V3_S0)

3. NVVDD (our GPUCORE) after IFPA/B_IOVDD

Intel:

NVIDIA GFX:

CPU 1V05

GPU FBVDDQ

3V3

tau (RC delay, ms):

if there is no processor.

Note:

Halt power sequencing at S5

stuff R6903 to circumvent

0.0

1V8

1V5

Expected 3.9V +/- 0.4V EN signal

or short gate to source.

VCCSA

MEMVTT

GPUCORE

All processor non-Core and non-Graphics (5 V, 3.3 V, 1.8 V 1.5 V, PCH Core/PLL/VRM)

Platform: Uncore:

PLACE_NEAR=U7600.12:15MM

1/16W

402

MF-LF

R6990

5%

68K

PLACE_NEAR=U7600.12:15MM

1/16W MF-LF

33K

5%

402

R6991

71 74

115

64 74

114

402

CERM-X5R

NOSTUFF

6.3V

0.47UF

10%

C6910

402

10%

6.3V

C6911

CERM-X5R

0.47UF

NOSTUFF

1/16W

402

33K

5%

R6902

MF-LF

6.3V

CERM-X5R

10%

402

0.47UF

C6901

NOSTUFF

65 74

115

15 19 47

115

72

115

R6920

402

1/16W MF-LF

5%

0

64 71

115

45 46

115

10%

6.3V CERM-X5R

0.47UF

NOSTUFF

402

C6920

MF-LF

33

1/16W

402

5%

R6910 R6911

5% 1/16W

402

33

MF-LF

NOSTUFF

71

115

92

110

74

114

5

72

115

5

15 19 28 40 47 48 115

66

114

R6937

402

1/16W MF-LF

5%

0

65 70

115

33

1/16W MF-LF

402

R6930

5%

74

114

15 19 47

115

11 99

1/16W MF-LF

10K

402

5%

R6901R6900

5%

MF-LF

1/16W

402

100K

86 88

1/16W

5%

402

MF-LF

0

R6940

64 74

115

72

115

5%

MF-LF

402

R6932

0

1/16W

64 74

115

74

114

MF-LF

R6933

5%

0

402

1/16W

72

115

95

115

5%

402

1/16W MF-LF

0

R6934

64

115

70

115

402

0

5%

MF-LF

1/16W

R6936

64 65

115

SSM3K15AMFVAPE

VESM

Q6900

PLACE_SIDE=BOTTOM

95

115

402

R6941

0

5%

MF-LF

1/16W

5

92 110

74

114

R6931

402

0

5%

MF-LF

1/16W

74

115

72

114

28

114

NOSTUFF

402

MF-LF

10K

5%

1/16W

R6903

1/16W

402

33

5%

MF-LF

R6929

69

115

MF-LF

402

5%

1/16W

0

R6935

64 74

114

402

1/16W MF-LF

5%

0

R6919

64 71

115

C6919

6.3V

0.47UF

CERM-X5R 402

10%

NOSTUFF

74LVC2G08GT

SOT833

4

8

U6921

5

95

115

28 74

115

5

95

115

5

69

115

C6934

CERM-X5R

10%

6.3V

0.47UF

402

NOSTUFF

6.3V

10%

NOSTUFF

CERM-X5R 402

0.47UF

C6935

402

MF-LF

0

1/16W

5%

R6922

28

115

402

1/16W MF-LF

0

5%

R6923

27 35 74

115

64 71

115

1/16W

5%

0

MF-LF

R6921

402

NOSTUFF

PLACE_SIDE=BOTTOM

U6900

TSSOP-HF

14

7

74LVC08

PLACE_SIDE=BOTTOM

U6900

TSSOP-HF

14

7

74LVC08

PLACE_SIDE=BOTTOM

74LVC08

TSSOP-HF

U6900

7

14

PLACE_SIDE=BOTTOM

U6900

TSSOP-HF

14

7

74LVC08

X7R-CERM

16V

10%

0402

C6900

0.1UF

10% 16V X7R-CERM

C6921

0402

SYNC_DATE=04/23/2012

SYNC_MASTER=D8_MARK

PM Regulator Enables

=PP3V3_S5_PWRCTL

PM_PGOOD_P3V3_S4_FET

PM_EN_REG_GPUCORE_S0

PM_EN_FET_P5V_S0

MAKE_BASE=TRUE

TBT_S0_EN

MAKE_BASE=TRUE

PM_EN_LDO_DDRVTT_S0

PM_EN_FET_VDDQ_S0

MAKE_BASE=TRUE

PM_EN_REG_CPU_P1V05_S0

PM_PGOOD_FBVDDQ_VDDQ_S0

PM_PGOOD_FET_P3V3_S0

=TBT_S0_EN

PM_PGOOD_REG_ALL_P1V05_S0

PM_EN_REG_P3V3_S5

PM_PGOOD_REG_P5V_S4

PM_EN_USB_PWR

CPU_SKTOCC_L

PM_EN_FET_P3V3_S4

PM_EN_REG_FBVDDQ_S0

=PP3V3_S5_PWRCTL

PM_PGOOD_REG_P1V8_S0

PM_EN_REG_VCCSA_S0

PM_EN_REG_CPUCORE_S0

PM_PGOOD_REG_VCCSA_S0

PM_PGOOD_REG_GPUCORE_S0

PM_PGOOD_FET_P3V3_S0

PM_EN_FET_P3V3_S0

PM_PGOOD_REG_FBVDDQ_S0 PM_PGOOD_FET_VDDQ_S0

MEMVTT_EN

PM_PGOOD_FET_P5V_S0

PM_PGOOD_REG_P1V05_S0 PM_PGOOD_REG_CPU_P1V05_S0

PM_EN_REG_P1V05_S0

=PP12V_S5_PWRCTL

PM_EN_FET_P3V3_S4

PM_PGOOD_REG_P5V_S4

PM_SLP_S5_L

CPU_SKTOCC

PM_EN_S4

PM_SLP_S4_L

=PP3V3_S5_PWRCTL

PM_EN_REG_VDDQ_S3

PM_SLP_S3_L

PM_PGOOD_REG_VDDQ_S3

PM_EN_FET_P12V_S0

=PP3V3_S5_PWRCTL

PU_U6900

PGOOD_P12V_S0

=PP3V3_S5_PWRCTL

PM_EN_S0

PM_PGOOD_REG_ALL_P1V05_S0

PM_PGOOD_FBVDDQ_VDDQ_S0

PM_PGOOD_REG_ALL_P1V05_S0_R

PM_EN_REG_P1V8_S0

PM_PGOOD_P5VRP3V3_S4

PM_PGOOD_REG_P5V_S4

PM_EN_REG_P5V_S4

prefsb

051-9504

7.0.0

69 OF 143

64 OF 117

1

2

1

2

1

2

1

2

1

12

2

1

2

1

2

12

1

2

1

2

12

1

2

3

12

1

2

12

2

1

3

71

2

5

6

2

1

2

1

12

8

9

10

3

2

1

11

12

13

6

5

4

2

1

2

1

6

64 65

6

64 65

117

6

64 65

6

65 74

112

115

6

64 65

6

64 65

116

6

64 65

115

64 65

115

64

115

IN

OUT

IN

OUT

IN

OUT

IN

OUT

G

D

S

G

D

S

V-

V+

08

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R7020 determination: rdar://10961528

Platform Power Good

RSMRST# is asserted when power good from regulator is de-asserted in the

The SMC guarantees proper assertion and de-assertion of RSMRST# for

Power off or loss of AC:

Asserted at least 10 ms after all suspend well power is valid

First

Second

Need AND Gate to deassert PM_PCH_PWROK to PCH when unexpected power loss happensradar://11043352

To PCH

Third

SMC_S5_PWRGD_VIN input is above comparator input level of 1.5 V.

to allow PCH to switch suspend well to battery without excessive loading

The iMac K70K72 designs does not support Deep Sx modes so both DPWROK and

normal operation via PM_DSW_PWRGD.

event AC is lost. Power good de-assertion should happen quickly enough

Secondary method:

To PCH

From SMC

Note:

Requirements:

Power on:

normal operation.

Primary method:

RSMRST# signals are shorted together

Intel Doc# 29517 Maho Bay PDG, Section 22.13 Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8

Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V

SMC asserts RSMRST# (PM_DSW_PWRGD) when SMC_S5_PWRGD_VIN input drops from

SMC de-asserts RSMRST# (PM_DSW_PWRGD) when S5_PWRGD input is asserted and

To SMC

From SMC

To PCH

to meet Intel spec.

To PCH

1.8 V to 1.5 V (as implemented) when 12 V S5 rail drops to 10 V.

Resume Reset

The SMC guarantees proper assertion and de-assertion of RSMRST# for

(9V/9.58V; 580MV HYSTERESIS)

PCH Power Goods

PGOOD COMPARATORS FOR PP12V_S0

To SMC, for 99ms delay

Derive SMC ALL_SYS_PWRGD

The end of the power sequence for S0 rails except CPU CORE.

5

25 66

115

38 47 48

116

R7021

5%

MF-LF

0

1/16W

402

110

MF-LF

5%

1/16W

402

R7020

0

MF-LF

1/16W

5%

402

NOSTUFF

R7023

R7022

0

1/16W

5%

MF-LF

NOSTUFF

402

19 48

115

47

116

65 71

115

47 48 65

114

65 71

115

47

R7030

MF-LF

1/16W

5%

68K

402

R7031

402

MF-LF

5% 1/16W

33K

19 65

115

47 48 65

114

R7032

RSMRST:SMC

MF-LF

5%

402

0

1/16W

5

47 65

112

19 65

115

R7035

MF-LF

1/16W

402

0

5%

RSMRST:GATE

64

115

64 70

115

15 19 26 35 43 89

115

5%

MF-LF

1/16W

1K

402

R7024

19

115

1/16W

402

5%

MF-LF

10K

R7086

SOT-363

Q7080

2N7002DW-X-G

R7084

402

10K

1/16W

5%

MF-LF

2N7002DW-X-G

Q7080

SOT-363

1%

402

MF-LF

1/16W

49.9K

R7083

603

16V

20%

0.1UF

CERM

C7080

R7081

402

1%

MF-LF

100K

1/16W

1%

MF-LF

402

2.0K

1/16W

R7082

LM397

U7080

CRITICAL

SOT23-5-HF

R7087

402

MF-LF

5%

1/16W

0

R7080

33.2K

1% 1/16W MF-LF 402

74LVC08

U7000

PLACE_SIDE=BOTTOM

7

14

TSSOP-HF

PLACE_SIDE=BOTTOM

TSSOP-HF

14

7

74LVC08

U7000

TSSOP-HF

14

7

PLACE_SIDE=BOTTOM

74LVC08

U7000

74LVC08

U7000

7

14

TSSOP-HF

PLACE_SIDE=BOTTOM

10%

X7R-CERM

16V

0.1UF

C7000

0402

0.1UF

10%

0402

C7021

16V X7R-CERM

SYNC_MASTER=D8_MARK

SYNC_DATE=04/23/2012

PM Power Good

PM_PCH_PWROK

=PP3V3_S5_PWRCTL

9V_COMP_REF

12V_COMP_REF

=PP3V3_S5_PWRCTL

=PP3V3_S4_PWRCTL

=PP12V_S5_PWRCTL

PGOOD_P12V_S0

PGOOD_P12V_S0_R

PM_PCH_SYS_PWROK

PGOOD_12V_S0_G1

=PP12V_S5_PWRCTL

=PP12V_S0_PWRCTL

SMC_S5_PWRGD_VIN

PM_RSMRST_PCH_L

=PP12V_S5_PWRCTL

PM_RSMRST_PCH_L

S5_PWRGD

PM_DSW_PWRGD

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

PM_PCH_APWROK

PGOOD_12V_S0_G2

PM_DSW_PWRGD

PM_PGOOD_REG_P3V3_S5

PM_RSMRST_PCH_L_R

=PP3V3_S5_PWRCTL

PM_PGOOD_REG_ALL_P1V05_S0

PM_PGOOD_REG_VCCSA_S0

ALL_SYS_PWRGD

PM_PGOOD_REG_CPUCORE_S0

SYS_PWROK_R

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD

PM_PCH_PWROK_APWROK

=PP3V3_S5_PWRCTL

SMC_DELAYED_PWRGD

prefsb

051-9504

7.0.0

70 OF 143

65 OF 117

12

1

2

12

1

2

1

2

12

1

2

3

5

4

1

2

6

2

1

2

1

2

12

1

2

3

4

5

12

1

2

6

5

4

11

12

13

8

9

10

3

2

1

2

1

2

1

6

64 65

6

64 65

6

72 74

6

64 65 74

64 74

115

6

64 65 74

6

64 65 74

115

6

64 65

117

6

64 65

5

47 65

112

6

64

65

VR_RDYS

IMONS

FS_DRP

VCC

ISEN1+

PWM1

ISEN1-

PWM2 ISEN2+ ISEN2-

PWM3

ISEN3-

ISEN3+

TMS

ISEN4-

ISEN4+

PWM4

FSS_DRPS

EN_VTT

RSET

VSENS

RAMP_ADJ

FBS

RGNDS

VR_RDY

COMPS

SVCLK

SVDATA

SVALERT*

VSEN

FB

RGND

PSICOMP

COMP

IMON

VR_HOT* TM

THRM

ISENS-

ISENS+

PWMS

HFCOMPS/DVCS

EN_PWR

ADDR_IMAXS_TMAX

NPSI_DE_IMAX

BT_FDVID_TCOMP

BTS_DES_TCOMPS

SICI

HFCOMP

PAD

IN

OUT

IN

BI

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

To Core VSense

To Core HF comp

Max peak current:

AXG voltage sense input

AXG sense from CPU

12.7 A (BUDGET)

CPU AXG S0 Regulator

30.0 A (BUDGET)

290 kHz

OC trip point:

Max avg current:

To sense amps

OC trip point:

To AXG HF comp

(core comp out)

63 A (BUDGET) 110 A (BUDGET)

Straps 1

Switching freq:

(pu 1)

(core hf comp)

(straps 1)

(axg hf comp)

(core fb in)

(pgood)

(pu 2)

(axg fb in)

(pgood)

290 kHz

To XDP

(pu 2)

(straps 2)

(axg imon out)

(straps 1)

Straps 2

(core vsen in)

Max avg current: Max peak current:

Switching freq:

To Core feedback

? A (nom)/? A (min)

Pull-ups 2

To Core PSI comp

(vr hot out)

(core imon out)

VRHot to ProcHot

CHANGES TO THE CPU CONTROLLER D8 VR_HOT RDAR://11093493

(pu 1)

(core psi comp)

To AXG VSense

? A (nom)/? A (min)

(axg vsen in)

Pull-ups 1

Core sense from CPU

(straps 1)

(axg comp out)

Core temp measurement

AXG temp measurement

(straps 2)

To AXG feedback

AXG compensation and feedback

Core voltage sense input

Power goods

Core compensation and feedback

To AXG voltage sense

CPU Core S0 Regulator

AXG IMON output

Core IMON output

To Core voltage sense

To sense amps

U7100

QFN

ISL6364

68

105

13

105

MF-LF

1/16W

0

R7175

5%

402

MF-LF

5%

0

1/16W

R7170

OMIT

L7330.2:51MM

XW7172

SM

402

1K

MF-LF

1/16W

R7172

5%

SIGNAL_MODEL=EMPTY

R7176

402

10

MF-LF

5%

1/16W

MF-LF

R7171

SIGNAL_MODEL=EMPTY

402

10

1/16W

5%

R7177

MF-LF

1/16W

402

1K

5%

R7163

MF-LF

1% 1/16W

402

249

R7162

1/16W

301

402

MF-LF

1%

402

MF-LF

1/16W

10

R7165

OMIT

SM

XW7100

U7100.49:9MM

RT7190

0603

6.8K

1/16W

R7190

5%

MF-LF

402

1K

R7192

1K

5%

402

MF-LF

1/16W

0603

6.8K

RT7192

R7100

MF-LF

5% 1/8W

805

2.2

1%

255K

MF

1/20W

201

R7102

1%

953K

201

1/20W MF

R7103

13 66

105

13 66

105

13 66

105

R7109

MF-LF

402

0

5%

1/16W

R7104

1%

MF 201

1/20W

255K

1% 1/16W MF-LF

R7195

402

2.74K

6.65K

1/16W

1%

MF-LF

R7196

402

110

1/16W

R7119

402

MF-LF

1%

NOSTUFF

R7118

90.9

1/16W MF-LF 402

1%

MF-LF

54.9

1%

402

1/16W

R7117

R7193

5%

402

MF-LF

1/16W

0

11 47 48 99

51 66

105

51 66

105

R7198

1/16W

1K

5%

MF-LF 402

R7199

10K

MF-LF

1/16W

5%

402

5

25 65

115

402

0

5%

MF-LF

1/16W

R7125

0

MF-LF

R7126

5%

1/16W

402

MF-LF

1/16W

R7127

0

5%

402

MF-LF

0

5%

R7128

1/16W

68

105

68

105

402

R7129

MF-LF

1/16W

0

5%

68 105

201

953K

1/20W MF

1%

R7101

201

MF

16.5K

1/20W

1%

R7105

201

26.1K

R7106

MF

1% 1/20W

1/16W

1%

1.18M

402

R7114

MF

CERM

50V

0402

5%

39PF

C7161

CERM 0402

82PF

50V

5%

C7131

0402

10% 50V X7R-CERM

390PF

C7133 C7136

X7R-CERM

10% 50V

390PF

0402

0.01UF

20% 16V X7R-CERM 0402

C7135

10%

CERM

50V

0402

C7130

0.0012UF

C7141

0.0012UF

10%

CERM

50V

0402

0.0012UF

0402

50V

10%

CERM

C7146

C7171

0.0012UF

10%

CERM

50V

0402

C7176

CERM

50V

10%

0402

0.0012UF

14.0K

402

MF-LF

1/16W

R7116

1%

0402

C7165

16V X7R-CERM

20%

0.01UF

NOSTUFF

10%

CERM

50V

C7148

0.0012UF

0402

NOSTUFF

C7178

10%

CERM

50V

0402

NOSTUFF

0.0012UF

0402

X7R-CERM

50V

10%

C7134

0.0033UF

11.8K

R7160

402

MF-LF

1% 1/16W

1%

1/16W

402

R7166

3.09K

MF-LF

1% 1/20W

24.3K

201

R7107

MF

1/20W

201

17.4K

R7108

1%

MF

X7R-CERM 0402

0.1UF

C7117

10% 16V

0402

X7R-CERM

C7150

0.1UF

10% 16V 16V

10%

0.1UF

0402

X7R-CERM

C7190

C7192

X7R-CERM 0402

0.1UF

10% 16V

0.1UF

0402

X7R-CERM

C7195

68 105

X6S

25V

10%

0805

C7100

10UF

R7131

402

MF-LF

1/16W

2.43K

1%

R7161

1%

2.43K

1/16W MF-LF 402

C7160

0.0018UF

0402

X7R-CERM

50V

10%

402

R7181

15.4K

1/16W MF-LF

1%

R7151

1%

MF-LF

13.7K

1/16W

402

215K

R7136

402

MF-LF

1/16W

1%

67 105

5%

MF-LF 402

1/16W

NOSTUFF

0

R7120

67

105

NOSTUFF

0

MF-LF

1/16W

R7121

5%

402 402

MF-LF

NOSTUFF

5% 1/16W

R7122

00

MF-LF

NOSTUFF

5% 1/16W

R7123

402

0

5% 1/16W

402

R7124

NOSTUFF

MF-LF

64

114

67

105

0

MF 201

R7112

5% 1/20W

NOSTUFF

0

5%

MF 201

R7110

NOSTUFF

1/20W

1%

MF

1/20W

201

105K

R7111

124K

1%

MF

1/20W

201

R7113

67

105

5%

10K

MF

1/20W

201

NOSTUFF

R7115

CERM-X7R

0.082UF

C7180

16V

10%

402

MF-LF

1/16W

R7180

90.9

1%

R7182

5%

402

MF-LF

100K

1/16W

NOSTUFF

R7152

1/16W MF-LF

402

5%

100K

NOSTUFF

R7150

0

MF-LF

402

5%

1/16W

67

105

R7197

5%

MF-LF 402

1/16W

100K

67

105

R7130

MF-LF 402

1% 1/16W

4.99K

R7133

402

1/16W

1%

249

MF-LF

1/16W MF-LF

R7132

499

1%

402

R7134

1/16W MF-LF

402

100

1%

R7135

10

MF-LF

1/16W

402

1%

67

105

1/16W

R7140

0

5%

402

MF-LF

R7141

402

5%

MF-LF

10

1/16W

SIGNAL_MODEL=EMPTY

5% 1/16W MF-LF

R7142

402

1K

SM

OMIT

XW7142

R7230.2:71MM

13

105

68

105

402

R7146

10

5% 1/16W MF-LF

SIGNAL_MODEL=EMPTY

5%

0

1/16W MF-LF

402

R7145

13

105

402

5%

1K

1/16W MF-LF

R7147

XW7142.2:2MM

SM

XW7147

OMIT

XW7172.2:5MM

XW7177

SM

OMIT

13

105

SYNC_DATE=02/28/2012

VReg CPU Core/AXG Cntl

SYNC_MASTER=D8_MLB

AGND_CPU

CPUCORE_IMON_R

REG_VCC_U7100

SNS_AXG_XW_N

AGND_CPU

REG_CPUAXG_VSEN

AGND_CPU

CPUAXG_IMON_R

=PPVAXG_S0_CPU

CPUAXG_COMP_RC

REG_CPUAXG_COMP

CPUAXG_FB_R_2

REG_CPUAXG_FB

CPUAXG_FB_R_1

CPUCORE_FB_R_1

=PPVCCIO_S0_CPU

REG_VCC_U7100REG_VCC_U7100

AGND_CPU

REG_CPUAXG_TM

REG_CPUCORE_TM

AGND_CPU

REG_CPUAXG_RGND

REG_CPUAXG_PGOOD

REG_CPUCORE_SW_FREQ

REG_CPUCORE_IMON

CPU_VIDALERT_L

REG_VCC_U7100

REG_CPUAXG_VSEN

REG_VCC_U7100

REG_PWM_CPUAXG_R

REG_PWM_CPUCORE_2_R

REG_CPUCORE_NPSI

CPUCORE_FB_R_2

AGND_CPU

CPU_VIDSOUT

CPU_VIDSCLK

REG_CPUCORE_FB

REG_CPUCORE_VSEN

CPU_VIDALERT_L

REG_CPUAXG_TCOMP REG_CPUCORE_SUTH

REG_CPUCORE_FDVID

AGND_CPU

PP12V_S0_CPUCORE_FLT

CPUCORE_EN_PWR_R

CPUAXG_FB_RC

REG_CPUAXG_HFCOMP

CPUCORE_PSICOMP_RC

REG_ISENAXG_PR

REG_PWM_CPUCORE_3_R

REG_PWM_CPUCORE_1_R

REG_PWM_CPUAXG

REG_PWM_CPUCORE_4_R

REG_CPUAXG_IMON

REG_ISENCORE_2_NR

REG_ISENCORE_3_P

REG_ISENCORE_4_P

REG_CPUCORE_RGND

REG_CPUCORE_VSEN

AGND_CPU

REG_CPUAXG_IMON

AGND_CPU

SNS_AXG_R_N

SNS_CORE_R_N

CPUCORE_COMP_RC

REG_CPUCORE_RGND

REG_CPUCORE_SW_FREQ REG_CPUCORE_RAMPADJ

REG_CPUCORE_RAMPADJ

REG_CPUAXG_SW_FREQ

REG_ISENCORE_4_NR

REG_ISENCORE_3_NR

REG_ISENCORE_2_P

CPU_VIDSOUT

CPU_VIDSCLK

REG_CPUCORE_SUTH

REG_CPUAXG_TCOMP

REG_CPUCORE_PGOOD

REG_CPUAXG_COMP

REG_CPUAXG_FB

REG_CPUCORE_IAUTO

REG_CPUCORE_PSICOMP

REG_CPUAXG_TM

REG_CPUAXG_VSEN

REG_CPUAXG_SW_FREQ

SNS_CPU_VCORE_N

SNS_AXG_XW_P

REG_ISENCORE_1_NR

REG_PWM_CPUCORE_3

REG_PWM_CPUCORE_4

REG_CPUCORE_PGOOD

=PP3V3_S0_VRD

REG_CPUAXG_PGOOD

=PP3V3_S0_VRD

SNS_CORE_XW_N

SNS_CORE_R_P

REG_CPUCORE_VRHOT_L

REG_ISENCORE_1_P

SNS_AXG_R_P

SNS_CPU_VAXG_N

REG_CPUAXG_RGND

REG_CPUAXG_HFCOMP

REG_CPUCORE_TM

REG_CPUCORE_IMON

REG_CPUCORE_HFCOMP

REG_CPUCORE_FDVID

PP12V_S0_CPUCORE_FLT

AGND_CPU

REG_CPUCORE_NPSI

REG_VCC_U7100

REG_PWM_CPUCORE_2

REG_ISENAXG_NR

REG_PWM_CPUCORE_1

CPU_PROCHOT_L

AGND_CPU

=PP5V_S0_REG_CPUCORE

SNS_CORE_XW_P

CPUCORE_FB_RC

REG_CPUCORE_PSICOMP

MAKE_BASE=TRUE

PM_PGOOD_REG_CPUCORE_S0

SNS_CPU_VCORE_P

REG_CPUCORE_COMP

REG_CPUCORE_VRHOT_L

REG_CPUCORE_RSET

REG_CPUCORE_EN_PWR

PM_EN_REG_CPUCORE_S0

REG_CPUCORE_COMP

REG_VCC_U7100

REG_CPUCORE_FB

SNS_CPU_VAXG_P

=PPVCORE_S0_CPU

AGND_CPU

REG_CPUCORE_HFCOMP

REG_CPUCORE_VSEN

prefsb

051-9504

7.0.0

71 OF 143

66 OF 117

17

14

34

35

46

38

45

36 42 41

39

47

48

23

43

44

37

22

40

33

20

2

19

21

13

18

12

10

11

4

7

3

6

8

9

15 31

49

25

24

26

16

1

27

28

29

30

32

5

12

12 1 2

12

1

2

1

2

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

1

2

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

1

2

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

12 12

1212

12

66 67 68

105

66

105

66

105

66 67 68

105

66

105

66 67 68

105

6

13 17

51

105

66

105

66

105

105 105

6

10 11 13 16 28

66

105

66

105

66 67 68

105

66

105

66

105

66 67 68

105

66

105

5

66

116

66 105

13 66

105

66

105

66

105

66

105

66

105

66 67 68

105

13 66

105

13 66

105

66

105

66 105

66

105

66

105

66

105

66 67 68

105

66 67 68

105

66

105

51 66 105

66

105

66

105

66 67 68

105

66 67 68

105

66 67 68

105

66

105

66

105

66

105

66 105

66

105

66

105

66

116

66 105

66

105

66 105

66

105

66

105

66

105

66

116

6

66 69 70 72 92 95

5

66

116

6

66 69 70 72 92 95

105

66

116

105

66

105

66

105

66

105

51 66

105

66 105

66

105

66 67 68

105

66 67 68

105

66

105

66

105

66 67 68

105

6

105

66

105

66 105

66

116

105

66

105

66

105

66

105

6

13 16

51

66 67 68

105

66 67 68

105

66

105

66

105

OUT

S

D

G

S

D

G

S

D

G

NC

IN

NC

IN

NC

NCNC

D

G

S

D

G

S

D

G

S

BOOT

UGATE

PHASE

NC NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

BOOT

UGATE

PHASE

NC NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Output Decoupling

CPU Phase 2

CPU Phase 3

CPU Phase 1

Filtered 12V Rail

66

105

805

MF-LF

1/8W

5%

2.2

R7237

NOSTUFF

MF-LF

402

1%

1/16W

1.02K

R7241

SIGNAL_MODEL=EMPTY

66

105

66

105

6

67 68

R7267

MF-LF

10

1/10W

5%

603

1/10W

5%

R7256

MF-LF

0

805

MF-LF

1/8W

5%

2.2

R7257

NOSTUFF

SIGNAL_MODEL=EMPTY

1.02K

R7261

402

1% 1/16W MF-LF

66

105

66

105

6

67 68

CRITICAL

IRF6802SDTRPBF

DIRECTFET-SA

Q7210

DIRECTFET-SA

IRF6802SDTRPBF

CRITICAL

Q7210

CRITICAL

DIRECTFET-SA

IRF6802SDTRPBF

Q7250

R7216

0

5% 1/10W MF-LF

603

66

105

66

105

1% 1W

0612

MF

R7230

0.0005

CRITICAL

R7250

0612

0.0005

1% 1W MF

CRITICAL

IRF6893MTRPBF

Q7211

CRITICAL

DIRECTFET-MX

CRITICAL

DIRECTFET-MX

IRF6893MTRPBF

Q7231

DIRECTFET-MX

Q7251

CRITICAL

IRF6893MTRPBF

QFN1

CRITICAL

U7230

ISL6612

QFN1

CRITICAL

U7250

ISL6612

0402

50V X7R-CERM

10%

220PF

C7221

SIGNAL_MODEL=EMPTY

C7241

10%

220PF

X7R-CERM

50V

0402

SIGNAL_MODEL=EMPTY

C7261

X7R-CERM

220PF

10% 50V

0402

SIGNAL_MODEL=EMPTY

10%

0.001UF

C7217

0402

NOSTUFF

50V X7R-CERM

C7237

10%

X7R-CERM

50V

NOSTUFF

0402

0.001UF

NOSTUFF

C7257

0.001UF

0402

50V X7R-CERM

10%

TANT

2V

20%

CASE-D2

C7280

CRITICAL

270UF-0.006OHM 270UF-0.006OHM

CRITICAL

C7281

CASE-D2

20% 2V TANT

C7282

270UF-0.006OHM

CRITICAL

CASE-D2

20% 2V TANT

CRITICAL

270UF-0.006OHM

C7283

CASE-D2

20% 2V TANT

CRITICAL

270UF-0.006OHM

C7284

CASE-D2

20% 2V TANT

270UF-0.006OHM

C7285

CRITICAL

TANT

2V

CASE-D2

20%

C7240

X7R-CERM

16V

10%

0402

0.1UF

16V

0402

C7220

0.1UF

10%

X7R-CERM

0.1UF

0402

10% 16V X7R-CERM

C7260

C7236

X7R

25V

10%

0.22UF

0603

C7256

X7R

25V

10%

0.22UF

0603

C7225

1.0UF

0603

10% 16V X7R

C7226

X7R

16V

10%

0603

1.0UF

C7227

1.0UF

0603

16V X7R

10%

C7245

X7R

16V

10%

0603

1.0UF

C7247

X7R

16V

10%

0603

1.0UF

0603

16V

1.0UF

10%

X7R

C7265 C7267

1.0UF

X7R

16V

10%

0603

C7214

EMC

0402

10% 25V X6S-CERM

1UF

0402

X6S-CERM

C7215

EMC

1UF

10% 25V

C7235

X6S-CERM

25V

10%

0402

1UF

EMC

C7234

X6S-CERM

25V

10%

0402

1UF

EMC

C7255

EMC

1UF

0402

10% 25V X6S-CERM

C7254

EMC

1UF

10% 25V X6S-CERM 0402

CRITICAL

C7212

10UF

0603

20% 16V X6S-CERM X6S-CERM

10UF

20%

C7213

0603

16V

C7233

X6S-CERM

16V

20%

0603

10UF

16V X6S-CERM 0603

C7232

20%

10UF

C7253

10UF

0603

20% 16V X6S-CERMX6S-CERM

10UF

0603

20% 16V

C7251

C7216

0.22UF

0603

10% 25V X7R

C7291

POLY

CRITICAL

16V

20%

180UF

TH1

CRITICAL

POLY

16V

20%

180UF

TH1

C7292

TH1

CRITICAL

C7293

POLY

16V

20%

180UF

TH1

CRITICAL

180UF

16V

20%

C7294

POLY

TH1

180UF

20%

CRITICAL

POLY

16V

C7295

0.24UH-30A-0.35MOHM

L7210

CRITICAL

SDP110808M-TH

CRITICAL

0.24UH-30A-0.35MOHM

L7230

SDP110808M-TH

0.24UH-30A-0.35MOHM

L7250

CRITICAL

SDP110808MR36MF-TH

CRITICAL

L7200

0.36UH-30A-0.6MOHM

1/8W MF-LF

2.2

5%

R7217

NOSTUFF

805

DFN

U7210

ISL6622

CRITICAL

66

105

R7210

0612

1% 1W MF

0.0005

CRITICAL

402

MF-LF

1/16W

1%

1.02K

R7221

SIGNAL_MODEL=EMPTY

66

105

6

67 68

1/10W

603

MF-LF

5%

10

R7247

R7236

MF-LF

1/10W

5%

0

603

VReg CPU Core Phases

SYNC_DATE=02/28/2012

SYNC_MASTER=D8_MLB

=PP12V_S0_REG_CPUCORE

PP12V_S0_CPUCORE_FLT

PPCPUCORE_S0_SENSE_1

REG_PHASE_CPUCORE_1

PPCPUCORE_S0_SENSE_2

REG_PHASE_CPUCORE_2

PPCPUCORE_S0_SENSE_3

REG_LGATE_CPUCORE_2

REG_BOOT_CPUCORE_1_RC

REG_UGATE_CPUCORE_1

PP12V_S0_CPUCORE_FLT

REG_PWM_CPUCORE_3

PP12V_S0_CPUCORE_FLT

REG_SNUBBER_CPUCORE_1

REG_LGATE_CPUCORE_3

REG_LVCC_U7250

REG_LVCC_U7230

REG_LVCC_U7210

REG_BOOT_CPUCORE_3_RC

REG_BOOT_CPUCORE_2_RC

REG_ISENCORE_1_N

REG_UGATE_CPUCORE_2

PPCPUCORE_S0_REG

REG_BOOT_CPUCORE_1

REG_ISENCORE_3_N

REG_PWM_CPUCORE_1

REG_LGATE_CPUCORE_1

REG_PWM_CPUCORE_2

REG_BOOT_CPUCORE_2

REG_BOOT_CPUCORE_3

REG_ISENCORE_1_NR

REG_ISENCORE_2_NR

REG_ISENCORE_3_NR

REG_SNUBBER_CPUCORE_2

REG_SNUBBER_CPUCORE_3

AGND_CPU

REG_ISENCORE_3_P

PPCPUCORE_S0_REG

REG_UGATE_CPUCORE_3

PPCPUCORE_S0_REG

REG_ISENCORE_1_P

REG_ISENCORE_2_P

REG_ISENCORE_2_N

PP12V_S0_CPUCORE_FLT

REG_PHASE_CPUCORE_3

prefsb

051-9504

7.0.0

72 OF 143

67 OF 117

1

2

12

1

2

1

2

1

2

12

37

2

8

45

1

6

37

2

8

1

2

43

21

43

21

5

34

7126

5

34

7126

5

34

7126

2

1

10

3 8

5

6

7

9

11

4

2

1

10

3 8

5

6

7

9

11

4

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

1

2

3

6

9

4

2

1

5

11

10

7

8

43

21

12

1

2

1

2

6

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

6

67 68

105

66 67 68

105

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

NC

S

D

G

OUT

NC

IN

NC

NCNC

D

G

S

D

S

G

S

G

D

BOOT

UGATE

PHASE

NC NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CPU Phase 4

AXG Phase

NOSTUFF

MF-LF

5%

R7347

1/10W

603

10

R7336

1/10W

0

5%

MF-LF

603

U7330

ISL6622

DFN

CRITICAL

66

105

66

105

IRF6802SDTRPBF

DIRECTFET-SA

CRITICAL

Q7250

NOSTUFF

5%

805

MF-LF

1/8W

R7317

2.2

R7316

0

603

MF-LF

5% 1/10W

6

67

66

105

66

105

SIGNAL_MODEL=EMPTY

R7321

1.02K

MF-LF

1/16W

1%

402

10

5% 1/10W MF-LF 603

R7327

66

105

1%

MF

1W

0612

0.0005

R7310

CRITICAL

Q7311

DIRECTFET-MX

IRF6893MTRPBF

CRITICAL

649135PBF

Q7331

DIRECTFET_S3C

CRITICAL

Q7330

CRITICAL

S1

649136PBF

CRITICAL

U7310

ISL6612

QFN1

C7321

10%

220PF

X7R-CERM

50V

0402

SIGNAL_MODEL=EMPTY

C7341

220PF

X7R-CERM

50V

10%

0402

MF-LF

402

1%

1/16W

301

R7342

10% 50V

0402

NOSTUFF

0.001UF

X7R-CERM

C7337

10%

0402

X7R-CERM

0.001UF

50V

C7317

NOSTUFF

0.1UF

10% 16V

0402

C7340

X7R-CERM

16V

10%

0402

C7320

0.1UF

X7R

25V

10%

0.22UF

0603

C7316

C7336

0.22UF

25V

0603

10%

X7R

10%

1.0UF

0603

C7325

16V 16V

10%

1.0UF

0603

X7R

C7327

0603

X7R

10% 16V

C7345

1.0UF 1.0UF

C7346

0603

10% 16V X7R

1.0UF

X7R

16V

10%

0603

C7347

1UF

C7314

0402

10% 25V X6S-CERM

EMC

C7315

EMC

1UF

0402

10% 25V X6S-CERM

X6S-CERM

EMC

1UF

0402

10% 25V

C7335C7334

X6S-CERM

25V

10%

0402

1UF

EMC

20% 16V X6S-CERM 0603

10UF

C7312 C7313

10UF

0603

20% 16V X6S-CERM

C7333

X6S-CERM

16V

20%

0603

10UF

C7332

X6S-CERM

16V

20%

0603

10UF

C7396

TH1

180UF

16V POLY

20%

CRITICAL

16V

20%

TH1

POLY

180UF

C7397

CRITICAL

POLY

16V

20%

TH1

C7398

180UF

CRITICAL

C7399

TH1

180UF

20% 16V POLY

CRITICAL

L7310

CRITICAL

SDP110808M-TH

0.24UH-30A-0.35MOHM

L7330

0.24UH-30A-0.35MOHM

CRITICAL

SDP110808M-TH

C0G-CERM

50V

5%

120PF

0402

C7342

SIGNAL_MODEL=EMPTY

6

17

66

105

SIGNAL_MODEL=EMPTY

MF-LF

1/16W

1%

1.02K

R7341

402

R7330

1%

0612

MF

CRITICAL

1W

0.0005

R7337

5%

MF-LF 805

1/8W

NOSTUFF

2.2

SYNC_DATE=02/28/2012

VReg CPU AXG Phases

SYNC_MASTER=D8_MLB

REG_LGATE_CPUCORE_4

PP12V_S0_CPUCORE_FLT

REG_UGATE_CPUCORE_4

REG_LVCC_U7310

REG_ISENAXG_N

AGND_CPU

REG_ISENCORE_4_NR

REG_SNUBBER_CPUAXG

REG_PWM_CPUCORE_4

REG_PWM_CPUAXG

REG_UGATE_CPUAXG

REG_BOOT_CPUCORE_4

REG_BOOT_CPUCORE_4_RC

REG_BOOT_CPUAXG_RC

REG_LVCC_U7330

REG_ISENCORE_4_P

REG_BOOT_CPUAXG

PPCPUCORE_S0_REG

REG_LGATE_CPUAXG

PP12V_S0_CPUCORE_FLT

REG_ISENCORE_4_N

REG_SNUBBER_CPUCORE_4

REG_PHASE_CPUAXG

PPCPUAXG_S0_SENSE

REG_PHASE_CPUCORE_4

PPCPUCORE_S0_SENSE_4

REG_ISENAXG_NR

PPCPUAXG_S0_REG

REG_ISENAXG_PR

AGND_CPU

REG_ISENAXG_P

prefsb

051-9504

7.0.0

73 OF 143

68 OF 117

1

2

1

2

3

6

9

4

2

1

5

11

10

7

8

45

1

6

1

2

1

2

12

1

2

43

21

5

34

7126

128

356

7

4

3

4

2

1

5

6

2

1

10

3 8

5

6

7

9

11

4

2

1

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

2

1

12

43

21

1

2

105

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

66 67 68

105

OUT

PHASE

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Vout = 0.5 * (1 + Ra / Rb)

(reg_phase_vccsas0)

Regulator requires

prevent noise in the audio frequencies

<Rb>

<Ra>

a minimum load to

Max avg current:

500 kHz

8.10 A (BUDGET)

8.50 A (BUDGET) ? A (min)/? A (max)

<Rb>

<Ra>

Max peak current: OC trip point: Switching freq:

Note:

To regulator:

CPU VccIO (1.05V) S0 Regulator

6

Q7410.2:30MM

C7481

1000PF

25V

EMC

402

5%

NP0-C0G

Q7410.2:30MM

1000PF

C7480

25V

402

EMC

NP0-C0G

5%

NOSTUFF

603

1/10W

5%

MF-LF

2.2

R7417

X5R 603

10UF

20%

6.3V

C7422

CRITICAL

FDMS3602S

POWER56

Q7410

2.2

5%

MF-LF

1/8W

805

R7401R7400

10

5%

MF-LF

1/8W

805

C7400

402

16V X5R

1UF

10%

CRITICAL

UTQFN

ISL95870

U7400

0

R7460

402

MF-LF

1/16W

5%

XW7435

SIGNAL_MODEL=EMPTY

SM

U1000.T2:8MM

R7435

3.01K

402

1/16W

1%

SIGNAL_MODEL=EMPTY

MF-LF

402

1/16W

R7430

MF-LF

3.01K

1%

SIGNAL_MODEL=EMPTY

64

115

402

MF-LF

1/16W

1%

2.74K

R7436

2.74K

402

1/16W MF-LF

1%

R7431

U7400.3:5MM

XW7400

SM

5

64

115

I44

MF-LF 402

5% 1/16W

20K

R7480

SM

XW7430

SIGNAL_MODEL=EMPTY

XW7535.2:8MM

13

104

13

104

C7411

0603

20%

10UF

X5R-CERM

25V

CRITICAL

POLY

2V

CASE-D2-HF

20%

330UF-0.009OHM

C7421

C7412

25V

0603

X5R-CERM

20%

10UF

0

603

MF-LF

5%

1/10W

R7416

PIC0605H-SM

L7410

1.0UH-20%-15A-0.0065OHM

2.2UF

402

20%

C7401

X5R-CERM

10V

402

R7450

MF-LF

1%

1/16W

10K

R7451

1% 1/16W

MF-LF

L7410.2:3MM

10K

402

C7435

C0G-CERM

10PF

0402

50V

5%

10PF

5% 50V

0402

C0G-CERM

C7430

CASE-D2-HF

20%

POLY

2V

330UF-0.009OHM

C7420

CRITICAL

C7440

0.047UF

X7R-CERM 0402

16V

10%

0402

C7416

16V X7R-CERM

0.1UF

10%

0.001UF

10%

X7R-CERM

50V

0402

NOSTUFF

C7417

CRITICAL

POLY

16V

20%

C7410

180UF

TH1

C7450

0.022UF

20% 16V

X7R-CERM

0402

R7450.2:3MM

1/10W

5%

200

603

R7418

MF-LF

1000PF

402

25V

5%

NP0-C0G

C7418

SYNC_MASTER=D8_KOSECOFF

VReg CPU 1.05V S0

SYNC_DATE=02/25/2012

SNS_CPU_VCCIO_P

SNS_CPU_VCCIO_N

SNS_CPU_P1V05S0_XW_N

REG_CPU_P1V05S0_RTN

PP1V05_S0_CPU_REG

REG_CPU_P1V05S0_OCSET

REG_CPU_PHASE_P1V05S0

REG_CPU_BOOT_P1V05S0

REG_CPU_UGATE_P1V05S0

REG_CPU_P1V05S0_VO

REG_CPU_P1V05S0_SREF

REG_CPU_P1V05S0_FB

REG_CPU_P1V05S0_OCSET

REG_CPU_P1V05S0_PGOOD

SNS_CPU_P1V05S0_XW_P

=PP3V3_S0_VRD

REG_CPU_P1V05S0_PGOOD

REG_CPU_LGATE_P1V05S0

=PP5V_S0_REG_CPU_P1V05

REG_PVCC_U7400

REG_CPU_P1V05S0_VO

PM_EN_REG_CPU_P1V05_S0

REG_CPU_P1V05S0_FSEL

REG_CPU_BOOT_P1V05S0_RC

REG_CPU_SNUBBER_P1V05S0

MAKE_BASE=TRUE

PM_PGOOD_REG_CPU_P1V05_S0

AGND_CPU_P1V05S0

REG_VCC_U7400

=PP12V_S0_REG_CPU_P1V05

prefsb

051-9504

7.0.0

74 OF 143

69 OF 117

2

1

2

1

2

1

6

1

345

7

2

1

2

1

2

1

12

11

15

10

2

5

9

7

8

4

13

14

1

16

3

6

1

2

1

121

2

1

2

1

2

1

2

1

2

1

2

1

2

21

2

1

2

1

2

212

1

2

1

2

1

2

1

2

12

1

2

1

104

69

104

69

104

69

104

69

116

104

6

66 70 72 92 95

69

116

104

6

104

69

104

6

OUT

PHASE

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

<Ra>

<Rb>

Vout = 0.5 * (1 + Ra / Rb)

30 A (BUDGET) ? A (min)/? A (max) 500 kHz

Note:

a minimum load to prevent noise in the audio frequencies

<Rb>

Regulator requires

To regulator:

OC trip point:

Max avg current:

Switching freq:

Max peak current:

<Ra>

(reg_phase_vccsas0)

CPU VccSA (0.925V) S0 Regulator

12.07 A (BUDGET)

C7518

402

25V

NP0-C0G

1000PF

5%

6

NOSTUFF

R7517

603

1/10W

5%

MF-LF

2.2

5% 1/10W MF-LF

603

R7516

0

C7501

603

16V X5R

2.2UF

10%

CRITICAL

Q7510

POWER56

FDMS3602S

2.2

MF-LF

5%

805

R7501

1/8W

603

C7522

X5R

10UF

20%

6.3V

10

R7500

5%

MF-LF

1/8W

805

C7500

402

16V X5R

1UF

10%

CASE-D2-HF

C7521

CRITICAL

POLY

2V

20%

330UF-0.009OHM

64 65

115

R7580

MF-LF 402

5% 1/16W

20K

SM

SIGNAL_MODEL=EMPTY U1000.T2:4MM

XW7535

SM

XW7530

SIGNAL_MODEL=EMPTY

XW7535.2:4MM

13

104

L7510.2:3MM

R7551

12.1K

402

1% 1/16W MF-LF

R7550

L7510.1:3MM

402

1/16W MF-LF

1%

12.1K

U7500

UTQFN

ISL95870

CRITICAL

64

115

R7535

MF-LF

1/16W

1%

402

SIGNAL_MODEL=EMPTY

2.32K

SIGNAL_MODEL=EMPTY

R7530

MF-LF

1/16W

402

1%

2.32K

R7536

402

MF-LF

1/16W

1%

2.74K

R7560

MF-LF

1/16W

5%

0

402

R7531

2.74K

1% 1/16W MF-LF

402

C7520

CASE-D2-HF

20%

POLY

2V

CRITICAL

330UF-0.009OHM

SM

XW7500

U7500.3:39MM

1UF

EMC

10% 25V X5R 402

C7580

Q7510.2:3MM

X5R

25V

402

EMC

1UF

10%

Q7510.2:3MM

C7581

1.0UH-20%-15A-0.0065OHM

L7510

PIC0605H-SM

C7535

5%

C0G-CERM

50V

0402

10PF

C7530

C0G-CERM 0402

50V

5%

10PF

10%

X7R-CERM

16V

C7540

0.047UF

0402

10%

0.1UF

X7R-CERM

16V

C7516

0402

C7517

0.001UF

NOSTUFF

0402

50V X7R-CERM

10%

0.012UF

R7550.2:3MM

C7550

X7R-CERM

50V

10%

0603

CRITICAL

TH1

C7510

180UF

20% 16V POLY

R7518

1/10W MF-LF

5%

200

603

SYNC_MASTER=D8_KOSECOFF

VReg CPU VccSA S0

SYNC_DATE=02/25/2012

REG_VCCSAS0_FB

REG_VCCSAS0_VO

AGND_VCCSAS0

=PP12V_S0_REG_VCCSA

REG_SNUBBER_VCCSAS0

PM_EN_REG_VCCSA_S0

SNS_VCCSAS0_XW_P

=PP5V_S0_REG_VCCSA

REG_VCC_U7500

SNS_CPU_VCCSA

REG_VCCSAS0_PGOOD

=PP3V3_S0_VRD

REG_VCCSAS0_FSEL

REG_VCCSAS0_PGOOD

REG_UGATE_VCCSAS0

REG_VCCSAS0_OCSET

REG_LGATE_VCCSAS0

REG_PVCC_U7500

REG_VCCSAS0_SREF

REG_BOOT_VCCSAS0_RC

REG_VCCSAS0_RTN

REG_VCCSAS0_VO

REG_PHASE_VCCSAS0

PPVCCSA_S0_REG

REG_VCCSAS0_OCSET

MAKE_BASE=TRUE

PM_PGOOD_REG_VCCSA_S0

REG_BOOT_VCCSAS0

SNS_VCCSAS0_XW_N

prefsb

051-9504

7.0.0

75 OF 143

70 OF 117

2

1

2

1

2

1

6

1

345

7

2

1

2

1

2

1

2

1

2

212

1

2

1

2

12

11

15

10

2

5

9

7

8

4

13

14

1

16

3

6

121

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

212

1

2

1

2

1

2

1

12

1

2

1

2

104

70

104

6

104

6

104

70

116

6

66 69 72 92 95

104

70

116

104

70

104

70

104

70

104

PGOOD2

FCCM

VIN

FB1

FSET1

EN2

FSET2

BOOT2

THRM

PGND

EN1

FB2

VOUT2VOUT1

ISEN2ISEN1

OCSET1

OCSET2

LGATE1

LGATE2

PHASE2

BOOT1

UGATE1

LDO5

PGOOD1

VCC1

VCC2

UGATE2

PHASE1

PAD

OUT

IN

OUT

OUTOUT

IN

PHASE

S

G

S

D

N-CH

P-CH

IN

G

D

S

G

D

S

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(reg_phase_p3v3s5)

Vout = 0.6 * (1 + Ra / Rb)

between PWM and ultrasonic DCM

(reg_p5vs4_isen)

(reg_p5vs4_ocset)

(reg_phase_p5vs4)

? A (design)/ 6.9 A (budget)

10 A (design)/ 6.08 A (budget)

6 A (design)/ 4.85 A (budget)

? A (nom)/? A (min)

Max avg current:

Max peak current:

OC trip point:

Max peak current:

5V S4 Regulator

? A (nom)/? A (min)

(reg_p5vs4_vout)

<Rb>

<Ra>

(reg_p3v3s4_ocset)

<Ra>

Switching freq:

<Rb>

BURSTMODE_EN_L

Vreg Mode

1

0 PWM

DCM

modes based on load requirements

This circuit toggles the Vreg

Switching freq:

350 kHz

OC trip point:

Vout = 0.6 * (1 + Ra / Rb)

(reg_p3v3s4_vout)

3.3V S5 Regulator

350 kHz

Max avg current:

? A (design)/ 6.6 A (budget)

(reg_p3v3s4_isen)

CRITICAL

QFN

ISL62383CRTZ

U7600

MF-LF

1/10W

R7656

603

0

5%

0.1UF

C7656

402

10% 25V X5R

NOSTUFF

1/10W

R7657

603

MF

1%

0.499

R7658

9.76K

402

1% 1/16W MF-LF

C7658

402

10% 10V X5R

27.0NF

R7659

MF-LF

402

1%

1/16W

9.76K

OMIT

SM

L7650.2:1MM

XW7650

R7670

MF-LF

1/16W

1%

402

75K

R7671

10K

1/16W MF-LF 402

1%

MF-LF

1/16W

976

402

1%

R7672

C7672

NP0-C0G

25V

5%

1000PF

402

R7673

16.5K

402

MF-LF

1/16W

1%

R7633

1/16W

402

MF-LF

16.5K

1%

R7630

1%

402

45.3K

MF-LF

1/16W

C7632

25V

5%

402

NP0-C0G

1000PF

1%

402

MF-LF

1/16W

976

R7632

MF

1/16W

10.0K

0.5%

402

R7631

OMIT

SM

XW7610

L7610.1:6MM

2.2UH-10A-12.5MOHM

PAB0705AR-SM

L7610

CRITICAL

C7618

0402

16V

0.01UF

10%

X7R-CERM

1/16W MF-LF

1%

402

15.8K

R7618

1%

402

MF-LF

1/16W

15.8K

R7619

R7616

603

1/10W

5%

0

MF-LF

C7616

0.1UF

402

25V X5R

10%

C7600

402

1UF

10% 16V X5R

C7602

X5R

10%

402

16V

1UF

C7603

X5R

10%

402

1UF

16V

R7602

2.2

5% 1/8W MF-LF 805

6

C7601

CERM

20%

603

6.3V

4.7UF

R7603

MF-LF

1/8W

805

1

5%

64

115

EMC

402

25V

5%

NP0-C0G

1000PF

C7640

L7610.1:6MM

R7617

603

1%

1/10W

MF

0.499

NOSTUFF

64

115

MF-LF

5%

402

R7680

1/16W

20K

402

5% 1/16W MF-LF

20K

R7640

65

115

6 6

64 74

115

25V NP0-C0G

5%

402

EMC

C7680

L7650.2:4MM

1000PF

20%

C7622

10UF

6.3V X5R 603

POWER56

FDMS3602S

Q7610

CRITICAL

C7662

20%

10UF

6.3V

603

X5R

C7660

CRITICAL

20%

6.3V POLY-TANT

330UF

CASE-D3L-SM

L7650

PIC1005H-SM

CRITICAL

2.2UH+/-20%-0.0069OHM-16A

402

5%

1000PF

NP0-C0G

25V

EMC

C7641

L7610.1:6MM

EMC

402

25V

5%

1000PF

C7681

L7650.2:4MM

NP0-C0G

C7661

CASE-D3L-SM

330UF

POLY-TANT

6.3V

20%

CRITICAL

C7682

X5R

25V

10%

1UF

EMC

402

Q7650.5:3MM

X5R

10%

EMC

402

1UF

25V

C7683

Q7650.5:3MM

C7643

402

EMC

1UF

10% 25V X5R

Q7610.2:3MM

402

10%

X5R

25V

1UF

C7642

EMC

Q7610.2:3MM

SSM6L36FE

NOSTUFF

SOT563

Q7600

6

48

112

R7601

1/16W

5%

10K

MF-LF

402

NOSTUFF

R7600

1K

1/16W MF-LF

5%

402

Q7655

FDMC0223S

CRITICAL

MLP3.3X3.3

Q7650

CRITICAL

MLP3.3X3.3

FDMC0225

ELEC

16V

20%

270UF

C7610

CRITICAL

8X9-TH2 8X9-TH2

CRITICAL

20% 16V ELEC

C7650

270UF

C7651

ELEC

16V

20%

270UF

CRITICAL

8X9-TH2

C7633

0.01UF

X7R-CERM

16V

10%

0402

0.01UF

10% 16V

C7673

0402

X7R-CERM

10%

0.001UF

X7R-CERM

50V

C7617

NOSTUFF

0402

10%

X7R-CERM 0402

NOSTUFF

0.001UF

C7657

50V

C7675

10%

X7R-CERM

50V

0402

NOSTUFF

0.001UF

CASE-B6S-SM

POLY

6.3V

20%

150UF

C7621

CRITICAL

20%

CASE-B6S-SM

POLY

6.3V

CRITICAL

150UF

C7620

SYNC_MASTER=D8_MLB

VReg 3.3V S5/5V S4

SYNC_DATE=02/28/2012

PP5V_S4_REG

REG_SNUBBER_P5VS4

PM_EN_REG_P3V3_S5

PM_EN_REG_P5V_S4

=PP12V_S5_REG_P3V3P5V_S5

REG_PHASE_P5VS4

REG_BOOT_P3V3S5

REG_P3V3S5_VOUT

REG_P3V3S5_OCSET

REG_PHASE_P3V3S5

REG_P3V3S5_ISEN

REG_U7600_FCCM

REG_P5VS4_VOUT

REG_P5VS4_ISEN

REG_UGATE_P3V3S5

REG_BOOT_P3V3S5_RC

REG_P5VS4_FB

REG_P3V3S5_FB

BURSTMODE_EN

PP5V_S5_LDO

REG_P5VS4_FSET

REG_P3V3S5_FSET

REG_VIN_U7600

REG_UGATE_P5VS4

REG_BOOT_P5VS4_RC

REG_U7600_FCCM_R

REG_P3V3S5_VOUT_R

BURSTMODE_EN_L

=PP5V_S5_PWRCTL

REG_LGATE_P3V3S5

REG_P3V3S5_PGOOD

REG_P5VS4_PGOOD

=PP3V3_S5_VRD

REG_P3V3S5_PGOOD

REG_U7600_FCCM

REG_P5VS4_PGOOD

REG_P5VS4_VOUT_R

=PP5V_S5_PWRCTL

REG_BOOT_P5VS4

REG_VCC2_U7600

REG_LGATE_P5VS4

REG_VCC1_U7600

REG_P5VS4_OCSET

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

PM_PGOOD_REG_P5V_S4

REG_SNUBBER_P3V3S5

PP3V3_S5_REG

051-9504

7.0.0

prefsb

76 OF 143

71 OF 117

1

3

17

8

6

24

2

21

29

19

12

28

279

26

10

11 25

16 20

23

15

14

18

7

5

4

22

13

1

2

1

2

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

1

345

7

2

11

2

21

2

1

2

1

2

1

2

1

2

1

2

1

4

5

2

1

3

6

1

2

12

5

123

4

5

123

4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

106

6

106

71

106

106 106

71

112

71

112

106 106

106

6

71

106

71

116

71

116

6

71

6

71

71 116

71

116

106

6

71

106

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

IN

OUT

NC NC

IN

OUT

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

VSW

PGND

TGR

TG

BG

VIN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

VDDQ (1.5V) S3 Regulator

9.0 A (BUDGET)

? A (nom)/? A (min)

Need copper around Q7710

<Ra>

1.8V S0 Regulator

Max avg current:

OC trip point:

to sink heat

<Rb>

Vout = 1.8 * (Ra / (Ra + Rb))

10mA (max)

<Rb>

PU: PWM

Vout = 0.8 * (1 + Ra / Rb)

<Ra>

400 kHz

PD: PFM (SKIP mode)

Critical:

? kHz

Switching freq:

Max peak current:

? A (nom)/? A (min)

1.7 A (BUDGET)

11.3 A (BUDGET)

0.6 A (BUDGET)

Switching freq:

OC trip point:

Max peak current:

Max avg current:

CRITICAL

QFN

U7700

TPS51916

NP0-C0G

1000PF

402

C7717

NOSTUFF

25V

5%

MF

R7717

NOSTUFF

1%

0.499

603

1/10W

C7716

0.1UF

10% 25V X5R 402

R7716

603

1/10W

0

MF-LF

5%

L7710.2:1MM

OMIT

XW7710

SM

X5R-CERM-1

CRITICAL

20%

22UF

603

6.3V

C7725

OMIT

SM

XW7725

C7725.1:3MM

X5R-CERM-1

22UF

6.3V

603

20%

C7726

CRITICAL

U7700.21:4MM

XW7700

SM

OMIT

C7727

CERM

0.22UF

10% 16V

402

MF-LF

402

49.9K

1%

1/16W

R7731

MF-LF

1/16W

R7730

402

1%

10K

64

114

64

115

CRITICAL

20% 2V POLY CASE-D2-HF

330UF-0.009OHM

C7721

CASE-D2-HF

POLY

2V

330UF-0.009OHM

20%

CRITICAL

C7720

6.3V X5R

10UF

20%

603

C7701

10% 16V

2.2UF

603

C7700

X5R

2.2

5%

MF-LF

1/8W

805

R7700

5

64

115

R7740

1/16W MF-LF 402

5%

20K

6

CRITICAL

PIMB053T-SM

L7750

1.0UH-7A

5%

47PF

50V CERM 402

C7758

1%

402

MF-LF

1/16W

59.0K

R7758

402

1% 1/16W MF-LF

47.0K

R7759

6.3V

20%

X5R-CERM-1

22UF

603

C7760

MF-LF

1/16W

5%

402

100K

R7770

NOSTUFF

100K

MF-LF

1/16W

5%

402

R7771

X5R 603

C7722

10UF

20%

6.3V

603

22UF

X5R-CERM-1

6.3V

20%

C7761

6

64

115

64

115

C7750

20%

603

6.3V X5R

10UF

20%

10UF

C7751

603

X5R

6.3V

ISL8014A

U7750

CRITICAL

QFN

SON5X6

CRITICAL

Q7710

CSD58872Q5D

Q7710.1:3MM

C7742

25V

1UF

10%

402

EMC

X5R

1UF

C7743

Q7710.1:3MM

25V

10%

X5R 402

EMC

6

10UF

20%

6.3V

603

C7723

X5R

1/16W MF-LF

1%

1K

402

R7735

C7753

10%

X5R

25V

EMC

402

U7750.1:3MM

1UF

X5R

10%

1UF

402

25V

EMC

C7752

U7750.1:3MM

MF-LF

402

1%

1/16W

10K

R7780

10%

X7R-CERM

50V

0402

C7731

0.01UF

C7730

X7R-CERM 0402

0.1UF

16V

10%

180UF

16V POLY

C7710

CRITICAL

20%

TH1

16V

CRITICAL

C7711

TH1

POLY

20%

180UF

5%

MF-LF

0

1/10W

R7711

603

Q7710.1:3MM

C7745

25V X5R

10%

402

1UF

Q7710.1:5MM

C7744

X5R

10%

1UF

402

25V

R7736

1%

44.2K

402

MF-LF

1/16W

1.0UH-27A-1.05MOHM

L7710

CRITICAL

SDP1182-SM

SYNC_DATE=02/25/2012

VReg VDDQ and 1.8V S0

SYNC_MASTER=D8_KOSECOFF

PPVDDQ_S3_REG

REG_PHASE_VDDQS3_L

=PP12V_S5_REG_VDDQ_S3

PP1V8_S0_REG

REG_P1V8S0_VFB

PPDDRVTT_S0_LDO

REG_SNUBBER_VDDQS3

REG_UGATE_VDDQS3_R

REG_UGATE_VDDQS3

=PP3V3_S0_VRD

REG_P1V8S0_PGOOD

=PP5V_S4_REG_VDDQ_S3

REG_VDDQS3_PGOOD

PM_EN_REG_VDDQ_S3

REG_BOOT_VDDQS3

PPDDRVTT_S3_LDO

PM_EN_LDO_DDRVTT_S0

LDO_DDRVTTS0_SNS

REG_VDDQS3_PGOOD

REG_PHASE_VDDQS3

=PPVDDQ_S3_LDO_DDRVTT

REG_BOOT_VDDQS3_RC

=PP5V_S0_VRD

REG_P1V8S0_SYNCH

PM_EN_REG_P1V8_S0

REG_P1V8S0_PGOOD

=PP3V3_S4_PWRCTL

MAKE_BASE=TRUE

PM_PGOOD_REG_P1V8_S0

MAKE_BASE=TRUE

PM_PGOOD_REG_VDDQ_S3

REG_VDDQS3_VDDQSNS

REG_VDDQS3_VREF

REG_VDDQS3_TRIP

REG_VDDQS3_MODE

REG_VDDQS3_REFIN

=PP5V_S0_REG_P1V8

AGND_VDDQS3

REG_PHASE_P1V8S0

REG_V5IN_U7700

REG_LGATE_VDDQS3

prefsb

051-9504

7.0.0

77 OF 143

72 OF 117

12

8

16

6

17

19 18

13

11 20 9 3 1

5

14

15

2

21

4

7

10

2

1

2

11

2

12

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

2

11

2

1

2

1

2

1

2

1

2

1

2

1

2

1

15

13

3

1

17

12

11

10

9

5

7

4

14

8

16 6

2

6

9

4

3

5

8

7

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

106

6

106

6

66 69 70 92 95

72

116

6

72

116

106

6

106

72

116

106

6

106

6

92

106

72

116

6

65 74

106

6

106

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

OC trip point:

Vout = 1.25V * (1 + Ra / Rb)

Vout = 3.425 250mA max output (Switcher limit)

? A (nom)/? A (min)

0.10 A (BUDGET)

0.04 A (BUDGET)

? kHz

<Ra>

<Rb>

Switching freq:

Max peak current:

3.425V "G3Hot" Regulator

Max avg current:

D8:CONTROLLER CHANGE FOR 3.42V SMC SUPPLY RDAR://11003901

D7/D7I: IMPLEMENT A CLEANER DISABLE FOR PP3V42_G3H REGULATOR RDAR://11132734

R7865

0.00

0603

1/10W

0% FF

0402

C7864

50V CERM

22PF

5%

LT3470AED

DFN

U7801

150K

1% 1/16W MF-LF 402

R7861

R7862

402

MF-LF

1/16W

49.9K

1%

C7865

22UF

20%

6.3V X5R-CERM1 0603

348K

R7863

1% 1/16W MF-LF 402

R7864

MF-LF

1/16W

1%

402

200K

L7861

33UH

CDPH4D19FHF-SM

0603

20% 25V X5R-CERM

10UF

C7861

1000PF

NOSTUFF

C7862

25V

5%

402

NP0-C0G

C7863

0.22UF

CERM 402

16V

10%

X5R

C7802

1UF

25V

402

10%

1UF

402

C7807

25V

10%

X5R

25V

10UF

20%

0603

X5R-CERM

C7806

VREG 3.42V G3HOT

SYNC_MASTER=D8_MLB

SYNC_DATE=04/11/2012

P3V42G3H_SHDN_L

PP12V_G3H_P3V42

=PP12V_G3H_P3V42

P3V42G3H_FB

PP3V42_G3H_REG

P3V42G3H_BOOST

P3V42G3H_SW

prefsb

051-9504

7.0.0

78 OF 143

73 OF 117

12

2

1

4

3

6

2

8

5

7

1

9

1

2

1

2

11

2

1

2

21

2

1

2

1

2

12

1

2

1

2

1

106

6

106

6

114

106

OUT

NC

OUT

IN

THRM

GND

PG

ON

NC

D1

D2

G

VCC

PAD

OUT

NC

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

OUT

NC

IN

G

D

S

G

D

S

IN

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

G

PG

THRM

GND

NC

D

VCC

S

ON

PAD

G

D

S

IN

OUT

NC

OUT

NC

THRM

GND

PG

ON

NC

D1

D2

G

VCC

PAD

IN

D

S

G

D

S

G

D

S

G

ON

NC

S

VCC

D

PG

G

GND

THRM

PAD

DGS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

376S1125

RADAR://11420274 NEW MOSFET Q7950 TO AVOID 50A 100US PULSE ON 12V S0.

Max peak current:

Max avg current:

6 A (BUDGET) 6 A (BUDGET) SOFT START ON BLC

BLC12V BYPASS STUFFING OPTION

5V S0 FET

RADAR://10865139 U7970 ENSURES S5_PWRGD ISN’T ASSERTED AFTER HARD SHUTDOWN.

VDDQ (1.5V) S0 FET

Max avg current:

9.0 A (BUDGET)

20.4 A (BUDGET)

Input: 2.4V to 5.5V

Max peak current:

Max avg current:

12V S0 FET

Max peak current:

Max avg current:

2.7 A (BUDGET)

NOSTUFF

NO BYPASS

STUFF

R7986:

R7911:

STUFF

BYPASS

Input: 2.4V to 5.5V

3.3V S0 FET (4.8A PK / 3.5A AVG)

Max peak current:

12V S5 FET

Max avg current: 7.533 A (BUDGET)

3.3V S4 FET (2.7A PK / 2.0A AVG)

12V S0 BLC FET

24.1 A (BUDGET)

Max peak current:

9.733 A (BUDGET)

11.3 A (BUDGET)

3.9 A (BUDGET)

6

MF-LF

10K

5% 1/16W

402

R7930

28 64

115

64

114

U7950

TDFN

CRITICAL

SLG5AP026

100

MF-LF

603

1/10W

5%

R7950

16V

603

X5R

10%

1UF

C7950

R7951

5%

100K

1/16W

402

MF-LF

6

64 74

114

U7930

SLG5AP004

CRITICAL

DFN

6

C7970

1UF

603

10%

X5R

16V

603

1/10W

5%

MF-LF

R7970

100

1/16W MF-LF

R7971

100K

402

5%

47 48

116

CRITICAL

IRFH3702TRPBF

PQFN

Q7940

CRITICAL

PQFN

Q7900

IRFH3702TRPBF

R7900

10K

5% 1/16W MF-LF 402

64

114

64

114

DFN

CRITICAL

U7940

SLG5AP004

U7900

SLG5AP004

CRITICAL

DFN

CRITICAL

U7920

DFN

SLG5AP004

Q7920

CRITICAL

PQFN

IRFH3702TRPBF

64

114

6

10K

R7982

1/16W

402

MF-LF

5%

5% 1/10W MF-LF

100

603

R7980

C7980

16V

10%

X5R 603

1UF

U7980

SLG5AP026

TDFN

CRITICAL

64 74

114

87

107

R7910

5%

MF-LF

402

10K

1/16W

5%

NOSTUFF

10K

R7911

MF-LF

402

1/16W

Q7970

649135PBF

DIRECTFET_S3C

CRITICAL

649135PBF

DIRECTFET_S3C

CRITICAL

Q7930

Q7980

DIRECTFET_S3C

649135PBF

CRITICAL

402

MF-LF

1/16W

1%

200K

R7983

R7974

1/16W MF-LF

0

5%

402

1/16W

1%

R7952

47.0K

MF-LF

1/16W MF-LF 402

22K

R7940

5%

22K

1/16W MF-LF 402

R7920

U7970

TDFN

CRITICAL

SLG5AP022-200030V

1/16W

0

MF-LF

5%

R7953

402

NOSTUFF

R7987

MF-LF

1/16W

5%

0

402

0

1/16W

R7973

402

MF-LF

5%

0.022UF

C7973

0402

X7R

50V

10%

CRITICAL

DIRECTFET-MX

IRF6717MTR1PBF

Q7950

10% 50V X7R-CERM 0805

0.022UF

C7953

0

5% 1/16W MF-LF

R7989

NOSTUFF

402

X7R-CERM

16V

10%

0.1UF

0402

C7900

X7R-CERM

10% 16V

0.1UF

0402

C7940

X7R-CERM

16V

10%

0.1UF

0402

C7921

C7930

0.1UF

10%

X7R-CERM

16V

0402

SYNC_MASTER=D8_MLB

FET-Controlled S0 and S4

SYNC_DATE=05/14/2012

=PP12V_S5_PWRCTL

PP1V5_S0_FET

PP3V3_S0_FET

PM_EN_FET_P12V_S0_R

=PP5V_S4_FET_P5V_S0

PM_PGOOD_FET_P12V_S0_BLC

PGOOD_P12V_S0

PP3V3_S4_FET

FET_EN_P12V_S0_R

PGOOD_P12V_S0

PP12V_S5_FET

FET_EN_P12V_S0

VIDEO_ON

=PP12V_G3H_FET_P12V_S0

PM_EN_REG_P3V3_S5

PM_PGOOD_P3V3_S4_FET

PM_PGOOD_FET_P3V3_S0

PM_EN_FET_VDDQ_S0

=PP3V3_S4_PWRCTL

PM_EN_FET_P3V3_S4

PM_PGOOD_FET_P5V_S0

=PP3V3_S4_PWRCTL

P3V3_S3_EN_G

=PPVDDQ_S3_FET_VDDQ_S0

FET_VCC_U7980

FET_EN_P12V_S0_BLC_R

PM_EN_FET_P12V_S0

P3V3_S0_EN_G

=PP3V3_S0_PWRCTL

PM_EN_FET_P12V_S0

PM_EN_FET_P5V_S0

PP5V_S0_FET

P5V_S0_EN_G

=PP3V3_S0_PWRCTL

FET_EN_VDDQ_S0

PM_PGOOD_FET_VDDQ_S0

SMC_PM_G2_EN

=PP3V3_S0_PWRCTL

FET_EN_P12V_S5

FET_VCC_U7970

FET_EN_P12V_S5_R

PM_PGOOD_FET_P12V_S5

FET_VCC_U7950

=PP3V3_S5_FET_P3V3_S4

PP12V_S0_BLC_FET

FET_EN_P12V_S0_BLC

=PP12V_G3H_FET_P12V_S5

=PP12V_G3H_FET_P12V_S0

=PP3V3_S5_FET_P3V3_S0

PM_EN_FET_P3V3_S0

=PP3V3_S4_PWRCTL

PP12V_S0_FET

PM_PGOOD_FET_P12V_S0

prefsb

051-9504

7.0.0

79 OF 143

74 OF 117

1

2

9

4

8

2

3

5

6

7

1

12

2

1

2

7

8

9

4

3

5

1

6

2

1

12

1

2

5

1

4

5

1

4

1

2

7

8

9

4

3

5

1

6

2

7

8

9

4

3

5

1

6

2

7

8

9

4

3

5

1

6

2

5

1

4

1

2

12

2

1

9

4

8

2

3

5

6

7

1

12

1

2

8

3

5

6

7

4

1

2

8

3

5

6

7

4

1

2

8

3

5

6

7

4

1

2

12

1

2

1

2

1

2

3

6

1

5

8

7

4

9

1

2

12

1

2

1

5

34

7126

2

1

12

2

1

2

1

2

1

2

1

6

64 65 74

6

64 65 74

6

64 65 74

6

64 65 74

6

114

6

91

115

64 65 74

115

6

113

64 65 74

115

113

6

74

64 71

115

27 35 64

115

64

115

6

65 72 74

64

115

6

65 72 74

114

6

113

114

6

28 74

114

6

28 74

113

6

28 74

113

115

113

6

113

6

74

6

65 72 74

115

IN

OUT

PEX_SVDD_3V3

PEX_TX0*

PEX_TX0PEX_RX0

PEX_RX1

PEX_RX6*

PEX_REFCLK*

PEX_WAKE*

PEX_CLKREQ*

PEX_RST*

PEX_REFCLK

PEX_RX15 PEX_RX15*

PEX_RX14*

PEX_RX14

PEX_RX12*

PEX_RX12

PEX_RX11*

PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*

PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7 PEX_RX7*

PEX_RX6

PEX_RX5 PEX_RX5*

PEX_RX4*

PEX_RX4

PEX_RX3*

PEX_RX3

PEX_RX2 PEX_RX2*

PEX_RX1*

PEX_TSTCLK_OUT*

PEX_TERMP

PEX_TX15

PEX_TX15*

PEX_TSTCLK_OUT

PEX_TX14*

PEX_TX14

PEX_TX13*

PEX_TX13

PEX_TX12

PEX_TX12*

PEX_TX11

PEX_TX11*

PEX_TX10

PEX_TX10*

PEX_TX9*

PEX_TX8*

PEX_TX9

PEX_TX8

PEX_TX7

PEX_TX6*

PEX_TX6

PEX_TX5*

PEX_TX5

PEX_TX4

PEX_TX3*

PEX_TX3

PEX_TX2

PEX_TX2*

PEX_TX1*

PEX_TX1

PEX_TX4*

PEX_RX0*

PEX_RX13*

PEX_RX13

PEX_TX7*

(1 OF 10)

NC

OUT

IN

OUT

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ALL LANES ARE REVERSED AND LANES 10,8,5,3,0 ARE POLARITY SWAPPED

ALL LANES ARE REVERSED AND LANES 10,8,7,6,5,3,2,1 ARE POLARITY SWAPPED

Power aliases required by this page:

- =PP3V3_GPU_VDD33

Page Notes

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

26 82

113

15 18

114

U8000

NV-GK107

BGA

OMIT_TABLE

R8002

1/20W1%201

MF

200

NOSTUFF

R8005

2.49K

201

1%

1/20W

MF

R8000

MF 5%

1/20W

201

0

10 98

CA036

0.22UF

GND_VOID=TRUE

6.3V X5R 020120%

CA037

0.22UF

GND_VOID=TRUE

6.3V X5R 020120%

GND_VOID=TRUE

0.22UF

6.3V X5R 020120%

CA038

CA039

0.22UF

6.3V X5R 020120%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA040

CA041

6.3V X5R 020120%

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

6.3V X5R 020120%

CA042

0.22UF

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA043

0.22UF

CA044

GND_VOID=TRUE

6.3V X5R 020120%

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA045

6.3V

GND_VOID=TRUE

X5R 0201

0.22UF

20%

CA046

10 98

20%

0.22UF

0201X5R6.3V

CA021

GND_VOID=TRUE

020120% X5R6.3V

CA020

GND_VOID=TRUE

0.22UF

CA023

20% 0201X5R6.3V

GND_VOID=TRUE

CA022

GND_VOID=TRUE

20% 0201X5R6.3V

0.22UF

X5R6.3V 020120%

GND_VOID=TRUE

CA024

0.22UF

GND_VOID=TRUE

X5R20% 6.3V

CA026

0201

GND_VOID=TRUE

20% 0201X5R6.3V

CA025

0.22UF

6.3V

GND_VOID=TRUE

20%

0.22UF

X5R

CA028

0201

20%

0.22UF

X5R6.3V

CA027

0201

GND_VOID=TRUE

020120%

0.22UF

X5R6.3V

GND_VOID=TRUE

CA029

20% 6.3V 0201

0.22UF

X5R

GND_VOID=TRUE

CA030

10 98

GND_VOID=TRUE

0.22UF

6.3V20% 0201X5R

CA031

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA047

6.3V

GND_VOID=TRUE

X5R 0201

0.22UF

20%

CA048

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA049

0201

GND_VOID=TRUE

X5R

0.22UF

6.3V20%

CA050

X5R6.3V 0201

0.22UF

20%

GND_VOID=TRUE

CA051

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA071

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA072

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA073

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA074

GND_VOID=TRUE

6.3V X5R 020120%

0.22UF

CA075

6.3V

GND_VOID=TRUE

X5R 0201

0.22UF

20%

CA076

CA077

X5R6.3V

GND_VOID=TRUE

0201

0.22UF

20%

0.22UF

X5R

GND_VOID=TRUE

6.3V 020120%

CA078

6.3V X5R 0201

0.22UF

20%

GND_VOID=TRUE

CA079

6.3V X5R 020120%

0.22UF

GND_VOID=TRUE

CA080

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA081

GND_VOID=TRUE

0201

0.22UF

20% 6.3V X5R

CA082

10 98

GND_VOID=TRUE

6.3V 0201

0.22UF

20% X5R

CA083

6.3V X5R 020120%

GND_VOID=TRUE

0.22UF

CA084

GND_VOID=TRUE

6.3V X5R 020120%

0.22UF

CA085

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

20%

CA086

10 98

GND_VOID=TRUE

0.22UF

020120% X5R6.3V

CA032

GND_VOID=TRUE

0.22UF

X5R20% 02016.3V

CA033

20% 0201X5R

0.22UF

CA035

6.3V

GND_VOID=TRUE

CA034

0.22UF

GND_VOID=TRUE

20% X5R6.3V 0201

6.3V X5R

0.22UF

20% 0201

GND_VOID=TRUE

CA056

6.3V X5R

0.22UF

20%

CA055

0201

GND_VOID=TRUE

6.3V X5R

0.22UF

20% 0201

CA057

GND_VOID=TRUE

10 98

CA059

0.22UF

GND_VOID=TRUE

6.3V X5R 020120%

0.22UF

GND_VOID=TRUE

6.3V X5R 020120%

CA058

0.22UF

GND_VOID=TRUE

6.3V 020120% X5R

CA061

6.3V 0201

0.22UF

20%

CA060

GND_VOID=TRUE

X5R

GND_VOID=TRUE

0201

0.22UF

CA062

X5R20% 6.3V

CA063

0.22UF

GND_VOID=TRUE

X5R 02016.3V20%

X5R

GND_VOID=TRUE

6.3V 020120%

0.22UF

CA064

GND_VOID=TRUE

X5R 020120%

CA065

6.3V

0.22UF

CA066

6.3V X5R 0201

GND_VOID=TRUE

20%

0.22UF

10 98

6.3V X5R 020120%

0.22UF

GND_VOID=TRUE

CA067

X5R 020120%

CA068

GND_VOID=TRUE

0.22UF

6.3V

GND_VOID=TRUE

6.3V X5R 0201

0.22UF

CA069

20%

CA070

6.3V X5R

0.22UF

GND_VOID=TRUE

020120%

18 98

KEPLER PCI-E

SYNC_MASTER=D8_AARON SYNC_DATE=03/13/2012

DP_TBTSNK1_AUXCH_C_N

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_C_N<3>

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

GPU_PEX_TERMP

PEG_R2D_C_N<13>

PEG_R2D_C_P<11>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_R2D_C_N<7>

PEG_R2D_C_P<8>

PEG_R2D_C_N<5>

PEG_R2D_C_P<3>

PEG_R2D_C_N<8>

PEG_R2D_C_P<13>

PEG_R2D_C_P<1>

GPU_RESET_L

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK1_EG_AUXCH_NDP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK0_EG_AUXCH_P

PEG_D2R_N<7>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_P<8>

PEG_D2R_P<9>

PEG_D2R_N<8>

PEG_D2R_N<9>

PEG_D2R_N<10>

PEG_D2R_P<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_N<12>

PEG_D2R_P<12>

PEG_D2R_P<13>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_N<14>

PEG_D2R_N<15>

PEG_R2D_C_N<1>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_R2D_C_P<5>

PEG_R2D_C_P<7>

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

PEG_R2D_C_P<12>

PEG_R2D_C_P<14>

PEG_R2D_C_N<15>

GPU_RESET_R_L

PEG_CLKREQ_L

PEG_D2R_P<6>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_R2D_C_N<4>

PEG_R2D_C_P<4>

PEG_R2D_C_P<15>

PEG_R2D_C_P<10>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_R2D_C_N<12>

PEG_D2R_P<15>

PEG_R2D_C_N<10>

PEG_R2D_C_N<11>

PEG_R2D_C_N<14>

PEG_CLK100M_P

PEG_CLK100M_N

PEX_TSTCLK_O_NG

PEX_TSTCLK_O_PL

=PP3V3_GPU_VDD33

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

PEG_R2D_C_N<10>

PEG_R2D_C_P<10>

PEG_R2D_C_P<11>

PEG_R2D_C_N<11>

PEG_R2D_C_P<12>

PEG_R2D_C_N<12>

PEG_R2D_C_P<13>

PEG_R2D_C_N<13>

PEG_R2D_C_P<15>

PEG_R2D_C_N<14>

PEG_R2D_C_N<15>

PEG_D2R_C_P<8>

PEG_D2R_C_N<8>

PEG_D2R_C_N<9>

PEG_D2R_C_P<9>

PEG_D2R_C_P<10>

PEG_D2R_C_N<10>

PEG_D2R_C_P<11>

PEG_D2R_C_P<12>

PEG_D2R_C_P<13>

PEG_D2R_C_N<12>

PEG_D2R_C_P<14>

PEG_D2R_C_N<13>

PEG_D2R_C_P<15>

PEG_D2R_C_N<15>

PEG_R2D_C_P<14>

PEG_D2R_C_N<11>

PEG_R2D_N<7>

PEG_R2D_P<7>

PEG_R2D_N<6>

PEG_R2D_P<6>

PEG_R2D_P<5>

PEG_R2D_P<4>

PEG_R2D_N<4>

PEG_R2D_N<3>

PEG_R2D_P<3>

PEG_R2D_N<2>

PEG_R2D_P<2>

PEG_R2D_C_N<0>

PEG_R2D_C_P<1>

PEG_R2D_C_N<4>

PEG_R2D_C_N<5>

PEG_R2D_C_P<5>

PEG_R2D_C_N<1>

PEG_R2D_P<10>

PEG_R2D_N<12>

PEG_R2D_P<11>

PEG_R2D_N<11>

PEG_R2D_N<1>

PEG_D2R_N<7>

PEG_D2R_P<6>

PEG_R2D_P<1>

PEG_R2D_N<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_N<0>

PEG_D2R_P<0>

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_D2R_C_N<0>

PEG_D2R_C_P<1>

PEG_D2R_C_N<2>

PEG_D2R_C_P<3>

PEG_D2R_C_P<4>

PEG_D2R_C_N<3>

PEG_D2R_C_P<5>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_P<2>

PEG_D2R_N<10>

PEG_D2R_P<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_N<13>

PEG_D2R_P<13>

PEG_D2R_N<15>

PEG_R2D_P<8>

PEG_D2R_P<14>

PEG_D2R_N<14>

PEG_D2R_P<12>

PEG_D2R_N<12>

PEG_D2R_C_N<6>

PEG_D2R_C_N<7>

PEG_D2R_C_P<7>

PEG_D2R_C_P<6>

PEG_D2R_P<9>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_D2R_N<9>

PEG_D2R_C_P<0>

PEG_R2D_C_N<2>

PEG_R2D_P<15>

PEG_R2D_C_P<0>

PEG_R2D_C_P<4>

PEG_R2D_C_P<2>

PEG_R2D_N<15>

PEG_R2D_P<14>

PEG_R2D_N<14>

PEG_R2D_N<13>

PEG_R2D_P<12>

PEG_R2D_N<10>

PEG_R2D_P<9>

PEG_R2D_C_N<3>

PEG_R2D_N<5>

PEG_D2R_N<4>

PEG_D2R_C_N<1>

PEG_D2R_C_N<14>

PEG_D2R_N<3>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_P<3>

PEG_D2R_N<5>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_N<6>

PEG_D2R_P<15>

PEG_R2D_P<13>

PEG_D2R_P<7>

PEG_R2D_P<0>

PEG_R2D_C_P<3>

PEG_R2D_C_N<7>

PEG_R2D_N<8>

PEG_R2D_N<9>

prefsb

051-9504

7.0.0

80 OF 143

75 OF 117

AG12

AJ14

AK14AN12

AN14

AM18

AK13

AJ11

AK12

AJ12

AL13

AN27

AM27

AP27

AP26

AM24

AN24

AP24

AP23

AM23

AN23

AM21

AN21

AP21

AP20

AN20

AM20

AN18

AP17

AP18

AM17

AN17

AM15

AN15

AP14

AP15

AM14

AK26

AP29

AL25

AK25

AJ26

AJ24

AK24

AG23

AH23

AK23

AJ23

AL22

AK22

AK21

AJ21

AG20

AJ20

AH20

AK20

AL19

AJ18

AK18

AG17

AH17

AK17

AK16

AL16

AK15

AJ15

AG14

AH14

AJ17

AM12

AM26

AN26

AK19

12

1212

21

21 21

21

36

107

36

107

36

107

36

107

75 98

108

75 98

81

81 81

81

75 98

108

78 81 82 83

75 98

75 98 75 98

75 98

NC NC NC NC

NC

NC NC

NC

XVDD

VDD

(10 OF 10)

FBVDDQFBVDDQ

(7 OF 10)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DE-COUPLING IS BASED ON NV DESIGN GUIDELINE DG-05587-001

GPU VCORE DE-COUPLING

Power aliases required by this page:

- =PPVCORE_GPU

- =PP1V35_GPU_FBVDDQ

Page Notes

(NONE)

Signal aliases required by this page:

BOM options provided by this page:

EDP = 30 A

GPU FB DE-COUPLING

EDP = 6500 MA

U8000

OMIT_TABLE

BGA

NV-GK107

U8000

OMIT_TABLE

BGA

NV-GK107

X6S-CERM

0603

22UF

20%

C8179

4V

C8174

4V

22UF

20%

X6S-CERM 0603

X6S 0402

4.7UF

20%

6.3V

C8169

4.7UF

X6S 0402

C8170

6.3V

20%

0402

X6S

4.7UF

C8171

6.3V

20%

C8172

X6S 0402

6.3V

20%

4.7UF

C8173

6.3V

0402

20%

X6S

4.7UF

0402

X6S

6.3V

C8175

20%

4.7UF

C8176

20%

0402

X6S

6.3V

4.7UF

20%

X6S

6.3V

0402

4.7UF

C8177 C8178

0402

X6S

6.3V

20%

4.7UF

20%

0402

X6S

6.3V

4.7UF

C8180

C8181

20%

0402

X6S

6.3V

4.7UF

C8185

20%

0402

X6S

6.3V

4.7UF

0.1UF

10%

X6S 0201

C8191

6.3V

0.1UF

10%

6.3V X6S 0201

C8192

0.1UF

6.3V X6S 0201

C8193

10%

0.1UF

10%

X6S

6.3V

0201

C8194

0201

X6S

6.3V

10%

0.1UF

C8182

0201

X6S

6.3V

10%

0.1UF

C8183

0201

X6S

6.3V

10%

0.1UF

C8198

0201

X6S

6.3V

10%

0.1UF

C8199

0201

X6S

6.3V

10%

0.1UF

C8122

6.3V X6S 0201

10%

0.1UF

C8123

0201

X6S

6.3V

10%

0.1UF

C8124

0201

X6S

6.3V

10%

0.1UF

C8130

X6S 0402

20%

6.3V

4.7UF

C8105 C8106

4.7UF

20%

0402

X6S

6.3V

4.7UF

C8107

20%

0402

X6S

6.3V

20%

47UF

4V X6S 0805

C8161

20%

4V X6S 0805

47UF

C8184 C8162

X6S-CERM 0603

4V

20%

22UF

C8111

1.0UF

20%

4V

X6S 0201

C8112

1.0UF

4V

0201

X6S

20%

1.0UF

20%

4V

X6S 0201

C8113

1.0UF

20%

4V

X6S 0201

C8131

20%

0402

X6S

6.3V

4.7UF

C8166

20%

0402

X6S

6.3V

4.7UF

C8167

X6S

6.3V

0402

20%

4.7UF

C8168

2V POLY CASE-D2-SM

20%

NOSTUFF

330UF-0.006OHM

C8150

CRITICAL

20%

0402

X6S

6.3V

NOSTUFF

4.7UF

C8151

20%

0402

X6S

6.3V

4.7UF

C8152

NOSTUFF

20%

0402

X6S

6.3V

4.7UF

NOSTUFF

C8153

20%

0402

X6S

6.3V

4.7UF

NOSTUFF

C8154

NOSTUFF

4.7UF

6.3V X6S 0402

20%

C8155

C8156

0201

X6S

6.3V

10%

0.1UF

C8157

0201

X6S

6.3V

10%

0.1UF

20%

X6S

6.3V

4.7UF

0402

C8132

0201

X6S

4V

20%

1.0UF

C8158

1.0UF

20%

4V

X6S 0201

C8159

NOSTUFF

4.7UF

6.3V X6S 0402

20%

C8165

NOSTUFF

4.7UF

6.3V X6S 0402

20%

C8163

X6S-CERM 0603

4V

20%

22UF

C8125

X6S-CERM 0603

4V

20%

22UF

C8126

X6S-CERM 0603

4V

20%

22UF

C8127

NOSTUFF

X6S-CERM 0603

4V

20%

22UF

C8128

NOSTUFF

0402

10UF

C8101

X6S

4V

20% 20%

4V X6S

10UF

C8102

0402 0402

NOSTUFF

C8120

10UF

X6S

4V

20% 20%

4V X6S

10UF

C8121

NOSTUFF

0402

SYNC_DATE=04/09/2012

SYNC_MASTER=D8_YAN

KEPLER CORE/FB POWER

=PPVCORE_GPU

=PP1V35_GPU_FBVDDQ=PP1V35_GPU_FBVDDQ

=PPVCORE_GPU

=PP1V35_GPU_FBVDDQ

=PPVCORE_GPU

prefsb

051-9504

7.0.0

81 OF 143

76 OF 117

AA23

AB17

N20

N22

P12

AA7

AA8

AA5

AA6

AA3

AA2

AA4

Y8

AA1

Y6

Y5

Y7

Y3

Y4

Y2

Y1

W8

W4

W5

W7

W3

W2

V8

V7

V6

V5

V4

V3

V1

U8

U7

U6

U4

U5

U1

R20

M23

AC23

AB15

AA19

V18

Y18

AA12

AA14

AA16

AA21

AB13

AB18

AB20

AB22

AC12

AC14

AC16

AC19

AC21

M12

M14

M16

M19

M21

N13

N15

N17

N18

P14

P16

P19

P21

P23

R13

R15

R17

R18

R22

T12

T14

T16

T19

T21

T23

U13

U15

U17

U18

U20

U22

V13

V15

V17

V20

V22

W12

W16

W19

W21

W23

Y13

Y15

Y17

Y20

Y22

V2

U2

U3

W14

Y27

W33

W27

W30

T33

V27

T30

T27

R27

N27

P27

M27

H9

L27

H24

H8

H23

H21

H22

H20

H19

H18

H16

H15

H13

H14

E16

B13

AG27

AF27

H12

H11

H10

E19

E13

B19

AE27

AD27

AB27

AA30

AA27

AC27

AB33

B16

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

76 78 83

76 78 79 80 76 78 79 80

76 78 83

76 78 79 80

76 78 83

OUT

BI

IN

BI

IN

NC NC NC NC NC NC

NC

OUT

NC

NC NC

BI

OUT

NC

NC NC

OUT

NC

NC NC

OUT

D

GS

IN

OUT

FBA_CMD5

FBA_CMD0

FBA_CLK1*

FBA_CLK1

FBA_CLK0*

FB_GND_SENSE

FBA_WCKB67

FBA_D0

FBA_WCKB67*

FBA_WCKB45*

FBA_WCKB23*

FBA_WCKB45

FBA_WCKB01*

FBA_WCKB23

FBA_WCK67*

FBA_WCKB01

FBA_WCK67

FBA_WCK45*

FBA_WCK23*

FBA_WCK45

FBA_WCK01*

FBA_WCK23

FBA_WCK01

FBA_D63

FBA_D62

FBA_D60 FBA_D61

FBA_D57 FBA_D58 FBA_D59

FBA_D56

FBA_D55

FBA_D54

FBA_D52 FBA_D53

FBA_D50 FBA_D51

FBA_D47

FBA_D49

FBA_D48

FBA_D45 FBA_D46

FBA_D42 FBA_D43 FBA_D44

FBA_D40 FBA_D41

FBA_D39

FBA_D37 FBA_D38

FBA_D34 FBA_D35 FBA_D36

FBA_D32 FBA_D33

FBA_D31

FBA_D30

FBA_D29

FBA_D27 FBA_D28

FBA_D24 FBA_D25 FBA_D26

FBA_D22

FBA_D19 FBA_D20

FBA_D16 FBA_D17 FBA_D18

FBA_D14 FBA_D15

FBA_D11 FBA_D12 FBA_D13

FBA_D9 FBA_D10

FBA_D8

FBA_D7

FBA_D6

FBA_D4 FBA_D5

FBA_D3

FBA_D2

FBA_D1

FB_VDDQ_SENSE

FBA_CMD_RFU

FB_CLAMP

FBA_CMD_RFU

FB_CAL_PU_GND

FB_CAL_TERM_GND

FBA_DEBUG

FB_CAL_PD_VDDQ

FBA_PLL_AVDD

FBA_DEBUG

FBA_DQS_WP7

FB_DLL_AVDD

FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6

FBA_DQS_WP3

FBA_DQS_WP2

FBA_DQS_WP1

FBA_DQS_WP0

FBA_DQS_RN7

FBA_DQS_RN6

FBA_DQS_RN5

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN1 FBA_DQS_RN2

FBA_DQS_RN0

FBA_DQM7

FBA_DQM5 FBA_DQM6

FBA_DQM4

FBA_DQM3

FBA_DQM2

FBA_DQM0 FBA_DQM1

FBA_CLK0

FBA_CMD31

FBA_CMD29 FBA_CMD30

FBA_CMD27 FBA_CMD28

FBA_CMD24 FBA_CMD25 FBA_CMD26

FBA_CMD22 FBA_CMD23

FBA_CMD21

FBA_CMD19 FBA_CMD20

FBA_CMD16 FBA_CMD17 FBA_CMD18

FBA_CMD14 FBA_CMD15

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD4

FBA_CMD1

FBA_CMD3

FBA_CMD2

FBA_D23

FBA_D21

FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9

FBA_CMD10

(3 OF 10)

MEM INTERFACE A

FBB_CMD31

FBB_CMD10

FBB_CMD14

FBB_CMD24 FBB_CMD25

FBB_CMD_RFU1

FBB_CMD_RFU0

FBB_D12

FBB_D10

FBB_D7

FBB_D1 FBB_D2 FBB_D3

FBB_CMD16

FBB_DQS_RN4

FBB_DQM4

FBB_CLK1

FBB_CMD22

FBB_CLK0

FBB_CLK0*

FBB_CLK1*

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9

FBB_CMD11 FBB_CMD12 FBB_CMD13

FBB_CMD15

FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21

FBB_CMD23

FBB_CMD26 FBB_CMD27

FBB_CMD29 FBB_CMD30

FBB_D0

FBB_D4 FBB_D5 FBB_D6

FBB_D8 FBB_D9

FBB_D11

FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29

FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DEBUG0 FBB_DEBUG1

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3

FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3

FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

FBB_PLL_AVDD

FBB_WCK01 FBB_WCK01*

FBB_WCK23 FBB_WCK23*

FBB_WCK45 FBB_WCK45*

FBB_WCK67 FBB_WCK67*

FBB_WCKB01*

FBB_WCKB23 FBB_WCKB23*

FBB_WCKB45 FBB_WCKB45*

FBB_WCKB67 FBB_WCKB67*

FB_VREF

FBB_WCKB01

FBB_D31

FBB_D30

FBB_CMD28

(4 OF 10)

MEM INTRERFACE B

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

RDAR://11427653 D8: NV GUIDELINE USES 22UF. APPLE USES 20UF

FB VREF GEN (TEST ONLY)

ESR = 0.05OHM

BOM options provided by this page:

(NONE)

PLACE CLOSE TO BGA

(NONE)

Signal aliases required by this page:

- =PP1V35_GPU_S0_FB

- =PP1V05_GPU_PEX_IOVDD

Power aliases required by this page:

Page Notes

NOTE:GDDR5 MODE H MAPPING

MEM VREFC & VREFD SWITCH

FB PLL & DLL VDD

79

108

79

108

79

108

79

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

PLACE_NEAR=U8000.H26:8.4MM

0.1UF

10%

X5R

NOSTUFF

6.3V

201

C8260

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

PLACE_NEAR=U8000.H25:8.4MM

MF

201

1%

1/20W

60.4

R8201

PLACE_NEAR=U8000.H27:8.4MM

201

MF

1%

1/20W

40.2

R8204

PLACE_NEAR=U8000.J27:8.4MM

40.2

201

MF

1/20W

1%

R8205

MF

60.4

201

1/20W

1%

NOSTUFF

R8202

1%

1/20W

MF

201

60.4

NOSTUFF

R8203

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

10K

1%

1/20W

MF

201

R8250

10K

1%

1/20W

MF

201

R8251

MF

1/20W

201

1%

10K

R8252

1/20W

10K

MF

201

1%

R8253

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

NOSTUFF

60.4

201

1%

1/20W

MF

R8207

NOSTUFF

60.4

1%

1/20W

201

MF

R8206

201

MF

1%

10K

1/20W

R8255

1/20W

1%

10K

201

MF

R8254

NOSTUFF

PLACE_NEAR=U8000.H26:8.4MM

MF

1.33K

1%

1/20W

201

R8258

PLACE_NEAR=U8000.H26:8.4MM

MF

201

1/20W

1%

1.33K

NOSTUFF

R8259

201

10K

MF 1%

1/20W

R8261

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

77 79

108

77 79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

79

108

77 79

108

77 79

108

79

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

77 80

108

77 80

108

80

108

80 108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

80

108

77 80

108

80

108

77 80

108

80

108

VESM

SSM3K15AMFVAPE

CRITICAL

Q8265

82 113

79 80

1/20W MF 201

100

5%

R8270

NOSTUFF

201

MF

5%

100

1/20W

R8271

NOSTUFF

NV-GK107

OMIT_TABLE

BGA

U8000

NV-GK107

OMIT_TABLE

BGA

U8000

10K

1%

MF

1/20W

201

R8256

10K

201

MF

1/20W

1%

R8257

78

CRITICAL

L8201

30-OHM-25%-5A-0.01-OHM

0603

L8202

30-OHM-25%-5A-0.01-OHM

0603

CRITICAL

5%

10K

1/20W MF 201

R8260

1.0UF

C8202

20% 4V X6S 0201

X6S

C8209

1.0UF

20% 4V

0201

0.1UF

C8203

0201

X6S

6.3V

10% 10%

C8204

0201

0.1UF

X6S

6.3V

C8205

0201

0.1UF

X6S

6.3V

10%

C8206

0201

X6S

4V

20%

1.0UF

C8207

0.1UF

10%

6.3V X6S 0201

20% 4V

C8201

20UF

X5R-CERM

0402

20%

X5R-CERM

4V

0402

C8208

20UF

SYNC_DATE=05/15/2012

KEPLER FRAME BUFFER I/F

SYNC_MASTER=D8_YAN

PP1V05_GPU_FB_PLL_AVDD

FB_B1_EDC<1>

FB_B1_EDC<3>

=PP1V35_GPU_S0_FB

FB_B1_WCLK_N<1>

FB_B0_EDC<3>

FB_CAL_TERM_GND

GPU_FBA_DEBUG1

=PP1V35_GPU_S0_FB

FB_A1_CKE_L

FB_B1_A<0>

=PP1V35_GPU_S0_FB

GPU_ALT_VREF

FB_B1_DQ<25>

FB_B1_CLK_N

FB_B1_A<7>

FB_B0_DQ<22>

FB_B0_RAS_L

FB_B1_DQ<5>

FB_B1_CKE_L

=PP1V35_GPU_S0_FB

FB_A1_WCLK_P<0>

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B0_CKE_L

FB_B1_RESET_L

FB_B0_RESET_L

FB_A1_DQ<4>

FB_A1_DQ<6>

FB_A1_DQ<11>

FB_A1_DQ<14>

FB_A0_DBI_L<2>

FB_CLAMP

FB_B1_DQ<3>

GPU_FBB_DEBUG0

GPU_FBB_DEBUG1

FB_A0_DQ<6>

FB_A1_A<4>

FB_A1_A<5>

FB_A0_CKE_L

FB_B0_DQ<9>

FB_B0_DQ<8>

FB_A0_WE_L

FB_A0_A<5>

FB_A0_A<4>

FB_A0_A<2>

FB_A0_A<3>

FB_A0_CS_L

FB_A0_CKE_L

FB_A0_CAS_L

FB_A0_DBI_L<1>

FB_A0_EDC<0>

FB_B1_A<1>

FB_A1_WE_L

FB_A0_DQ<16>

FB_A0_DQ<17>

FB_A0_ABI_L

FB_A0_DQ<10>

FB_A0_DQ<11>

FB_A0_DQ<20>

FB_A0_DQ<23>

FB_A0_DQ<28>

FB_A0_RESET_L

FB_VREF

FB_A1_RESET_L

FB_A0_A<8>

FB_A0_A<6>

FB_A0_A<7>

FB_A0_DQ<21>

FB_A0_A<1>

FB_A0_RAS_L

FB_A0_RESET_L

FB_A1_A<2>

FB_A1_A<3>

FB_A1_CS_L

FB_A1_A<0>

FB_A1_A<8>

FB_A1_ABI_L

FB_A1_RAS_L

FB_A1_A<1>

FB_A1_CKE_L

FB_A1_RESET_L

FB_A0_DBI_L<0>

FB_A0_DBI_L<3>

FB_A1_DBI_L<0>

FB_A1_DBI_L<1>

FB_A1_DBI_L<3>

FB_A0_EDC<1>

FB_A0_EDC<3>

FB_A1_EDC<0>

FB_A1_EDC<3>

PP1V05_GPU_FB_PLL_AVDD

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_A0_DQ<2>

FB_A0_DQ<3>

FB_A0_DQ<5>

FB_A0_DQ<4>

FB_A0_DQ<13>

FB_A0_DQ<12>

FB_A0_DQ<15>

FB_A0_DQ<14>

FB_A0_DQ<18>

FB_A0_DQ<19>

FB_A0_DQ<22>

FB_A0_DQ<24>

FB_A0_DQ<27>

FB_A0_DQ<29>

FB_A0_DQ<30>

FB_A0_DQ<31>

FB_A1_DQ<1>

FB_A1_DQ<0>

FB_A1_DQ<2>

FB_A1_DQ<5>

FB_A1_DQ<7>

FB_A1_DQ<9>

FB_A1_DQ<8>

FB_A1_DQ<12>

FB_A1_DQ<10>

FB_A1_DQ<13>

FB_A1_DQ<16>

FB_A1_DQ<17>

FB_A1_DQ<15>

FB_A1_DQ<19>

FB_A1_DQ<18>

FB_A1_DQ<21>

FB_A1_DQ<20>

FB_A1_DQ<22>

FB_A1_DQ<23>

FB_A1_DQ<24>

FB_A1_DQ<27>

FB_A1_DQ<26>

FB_A1_DQ<25>

FB_A1_DQ<29>

FB_A1_DQ<28>

FB_A1_DQ<31>

FB_A0_WCLK_P<0>

FB_A0_WCLK_P<1>

FB_A0_WCLK_N<0>

FB_A0_WCLK_N<1>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

FB_A0_CLK_N

FB_A1_CLK_P

FB_B0_DQ<30>

FB_B1_WCLK_P<1>

FB_B1_WCLK_P<0>

FB_B0_WCLK_N<1>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<0>

FB_B1_EDC<2>

FB_B1_EDC<0>

FB_B0_EDC<2>

FB_B0_EDC<1>

FB_B0_EDC<0>

FB_B1_DBI_L<3>

FB_B1_DBI_L<2>

FB_B0_DBI_L<2>

FB_B0_DBI_L<1>

FB_B0_DBI_L<0>

GPU_FBB_DEBUG1

FB_B1_DQ<30>

FB_B1_DQ<29>

FB_B1_DQ<28>

FB_B1_DQ<27>

FB_B1_DQ<26>

FB_B1_DQ<24>

FB_B1_DQ<23>

FB_B1_DQ<22>

FB_B1_DQ<20>

FB_B1_DQ<17>

FB_B1_DQ<16>

FB_B1_DQ<9>

FB_B1_DQ<8>

FB_B1_DQ<7>

FB_B1_DQ<6>

FB_B1_DQ<4>

FB_B1_DQ<2>

FB_B0_DQ<29>

FB_B0_DQ<28>

FB_B0_DQ<27>

FB_B0_DQ<26>

FB_B0_DQ<24>

FB_B0_DQ<23>

FB_B0_DQ<20>

FB_B0_DQ<19>

FB_B0_DQ<18>

FB_B0_DQ<17>

FB_B0_DQ<16>

FB_B0_DQ<15>

FB_B0_DQ<14>

FB_B0_DQ<11>

FB_B0_DQ<6>

FB_B0_DQ<5>

FB_B0_DQ<4>

FB_B0_DQ<0>

FB_B1_CKE_L

FB_B1_RESET_L

FB_B1_WE_L

FB_B1_A<5>

FB_B1_A<4>

FB_B1_A<2>

FB_B0_A<8>

FB_B0_ABI_L

FB_B0_WE_L

FB_B0_A<3>

FB_B0_CS_L

FB_B1_CLK_P

FB_B1_CS_L

FB_B0_DQ<3>

FB_B0_DQ<2>

FB_B0_DQ<1>

FB_B0_DQ<7>

FB_B0_DQ<10>

FB_B0_DQ<12>

FB_B1_ABI_L

FB_B0_CKE_L

FB_A1_DQ<30>

FB_B1_DQ<19>

FB_B1_DQ<18>

FB_B1_DQ<15>

FB_B1_DQ<13>

FB_B1_DQ<14>

FB_A0_DQ<25>

FB_A1_CLK_N

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A0_DQ<26>

FB_B0_DQ<25>

FB_B0_A<0>

FB_B0_A<6>

FB_B0_A<7>

FB_B0_A<5>

FB_B0_A<4>

FB_B0_A<2>

FB_B1_DQ<10>

GPU_FBB_DEBUG0

FB_VREF

FB_B1_RAS_L

FB_B0_DQ<21>

FB_A0_DQ<9>

FB_A0_DQ<7>

FB_A1_DBI_L<2>

FB_A1_CAS_L

FB_B1_DQ<12>

FB_A0_CLK_P

FB_A1_A<6>

FB_A0_DQ<0>

FB_B0_A<1>

FB_B1_A<6>

FB_A0_DQ<1>

FB_SW_LEG

FB_B1_WCLK_N<0>

FB_B0_WCLK_P<1>

FB_B1_DQ<31>

FB_B1_DQ<11>

FB_B0_DBI_L<3>

FB_A0_DQ<8>

FB_A0_A<0>

GPU_FBA_DEBUG0

PP1V05_GPU_FB_DLL_AVDD

FB_B1_DQ<21>

FB_A0_EDC<2>

=PP1V35_GPU_S0_FB

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

SNS_GPUVDDQ_N

SNS_GPUVDDQ_P

FB_A1_A<7>

FB_B1_A<8>

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_GPU_FB_DLL_AVDD

=PP1V05_GPU_PEX_IOVDD

FB_B0_DQ<13>

=PP1V35_GPU_S0_FB

FB_B0_DQ<31>

FB_B1_DQ<1>

FB_B1_DQ<0>

FB_B1_A<3>

FB_B0_CAS_L

PP1V05_GPU_FB_PLL_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

=PP1V05_GPU_PEX_IOVDD

FB_A1_DQ<3>

FB_B0_CLK_N

FB_B0_CLK_P

FB_B1_CAS_L

prefsb

051-9504

7.0.0

82 OF 143

77 OF 117

2

1

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

3

1

2

1

2

U32

U30

AC31

AB31

R31

F2

AJ32

L28

AJ33

AJ31

J33

AH31

J31

J32

AK34

J30

AJ34

AG31

J34

AG30

L30

H34

K31

AG33

AG32

AF31

AG34

AD32

AC30

AD33

AD34

AK32

AK33

AM33

AL31

AP30

AP32

AM30

AN32

AN31

AM31

AN29

AJ30

AK28

AM29

AJ29

AK29

AD28

AD29

AC29

AG29

AF28

AD30

AG28

AF29

L33

L32

L34

P33

L31

P34

P32

P31

H33

C33

F33

C34

D32

B33

E32

F30

H28

G29

E31

H29

J29

J28

P28

R29

N31

P29

M28

L29

M29

F1

AC32

E1

R32

H27

H25

AC28

J27

U27

R28

AF33

K27

AE31

AK30

AN33

M33

E33

G31

M31

AF32

AM34

AK31

AF30

M34

H30

E34

M30

AF34

AL29

AM32

AD31

M32

F34

P30

F31

R30

V31

Y34

Y33

AA34

Y31

Y29

W31

Y30

AA33

Y28

AA32

AC34

AC33

AA31

AA29

AA28

V33

Y32

V34

U31

U34

R33

T31

R34

U29

H32

F32

U33

U28

V28

V29

V30

E17

D15

B15

G17

F17

C20

C12

F4

E6

G12

E9

G8

F9

D18

D22

F23

E20

B18

D12

E12

F20

D13

E14

F14

A12

B12

C14

B14

G15

F15

E15

A14

D14

A15

C17

E18

F18

A20

B20

C18

G18

D16

A18

A17

B17

G9

F11

G11

F12

G6

F5

F6

G4

E2

F3

C2

D4

D3

C1

B3

C4

B5

C5

A11

C11

D11

B11

D8

A8

F24

G23

E24

G24

D21

E21

G21

F21

G27

D27

G26

E27

E29

F29

E30

D30

A32

C31

C32

B32

D29

A29

C29

B29

B21

C23

A21

C21

B24

C24

B26

C26

G14

G20

E11

E3

A3

C9

F27

C30

A24

D9

E4

B2

A9

D28

A30

B23

D10

D5

C3

B9

E23

E28

B30

A23

H17

F8

E8

A5

A6

D24

D25

B27

C27

D7

C6

B6

F26

E26

A26

A27

H26

D6

B8

C8

D17

1

2

1

2

21

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

77 78

108

77 78

77 79

108

77 78

77 80

108

77 78

77 80

108

77 80

108

77 80

108

77

77 79

108

77 79

108

77

113

77 79

108

77

115

77

108

77 108

77

113

77

115

77 78

77

108

77

108

77

115

77 78 83

77 78

77

115

77 78 83

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU SIGNAL & SENSE ALIAS

GPU POWER ALIAS

THESE POWER ALIASES ARE CRAETED TO MATCH D8 GK104

PU/PD IS BASED ON RECOMMENDATION FROM NV FOR NVDIA GPU JTAG DEBUGGER

GPU VIDS ALIAS (VR VID0 IS TIED LOW)

0

5%

RA850

MF

1/20W

201

0

1/20W

201

5%

RA851

MF

5%

0

MF

1/20W

201

RA852

5%

0

MF

1/20W

201

RA853

0

5%

RA854

MF

201

1/20W

5%

0

RA855

MF

1/20W

201

RA863

180

1/16W

5%

MF-LF

402

10K

RA862

MF

5%

1/20W

201

RA861

10K

201

5%

1/20W

MF

201

1%

1/20W

270

RA864

RA860

MF

1/20W

5%

201

10K

NOSTUFF

SYNC_DATE=04/09/2012

SYNC_MASTER=D8_YAN

GPU SIGNAL & POWER ALIASES

REG_GPUCORE_VID2

REG_GPUCORE_VID6

GPU_JTAG_TDO

=PP1V05_GPU_IFPCD_IOVDD

GPU_JTAG_TDI

GPU_JTAG_TCK

GPU_JTAG_TMS

GPU_TDIODE_P

SNS_GPUVDDQ_N

SNS_GPUVDDQ_P

GPU_TDIODE_N

=PP3V3_S0_GPU_IFPX_PLLVDD

=PP1V05_GPU_IFPEF_IOVDD

=PP1V35_S0_GPU_FBVDDQ

=PP1V35_GPU_S0_FB

GPU_VCORE_VID0

GPU_VDD_SENSE

GPU_GND_SENSE

REG_GPUCORE_VID3

GPU_VCORE_VID2

=PP3V3_S0_GPU_MISC

=PP3V3_S0_GPU_VDD33

=PPVCORE_S0_GPU

=PP3V3_GPU_IFPX_PLLVDD

=PP1V05_S0_GPU_IFPEF_IOVDD

=PP1V05_GPU_PEX_IOVDD

GPU_VCORE_VID5

REG_GPUCORE_VID5

GPU_VCORE_VID4

GPU_VCORE_VID3

GPU_VCORE_VID1

REG_GPUCORE_VID1

=PP3V3_GPU_MISC

=PP1V05_S0_GPU_PEX_PLLVDD

REG_GPUCORE_VID4

=PP1V05_S0_GPU_PEX_IOVDD

=PP3V3_GPU_VDD33

=PPVCORE_GPU

=PP1V05_S0_GPU_IFPCD_IOVDD

=PP1V35_GPU_FBVDDQ

=PP1V05_GPU_PEX_PLLVDD

VSNS_FBVDDQ_N

MAKE_BASE=TRUE

VSNS_FBVDDQ_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_TDIODEP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_TDIODEN

VSNS_GPU_VDD

MAKE_BASE=TRUE

VSNS_GPU_VSS

MAKE_BASE=TRUE

=PP3V3_S0_GPU

prefsb

051-9504

7.0.0

83 OF 143

78 OF 117

12

1

2

1

2

1

2

1

2

1

2

92

110

92

110

81

113

81

113

81

108

81

113

81

77

81

6

81

6

77

82

110

83

92

110

82

110

6

51

81

6

77 83

82

110

92

110

82

110

82

110

82

110

92

110

81

6

92

110

6

75 81 82 83

76 83

6

76 79 80

81 83

95

110

95

110

92

110

92

110

6

92

A11/A6

SEN

WCK01*

WCK01

EDC3

EDC0

A10/A0

DQ0

DQ13

DQ12

DQ24

CK

A9/A1

BA1/A5 BA2/A4

CAS*

CK*

CKE*

CS*

DQ9

DQ11

DQ14

DQ16

DQ19

DQ23

DQ25 DQ26 DQ27

DQ31

EDC1 EDC2

MF

RAS*

WCK23 WCK23*

WE*

ZQ

BA0/A2

DQ28 DQ29

DQ22

DQ21

DQ17

DQ15

DQ10

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DBI3*

DBI0*

DBI2*

DBI1*

BA3/A3

A8/A7

ABI*

RESET*

DQ18

DQ20

NC

A12/RFU/NC

DQ30

NC

(MF=1)

(1 OF 2)

IN IN

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

MF SEN

CAS*

A11/A6

BA1/A5

DQ29

WCK01*

WCK23 WCK23*

RESET*

EDC1 EDC2

NC

DQ28

A10/A0

CKE*

BA0/A2

DQ3 DQ4 DQ5 DQ6

DQ8

DQ9 DQ10 DQ11

BA3/A3

BA2/A4

WE*

DBI2*

A9/A1

A8/A7

CK*

DQ30

ABI*

CK

CS*

DBI1*

DBI3*

DQ0

DQ1

DQ2

DQ7

DQ12

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ25 DQ26

EDC0

EDC3

RAS*

DQ13

DQ15

DQ27

DBI0*

DQ14

DQ31

DQ24

WCK01

ZQ

A12/RFU/NC

NC

(1 OF 2)

(MF=0)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

NC

BI

IN

BI

IN

BI

IN

BI

IN

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Signal aliases required by this page:

PLACE CLOSE TO U8400

Page Notes

- =PP1V5R1V35_S0_FB_VDD

Power aliases required by this page:

PLACE CLOSE TO U8450

This memory device is in Mirrored Mode.

CK TERMINATION - A0

BOM options provided by this page:

(NONE)

CK TERMINATION - A1

C8400

6.3V

4.7UF

X5R 402

20%

FBA

X5R

C8401

4.7UF

402

20%

6.3V

FBA

C8402

X5R 402

20%

6.3V

FBA

4.7UF

C8403

4.7UF

X5R 402

20%

6.3V

FBA

C8404

4.7UF

X5R 402

20%

6.3V

FBA

4.7UF

20%

C8405

X5R 402

6.3V

FBA

C8450

4.7UF

X5R 402

20%

6.3V

FBA

6.3V

C8451

4.7UF

X5R 402

20%

FBA

C8452

4.7UF

X5R 402

20%

6.3V

FBA

C8453

4.7UF

X5R 402

20%

6.3V

FBA

C8454

4.7UF

X5R 402

20%

6.3V

FBA

C8455

4.7UF

X5R 402

20%

6.3V

FBA

R8400

1/20W

FBA

MF

201

1%

120

R8450

120

MF

201

1%

1/20W

FBA

U8450

OMIT_TABLE

32MX32-1.5GHZ-MFH

K4G10325FG-HC03

BGA

1%

201

FBA

R8401

40.2

1/20W

MF

PLACE_NEAR=U8400.J12:8.4MM

MF

1/20W

PLACE_NEAR=U8450.J12:8.4MM

FBA

R8451

1%

40.2

201

R8402

201

MF

1%

1/20W

FBA

40.2

PLACE_NEAR=U8400.J11:8.4MM

PLACE_NEAR=U8450.J11:8.4MM

R8452

40.2

MF

201

1%

1/20W

FBA

PLACE_NEAR=U8400.J14:8.4MM

FBA

R8434

931

MF 201

1% 1/20W

PLACE_NEAR=U8400.J14:8.4MM

MF

R8430

549

201

1% 1/20W

FBA

PLACE_NEAR=U8400.J14:8.4MM

R8431

1/20W

1.33K

MF 201

1%

FBA

77 79 80

PLACE_NEAR=U8450.J14:8.4MM

1/20W

R8481

MF 201

1%

1.33K

FBA

77 79 80

PLACE_NEAR=U8450.J14:8.4MM

R8484

MF 201

931

1% 1/20W

FBA

PLACE_NEAR=U8450.J14:8.4MM

R8480

549

MF

1% 1/20W

201

FBA

PLACE_NEAR=U8400.U10:16MM

R8432

549

MF 201

1% 1/20W

FBA

77 79 80

PLACE_NEAR=U8400.U10:20MM

1/20W MF 201

1%

931

R8435

FBA

1%

MF 201

1/20W

1.33K

R8433

FBA

PLACE_NEAR=U8400.U10:20MM

1.33K

PLACE_NEAR=U8450.U10:8.4MM

201

R8483

MF

1% 1/20W

FBA

77 79 80

1%

PLACE_NEAR=U8450.U10:8.4MM

201

FBA

R8485

931

MF

1/20W

PLACE_NEAR=U8450.U10:8.4MM

R8482

549

MF

1% 1/20W

201

FBA

C8456

1UF

X5R 0201

20%

6.3V

FBA

C8457

1UF

X5R 0201

20%

6.3V

FBA

C8458

1UF

X5R 0201

20%

6.3V

FBA

C8459

1UF

X5R 0201

20%

6.3V

FBA

20%

C8460

1UF

X5R 0201

6.3V

FBA

C8461

1UF

X5R 0201

20%

6.3V

FBA

C8462

1UF

X5R 0201

20%

6.3V

FBA

C8463

1UF

X5R 0201

20%

6.3V

FBA

0201

C8464

1UF

X5R

20%

6.3V

FBA

C8465

1UF

X5R 0201

20%

6.3V

FBA

C8406

1UF

X5R 0201

20%

6.3V

C8407

1UF

X5R 0201

20%

6.3V

FBA

C8408

1UF

X5R 0201

20%

6.3V

FBA

C8409

1UF

X5R 0201

20%

6.3V

FBA

C8410

X5R 0201

20%

6.3V

1UF

FBA

C8411

1UF

X5R 0201

20%

6.3V

FBA

C8412

1UF

X5R 0201

20%

6.3V

FBA

C8413

1UF

X5R 0201

20%

6.3V

FBA

C8414

1UF

X5R 0201

20%

6.3V

FBA

C8415

1UF

X5R 0201

20%

6.3V

FBA

U8450

OMIT_TABLE

K4G10325FG-HC03

32MX32-1.5GHZ-MFH

BGA

R8454

201

5%

1K

MF

1/20W

FBA

1/20W

1K

FBA

MF

5%

201

R8404

201

FBA

1/20W

MF

1K

5%

R8403

FBA

1/20W

MF

1K

5%

201

R8453

0201

10V

10%

X5R-CERM

0.01UF

C8490

FBA

PLACE_NEAR=U8400.J11:8.4MM

PLACE_NEAR=U8450.J11:8.4MM

FBA

0201

X5R-CERM

10V

10%

0.01UF

C8491

PLACE_NEAR=U8400.J14:8.4MM

0402

CERM

50V

10%

820PF

FBA

C8431

PLACE_NEAR=U8400.A10:8.4MM

0402

C8432

FBA

820PF

50V CERM

10%

C8433

CERM

PLACE_NEAR=U8400.U10:8.4MM

0402

FBA

820PF

50V

10%

PLACE_NEAR=U8450.A10:20MM

0402

FBA

820PF

C8482

50V CERM

10%

PLACE_NEAR=U8450.J14:8.4MM

0402

C8481

CERM

50V

10%

820PF

FBA

PLACE_NEAR=U8450.U10:20MM

C8483

0402

10%

CERM

50V

820PF

FBA

U8400

OMIT_TABLE

32MX32-1.5GHZ-MFL

K4G10325FG-HC03

BGA

U8400

32MX32-1.5GHZ-MFL

K4G10325FG-HC03

OMIT_TABLE

BGA

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77 79

108

77 79

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

C8416

0.1UF

X5R 201

10%

6.3V

FBA

C8417

0.1UF

X5R 201

10%

6.3V

FBA

C8418

0.1UF

X5R 201

10%

6.3V

FBA

C8419

0.1UF

X5R 201

10%

6.3V

FBA

C8420

0.1UF

X5R 201

10%

6.3V

FBA

C8421

0.1UF

X5R 201

10%

6.3V

FBA

C8422

0.1UF

X5R 201

10%

6.3V

FBA

C8423

0.1UF

X5R 201

10%

6.3V

FBA

C8424

0.1UF

X5R 201

10%

6.3V

FBA

C8425

0.1UF

X5R 201

10%

6.3V

FBA

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77 79

108

77 79

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

C8467

0.1UF

X5R 201

10%

6.3V

FBA

C8466

0.1UF

X5R 201

10%

6.3V

FBA

C8471

0.1UF

X5R 201

10%

6.3V

FBA

0.1UF

C8475

X5R 201

10%

6.3V

FBA

C8470

0.1UF

X5R 201

10%

6.3V

FBA

0.1UF

C8474

X5R 201

10%

6.3V

FBA

X5R

C8469

0.1UF

201

10%

6.3V

FBA

0.1UF

C8473

X5R 201

10%

6.3V

FBA

X5R

C8468

0.1UF

201

10%

6.3V

FBA

201

X5R

6.3V

10%

0.1UF

C8472

FBA

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

SYNC_DATE=04/09/2012

GDDR5 Frame Buffer A

SYNC_MASTER=D8_YAN

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A0_VREFD

FB_SW_LEG

FB_A0_CK_MID

FB_A0_EDC<1>

FB_A1_CK_MID

FB_A0_A<4>

FB_A0_A<2>

FB_A0_CAS_L

FB_A1_EDC<3>

FB_A1_VREFC

FB_A1_DBI_L<1>

FB_A1_DQ<9>

FB_A1_DQ<14>

FB_A1_DQ<15>

FB_A1_DQ<11>

FB_A1_DQ<10>

FB_A1_DQ<18>

FB_A1_DQ<19>

FB_A1_DQ<20>

FB_A1_A<6>

FB_A1_EDC<0>

FB_A1_DQ<24>

FB_A1_CLK_P

FB_A1_A<1>

FB_A1_A<5>

FB_A1_A<4>

FB_A1_CLK_N

FB_A1_CS_L

FB_A1_DQ<16>

FB_A1_DQ<23>

FB_A1_DQ<25>

FB_A1_DQ<27>

FB_A1_DQ<31>

FB_A1_EDC<1>

FB_A1_EDC<2>

FB_A1_RAS_L

FB_A1_WCLK_P<1>

FB_A1_WCLK_N<1>

FB_A1_WE_L

FB_A1_A<2>

FB_A1_DQ<28>

FB_A1_DQ<29>

FB_A1_DQ<22>

FB_A1_DQ<17>

FB_A1_DQ<8>

FB_A1_DQ<7>

FB_A1_DQ<5>

FB_A1_DQ<4>

FB_A1_DQ<3>

FB_A1_DBI_L<3>

FB_A1_DBI_L<0>

FB_A1_DBI_L<2>

FB_A1_A<3>

FB_A1_A<7>

FB_A1_A<8>

FB_A1_DQ<30>

=PP1V35_GPU_FBVDDQ

FB_SW_LEGFB_SW_LEG

FB_A1_CAS_L

FB_A1_WCLK_P<0>

FB_A1_DQ<26>

FB_A1_DQ<21>

FB_A1_WCLK_N<0>

FB_A1_CKE_L

FB_A1_A<0>

FB_A0_WCLK_P<0>

FB_A0_DQ<31>

FB_A0_DBI_L<0>

FB_A0_DQ<27>

FB_A0_DQ<13>

FB_A0_RAS_L

FB_A0_EDC<3>

FB_A0_DQ<26>

FB_A0_DQ<18>

FB_A0_DQ<12>

FB_A0_DQ<7>

FB_A0_DQ<2>

FB_A0_DQ<1>

FB_A0_DQ<0>

FB_A0_DBI_L<3>

FB_A0_DBI_L<1>

FB_A0_CS_L

FB_A0_DQ<30>

FB_A0_A<1>

FB_A0_DBI_L<2>

FB_A0_WE_L

FB_A0_A<3>

FB_A0_DQ<11>

FB_A0_DQ<10>

FB_A0_DQ<9>

FB_A0_DQ<8>

FB_A0_DQ<6>

FB_A0_DQ<5>

FB_A0_DQ<4>

FB_A0_DQ<3>

FB_A0_A<0>

FB_A0_DQ<28>

FB_A0_RESET_L

FB_A0_DQ<29>

FB_A0_A<6>

FB_A0_VREFC

FB_A0_VREFD

FB_A0_CLK_N

FB_A1_DQ<6>

FB_A1_DQ<2>

FB_A1_DQ<1>

FB_A1_DQ<0>

FB_A0_CLK_N

FB_A0_CKE_L

FB_A0_WCLK_P<1>

=PP1V35_GPU_FBVDDQ

FB_A1_VREFD

FB_A0_DQ<14>

FB_A0_DQ<15>

FB_A0_DQ<16>

FB_A0_DQ<17>

FB_A0_DQ<19>

FB_A0_DQ<20>

FB_A0_DQ<21>

FB_A0_DQ<22>

FB_A0_DQ<23>

FB_A0_DQ<24>

FB_A0_DQ<25>

=PP1V35_GPU_FBVDDQ

FB_A1_DQ<12>

FB_A1_DQ<13>

FB_A1_CLK_N

FB_A0_A<7>

FB_A0_A<5>

FB_A0_CLK_P

FB_A0_SEN

FB_A0_ABI_L

FB_A0_EDC<0>

FB_A0_EDC<2>

FB_A1_CLK_P

FB_A0_CLK_P

FB_A0_ZQ

FB_A0_MF

FB_A0_WCLK_N<0>

FB_A0_WCLK_N<1>

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_A0_VREFC

FB_A0_A<8>

=PP1V35_GPU_FBVDDQ

FB_A1_ZQ

FB_A1_MF

FB_A1_SEN

FB_A1_RESET_L

FB_A1_ABI_L

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_A1_VREFC

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_A1_VREFD

prefsb

051-9504

7.0.0

84 OF 143

79 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

H5

J10

P5

P4

C2

R2

K4

U4

N13

N11

A4

J12

K5

H10 H11

G3

J11

J3

L12

U13

T13

M11

A11

B13

F13

A2 B4 B2

F2

R13 C13

J1

L3

D4 D5

G12

J13

K11

E4 E2

F11

E13

A13

M13

T11

U11

M2

M4

N2

N4

T2

T4

U2

D2

P2

D13

P13

K10

H4

J4

J2

B11

E11

A5 J5

F4

U5

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

C12

C11

C4

C3

C1

A14

U14

U12

U3

U1

R14

R12

R11

A12

R4

R3

R1

N14

N12

N3

N1

M10

M5

K13

A3

K2

H13

H2

F10

E14

E12

E3

E1

C14

A1

K14

K1

H14

H1

G10

G5

D10

B10

T10

T5

P10

L10

L5

B5

U10

A10

J14

E5

D14

D12

D3

D1

B14

T14

T12

T3

T1

P14

P12

P3

B12

P1

N10

M14

F14

F12

F3

F1

E10

B1

L4

L1

G14

G11

G4

G1

D11

C10

R10

R5

P11

L14

L11

N5

M12

M3

M1

L13

L2

K12

B3

K3

H12

H3

G13

G2

F5

C5

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

J1

J10

L3

K5

K10

N2

D5

P4 P5

J2

C13 R13

U5

N4

H4

J3

H11

B2 E4 E2 F4

A11 A13 B11 B13

H10

K11

L12

P13

H5

K4

J11

M4

J4

J12

G12

D13

P2

A4 A2 B4

F2

E11

U11 U13 T11 T13 N11 N13 M11 M13

U2 T4

C2

R2

G3

E13

F13

T2

D2

F11

M2

U4

D4

J13

J5

A5

U14

U12

U3

U1

R14

R12

R11

R4

R3

R1

N14

N12

N3

N1

M10

M5

K13

K2

H13

H2

F10

F5

E1

C14

C11

C4

C3

C1

A14

A1

T10

T5

P10

L10

L5

K14

K1

H14

H1

G10

G5

D10

B10

B5

U10

A10

J14

T14

T12

T3

T1

P14

P12

P3

P1

N10

N5

M14

M12

M3

M1

L13

L2

K12

K3

H12

H3

G13

G2

F14

F12

F3

F1

E10

E5

D14

D12

D3

D1

R10

R5

P11

L14

L11

L4

L1

G14

G11

G4

G1

D11

C10

C5

B1

B3 B12 B14

A12

A3

E12 E14

E3

C12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

79

113

108

79

113

76 78 79 80

79

113

79

113

77 79

108

76 78 79 80

79

113

76 78 79 80

77 79

108

77 79 108

79

113

76 78 79 80

79

113

76 78 79 80

79

113

IN

BI

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

MF SEN

CAS*

A11/A6

BA1/A5

DQ29

WCK01*

WCK23 WCK23*

RESET*

EDC1 EDC2

NC

DQ28

A10/A0

CKE*

BA0/A2

DQ3 DQ4 DQ5 DQ6

DQ8

DQ9 DQ10 DQ11

BA3/A3

BA2/A4

WE*

DBI2*

A9/A1

A8/A7

CK*

DQ30

ABI*

CK

CS*

DBI1*

DBI3*

DQ0

DQ1

DQ2

DQ7

DQ12

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

DQ25 DQ26

EDC0

EDC3

RAS*

DQ13

DQ15

DQ27

DBI0*

DQ14

DQ31

DQ24

WCK01

ZQ

A12/RFU/NC

NC

(1 OF 2)

(MF=0)

BI

NC

BI

IN

BI

IN

BI

IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI

IN

NC

A11/A6

SEN

WCK01*

WCK01

EDC3

EDC0

A10/A0

DQ0

DQ13

DQ12

DQ24

CK

A9/A1

BA1/A5 BA2/A4

CAS*

CK*

CKE*

CS*

DQ9

DQ11

DQ14

DQ16

DQ19

DQ23

DQ25 DQ26 DQ27

DQ31

EDC1 EDC2

MF

RAS*

WCK23 WCK23*

WE*

ZQ

BA0/A2

DQ28 DQ29

DQ22

DQ21

DQ17

DQ15

DQ10

DQ8

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DBI3*

DBI0*

DBI2*

DBI1*

BA3/A3

A8/A7

ABI*

RESET*

DQ18

DQ20

NC

A12/RFU/NC

DQ30

NC

(MF=1)

(1 OF 2)

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

This memory device is in Mirrored Mode.

- =PP1V5R1V35_S0_FB_VDD

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

(NONE)

CK TERMINATION - B1

PLACE CLOSE TO U8500

PLACE CLOSE TO U8550

CK TERMINATION - B0

(NONE)

77

108

77

108

C8500

6.3V

20%

402

X5R

4.7UF

FBB

C8501

6.3V

20%

402

X5R

4.7UF

FBB

C8502

6.3V

20%

402

X5R

4.7UF

FBB

C8505

6.3V

20%

402

X5R

4.7UF

FBB

C8504

6.3V

20%

402

X5R

4.7UF

FBB

C8503

20%

402

X5R

4.7UF

6.3V

FBB

20%

C8550

6.3V

402

X5R

4.7UF

FBB

C8551

6.3V

20%

402

X5R

4.7UF

FBB

C8552

6.3V

20%

402

X5R

4.7UF

FBB

C8553

6.3V

20%

402

X5R

4.7UF

FBB

C8554

6.3V

20%

402

X5R

4.7UF

FBB

6.3V

C8555

20%

402

X5R

4.7UF

FBB

1/20W

MF

1%

201

120

R8550

R8502

1/20W

1%

201

MF

40.2

FBB

PLACE_NEAR=U8500.J11:8.4MM

R8501

FBB

40.2

1/20W

1%

201

MF

PLACE_NEAR=U8500.J12:8.4MM

201

MF

1/20W

1%

R8552

40.2

FBB

PLACE_NEAR=U8550.J11:8.4MM

1%

R8551

1/20W

201

MF

40.2

FBB

PLACE_NEAR=U8550.J12:8.4MM

R8531

1.33K

1/20W

1%

201

MF

FBB

PLACE_NEAR=U8500.J14:8.4MM

77 79 80

R8534

931

1/20W

1%

201

MF

FBB

PLACE_NEAR=U8500.J14:8.4MM

R8530

1/20W

1%

201

549

MF

FBB

PLACE_NEAR=U8500.J14:8.4MM

MF 201

R8533

1/20W

1%

FBB

PLACE_NEAR=U8500.U10:8.4MM

1.33K

1/20W

R8535

1%

MF

FBB

PLACE_NEAR=U8500.U10:8.4MM

201

931

1/20W MF 201

R8532

1%

549

FBB

PLACE_NEAR=U8500.U10:8.4MM

77 79 80

R8580

1/20W

1%

201

MF

549

FBB

PLACE_NEAR=U8550.J14:8.4MM

77 79 80

FBB

R8584

1/20W

201

MF

1%

931

FBB

PLACE_NEAR=U8550.J14:8.4MM

R8581

1%

MF

1.33K

201

1/20W

FBB

PLACE_NEAR=U8550.J14:8.4MM

77 79 80

FBB

201

R8585

1/20W

1%

MF

931

FBB

PLACE_NEAR=U8550.U10:8.4MM

R8582

1/20W

1%

MF

549

201

FBB

PLACE_NEAR=U8550.U10:8.4MM

R8583

1/20W

1%

201

MF

1.33K

FBB

PLACE_NEAR=U8550.U10:8.4MM

C8506

6.3V

20%

0201

X5R

1UF

FBB

C8507

6.3V

20%

0201

X5R

1UF

FBB

C8508

6.3V

20%

0201

X5R

1UF

FBB

C8509

6.3V

20%

0201

X5R

1UF

FBB

C8510

6.3V

20%

0201

X5R

1UF

FBB

C8511

6.3V

20%

0201

X5R

1UF

FBB

C8512

6.3V

20%

0201

X5R

1UF

FBB

C8513

6.3V

20%

0201

X5R

1UF

FBB

C8514

6.3V

20%

0201

X5R

1UF

FBB

C8515

6.3V

20%

0201

X5R

1UF

FBB

C8556

6.3V

20%

0201

X5R

1UF

FBB

C8557

6.3V

20%

0201

X5R

1UF

FBB

C8558

6.3V

20%

0201

X5R

1UF

FBB

C8559

6.3V

20%

0201

X5R

1UF

FBB

1UF

C8560

20%

0201

X5R

6.3V

FBB

C8561

6.3V

20%

0201

X5R

1UF

FBB

C8562

6.3V

20%

0201

X5R

1UF

FBB

C8563

0201

X5R

1UF

6.3V

20%

FBB

C8564

6.3V

20%

0201

X5R

1UF

FBB

0201

C8565

6.3V

20%

X5R

1UF

FBB

1/20W

R8554

5%

1K

MF

201

FBB

K4G10325FG-HC03

U8500

32MX32-1.5GHZ-MFL

OMIT_TABLE

BGA

FBB

R8504

1/20W

201

MF

1K

5%

R8503

FBB

1/20W

201

MF

1K

5%

1K

MF

201

1/20W

FBB

R8553

0.01UF

C8590

FBB

0201

X5R-CERM

10V

10%

PLACE_NEAR=U8500.J11:8.4MM

C8591

0.01UF

10% 10V X5R-CERM 0201

FBB

PLACE_NEAR=U8550.J11:8.4MM

0402

CERM

50V

10%

820PF

C8531

FBB

PLACE_NEAR=U8500.J14:8.4MM

PLACE_NEAR=U8500.A10:30MM

0402

CERM

50V

10%

820PF

C8532

FBB

PLACE_NEAR=U8500.U10:25MM

820PF

10%

C8533

0402

CERM

50V

FBB

0402

CERM

50V

10%

820PF

C8581

FBB

PLACE_NEAR=U8550.J14:8.4MM

0402

CERM

50V

10%

820PF

C8582

FBB

PLACE_NEAR=U8550.A10:8.4MM

CERM 0402

50V

10%

820PF

C8583

FBB

PLACE_NEAR=U8550.U10:8.4MM

K4G10325FG-HC03

U8500

32MX32-1.5GHZ-MFL

BGA

OMIT_TABLE

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77 80

108

77 80

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

120

FBB

R8500

1/20W

1%

201

MF

77

108

77

108

77

108

77

108

77

108

C8516

6.3V

10%

201

X5R

0.1UF

FBB

C8517

6.3V

10%

201

X5R

0.1UF

FBB

C8518

6.3V

10%

201

X5R

0.1UF

FBB

C8519

6.3V

10%

201

X5R

0.1UF

FBB

C8520

6.3V

10%

201

X5R

0.1UF

FBB

C8521

6.3V

10%

201

X5R

0.1UF

FBB

C8522

6.3V

10%

201

X5R

0.1UF

FBB

C8523

6.3V

10%

201

X5R

0.1UF

FBB

C8524

6.3V

10%

201

X5R

0.1UF

FBB

C8525

6.3V

10%

201

X5R

0.1UF

FBB

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77 80

108

77 80

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

U8550

32MX32-1.5GHZ-MFH

K4G10325FG-HC03

BGA

OMIT_TABLE

C8567

6.3V

10%

X5R

0.1UF

201

FBB

C8566

6.3V

10%

201

X5R

0.1UF

FBB

C8571

6.3V

10%

201

X5R

0.1UF

FBB

C8575

6.3V

10%

201

X5R

0.1UF

FBB

C8570

6.3V

10%

201

X5R

0.1UF

FBB

C8574

0.1UF

6.3V

10%

201

X5R

FBB

C8569

6.3V

10%

201

X5R

0.1UF

FBB

C8573

6.3V

10%

201

X5R

0.1UF

FBB

C8568

10%

201

X5R

0.1UF

6.3V

FBB

C8572

6.3V

10%

201

X5R

0.1UF

FBB

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

77

108

32MX32-1.5GHZ-MFH

BGA

U8550

OMIT_TABLE

K4G10325FG-HC03

SYNC_DATE=04/09/2012

GDDR5 Frame Buffer B

SYNC_MASTER=D8_YAN

FB_B1_DQ<28>

=PP1V35_GPU_FBVDDQ

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B1_VREFC

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.25 MM

FB_B0_VREFC

FB_B0_DQ<31>

FB_B0_DQ<30>

FB_B0_DQ<29>

FB_B0_A<8>

FB_B0_WCLK_N<1>

FB_B0_WCLK_P<0>

FB_B0_CK_MID

FB_B0_CLK_P

FB_B0_ZQ

FB_B0_A<0>

FB_B0_A<1>

FB_B0_A<3>

FB_B1_ZQ

FB_B0_DBI_L<2>

FB_B0_DBI_L<3>

FB_B0_DQ<3>

FB_B0_DQ<8>

FB_B0_MF

FB_B1_CK_MID

FB_B0_EDC<0>

FB_B0_A<4>

FB_B0_A<7>

=PP1V35_GPU_FBVDDQ

FB_B1_MF

FB_B1_SEN

FB_B1_A<3>

FB_B1_A<7>

FB_B1_A<1>

FB_B1_A<0>

FB_B1_A<6>

FB_B1_CKE_L

FB_B1_CLK_P

FB_B1_CAS_L

FB_B0_SEN

FB_B0_A<6>

FB_B0_CKE_L

FB_B0_CAS_L

FB_B0_WCLK_P<1>

=PP1V35_GPU_FBVDDQ

FB_B1_WCLK_N<1>

FB_SW_LEG

=PP1V35_GPU_FBVDDQ

FB_SW_LEG

FB_B0_CLK_N

FB_B1_CLK_NFB_B1_CLK_P

FB_B0_WE_L

FB_B0_RESET_L

FB_B1_DQ<8>

FB_B0_DQ<10>

FB_B1_A<8>

FB_B0_VREFC

FB_B0_DQ<19>

FB_B0_DQ<21>

FB_B0_DQ<23>

FB_B0_DQ<5>

FB_B0_DQ<7>

FB_B1_VREFD

FB_B1_VREFC

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<0>

FB_B1_EDC<3>

FB_B1_EDC<0>

FB_B1_DQ<0>

FB_B1_DQ<13>

FB_B1_DQ<12>

FB_B1_DQ<24>

FB_B1_A<5>

FB_B1_A<4>

FB_B1_DQ<9>

FB_B1_DQ<14>

FB_B1_DQ<16>

FB_B1_DQ<19>

FB_B1_DQ<23>

FB_B1_DQ<25>

FB_B1_DQ<26>

FB_B1_DQ<27>

FB_B1_DQ<31>

FB_B1_EDC<1>

FB_B1_EDC<2>

FB_B1_RAS_L

FB_B1_WE_L

FB_B1_DQ<29>

FB_B1_DQ<22>

FB_B1_DQ<21>

FB_B1_DQ<17>

FB_B1_DQ<15>

FB_B1_DQ<10>

FB_B1_DQ<7>

FB_B1_DQ<6>

FB_B1_DQ<5>

FB_B1_DQ<4>

FB_B1_DQ<3>

FB_B1_DQ<1>

FB_B1_DBI_L<3>

FB_B1_DBI_L<0>

FB_B1_DBI_L<1>

FB_B1_ABI_L

FB_B1_RESET_L

FB_B1_DQ<18>

FB_B1_DQ<20>

FB_B1_DQ<30>

FB_B1_DQ<2>

FB_B1_CLK_N

FB_B1_CS_L

FB_B0_DQ<24>

FB_B0_DBI_L<0>

FB_B0_DQ<27>

FB_B0_DQ<15>

FB_B0_DQ<13>

FB_B0_RAS_L

FB_B0_EDC<3>

FB_B0_DQ<26>

FB_B0_DQ<25>

FB_B0_DQ<20>

FB_B0_DQ<18>

FB_B0_DQ<16>

FB_B0_DQ<2>

FB_B0_DQ<1>

FB_B0_DQ<0>

FB_B0_DBI_L<1>

FB_B0_CLK_P

FB_B0_ABI_L

FB_B0_CLK_N

FB_B0_DQ<9>

FB_B0_DQ<6>

FB_B0_DQ<4>

FB_B0_DQ<28>

FB_B0_EDC<2>

FB_B0_WCLK_N<0>

FB_B0_A<5>

FB_B0_A<2>

FB_B0_DQ<12>

FB_B0_DQ<11>

FB_B0_EDC<1>

FB_B0_CS_L

FB_B1_A<2>

FB_B1_DQ<11>

FB_B0_DQ<22>

FB_B0_DQ<14>

FB_B0_DQ<17>

=PP1V35_GPU_FBVDDQ

FB_B1_WCLK_P<1>

FB_B1_DBI_L<2>

=PP1V35_GPU_FBVDDQ

FB_B1_VREFD

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B0_VREFD

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1 mm

FB_B0_VREFD

prefsb

051-9504

7.0.0

85 OF 143

80 OF 117

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1212

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

U14

U12

U3

U1

R14

R12

R11

R4

R3

R1

N14

N12

N3

N1

M10

M5

K13

K2

H13

H2

F10

F5

E1

C14

C11

C4

C3

C1

A14

A1

T10

T5

P10

L10

L5

K14

K1

H14

H1

G10

G5

D10

B10

B5

U10

A10

J14

T14

T12

T3

T1

P14

P12

P3

P1

N10

N5

M14

M12

M3

M1

L13

L2

K12

K3

H12

H3

G13

G2

F14

F12

F3

F1

E10

E5

D14

D12

D3

D1

R10

R5

P11

L14

L11

L4

L1

G14

G11

G4

G1

D11

C10

C5

B1

B3 B12 B14

A12

A3

E12 E14

E3

C12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

J1

J10

L3

K5

K10

N2

D5

P4 P5

J2

C13 R13

U5

N4

H4

J3

H11

B2 E4 E2 F4

A11 A13 B11 B13

H10

K11

L12

P13

H5

K4

J11

M4

J4

J12

G12

D13

P2

A4 A2 B4

F2

E11

U11 U13 T11 T13 N11 N13 M11 M13

U2 T4

C2

R2

G3

E13

F13

T2

D2

F11

M2

U4

D4

J13

J5

A5

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

C12

C11

C4

C3

C1

A14

U14

U12

U3

U1

R14

R12

R11

A12

R4

R3

R1

N14

N12

N3

N1

M10

M5

K13

A3

K2

H13

H2

F10

E14

E12

E3

E1

C14

A1

K14

K1

H14

H1

G10

G5

D10

B10

T10

T5

P10

L10

L5

B5

U10

A10

J14

E5

D14

D12

D3

D1

B14

T14

T12

T3

T1

P14

P12

P3

B12

P1

N10

M14

F14

F12

F3

F1

E10

B1

L4

L1

G14

G11

G4

G1

D11

C10

R10

R5

P11

L14

L11

N5

M12

M3

M1

L13

L2

K12

B3

K3

H12

H3

G13

G2

F5

C5

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

H5

J10

P5

P4

C2

R2

K4

U4

N13

N11

A4

J12

K5

H10 H11

G3

J11

J3

L12

U13

T13

M11

A11

B13

F13

A2 B4 B2

F2

R13 C13

J1

L3

D4 D5

G12

J13

K11

E4 E2

F11

E13

A13

M13

T11

U11

M2

M4

N2

N4

T2

T4

U2

D2

P2

D13

P13

K10

H4

J4

J2

B11

E11

A5 J5

F4

U5

76 78 79 80

80

113

76 78 79 80

80

113

108

77 80 108

108

76 78 79 80

77 80

108

77 80

108

80

113

80

113

80

113

76 78 79 80

80

113

80

113

80

113

BI

IN

OUT

IN

OUT

IN

OUT

IN

NC

NC NC

NC

NC NC NC

NC

NC NC NC NC

NC NC

OUT

BI

OUT

BI

OUT

NC

NC NC NC

NC

NC NC

NC

BI

IFPEF_PLLVDD IFPEF_RSET

IFPD_RSET

IFPD_PLLVDD

I2CA_SDA

IFPF_IOVDD

IFPAB_PLLVDD IFPAB_RSET

IFPC_PLLVDD IFPC_RSET

IFPC_L1

IFPC_L0*

IFPC_L0

IFPC_AUX_I2CW_SCL

IFPB_TXD7*

IFPA_TXD3*

IFPB_TXC

DACA_VREF DACA_RSET

IFPE_IOVDD

I2CA_SCL

IFPC_L3*

IFPF_L3*

IFPF_L3

IFPF_L2*

IFPF_L2

IFPF_L1*

IFPF_L1

IFPF_L0*

IFPF_L0

IFPF_AUX_I2CZ_SDA*

IFPF_AUX_I2CZ_SCL

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX_I2CY_SDA*

IFPE_AUX_I2CY_SCL

IFPD_L3*

IFPD_L3

IFPD_L2

IFPD_L1*

IFPD_L1

IFPD_L0*

IFPD_L0

IFPD_IOVDD

IFPC_L3

IFPC_L1*

IFPC_IOVDD

IFPC_AUX_I2CW_SDA*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD6

IFPB_TXD5*

IFPB_TXD5

IFPB_TXD4*

IFPB_TXD4

IFPB_TXC*

IFPB_IOVDD

IFPA_TXD3

IFPA_TXD2*

IFPA_TXD2

IFPA_TXD1*

IFPA_TXD1

IFPA_TXD0*

IFPA_TXD0

IFPA_TXC

IFPA_IOVDD

I2CS_SDA

I2CS_SCL

I2CC_SDA

I2CC_SCL

I2CB_SDA

I2CB_SCL

DACA_VSYNC

DACA_VDD DACA_RED

DACA_HSYNC

DACA_GREEN

DACA_BLUE

CEC

IFPA_TXC*

IFPD_L2*

IFPC_L2

IFPC_L2*

IFPD_AUX_I2CX_SCL

IFPD_AUX_I2CX_SDA*

(5 OF 10)

OUT

NC

BI

OUT

NC NC

NC

THERMDP THERMDN

JTAG_TRST*

JTAG_TMS

JTAG_TDO

JTAG_TDI

JTAG_TCK

STRAP3 STRAP4

STRAP2

STRAP1

STRAP0

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

VID_PLLVDD

PLLVDD

SP_PLLVDD

TESTMODE

MULTI_STRAP_REF0_GND

ROM_SO

ROM_SI

ROM_SCLK

ROM_CS*

VDD33

GPIO20

GPIO16

GPIO0 GPIO1 GPIO2

GPIO5 GPIO6 GPIO7 GPIO8 GPIO9

GPIO10

GPIO13 GPIO14 GPIO15

GPIO17 GPIO18 GPIO19

GPIO21

GPIO11 GPIO12

GPIO4

GPIO3

(6 OF 10)

IN

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

ESR = 0.05OHM

DISABLE PHYS A, B & C FOR D8

GPU 3V3 VDD

IFP CD IOVDD

Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other

IFP EF IOVDD

IFPX PLLVDD

- =PP1V8_GPU_DPLL

Power aliases required by this page:

- =PP1V05_GPU_DPLL

- =PP1V05_GPU_IFPEF_IOVDD

PD FOR RSET

- =PP1V05_GPU_IFPCD_IOVDD

- =PP1V8_GPU_IFPA_IOVDD

- =PP3V3_GPU_IFPX_PLLVDD

Signal aliases required by this page:

- =PP3V3_GPU_VDD33

BOM options provided by this page:

Page Notes

- =PP3V3_GPU_IFPB_IOVDD

- J31:YES

- J5:YES

(NONE)

PD FOR AUX CHANNELS (FOR NVIDIA)

DDC MAPPING

I2CA -> IFPE DDC

(was ext SSC cntl)

I2CC -> Not used

---------------------

ESR = 0.05OHM

GPU PLL VDD

I2CB -> IFPF DDC

ESR = 0.05OHM

82

78

82

113

82

113

82

108

82

108

PLACE_NEAR=U8000.J1:5MM

0201

1/20W

MF

R8609

40.2K

0.1%

82

113

82

113

82

113

82

113

82

113

85

107

85

107

MF

100K

201

1%

1/20W

R8613

201

MF

1%

100K

1/20W

R8614

MF

201

1%

100K

1/20W

R8615 R8616

100K

MF

1/20W

1%

201

MF

1%

1/20W

100K

R8617

100K

1/20W

1%

MF

201

R8618

PLACE_NEAR=U8000.AN2:5MM

1%

1/20W

MF

201

1K

R8606

PLACE_NEAR=U8000.AD6:5MM

R8607

1K

MF

1/20W

1%

201

85

107

85

107

82

108

82

108

FERR-220-OHM-2A

0603

CRITICAL

L8606

L8605

FERR-220-OHM-2A

CRITICAL

0603

CRITICAL

0603

FERR-220-OHM-2A

L8607

R8623

4.7K

1%

1/20W

MF

201

1%

201

1/20W

MF

R8624

4.7K

82

108

82

113

10K

201

MF

1/20W

1%

R8603

201

MF

1/20W

1%

10K

R8619

201

1/20W

5%

MF

10K

R8610

10K

1/20W

MF

5%

201

R8622

201

1/20W

MF

5%

10K

R8620

0402

X6S

6.3V

20%

PLACE_NEAR=U8000.AG7:20MM

C8619

4.7UF

C8625

4.7UF

20%

6.3V X6S 0402

PLACE_NEAR=U8000.AG6:20MM

C8633

PLACE_NEAR=U8000.AC7:20MM

6.3V

20%

0402

X6S

4.7UF

PLACE_NEAR=U8000.AC7:20MM

C8634

0402

X6S

6.3V

20%

4.7UF

PLACE_NEAR=U8000.AG7:5.5MM

C8617

0.1UF

10%

6.3V X6S 0201

PLACE_NEAR=U8000.AB8:3.8MM

10%

6.3V X6S

0.1UF

C8618

0201

PLACE_NEAR=U8000.AG7:3.8MM

0201

10%

6.3V X6S

C8612

0.1UF

PLACE_NEAR=U8000.AG6:5MM

C8657

0201

10%

6.3V X6S

0.1UF

10%

X6S

6.3V

0201

0.1UF

C8658

PLACE_NEAR=U8000.AG6:4.5MM

X6S 0201

0.1UF

6.3V

10%

C8637

PLACE_NEAR=U8000.AC7:6MM

C8638

0.1UF

0201

X6S

6.3V

10%

PLACE_NEAR=U8000.AC7:6.5MM

PLACE_NEAR=U8000.AC8:3.8MM

0201

0.1UF

X6S

6.3V

10%

C8631

PLACE_NEAR=U8000.AC8:3.8MM

C8632

0201

0.1UF

X6S

6.3V

10%

6.3V

0201

C8643

X6S

0.1UF

10% 10%

6.3V X6S

0.1UF

0201

C8644

10%

6.3V X6S 0201

C8649

0.1UF

10%

X6S 0201

0.1UF

C8650

6.3V

C8646

0402

X6S

20%

4.7UF

6.3V

PLACE_NEAR=U8000.AG6:20MM

20%

1.0UF

4V

0201

C8656

X6S

PLACE_NEAR=U8000.AC8:20MM

C8635

1.0UF

X6S 0201

4V

20%

PLACE_NEAR=U8000.AC8:20MM

X6S

4V

C8636

1.0UF

20%

0201

PLACE_NEAR=U8000.AD8:3.8MM

0201

0.1UF

X6S

6.3V

10%

C8654

201

NOSTUFF

2.2K

MF

1/20W

5%

R86255%R8626

NOSTUFF

201

MF

1/20W

2.2K

NOSTUFF

201

MF

5%

R8627

2.2K

1/20W

NOSTUFF

201

5%

MF

2.2K

R8628

1/20W

20%

1UF

C8615

X5R

6.3V

0201

PLACE_NEAR=U8000.AB8:20MM

C8642

1UF

20%

6.3V X5R 0201

MF

1/20W

1%

201

R8632

100K 100K

MF

201

1%

1/20W

R8631

201

100K

1%

MF

1/20W

R8629

201

1/20W

MF

1%

100K

R8630

4V

X5R-CERM

0402

C8651

20UF

20%

81 84

107

81 84

107

U8000

NV-GK107

BGA

OMIT_TABLE

CRITICAL

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

75 81

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

36

107

MF

1/20W

201

1%

10K

R8600

201

MF

1/20W

10K

1%

R8601

1%

1/20W

MF

201

10K

R8602

201

1%

1/20W

MF

10K

R8604

0603

330-OHM-1.2A

L8604

CRITICAL

NV-GK107

OMIT_TABLE

BGA

U8000

R8608

1/20W

10K

MF

1%

201

78

108

78

113

78

113

78

113

82

KEPLER EDP/DP/GPIO

SYNC_DATE=04/09/2012

SYNC_MASTER=D8_YAN

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.41MM

PP1V05_GPU_PLLVDD

=PP1V05_GPU_PEX_PLLVDD

GPU_GPIO_1

GPU_GPIO_4

GPU_GPIO_12

GPU_TESTMODE

DP_INT_EG_ML_N<3>

DP_INT_EG_ML_N<2>

GPU_SSC_SMB_DAT

DP_INT_EG_AUX_P

GPU_SMB_CLK

DP_TBTSNK1_DDC_CLK

GPU_SSC_SMB_CLK

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

IFPEF_RSET

GPU_SMB_DAT

=PP3V3_GPU_VDD33

IFPD_RSET

PP3V3_GPU_IFPX_PLLVDD

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK1_EG_AUXCH_N

PP1V05_GPU_IFPEF_IOVDD

PP1V05_GPU_IFPD_IOVDD

MAKE_BASE=TRUE

PP1V05_GPU_SP_PLLVDD

GPU_XTAL_OUTBUFF

PP1V05_GPU_VID_PLLVDD

GPU_GPIO_19

GPU_JTAG_TCK

GPU_JTAG_TDI

GPU_TDIODE_N

GPU_OSC_27M_XTALOUT

PP1V05_GPU_IFPEF_IOVDD

GPU_IFPX_PLLVDD

GPU_IFPAB_PLLVDD

=PP3V3_GPU_VDD33

DP_TBTSNK0_EG_AUXCH_N

GPU_OSC_27M_XTALIN

GPU_MLS_STRAP1

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_P<0>

DP_TBTSNK0_EG_AUXCH_N

DP_TBTSNK1_ML_C_N<0>

DP_INT_EG_AUX_N

DP_TBTSNK1_EG_AUXCH_N

GPU_ROM_CS_L

GPU_ROM_SI

GPU_JTAG_TDO

GPU_GPIO_0

GPU_GPIO_2

GPU_GPIO_15

GPU_GPIO_6

PP1V05_GPU_VID_PLLVDD

GPU_GPIO_21

GPU_GPIO_7

GPU_GPIO_8

DP_TBTSNK1_EG_AUXCH_P

DP_TBTSNK1_ML_C_P<1>

GPU_GPIO_5

GPU_ROM_SO

GPU_IFPB_IOVDD GPU_IFPC_IOVDD

GPU_GPIO_3

IFPEF_RSET

DP_TBTSNK0_ML_C_P<2>

IFPD_RSET

GPU_IFPX_PLLVDD

DP_TBTSNK1_ML_C_P<0>

GPU_TESTMODE

DP_INT_EG_ML_P<1>

GPU_IFPAB_PLLVDD

GPU_GPIO_16

MULTI_STRAP_REF

=PP3V3_GPU_VDD33

=PP3V3_GPU_IFPX_PLLVDD

=PP1V05_GPU_IFPCD_IOVDD

=PP1V05_GPU_IFPEF_IOVDD

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_EG_AUXCH_P

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

DP_INT_EG_ML_P<2>

DP_INT_EG_ML_N<1>

GPU_MLS_STRAP0

DP_TBTSNK0_ML_C_N<2>

DAC_AVDD

=PP3V3_GPU_MISC

DP_TBTSNK0_EG_AUXCH_P

GPU_IFPC_IOVDD

GPU_IFPB_IOVDD

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

GPU_MLS_STRAP2

GPU_MLS_STRAP3

GPU_MLS_STRAP4

=PP3V3_GPU_MISC

GPU_IFPA_IOVDD

GPU_XTAL_SSIN

PP1V05_GPU_PLLVDD

PP1V05_GPU_SP_PLLVDD

GPU_TDIODE_P

GPU_GPIO_17

GPU_GPIO_14

GPU_GPIO_13

GPU_GPIO_11

GPU_GPIO_10

GPU_GPIO_9

GPU_JTAG_TMS

GPU_JTAG_TRST_L

GPU_GPIO_20

GPU_GPIO_18

DP_TBTSNK1_DDC_DATA

DP_INT_EG_ML_N<0>

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 MM

PP3V3_GPU_IFPX_PLLVDD

=PP3V3_GPU_VDD33

DP_INT_EG_AUX_P

GPU_ROM_SCLK

DP_INT_EG_AUX_N

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

PP1V05_GPU_IFPEF_IOVDD

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2mm

PP1V05_GPU_IFPD_IOVDD

MIN_NECK_WIDTH=0.2mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM

prefsb

051-9504

7.0.0

86 OF 143

81 OF 117

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

121

2

121

2

1

2

1

121

2

12 12

2

1

AB8

AD6

AN2

AG7

R5

AC8

AH8

AJ8

AF7

AF8

AJ3

AJ1

AK1

AG3

AL8

AH6

AJ9

AP9

AP8

AC7

R4

AG4

AF1

AG1

AD5

AD4

AF5

AF4

AE4

AE3

AF2

AF3

AC5

AC4

AC3

AC2

AC1

AD1

AD3

AD2

AB4

AB3

AK5

AK4

AL3

AM4

AM3

AM2

AM1

AG6

AG5

AJ2

AF6

AG2

AK8

AM8

AN8

AL7

AM7

AP5

AP6

AH9

AG9

AJ6

AK6

AL6

AM5

AN5

AN3

AP3

AM6AG8

T3

T4

R3

R2

R6

R7

AN9

AG10

AK9

AM9

AL10

AL9

L3

AN6

AL4

AH3

AH4

AK3

AK2

1

2

1

2

1

2

1

2

21

K3

K4

AN11

AP11

AP12

AM11

AM10

J5

J3

J6

J7

J2

H1

J4

H2

H3

AD7

AD8

AE8

AK11

J1

H7

H5

H4

H6

J8

L8

P4

R8

P6

M3

L6

L7

M7

N8

M1

M2

L1

M4

N4

P2

M6

R1

P3

P1

K8

M8

M5

N3

P7

P5

1

2

81 115

78 83

81

108

81 84

107

81

113

75 78 81 82 83

81

113

81

115

81

115

75 81

81

115

81

115

81 83

115

81

115

81

113

75 78 81 82 83

75 81

81

113

81

113

81

113

81

113

81

108

81

113

75 78 81 82 83

78

78 81

75 81

81

113

81

113

78 81

81

113

81

113

81

115

81 83

115

81

115

75 78 81 82 83

81 84

107

81

115

81

115

OUT

IN

OUT

NC

IN

OUT

BI

D

GS

VCC

GND

THRM

SCLK

CS*

SO

SI

HOLD*

WP*

PAD

B

Y

A

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

USE 1% FOR ACCURACY

CONFIG STRAPS - MLPS

GP

Native Func

GPIOs

GP

Native Func

GP

GPIOs

ISOLATION R’s for GPU Int Temp Sense

197S0464

GPU XTAL 27 MHZ

GP

GPU VBIOS ROM

GPU overtemp masking

5% MF

1/20W

201

R8798

NOSTUFF

0

R8799

MF

0

5%

1/20W

201

47 48 82

116

10K

R8797

1/20W

201

MF

5%

R8796

201

10K

5%

1/20W

MF

82

82 95

113

81

108

81

108

R8723

GPU_ROM:YES

5%

33

MF

201

1/20W

C8721

GPU_ROM:YES

0.1UF

10%

6.3V

X5R

201

R8781

MF

5%

1/20W

201

0

R8780

201

1/20W

MF

5%

0

5.62K

NOSTUFF

201

R8701

1%

MF

1/20W

81

113

81

113

1/20W

R8702

201

MF

1%

3.24K

NOSTUFF

81

113

R8707

1/20W

MF

5.62K

201

1%

NOSTUFF

81

113

81

113

1/20W

1%

3.24K

201

MF

NOSTUFF

R8708

81 82

113

1%

1/20W

MF

3.24K

201

NOSTUFF

R8710

81 82

113

81 82

108

1%

201

MF

1/20W

45.3K

R8700

34.8K

R8703

1%

201

1/20W

MF

R8722

MF

5%

0

1/20W

201

NO STUFF

201

R8721

1/20W

MF

GPU_ROM:YES

5%

0

R8724

GPU_ROM:YES

33

201

1/20W

5%MF

MF

201

10K

1%

1/20W

R8706

1/20W

45.3K

R8709

1%

201

MF

NOSTUFF

35.7K

201

MF

1/20W

1%

R8714

R8726

GPU_ROM:YES

201

MF5%

1/20W

33

R8793

5%

1/20W

MF

10K

201

NOSTUFF

R8794

10K

5%

1/20W

MF

201

5%

10K

MF

201

R8790

1/20W

NOSTUFF

R8713

10K

NOSTUFF

201

MF

1%

1/20W

1%

10K

MF

201

R8712

NOSTUFF

R8704

201

MF

1/20W

1%

10K

26 75 113

47 48

82

116

R8752

201

MF

1/20W

5%

10K

47

116

1/20W

R8791

NOSTUFF

10K

5%

MF 201

SSM3K15AMFVAPE

Q8701

VESM

NOSTUFF

CRITICAL

1MBIT

USON

U8701

MX25V1005C

R8720

201

5%

GPU_ROM:YES

MF

1/20W

10K

R8725

33

1/20W5%201

MF

GPU_ROM:YES

201

MF

1/20W

1%

4.99K

R8705

R8715

15K

1%

1/20W

MF

201

R8711

15K

OMIT_TABLE

1%

1/20W

MF

201

0201

NP0-C0G-CERM

25V

5%

18PF

C8700

0201

NP0-C0G-CERM

25V

5%

18PF

C8701

74LVC1G08GW

SOT353

U8702

CRITICAL

2.50X2.00MM-SM

27MHZ-30PPM-18PF-60OHM

Y8700

0.1UF

0402

10% 16V X7R-CERM

U8702.5:3MM

C8702

FB:BOTH_SAMSUNG

R8711

RES,MF,20.0k ,1,1/20W,0201

118S0175

1

118S0105

RES,MF,15.0k ,1,1/20W,0201

FB:BOTH_HYNIX

R8711

SYNC_DATE=07/27/2012

SYNC_MASTER=D8_YAN

KEPLER GPIOS,CLK & STRAPS

=PP3V3_GPU_VDD33

=PP3V3_S0_SMC

SMC_GFX_OVERTEMP

GPU_RESET_L

GPU_GPIO_8

MAKE_BASE=TRUE

GPU_VCORE_VID0

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

EG_BKLT_EN

GPU_GPIO_13

GPU_VCORE_VID5

MAKE_BASE=TRUE

GPU_GPIO_12

GPU_GPIO_11

GPU_GPIO_10

GPU_GPIO_9

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_HDMI_EG_HPD

GPU_ALT_VREF

MAKE_BASE=TRUE

GPU_OSC_27M_XTALOUT

GPU_OSC_27M_XTALIN

GPU_ROM_SO_R

GPU_ROM_SI_R

=PP3V3_GPU_VDD33

GPU_MLS_STRAP3

GPU_MLS_STRAP2

GPU_MLS_STRAP0

GPU_MLS_STRAP1

GPU_ROM_SO

GPU_ROM_SI

GPU_SMB_CLK_R

GPU_GPIO_14

GPU_GPIO_15

GPU_SMB_DAT_R

=PP3V3_GPU_VDD33

GPU_ROM_SCLK

=PP3V3_GPU_VDD33

GPU_MLS_STRAP4

GPU_GPIO_17

GPU_GPIO_16

GPU_GPIO_18

GPU_GPIO_19

GPU_GPIO_20

GPU_GPIO_21

GPU_GPIO_0

GPU_GPIO_1

GPU_GPIO_3

GPU_GPIO_2

GPU_GPIO_4

GPU_GPIO_5

GPU_GPIO_6

GPU_GPIO_7

GPU_ROM_WP_L

GPU_ROM_SCLK_R

GPU_ROM_SI

GPU_ROM_SCLK

GPU_ROM_SO

GPU_SMB_DAT

GPU_SMB_CLK

=PP3V3_GPU_VDD33

SMC_GFX_OVERTEMP_R_L

FBVDD_ALTVO

EG_BKLT_EN

SMC_GFX_THROTTLE_L

SMC_GFX_THROTTLE_R_L

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

FB_CLAMP_TOGGLE_REQ_L

MAKE_BASE=TRUE

GPU_PSI_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_DP_EXTA_CA_DET_EG

NO_TEST=TRUE

NC_DP_EXTB_CA_DET_EG

MAKE_BASE=TRUE

DP_INT_EG_HPD

MAKE_BASE=TRUE

FBVDD_ALTVO

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

DP_TBTSNK1_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_20_RSVD

NO_TEST=TRUE

NC_GPU_GPIO_21_RSVD

MAKE_BASE=TRUE

GPU_VCORE_VID4

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

GPU_LCD_BKLT_PWM

=PP3V3_GPU_VDD33

SMC_GFX_OVERTEMP

SMC_GFX_OVERTEMP_Q

GPU_ROM_CS_L_R

GPU_ROM_CS_L

prefsb

051-9504

7.0.0

87 OF 143

82 OF 117

12

1

2

1

2

12

2

1

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

1

2

1

2

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

8

4

9

6

1

2

5

7

3

1

2

12

1

2

1

2

1

2

1

2

1

4

3

1

2

5

42

13

2

1

75 78 81 82 83

6

48 51

81

78

110

82

116

78

110

78

110

82

81 78

110

81

77

113

75 78 81 82 83

50

108

81

50

108

75 78 81 82 83

81

113

108

81 82

113

81 82 108

81 82 113

81

108

81

108

75 78 81 82 83

82

116

82

116

82

116

82

116

92

110

84

112

82 95

113

36

107

36

107

78

110

78

110

84

107

75 78 81 82 83

116

113

81 113

NC

OUT

GND

(9 OF 10)

GND

(8 OF 10)

GND_SENSE

NC

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_IOVDDQ

PEX_PLLVDD

NC

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDD

NC

PEX_IOVDDQ NC NC NC

PEX_IOVDDQ

BUFRST*

NC

PEX_PLL_HVDD

VDD_SENSE

GND_OPT

PEX_IOVDDQ

(2 OF 10)

NC NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU SP PLLVDD

ESR = 0.05OHM

PLACE XW8800 & XW8804 CLOSE TO C8803

Signal aliases required by this page:

BOM options provided by this page:

Page Notes

(NONE)

Power aliases required by this page:

- =PP3V3_GPU_VDD33

- =PP1V05_GPU_PEX_PLLVDD

- =PP1V05_GPU_PEX_IOVDD

EDP = 2000 MA

PEX IOVDD & PEX IOVDDQ

EDP = 1100MA

MF

10K

1/20W

1%

201

R8800

NOSTUFF

78

0603

CRITICAL

FERR-220-OHM-2A

L8804

NOSTUFF

100

5% 1/20W MF 201

R8810

NOSTUFF

100

1/20W MF 201

5%

R8811

22UF

C8803

20% 4V

0603

X6S-CERM

20%

X6S-CERM

22UF

C8804

0603

4V

C8800

0603

X6S-CERM

4V

20%

22UF

C8801

0603

X6S-CERM

4V

20%

22UF

20%

6.3V

0402

X6S

4.7UF

C8805

0402

X6S

6.3V

20%

4.7UF

C8802

0402

X6S

6.3V

20%

4.7UF

C8827

C8822

4.7UF

20%

6.3V

X6S 0402

4.7UF

20%

6.3V

X6S 0402

C8823

0201

X6S

6.3V

10%

0.1UF

C8829

0201

X6S

6.3V

10%

0.1UF

C8825

22UF

20% 4V

0603

X6S-CERM

C8830

X6S

0402

6.3V

20%

C8831

4.7UF

0201

X6S

6.3V

10%

C8836

0.1UF

0201

X6S

6.3V

10%

C8837

0.1UF

C8816

1.0UF

20% 4V X6S 0201

1.0UF

20% 4V X6S 0201

C8810

1.0UF

20% 4V X6S 0201

C8813

1.0UF

20% 4V X6S 0201

C8807

0201

X6S

4V

20%

1.0UF

C8828

20% 4V X6S

10UF

0402

C8815

20% 4V X6S

10UF

0402

C8809

20% 4V X6S

10UF

0402

C8812

20% 4V X6S

10UF

0402

C8806

OMIT_TABLE

NV-GK107

BGA

U8000

OMIT_TABLE

BGA

NV-GK107

U8000

OMIT_TABLE

BGA

NV-GK107

U8000

KEPLER PEX PWR/GNDS

SYNC_DATE=04/09/2012

SYNC_MASTER=D8_YAN

=PP1V05_GPU_PEX_IOVDD

=PP3V3_GPU_VDD33

GPU_BUFRSTN

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_PEX_IOVDD

=PPVCORE_GPU

=PP1V05_GPU_PEX_PLLVDD

=PP1V05_GPU_PEX_IOVDD

GPU_GND_SENSE

MIN_NECK_WIDTH=0.10 mm

VOLTAGE=0V

MIN_LINE_WIDTH=0.25 mm

GPU_VDD_SENSE

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.10 mm

PP1V05_GPU_SP_PLLVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM

prefsb

051-9504

7.0.0

88 OF 143

83 OF 117

1

2

21

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

K33

K32

K30

G7

K28

K2

G33

G5

G32

G3

G30

G22

G28

G25

G2

G19

G13

G10

G16

F28

F7

E25

E5

E7

E10

E22

D2

D31

D33

C7

N5

N33

N32

N28

N30

N23

N21

N2

N16

N19

N14

N12

M22

M20

M17

M18

M15

M13

K5

K7

P18

P22

P20

R16

R21

R19

R23

T15

T13

T17

T18

T2

T22

T20

T28

T32

T5

U12

T7

U14

U16

U19

U23

U21

V16

V14

V12

V21

V19

V23

W13

W15

W17

W20

W18

W22

W28

Y12

Y14

Y16

Y21

Y19

AH11

Y23

N7

R12

R14

P17

P15

P13

AH32

AH30

AH28

AH24

AH22

AH2

AH19

AE33

AE5

AC15

AA15

AG11

A2

A33

AA13

AA17

AA18

AA20

AA22

AB16

AB23

AC13

AC17

AC18

AC20

AC22

AE2

AE28

AE30

AE32

AE7

AH10

AH16

AH5

AH7

AK10

AH29

AB28

AH13

AB7

AB5

AB32

AB30

AB12

AB14

AB21

AB2

AB19

AH33

AJ7

AN30

AN25

AN19

AN22

AN16

AN13

AN10

AM25

AN1

AM22

AM19

AM16

AL5

AM13

AL33

AL32

AL30

AL28

AL24

AL26

AL23

AL21

AL20

AL2

AL18

AL14

AL15

AL17

AL12

AK7

C28

C25

C19

C22

C10

C13

B7

B34

B4

B25

B28

B31

B22

B10

B1

AP33

AP2

AN34

AN7

AN4

L5

AJ4

AL27

AM28

AN28

AH27

AG26

V32

T8

P8

D20

AL11

D19

C15

AG19

AG21

AG22

AG24

AH25

AH21

AJ5

AG13

D23

D26

H31

AG15

AJ27

AK27

L2

AJ28

AC6

AH12

L4

W32

C16

AG16

AG18

AG25

AH15

AH18

AH26

77 78 83

75 78 81 82

113

78 81 83

77 78 83

76 78

78 81 83

77 78 83

S

GND

OUTPUT

MUX

SELECTOR

I1

I0

Y

VCC

IN

OUT

IN

OUT

IN

OUT

NC NC

BI

IN

NC NC

BI

OUT

IN

BI

IN

BI

DIN1_1-

DIN1_1+

VDD

GND

DIN1_0-

DIN1_3-

DOUT_0+

DOUT_1-

DAUX1-

DIN2_0+ DIN2_0-

DAUX2+

DIN2_3-

DIN2_3+

DIN2_2-

DIN2_2+

HPDIN

AUX+

DIN2_1-

DDC_AUX_SEL

DIN2_1+

DOUT_3-

DOUT_3+

DOUT_2-

DOUT_2+

DDC_DAT1

DDC_CLK1

DOUT_1+

DIN1_2+

GPU_SEL

HPD_2

DDC_CLK2

DAUX2-

DDC_DAT2

DIN1_3+

DAUX1+

DIN1_2-

HPD_1

XSD*

DIN1_0+

GND

AUX-

DOUT_0-

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PD is on the LR page

TP to DP aliases

U9220

BKLT_PWM

SOT487

74LVC1G157

48

107

82

107

21 62 84 99

BKLT_PWM

R9222

1/16W

5%

402

47

MF-LF

L9201

BKLT_PWM

FERR-220-OHM

0402

89

107

470K

5%

201

MF

1/20W

R9266

470K

5%

1/20W

MF

201

R9267

470K

5%

1/20W

MF

201

R9265

470K

5%

1/20W

MF

201

R9264

470K

5%

1/20W

MF

201

R9263

R9262

1/20W

5%

470K

MF

201

470K

5%

1/20W

201

MF

R9261

R9260

470K

201

MF

5%

1/20W

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

5%

402

0

1/16W MF-LF

R9290

16V

402

1UF

10%

X5R

C9290

6.3V X5R

0.1UF

10%

C9268

201

C9269

10%

6.3V

201

0.1UF

X5R

82

112

81

107

81

107

81

107

81

107

81

107

81

107

81

107

81

107

87

107

87

107

87

107

87

107

87

107

87

107

87

107

87

107

201

0.1UF

X5R

10%

6.3V

C9208

X5R

10%

6.3V

0.1UF

201

C9209

87

107

81

107

81

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

201

0.1UF

6.3V

10%

X5R

C9211

C9210

201

0.1UF

6.3V

10%

X5R

84

107

84

107

MF

1/20W

5%

201

100K

R9200

36

107

201

MF

1/20W

10K

5%

R9201

21 62 84 99

87

107

87

112

R9202

1/20W

201

100K

5%

MF

R9203

201

MF

1/20W

5%

100K

R9204

MF

1/20W

5%

10K

201

36

R9211

470K

MF

1/20W

5%

201

R9210

470K

5%

1/20W

MF

201

470K

R9213

MF

1/20W

5%

201

1/20W

470K

R9212

5%

MF

201

X5R

0201

C9200

6.3V

10%

0.15UF

0201

C9201

6.3V

X5R

10%

0.15UF

0201

C9202

6.3V

X5R

10%

0201

C9203

6.3V

X5R

10%

0.15UF

0201 X5R

C9204

6.3V

10%

0.15UF

10%

0201

C9205

6.3V

X5R

0.15UF

0201

C9206

6.3V

X5R

10%

C9207

6.3V

10%

0.15UF

0201 X5R

0201

X5R

6.3V

20%

0.22UF

C9250

0.22UF

20%

6.3V

X5R

C9251

0201

C9252

X5R

6.3V

20%

0.22UF

0201

C9253

X5R

6.3V

20%

0.22UF

20%

6.3V

X5R

C9254

0201

C9255

X5R

6.3V

20%

0.22UF

20%

6.3V

X5R

C9256

0201

0.22UF

20%

6.3V

X5R

C9257

0201

TFBGA

CRITICAL

CBTL06142EEE

U9200

0.1UF

C9291

X7R-CERM 0402

16V

10%

402

C9270

BKLT_PWM

0.1uF

16V

10%

X5R

SYNC_DATE=03/13/2012

Internal DP MUXing

SYNC_MASTER=D8_AARON

PP1V5_S0_DP_BIAS

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.20 MM

=PP1V5_S0_DP

DP_TBTSRC_ML_C_P<0>

DP_TBTSRC_ML_C_N<1>

DP_TBTSRC_ML_C_N<3>

DP_INTPNL_AUX_N

DP_INTPNL_AUX_P

DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_ML_C_P<1>

DP_TBTSRC_ML_C_P<2>

TP_DP_TBTSRC_ML_CN<2>

DP_INT_EG_AUX_C_P

DP_TBTSRC_ML_C_P<0>

DP_TBTSRC_ML_C_N<1>

DP_INTPNL_HPD

DP_INTPNL_ML_C_N<1>

DP_INT_EG_ML_N<1>

DP_INT_EG_ML_P<1>

=PP3V3_S0_INTDPMUX

DP_INT_EG_ML_N<0>

DP_INT_EG_ML_N<3>

DP_INTPNL_ML_C_P<0>

DP_INT_EG_AUX_C_N

DP_TBTSRC_ML_C_N<0>

DP_TBTSRC_AUX_C_P

DP_TBTSRC_ML_C_N<3>

DP_TBTSRC_ML_C_P<3>

DP_TBTSRC_ML_C_N<2>

DP_TBTSRC_ML_C_P<2>

DP_TBTSRC_ML_C_P<1>

DP_INTPNL_ML_C_N<3>

DP_INTPNL_ML_C_P<3>

DP_INTPNL_ML_C_N<2>

DP_INTPNL_ML_C_P<2>

DP_INTPNL_ML_C_P<1>

DP_INT_EG_ML_P<2>

DP_TBT_SEL

DP_TBTSRC_HPD

DP_INT_EG_ML_P<3>

DP_INT_EG_ML_N<2>

DP_INT_EG_HPD

DP_INT_EG_ML_P<0>

DP_INTPNL_ML_C_N<0>

GPU_LCD_BKLT_PWM

=PP3V3_S0_INTDPMUX

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_ML_CP<2>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CP<0>

LCD_BL_FILT

LCD_BKLT_PWM

LCD_BL_PWM

DP_TBT_SEL

BDV_BKL_PWM

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CP<3>

DP_INT_EG_AUX_N

DP_INT_EG_AUX_P

DP_TBTSRC_AUXCH_P

DP_TBTSRC_AUXCH_N

=PP1V5_S0_DP

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_ML_CN<3>

DP_INTPNL_ML_P<1> DP_INTPNL_ML_N<1>

DP_INTPNL_ML_P<2> DP_INTPNL_ML_N<2>

DP_INTPNL_ML_P<3> DP_INTPNL_ML_N<3>

DP_INTPNL_ML_N<0>

DP_TBTSRC_ML_P<0>

DP_TBTSRC_ML_P<1>

DP_TBTSRC_ML_N<1>

DP_TBTSRC_ML_N<0>

DP_TBTSRC_ML_N<2>

DP_TBTSRC_ML_C_N<2>

DP_TBTSRC_ML_P<3>

DP_TBTSRC_ML_C_P<3>

DP_TBTSRC_ML_N<3>

DP_TBTSRC_ML_P<2>

DP_INTPNL_ML_P<0>

=PP3V3_S0_INTDPMUX

DP_TBTSRC_AUXCH_N

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<3>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<0>

DP_TBTSRC_ML_P<1>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<1>

MAKE_BASE=TRUE

DP_TBTSRC_ML_N<2>

MAKE_BASE=TRUE

DP_TBTSRC_AUXCH_P

DP_TBTSRC_ML_N<3>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<0>

MAKE_BASE=TRUE

DP_TBTSRC_ML_P<2>

MAKE_BASE=TRUE

=PP3V3_S0_INTDPMUX

DP_TBTSRC_AUX_C_N

DP_GPU_MUX_EN

prefsb

051-9504

7.0.0

92 OF 143

84 OF 117

1 3

4

6

25

12

21

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

2

1

2

1

2

1

12

1

2

1

2

1

2

1

2

1

2

121

2

121

2

12

A5

B5

J4

A2

H4G8C8

B3

A4

A9

B2

D1

J9

B8 B9

H6

F9

F8

E9

E8

J1

H2

D9

C2

D8

F1

F2

E1

E2

J8

H8

D2

B6

A1

H3

H5

J6

J5

A8

H9

A6

J2

B7

B4

H7

G2

H1

B1

2

1

2

1

6

84

107

84

107

84

107

84

107

84

107

84

107

6

84

107

6

84

107

6

84

6

84

107

84

107

6

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

6

84

107

112

IN

OUT

IN

BI

IN

BI

VCC

OUTA1+ OUTA1-

OUTA0+ OUTA0-

SAO

OUTB1+ OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

ENB

SAI

INB-

INB+

SBI

GND

THRM

PAD

OUT

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Dual-Port Host DDC Crossbar

81

107

88

112

36

117

88

112

81

107

81

107

81

107

402

0.1UF

10V CERM

20%

C9300

CRITICAL

QFN

TS3DS10224

U9300

86

112

86

112

SYNC_MASTER=D7_MLB

SYNC_DATE=03/15/2012

TBT DDC Crossbar

=PP3V3_S0_DP

DP_TBTPA_DDC_DATA

DP_TBTPB_DDC_DATA

DP_TBTPB_DDC_CLK

DP_TBTPA_DDC_CLK

DP_TBTSNK1_DDC_CLK DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_DATA

DP_TBTSNK0_DDC_CLK

TBT_DDC_XBAR_EN_L

prefsb

051-9504

7.0.0

93 OF 143

85 OF 117

2

1

13

20 19

18 17

15

6 7

9

8

11

16

2

1

10

14

4

3

12

5

21

6

87

IN

OUT

IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

DPMLO+ DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIOAUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX LSRX

HPDOUT

HPD

OUT

BI

IN

OUT

IN

BI

IN

OUT

ML_LANE1N

CONFIG1

SHLD

GND4

DP_PWR

CONFIG2

AUX_CHN

HPD

AUX_CHP

GND2

ML_LANE3N

GND1

ML_LANE3P

ML_LANE0N

ML_LANE1P

GND3

GND0

ML_LANE0P

SHLD

RETURN

ML_LANE2N

ML_LANE2P

PORT A

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Two Rs in series required by CD3210

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

IV3P3 1100mA 1030mA 1200mA

Nominal Min Max

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

(0-18.9V)

NOTE: Polarity Swapped for layout!

For 12V systems:

for single-fault protection(S0,S3 only)

(Both D’s)

TBT: Terminated

18.9V Max

470k R’s for ESD protection on AC-coupled signals.

(0-18.9V)

TBT: TX_1

TBT: RX_1 Bias Sink

Low: 0 - 0.8V

High: 2.0 - 5.0V

to 100K (DPv1.1a).

Sink HPD range:

greater than or equal

DP Source must pull

(Both C’s)

DP Dir

TBT: LSX_R2P/P2R (P/N)

TBT: LSX_A_R2P/P2R (P/N)

(Both C’s)

DP Dir

down HPD input with

3.3V/HV Power MUX

wake from Thunderbolt devices.

V3P3 must be S4 to support

12V: See below

TBT: TX_0

TBT Dir

(Both C’s)

NOTE: Polarity Swapped for layout!

(Both C’s)

Nominal Min Max IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

NOTE: Polarity Swapped for layout!

TBT Dir

Thunderbolt Connector A

514-0831

36

107

36

107

25V

0201

X5R-CERM

0.01UF

10%

C9402

5%

201

1/20W

MF

R9401

12

R9494

1/20W

201

MF

1K

5%

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

201

1/20W MF

5%

1K

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

R9495

201

1/20W MF

100K

5%

R9441

L9498

SIGNAL_MODEL=EMPTY

CRITICAL

650NH-5%-0.430MA-0.52OHM

GND_VOID=TRUE

0603

CRITICAL

0603

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

650NH-5%-0.430MA-0.52OHM

L9499

10V

0.1UF

20%

CERM 402

C9481

22UF

20%

X5R-CERM-1

6.3V

603

CRITICAL

C9480

100UF

POLY-TANT

CRITICAL

6.3V

20%

CASE-B2-SM

C9487

201

1/20W

MF

5%

1M

R9452

201

1/20W MF

1M

5%

R9451

201

1/20W

MF

5%

2.2K

R9498

GND_VOID=TRUE

201

1/20W MF

5%

2.2K

R9499

GND_VOID=TRUE

FERR-120-OHM-3A

0603

L9400

36

107

603-1

10% 50V X7R

0.1UF

C9410

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

CRITICAL

D9499

GND_VOID=TRUE

CRITICAL

TSLP-2-7

D9498

BAR90-02LRH

5%

GND_VOID=TRUE

201

MF

470K

1/20W

R9470

5%

470K

GND_VOID=TRUE

MF

1/20W

201

R9471

0.22UF

20%

6.3V

X5R

0201

C9471

GND_VOID=TRUE

X5R

20%

0.22UF

6.3V

GND_VOID=TRUE

0201

C9470

36

107

36

107

6.3V

X5R

20%

0.22UF

0201

C9472

GND_VOID=TRUE

0.22UF

GND_VOID=TRUE

6.3V

X5R

20%

0201

C9473

470K

5%

MF

1/20W

201

R9473

GND_VOID=TRUE

5%

MF

1/20W

201

GND_VOID=TRUE

470K

R9472

0.01UF

0201

10%

X5R-CERM

25V

C9405

25V

0201

10%

X5R-CERM

0.01UF

C9406

CD3210A0RGP

CRITICAL

QFN

U9410

36

117

48

64 88

TBTHV:P15V

1/16W MF-LF

22.6K

1%

402

R9410

1%

402

1/16W

TBTHV:P15V

MF-LF

22.6K

R9411

1/16W

1%

402

36.5K

R9412

MF-LF

C9411

X7R

10%

603-1

50V

0.1UF

HVQFN

CBTL05023

CRITICAL

U9420

201

1/20W

MF

100K

5%

R9429

201

1/20W MF

100K

5%

R9428

201

X5R

6.3V

10%

0.1UF

C9420

201

X5R

6.3V

10%

0.1UF

C9421

36

112

85

112

85

112

15 88

112

36

107

201

5%

1M

MF

1/20W

R9426

10K

5%

MF

1/20W

201

R9427

201

X5R

6.3V

0.1UF

10%

C9425

36

107

36

107

36

107

36

107

36

107

0.22UF

20%

0201

X5R

6.3V

C9432

0.22UF

6.3V

20% X5R

0201

C9433

36

107

36

107

201X5R

6.3V

0.1UF

10%

C9430

201X5R

6.3V

10%

0.1UF

C9431

36

107

36

107

20%

0.22UF

6.3V

X5R

0201

C9478

X5R

20%

6.3V

0.22UF

0201

C9479

36

107

36

107

1/20W

MF

5%

470K

201

R9479

201

1/20W

MF

5%

470K

R9478

10%

4.7UF

X5R-CERM

25V

0603

C9415

22.6K

1/16W MF-LF

402

1%

TBTHV:P15V

R9413

1% 1/16W

402

MF-LF

22.6K

TBTHV:P15V

R9414

74AUP1T97

U9460

SOT891

CRITICAL

36

107

0.1UF

10%

0201

X5R-CERM

16V

C9460

J9400

CRITICAL

DUAL-MDP-D8

F-ANG-TH

65

C9474

0.47UF

CERM-X5R-1

20%

4V

201

GND_VOID=TRUE

C9475

0.47UF

20%

4V

CERM-X5R-1

201

GND_VOID=TRUE

C9476

201

CERM-X5R-1

4V

20%

0.47UF

GND_VOID=TRUE

4V

CERM-X5R-1

C9477

201

20%

0.47UF

GND_VOID=TRUE

C0G-NP0

C9498

5%

30PF

0402

50V

C9499

30PF

5% 50V C0G-NP0 0402

16V

10%

330PF

C9494

X7R-CERM 0201

0201

X7R-CERM

16V

10%

330PF

C9495

X7R-CERM

50V

10%

0.01UF

C9400

0402

C9401

10% 50V

0.01UF

0402

X7R-CERM

SYNC_DATE=03/13/2012

Thunderbolt Connector A

SYNC_MASTER=D8_AARON

114S0338

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

2

TBTHV:P12V

R9410,R9413

TBTHV:P12V

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

114S0338

R9411,R9414

2

DP_TBTPA_ML_P<3>

TBT_A_R2D_P<1> TBT_A_R2D_N<1>

PP3V3RHV_SW_TBTAPWR

MIN_NECK_WIDTH=0.20 MM VOLTAGE=12V

MIN_LINE_WIDTH=0.38 MM

TBT_A_LSRX_UNBUF

DP_TBTPA_ML_C_P<3> DP_TBTPA_ML_C_N<3>

TBT_A_D2R_N<0> TBT_A_D2R_P<0>

TBT_A_D2R_C_P<1>

TBT_A_D2R_N<1> TBT_A_D2R_P<1>

TBT_A_BIAS

TBT_A_D2R_C_N<0>

DP_A_LSX_ML_N<1>

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R1_AUXDDC_P

TBT_A_R2D_N<0>

DP_A_LSX_ML_P<1>

TBT_A_R2D_P<0>

DP_TBTPA_ML_N<1>

=PP3V3_S4_TBT

TBT_A_CIO_SEL

DP_A_AUXCH_DDC_N

DP_TBTPA_ML_C_P<1>

TBT_A_R2D_C_P<0> TBT_A_R2D_C_N<0>

TBT_A_CONFIG1_BUF

DP_TBTPA_DDC_DATA

DP_A_LSX_ML_N<1>

DP_A_LSX_ML_P<1>

DP_TBTPA_ML_P<1>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<1>

TBT_A_HPD

DP_TBTPA_DDC_CLK

TBT_A_CONFIG1_RC

DP_A_AUXCH_DDC_P

DP_AUXIO_EN

TBT_A_LSTX

=PPHV_SW_TBTAPWRSW

TBTAPWRSW_ISET_S0_R

TBT_A_DP_PWRDN

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_N DP_TBTPA_AUXCH_P

DP_TBTPA_AUXCH_C_P

=TBTAPWRSW_EN

=PP3V3_S4_TBTAPWRSW

TBT_A_HV_EN

=TBT_S0_EN

TBTAPWRSW_ISET_S3_R

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_V3P3

TBT_A_LSRX

DP_TBTPA_ML_C_N<1>

=PP3V3_S4_TBT

TBT_A_D2R_C_P<0>

TBT_A_HPD

DP_A_AUXCH_DDC_N

DP_A_AUXCH_DDC_P

TBT_A_D2R_C_N<1>

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_RC

DP_TBTPA_ML_N<3>

VOLTAGE=3.3V

TBT_A_BIAS

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

TBTACONN_1_C

MIN_NECK_WIDTH=0.20 MM VOLTAGE=18.9V

TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=12V

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18V

MIN_NECK_WIDTH=0.20 MM

prefsb

051-9504

7.0.0

94 OF 143

86 OF 117

2

1

12

121

2

1

2

21

2

1

2

11

2

121

2

121

2

21

2

1

AK

1

2

1

2

12

1

2

1

2

12

9

18

10

5

17

11

16

123

4

13

21

12

14

7

6

8

15

20

19

121

2

1

2

1

19

20

15

3

10

11

5

8

7

2

23

22

25

21

9

1

24

4

16 18

6

14

13

12 17

1

2

1

2

1

2

1

2

1

2

1

12

2

1

121

2

6

3

4

2

1

5

2

1

11

4

515049

47

464544

43

14

20

6

18

2

16

8

12

42

7

10

5

9

13

1 3

48

41

52

19

17

15

12

212

1

212

1

2

1

2

1

107

115

107

86

117

107

86

107

86

107

6

36 37 38 86 88

86

107

86

107

86

107

86

117

86

107

6

107

6

48

6

36 37 38 86 88

107

86

107

86

107

86

117

107

86

117

116

OUT

IN

NC

OUT

BI

IN

BI

OUT

BI

IN

OUT

NC

GND

Y1 Y2

A

NC

VCC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

On a H->L transition of A, Y2 follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video Y1 is simply an inverted version of A, with no delay

The delay applies only on a L->H transition on A. This guarantees video is valid before the backlight is enabled.

Backlight Control

ipd

U9500 OUTPUT Y2 IS A NON-INVERTED, DELAYED VERSION OF INPUT A

K6X BACKLIGHT CONTROL SUPPORT

guarantee backlight is only on when Panel has valid video

TO DIAGS LED

used by diag LED

155S0367

Display TCon Master

To BLC

518S0852

Display TCon Slave

INTERNAL DP (STRAIGHT)

518S0778

C9506

0.1UF

CERM

10V

20%

NOSTUFF

402

87 89 90

112

74 87

107

MF-LF

1/16W

402

0

5%

R9501

NOSTUFF

X5R-CERM 0805

16V

10%

10UF

C9520

50

113

50

113

50

56

107

84

112

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

84

107

74 87

107

89

112

F-RT-SM

J9500

CRITICAL

20525-140E-01

CRITICAL

53780-8606

J9520

DEVELOPMENT

M-RT-SM

0805

10% 16V

10UF

X5R-CERM

C9530

DEVELOPMENT

L9520

FERR-250-OHM

SM

DEVELOPMENT

NOSTUFF

0

5%

MF-LF

402

1/16W

R9502

0.001UF

20% 50V

0402

C9501

CERM

0.001UF

20% 50V CERM 0402

C9531

DEVELOPMENT

FERR-120-OHM-3A

L9500

0603

87 89 90

112

R9504

MF-LF

402

1/16W

5%

47

2

74AUP2G14GM

SOT886

5

U9502

BAT54XG

D9501

SOT23

C9502

402

CERM

0.1UF

10V

20%

5

2

74AUP2G14GM

SOT886

U9501

0

5%

MF-LF

1/16W

R9506

NOSTUFF

402

5

87

107

0

5%

MF-LF

402

1/16W

R9505

5

87

107

C9504

0.1UF

20% 10V

402

CERM

10% 16V

0805

X5R-CERM

10UF

C9503

20.0K

402

1/16W

1%

R9503

MF-LF

SOT886

2

5

74AUP2G14GM

U9501

74AUP2G14GM

U9502

5

2

SOT886

U9500

SN1105002

SC70

CRITICAL

NOSTUFF

SYNC_DATE=08/14/2012

Internal DP Support

SYNC_MASTER=D8_MLB

VIDEO_ON

VIDEO_ON_L

BLC_EN

LCD_BKL_ON_DLY

DP_INTPNL_ML_N<2>

VIDEO_ON

I2C_TCON_MAS_SCL

=PP12V_S0_LCD

VOLTAGE=12V MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

PP12V_LCD_EXT

DP_INTPNL_ML_N<3>

DP_INTPNL_AUX_N

=I2C_TCON_SLA_SDA

DP_INTPNL_HPD

I2C_TCON_MAS_SDA

BLC_VSYNC

DP_INTPNL_AUX_P

DP_INT_SPDIF_AUDIO

=I2C_TCON_SLA_SCL

=PP12V_S0_LCD

VOLTAGE=12V

PP12V_LCD

DP_INTPNL_ML_P<3>

DP_INTPNL_ML_P<2>

DP_INTPNL_ML_N<1>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_N<0>

DP_INTPNL_ML_P<0>

VIDEO_ON_L

=PP3V3_S0_DP

VIDEO_ON_L_DLY

=PP3V3_S0_DP

VIDEO_ON_K6X_L

BLC_EN

=PP3V3_S0_DP

BLC_EN_DELAY

VIDEO_ON

VIDEO_ON_D8_L

prefsb

051-9504

7.0.0

95 OF 143

87 OF 117

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

2

1

12

2

1

42

51

50

49

48

52

47

46

45

44

43

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

21 22 23

25

24

16

18

17

19 20

15

11 12 13 14

8 9

10

7

6

1 2

5

3 4

41

1

2

4

3

5

6

8

7

2

1

21

12

2

1

2

1

21

12

34

13

2

1

16

12

2

1

2

1

12

34

16

2

5 4

3

6

1

74 87

107

6

87

115

6

87

115

6

85 87

6

85 87

6

85 87

6

85 87

112

IN

OUT

IN

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND

THRM

OUT

VHV

ISET_V3P3

RSVD

V3P3

PAD

IN

DPMLO+ DPMLO-

VDD

DP-

DP+

DDC_CLK

AUX+

AUX-

AUXIO_EN

AUXIOAUXIO+

THMPAD

GND

BIASIN

BIASOUT

DDC_DAT

CA_DETOUT

CA_DET

DP_PD

LSTX LSRX

HPDOUT

HPD

OUT

BI

IN

OUT

IN

BI

IN

OUT

GND1

ML_LANE0N

ML_LANE1P

AUX_CHN

AUX_CHP

CONFIG1 CONFIG2

DP_PWR

GND2

HPD

ML_LANE3N

ML_LANE3P

SHLD

GND4

ML_LANE0P

GND0

RETURN

ML_LANE2N

ML_LANE2P

GND3

ML_LANE1N

PORT B

NC

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(Both C’s)

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

Nominal Min Max

NOTE: Polarity Swapped for Layout!

(Both C’s)

3.3V/HV Power MUX

TBT Dir

TBT: LSX_R2P/P2R (P/N)

Two Rs in series required by CD3210

High: 2.0 - 5.0V Low: 0 - 0.8V

470k R’s for ESD protection on AC-coupled signals.

(Both C’s)

TBT: RX_1 Bias Sink

(0-18.9V)

TBT Dir

(Both C’s)

TBT: LSX_A_R2P/P2R (P/N)

TBT: TX_1

DP Dir

greater than or equal

Sink HPD range:

to 100K (DPv1.1a).

(Both D’s)

TBT: Terminated

TBT: TX_0

DP Dir

DP Source must pull down HPD input with

IV3P3 1100mA 1030mA 1200mA

V3P3 must be S4 to support wake from Thunderbolt devices.

below

18.9V Max

12V: See

for single-fault protection(S0,S3 only)

Nominal Min Max

Thunderbolt Connector B

For 12V systems:

NOTE: Polarity Swapped for Layout!

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

514-0831

36

107

36

107

C9602

0201

X5R-CERM

10%

0.01UF

25V

1/20W

201

MF

5%

12

R9601

MF

1K

R9694

201

1/20W

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

5%

SIGNAL_MODEL=EMPTY

R9695

201

1/20W MF

GND_VOID=TRUE

1K

5%

R9641

100K

5%

MF

1/20W

201

L9698

650NH-5%-0.430MA-0.52OHM

CRITICAL

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

0603

L9699

GND_VOID=TRUE

0603

650NH-5%-0.430MA-0.52OHM

SIGNAL_MODEL=EMPTY

CRITICAL

C9681

0.1UF

402

CERM

10V

20%

C9680

6.3V

X5R-CERM-1

22UF

603

20%

CRITICAL

C9687

100UF

CASE-B2-SM

POLY-TANT

20%

6.3V

CRITICAL

R9652

201

1/20W

MF

1M

5%

R9651

201

1/20W MF

5%

1M

R9698

201

1/20W

MF

2.2K

5%

GND_VOID=TRUE

R9699

201

1/20W MF

2.2K

5%

GND_VOID=TRUE

L9600

0603

FERR-120-OHM-3A

36

107

C9610

0.1UF

603-1

X7R

50V

10%

D9699

BAR90-02LRH

TSLP-2-7

CRITICAL

GND_VOID=TRUE

D9698

TSLP-2-7

BAR90-02LRH

CRITICAL

GND_VOID=TRUE

R9670

GND_VOID=TRUE

5%

470K

MF

1/20W

201

R9671

470K

5%

MF

1/20W

201

GND_VOID=TRUE

C9671

0.22UF

20%

6.3V

X5R

GND_VOID=TRUE

0201

C9670

X5R

20%

6.3V

GND_VOID=TRUE

0201

0.22UF

36

107

36

107

C9672

GND_VOID=TRUE

6.3V

X5R

20%

0.22UF

0201

C9673

GND_VOID=TRUE

6.3V

X5R

20%

0.22UF

0201

R9673

GND_VOID=TRUE

5%

470K

MF 201

1/20W

R9672

470K

5%

MF

1/20W

201

GND_VOID=TRUE

C9605

0201

0.01UF

X5R-CERM

10% 25V

C9606

0201

0.01UF

X5R-CERM

10% 25V

U9610

CD3210A0RGP

CRITICAL

QFN

36

117

48

64 86

R9610

1%

402

MF-LF

1/16W

TBTHV:P15V

22.6K

R9611

TBTHV:P15V

1/16W

402

MF-LF

1%

22.6K

MF-LF 402

R9612

1/16W

36.5K

1%

C9611

10%

X7R

0.1UF

50V

603-1

U9620

CRITICAL

CBTL05023

HVQFN

R9629

201

1/20W

MF

5%

100K

R9628

201

1/20W MF

5%

100K

C9620

10%

201

X5R

0.1UF

6.3V

C9621

10%

201

X5R

6.3V

0.1UF

36

112

85

112

85

112

15 86

112

36

107

R9626

201

1/20W

MF

1M

5%

R9627

201

1/20W MF

10K

5%

C9625

10%

201

X5R

6.3V

0.1UF

36

107

36

107

36

107

36

107

36

107

X5R

20%

6.3V

0.22UF

0201

C9632

C9633

X5R

20%

6.3V

0.22UF

0201

36

107

36

107

C9630

10%

201X5R

6.3V

0.1UF

C9631

10%

201X5R

6.3V

0.1UF

36

107

36

107

0.22UF

6.3V

20% X5R

0201

C9678

C9679

X5R

6.3V

20%

0.22UF

0201

36

107

36

107

R9679

201

1/20W

MF

470K

5%

R9678

201

1/20W

MF

470K

5%

R9613

TBTHV:P15V

1/16W MF-LF

402

1%

22.6K

R9614

TBTHV:P15V

1%

MF-LF 402

1/16W

22.6K

C9615

0603

4.7UF

X5R-CERM

25V

10%

U9660

74AUP1T97

SOT891

CRITICAL

C9660

0.1UF

10%

0201

X5R-CERM

16V

36

107

DUAL-MDP-D8

CRITICAL

J9400

F-ANG-TH

65

C9676

201

CERM-X5R-1

4V

20%

0.47UF

GND_VOID=TRUE

C9677

0.47UF

20%

4V

CERM-X5R-1

201

GND_VOID=TRUE

C9674

201

CERM-X5R-1

4V

20%

0.47UF

GND_VOID=TRUE

C9675

201

CERM-X5R-1

4V

20%

0.47UF

GND_VOID=TRUE

50V

0402

30PF

5%

C0G-NP0

C9698

C9699

30PF

5% 50V C0G-NP0 0402

0201

X7R-CERM

16V

10%

330PF

C9695

16V

10%

330PF

X7R-CERM 0201

C9694

0.01UF

10% 50V

C9600

X7R-CERM 0402

X7R-CERM

50V

10%

C9601

0.01UF

0402

Thunderbolt Connector B

SYNC_MASTER=D8_AARON SYNC_DATE=03/13/2012

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

114S0338

R9611,R9614

2

TBTHV:P12V

R9610,R9613

2

114S0338

RES,MTL FILM,1/16W,17.8K,1,0402,SMD,LF

TBTHV:P12V

TBT_B_R2D_P<0> TBT_B_R2D_N<0>

TBTBCONN_7_C

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=12V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_SW_TBTBPWR

TBT_B_D2R_C_N<0>

TBT_B_HPD

TBT_B_D2R_C_P<0>

DP_B_LSX_ML_N<1>

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MM

TBT_B_D2R1_AUXDDC_P

DP_TBTPB_ML_N<3>

DP_TBTPB_ML_P<3>

DP_TBTPB_ML_C_P<3>

TBT_B_R2D_N<1>

TBT_B_R2D_P<1>

TBT_B_BIAS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

TBTBCONN_20_RC

VOLTAGE=18V

MIN_LINE_WIDTH=0.38 MM

PPHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=12V

DP_B_AUXCH_DDC_P DP_B_AUXCH_DDC_N

TBT_B_D2R_C_P<1>

DP_TBTPB_ML_C_N<1>

TBT_B_LSRX_UNBUF

DP_TBTPB_ML_C_P<1>

TBTBPWRSW_ISET_V3P3

=PP3V3_S4_TBT

DP_TBTPB_AUXCH_P

DP_TBTPB_ML_N<1>

DP_AUXIO_EN

TBT_B_LSRX

=PP3V3_S4_TBT

TBTBPWRSW_ISET_S0_R

=PP3V3_S4_TBTBPWRSW

=PPHV_SW_TBTBPWRSW

=TBT_S0_EN

TBTBPWRSW_ISET_S3_R

TBT_B_HV_EN

TBTBPWRSW_ISET_S0

TBTBPWRSW_ISET_S3

=TBTBPWRSW_EN

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0> TBT_B_R2D_C_N<0>

DP_TBTPB_ML_P<1>

TBT_B_LSTX

DP_TBTPB_AUXCH_N

DP_TBTPB_ML_C_N<3>

TBT_B_R2D_C_N<1>

DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

DP_B_AUXCH_DDC_N DP_B_AUXCH_DDC_P

DP_B_LSX_ML_P<1> DP_B_LSX_ML_N<1>

DP_TBTPB_DDC_CLK

DP_TBTPB_DDC_DATA

TBT_B_CONFIG1_BUF

TBT_B_HPD

TBT_B_DP_PWRDN

DP_TBTPB_HPD

TBT_B_CONFIG1_RC

TBT_B_CIO_SEL

TBT_B_BIAS

TBT_B_D2R1_AUXDDC_N

DP_B_LSX_ML_P<1>

TBT_B_D2R_N<1> TBT_B_D2R_P<1>

TBT_B_D2R_C_N<1>

TBT_B_D2R_N<0> TBT_B_D2R_P<0>

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_RC

prefsb

051-9504

7.0.0

96 OF 143

88 OF 117

2

1

12

121

2

1

2

21

2

1

2

11

2

121

2

121

2

21

2

1

AK

1

2

1

2

12

1

2

1

2

12

9

18

10

5

17

11

16

123

4

13

21

12

14

7

6

8

15

20

19

121

2

1

2

1

19

20

15

3

10

11

5

8

7

2

23

22

25

21

9

1

24

4

16 18

6

14

13

12 17

1

2

1

2

1

2

1

2

1

2

1

12

121

2

1

6

3

4

2

1

5

2

1

27

25

29

38

36

24 26

40

28

22

32

30

53

54

565758

5960616263

64

55

34

23

21

39

37

35

33

31

12

212

1

212

1

2

1

2

1

107

115

107

88

107

88

107

88

117

116

88

107

88

107

6

36 37 38 86 88

107

6

36 37 38 86 88

6

48

6

107

88

107

88

107

88

107

88

107

88

117

88

117

107

88

107

88

117

NC NC

OUT

B

Y

A

IN

NC

G

D

S

NC

B

Y

A

NC

G

S

D

NC

NC NC

S

D

G

NC

THRM_PAD

VDD

GND

COMP

DIS/EN*

BP

GDRV

ISNS

RC

SS

FB

NC

D

GS

Y

A

B

08

D

GS

Y

A

B

08

IN

GND

OUT

GND

OUT

IN

NC

P1.26/RTCK

P1.27/TDO

P0.3/SDA0/MAT0.0/EINT1 P0.4/SCK0/CAP0.1/AD0.6

P0.10/CAP1.0

P0.9/RXD1/PWM6/EINT3

P0.8/TXD1/PWM4

P0.29/AD0.2/CAP0.3/MAT0.3

VDD

VDDA VREF

P0.23

P0.27/AD0.0/CAP0.1/MAT0.1

P0.30/AD0.3/EINT3/CAP0.0

P0.0/TXD0/PWM1 P0.1/RXD0/PWM3/EINT0 P0.2/SCL0/CAP0.0

P0.5/MISO0/MAT0.1/AD0.7 P0.6/MOSI0/CAP0.2 P0.7/SSEL0/PWM2/EINT2

P0.11/CAP1.1/SCL1 P0.12/MAT1.0 P0.13/MAT1.1 P0.14/EINT1/SDA1 P0.15/EINT2 P0.16/EINT0/MAT0.2/CAP0.2 P0.17/CAP1.2/SCK1/MAT1.2 P0.18/CAP1.3/MISO1/MAT1.3 P0.19/MAT1.2/MOSI1/CAP1.2 P0.20/MAT1.3/SSEL1/EINT3 P0.21/PWM5/CAP1.3 P0.22/CAP0.0/MAT0.0

P0.25/AD0.4/AOUT P0.26/AD0.5

P0.28/AD0.1/CAP0.2/MAT0.2

P0.31

P1.16/TRACEPKT0 P1.17/TRACEPKT1 P1.18/TRACEPKT2 P1.19/TRACEPKT3 P1.20/TRACESYNC P1.21/PIPESTAT0 P1.22/PIPESTAT1 P1.23/PIPESTAT2

P1.24/TRACECLK

P1.25/EXTIN0

P1.28/TDI P1.29/TCK P1.30/TMS

P1.31/TRST*

RESET*

RTCX1 RTCX2

VBAT

VSS

VSSA

XTAL1 XTAL2

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

APN 998-3605

(WAS BLC_BLON)

14V BLC PRE-REGULATOR

(IPU)

BLC_EN IS DRIVEN BY TCON (CSA95)

353S3748

(WAS BLC_GPIO)

BLC MCU

D8:SUOPERTEX GPIOS FOR BLC ISP RDAR://10987156

D8 PROTO 2 BLC ADDING 3.3V VOLTAGE REFERENCE RDAR://11280328

MCU ISP PROG AND TEST CONNECTOR

R9716

MF-LF

1/16W

0

5%

402

R9717

402

10M

5% 1/16W MF-LF

402

MF-LF

1/16W

5%

4.7K

R9718

NOSTUFF

5% 1/16W MF-LF 402

4.7K

R9719

NOSTUFF

1/16W

5%

MF-LF

402

10K

R9715

R9705

10K

5% 1/16W MF-LF 402

5% 1/16W

402

R9707

MF-LF

100K

1K

R9706

5% 1/16W MF-LF

402

MF-LF1/16W

5%

1K

402

R9702

SOD323-SM

BAS316DG

D9700

R9703

100K

5% 1/16W MF-LF 402

16V

C9705

1UF

10%

402

X5R

402

MF-LF

1/16W

5%

4.7K

NOSTUFF

R9720

402

MF-LF

1/16W

5%

4.7K

R9721

NOSTUFF

402

5%

0

MF-LF

R9726

1/16W

NOSTUFF

MF-LF

402

R9728

1K

5%

1/16W

MF-LF

1/16W

402

5%

R9727

10K

J9700

DEVELOPMENT

CF20151D0R0-NH

F-RT-SM

C0G-CERM

C9701

1000PF

5% 50V

603

C9702

1000PF

5% 50V C0G-CERM 603

C9703

1000PF

5% 50V C0G-CERM 603

1000PF

C9725

5%

603

50V C0G-CERM

C9709

C0G-CERM

50V

603

5%

1000PF

91

112

74LVC1G08GW

SOT353

U9780

89

112

603

MF-LF

1/10W

100K

R9780

1%

1KOHM-25%-0.6A

L9702

NOSTUFF

0603

2.2UF

10% 16V X5R 603

C9735

L9704

0603

1KOHM-25%-0.6A

0

R9722

5% 1/16W MF-LF

402

C0G-CERM 603

5%

C9722

1000PF

50V

603

MF-LF

1% 1/10W

R9724

10K

BSH111DG

SOT23-3

Q9700

10K

R9725

MF-LF

603

1%

1/10W

J9701

HB3902U-L

M-ST-TH

NOSTUFF

1210

10%

X5R

35V

C9748

10UF

PRE_BOOST:Y

TO277A

SS12P4S

D9740

MLP5X6-LFPAK-Q5A

CSD16412Q5A

PRE_BOOST:Y

Q9740

PRE_BOOST:Y

49.9K

1%

R9750

1/10W

603

MF-LF

12UH-7A-0.02OHM

NOSTUFF

L9740

PIMB136T-SM

NOSTUFF

1%

1/8W

R9744

MF-LF

805

10

PRE_BOOST:Y

R9749

MF

1W

2010

1%

0.010

PRE_BOOST:Y

MF-LF

1/10W

1%

R9748

1.0K

603

PRE_BOOST:Y

1.0UF

C9744

10% 50V X7R 0805

PRE_BOOST:Y

330K

R9743

603

1/10W MF-LF

5%

PRE_BOOST:Y

50V

1.0UF

X7R 0805

10%

C9743

PRE_BOOST:Y

C9742

CERM

5%

603

270PF

50V

PRE_BOOST:Y

603-1

0.1UF

C9746

50V

10%

X7R

PRE_BOOST:Y

X7R

10%

50V

603-1

0.1UF

C9741

PRE_BOOST:Y

R9745

805

1% 1/8W MF-LF

1.10K

PRE_BOOST:Y

10K

1%

1/10W

R9742

MF-LF

603

PRE_BOOST:Y

C9740

1500PF

50V

603

CERM

10%

MF-LF

2512

R9752

1W1%

0.001

U9790

SOT353

74LVC1G08GW

2N7002

SOT23-HF1

Q9701

R9790

MF-LF

1/16W

5%

402

10K

5%

1/16W

R9791

10K

402

MF-LF

1/16W

5%

MF-LF 402

R9793

10K

R9792

10K

402

5%

MF-LF

1/16W

X5R-CERM

C9771

603

25V

10%

2.2UF

X5R-CERM

10% 25V

0603

C9770

4.7UF

PRE_BOOST:Y

R9740

603

MF-LF

0

5% 1/10W

PRE_BOOST:Y

22K

R9741

5%

MF-LF

1/10W

603

NOSTUFF

POWER56

FDMS6681Z

Q9741

603

R9747

1/10W

30.1

MF-LF

1%

PRE_BOOST:Y

R9797

0

402

MF-LF1/16W

5%

PRE_BOOST:Y

MSOP

TPS40210

U9740

R9781

100K

MF-LF

5% 1/16W

402

PRE_BOOST:Y

10% 50V

0402

C9745

390PF

X7R-CERM

PRE_BOOST:Y

0603

X7R-CERM

50V

10%

0.068UF

C9747

PRE_BOOST:Y

MF-LF

R9751

1/10W

1%

603

49.9K

Q9711

CRITICAL

VESM

SSM3K15AMFVAPE

8

4

SOT902

CRITICAL

74LVC2G08

U9710

6.3V X5R 201

10%

0.1UF

C9710

SSM3K15AMFVAPE

Q9710

VESM

CRITICAL

8

4

74LVC2G08

SOT902

CRITICAL

U9710

R9712

0

402

1/16W

MF-LF

5%

R9713

0

402

5%

1/16W

MF-LF

1/16W

402

MF-LF

R9711

100K

5%

NOSTUFF

100K

5% 1/16W

402

R9710

MF-LF

NOSTUFF

MF-LF1/16W

0

402

R9730

5%

402

MF-LF

0

R9731

1/16W

5%

C0G-CERM 0402

C9706

50V

5%

18PF

C9707

C0G-CERM

50V

5%

0402

18PF

ELEC

25V

20%

470UF

C9749

10X10.8-SM

L78M08ABDT

U9770

DPAK

1KOHM-25%-0.6A

L9703

0603

1/16W

5%

R9732

10K

NOSTUFF

MF-LF 402 402

5% 1/16W

R9733

MF-LF

10K

SOT23-3

REF3333

U9720

10%

X5R

16V

603

2.2UF

C9720

X5R-CERM

10%

6.3V

603

C9721

4.7UF

0.100

0.1%

R9701

1/4W

MF

1206

25V

C9733

1000PF

CERM

5%

603

2.2UF

X5R

10% 16V

C9734

603

CRITICAL

12.000MHZ-30PPM-10PF-85C

3.2X2.5MM-SM

Y9705

0402

C9791

0.1UF

10% 16V X7R-CERM

0402

C9792

X7R-CERM

16V

10%

0.1UF

X7R-CERM

0.1UF

10% 16V

0402

C9704

C9708

0402

16V

10%

X7R-CERM

0.1UF

C9790

10%

0.1UF

X7R-CERM

16V

0402

U9700

LPC2132FBD64

OMIT_TABLE

LQFP

SYNC_MASTER=D8_MLB

Backlight Controller MCU

SYNC_DATE=04/23/2012

BLC_MCU_RXD0 BLC_MCU_B_SDA_CONN

LCD_BKLT_PWM

BOOST_BYPASS

PP12V_S0_BLC_VINP

BOOST_FET_DRAIN

BLC_P3V3_REF

BOOST_FB

BOOST_ISNS_R

BLC_MCU_XTAL_IN

BLC_MCU_XTAL_OUT

BLC_MCU_RESET_L

TP_BLC_MCU_TP_2

SMB_PCH_BLC_SCL

PP5V_S0_BLC_R

BLC_P3V3S

LED_DRIVER_OVP3P

LCD_BKLT_PWM

BLC_P3V3S

BLC_EXT_BOOT_L

=PP3V3_S0_BLC

BLC_P3V3S

BLC_P3V3_REF

BLC_P3V3S

BLC_MCU_PWM5_R

PP5V_S0_BLC_R

BLC_P_ON

BOOST_GDRV

BLC_P3V3S

SMB_PCH_BLC_SDA

BLC_MCU_RXD0

PCH_BLC_MCU_RESET

BLC_UVLO

BLC_VSYNC

SMB_PCH_BLC_SDA

PM_PCH_PWROK

PCH_BLC_EXT_BOOT

BLC_MCU_UVLO

BLC_P3V3S

PP12V_S0_BLC_VIN2

PP8V_BLC

BLC_EN_R

TP_PCH_GPIO6_TACH2

BLC_MCU_RESET_L

BLC_MCU_TRST

BLC_P3V3S

BOOST_ISNS

BOOST_VDD

FLAG_V

BLC_ENA

BLC_MCU_TMS

BLC_MCU_RTCK

BLC_PWM_3_R

BLC_MCU_TCK

BOOST_COMP_C

BLC_BST

BOOST_COMP

PRE_REG_OUT_R

BOOST_GDRV_R

BLC_EN

BLC_PWM_2_R

BLC_MCU_TDI

BOOST_RC

BLC_BL

BLC_ENA

BLC_ENA1

FLAG_V

SMB_TCON_BLC_SDA

BLC_MCU_TXD0

=PP3V3_S0_BLC

BLC_EN

BLC_MCU_TDI

BLC_MCU_RTCK BLC_MCU_TDO

BLC_MCU_TCK

BLC_MCU_TXD0

BLC_PWM_1_R

BLC_GOOD

BLC_MCU_TDO

BLC_MCU_RXD0

SMB_TCON_BLC_SCL

BLC_MCU_XTAL_OUT_R

PP5V_S0_BLC_R

BLC_MCU_BV

BLC_MCU_FLAG_V

PRE_REG_OUT

SMC_BLC_MUX_TX_L

SMC_BLC_MUX_RX_L

BLC_MCU_RESET

BLC_MCU_RESET_L

BLC_VSYNC

STRCLK_R1

BLC_P3V3A

PP3V3_S0_BLC_R

PRE_REG_OUT

BLC_MCU_RESET_R_L

BLC_EXT_BOOT

BLC_MCU_TXD0

PM_PCH_PWROK

BLC_VSYNC_R

BLC_DIM_MCU

BLC_MCU_PWM5

LED_DRIVER_OVP2P

LED_DRIVER_OVP1P

SMB_PCH_BLC_SDA

BLC_MCU_TMS

BOOST_EN_L

BLC_BST_R

BOOST_EN_GATE

BLC_P3V3S

BLC_P3V3A

BLC_P3V3S

BOOST_BYPASS_GATE

BOOST_SS

BOOST_BP

prefsb

051-9504

7.0.0

97 OF 143

89 OF 117

1

2

12

1

2

1

2

12

1

2

1

2

12

AK

1

2

1

2

1

2

12

1

2

1 2 3 4 5 6 7 8 9 10

12

11

13 14 15

17

16

2

1

2

1

2

1

2

1

2

1

4

3

1

2

5

1

2

21

2

1

21

12

2

11

2

3

2

1

12

2

1

2

1

3

2

5

123

4

1

2

21

12

1

2

12

2

1

12

2

1

2

1

2

1

12

1

2

12

4

3

1

2

5

3

2

1

2

12

1

2

1

2

1

2

1

2

12

3 2 1

5

4

12

11

10

6

4

3

9

8

7

1

2

5

1

2

1

2

1

2

1

2

3

1

6

7

2

1

2

3

5

2

3

12

1

2

1

2

12

2

1

2

1

2

1

2

3

21

121

2

3

21

2

1

2

1

12

2

1

2

1

42

13

2

1

2

1

2

1

2

1

2

1

24 64

26 27

35

34

33

14

234351

7

63

58

11

15

19 21 22

29 30 31

37 38 39 41 45 46 47 53 54 55

1 2

9

10

13

17

16 12 8 4 48 44 40 36 32 28

60 56 52 20

57

3 5

49

6

1825425059

62 61

89

112

84 89

107

91

112

91

109

89 91

109

89

112

50

109

89 90 91

109

89 91

109

90

114

84 89

107

89 91

109

112

6

89

89 91

109

89 91

109

89 91

109

112

89 90 91

109

90 91

112

109

89 91

109

50 89

109

89

112

21

114

91

112

87 89

112

50 89

109

15 19 26 35 43 65 89

115

21

114

112

89 91

109

90 91

109

90

109

112

89

112

89

112

89

112

89 91

109

89 90 91

113

89

112

89

112

89

112

90

109

89

112

109

91 112

109

87 89 90

112

90

109

89

112

91

112

89 90 91

113

50

109

89

112

6

89

87 89 90

112

89

112

89

112

89

112

89

112

89

112

90

109

5

89

112

89

112

50

109

89 90 91

109

91

112

89 90

109

48

116

48

116

112

89

112

87 89

112

90

109

89

109

89 90

109

112

48

112

89

112

15 19 26 35 43 65 89

115

112

90

114

90

114

50 89

109

89

112

89

112

89

112

89 91

109

89 91

109

89 91

109

89

89 91

109

112

OUT

IN

OUT

IN

G

D

S

OUT

G

D

S

IN

OUT

G

D

S

IN

S

G

D

S

G

D

S

G

D

VDD3

VIN

VDD1

VDD2

VDD

GATE1

CS1

FDBK1

OVP1

FLT1

CS2

GATE2

OVP2

GATE3

FLT2

FDBK2

FDBK3

FLT3

CS3

OVP3

GND1

GND

GND2

GND3

THRM

PWMD2

PWMD1

PWMD3

IREF3

IREF2

IREF1

CLK

EN

COMP1

COMP3

COMP2

SKIP

VIN_SNS

FLG

SC

NC

PAD

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

805

R9820

100K

1/8W

1%

MF-LF

603

1000PF

C9824

100V X7R

10%

90 91

109

89

109

X7R

100V

603

NOSTUFF

C9825

1000PF

10%

91

109

R9803

1%

2.0K

1/10W

603

MF-LF

603

1%

MF-LF1/10W

2.0K

R9804

2.0K

R9801

MF-LF1/10W

603

1%

NOSTUFF

150PF

C9829

402

50V

5%

CERM

91

109

91

109

91

109

SOD323-SM

BAS316DG

D9800

89

114

90 91

114

87 89

112

0

R9834

5% 1/10W MF-LF 603

NOSTUFF

HWSON-8

Q9821

RJK1211DNS

R9824

1%

603

634K

1/10W

NOSTUFF

MF-LF

1/16W

24.9K

0.1%

MF-LF

603

R9806

1% 1W

4.7

2512

MF

R9826

NOSTUFF

220

R9825

1/10W MF-LF

5%

603

TO277A

SS5P10-M3

SD9820

XW9800

SHORT-1206

90 91

114

89

114

SD9860

SS5P10-M3

TO277A

1% 1/10W MF-LF 603

1M

R9808

1000PF

10%

X7R

C9864

603

100V

R9860

100K

MF-LF

1%

805

1/8W

1%

MF 2512

NOSTUFF

R9866

1W

4.7

50V

NOSTUFF

150PF

C9869

CERM

5%

402

220

1/10W MF-LF

5%

R9865

603

R9863

603

1/10W

0

5%

MF-LF

RJK1211DNS

Q9861

HWSON-8

R9864

634K

603

1%

MF-LF

NOSTUFF

1/10W

91

109

LED_FLT_R_3

R8667

22

5%

805

1/8W

MF-LF

100V

NOSTUFF

10%

1000PF

C9865

X7R 603

1.0K

1%

R9869

603

MF-LF

1/10W

0

R9874

5% 1/10W MF-LF 603

NOSTUFF

91

109

91 109

90 91

114

89

114

SS5P10-M3

SD9840

TO277A

1%

603

MF-LF

1.0K

R9805

1/10W

100V

1000PF

603

C9844

10%

X7R

R9840

100K

1/8W MF-LF

1%

805

NOSTUFF

R9846

4.7

2512

1W MF

1%

C9849

NOSTUFF

150PF

5% 50V

402

CERM

X7R

1000PF

C9845

NOSTUFF

100V

10%

603

R9845

1/10W

220

5%

MF-LF

603

R9843

0

MF-LF

603

5%

1/10W

HWSON-8

RJK1211DNS

Q9841

NOSTUFF

634K

R9844

1/10W

1%

MF-LF

603

91

109

22

R8647

5%

1/8W

LED_FLT_R_2

805

MF-LF

1%

1/10W

1.0K

R9849

MF-LF

603

NOSTUFF

1/10W

603

MF-LF

5%

R9854

0

PLACE_NEAR=U9800.9:3MM

1UF

10%

603-2

C9808

X5R-X7R

16V

Q9820

DIRECTFET-SJ

IRF6645PBF

Q9840

DIRECTFET-SJ

Q9860

IRF6645PBF

0603

FF

0%

1/10W

R9891

0.00

1/10W

0603

0%

FF

R9892

0.00

0603

FF

0%

1/10W

0.00

R9893

DFLS1100

D9820

POWERDI-123

NOSTUFF

D9840

POWERDI-123

DFLS1100

POWERDI-123

NOSTUFF

D9860

DFLS1100

25V

2.7NF

10%

NOSTUFF

C9880

X7R-CERM 0603

QFN

HV9989K6-G

U9800

0603

0%

FF

0.00

R9881

1/10W

C9833

10%

1000PF

100V

603

X7R

CRITICALCRITICAL

10% 100V X7R 603

1000PF

C9832C9859

1000PF

100V

603

10%

X7R

CRITICAL

1000PF

X7R

10%

CRITICAL

C9822

603

100V

CRITICAL

C9821

1000PF

100V

10%

X7R 603603

CRITICAL

C9820

1000PF

10% 100V X7R

C9812

1UF

X7R

10%

0603

25V

C9813

1UF

10% 25V

0603

X7R

1.0K

1/10W MF-LF

603

1%

R9829

10%

0603

CERM-X5R

50V

0.47UF

C9802

OMIT_TABLE

33UH-20%-10A-0.0351OHM

IHLP6767GZ-SM

L9820

OMIT_TABLE

IHLP6767GZ-SM

33UH-20%-10A-0.0351OHM

L9840

OMIT_TABLE

33UH-20%-10A-0.0351OHM

IHLP6767GZ-SM

L9860

R9835

0

5% 1/10W MF-LF

603

5%

1/10W

R9855

603

MF-LF

0

1/10W

5%

603

MF-LF

R9875

0

1/10W

NOSTUFF

0

5%

603

MF-LF

R9847

0.03

R9828

2512-LF

MF

2W

1%

1% 2W MF 2512-LF

0.03

R9848

2512-LF

1% 2W MF

0.03

R9868

0603

1000PF

C9830

100V X7R-CERM

10%

C9850

10%

0603

1000PF

X7R-CERM

100V

1000PF

10%

X7R-CERM 0603

C9870

100V

5%

0603

C0G-CERM

100PF

C9851

C9871

0603

5%

C0G-CERM

100V

100PF

C9831

0603

5%

C0G-CERM

100V

100PF

C9881

100V 0603

5%

C0G-CERM

NOSTUFF

C9882

100V

C0G-CERM

5%

100PF

0603

NOSTUFF

100V

5%

100PF

C9883

0603C0G-CERM

1/10W

120K

MF-LF

5%

603

R9880

22

R9827

LED_FLT_R_1

805

5%

1/8W

MF-LF

100K

1%

402

R9897

1/16W

50V CERM 0603-1

C9806

10%

PLACE_NEAR=U9800.15:3MM

0.0022UF

XW9803

SHORT-1206

R9822

MF-LF

2.94K

603

1/10W

1%

845

R9821

603

MF-LF

1/10W

1%

2.94K

1/10W

R9842

1%

MF-LF 603

R9841

1% 1/10W MF-LF 603

845

1% 1/10W MF-LF 603

2.94K

R9862

1% 1/10W MF-LF 603

845

R9861

1206-1

X5R

10% 25V

10UF

C9873

10UF

C9872

1206-1

X5R

25V

10%

C9874

X5R

10% 25V

1206-1

10UF

10%

1206-1

25V X5R

C9875

10UF

C9877

10UF

1206-1

25V X5R

10%

C9876

10UF

10%

X5R

25V

1206-1

1

R9896

402

5% 1/16W MF-LF

0.1%

0603

FF

1/10W

6.2

R9830

0603

FF

51

R9833

0.1%

1/10W FF 0603

0.1% 1/10W

6.2

R9831

FF 0603

0.1% 1/10W

6.2

R9832

R9853

0603

FF

1/10W

0.1%

51

R9852

0603

6.2

FF

1/10W

0.1%

R9851

0603

6.2

FF

1/10W

0.1%

R9850

0603

6.2

FF

1/10W

0.1%

R9873

51

0603

0.1% 1/10W FF

R9872

0.1% 1/10W FF

6.2

0603

6.2

1/10W

0.1%

R9870

0603

FF

R9871

0.1% 1/10W FF

6.2

0603

PLACE_NEAR=U9800.12:3MM

C9891

100PF

5%

CERM 603

50V

PLACE_NEAR=U9800.4:4MM

CERM

5%

C9890

100PF

603

50V

C9892

PLACE_NEAR=U9800.27:3MM

CERM

50V

5%

100PF

603

5%

R9823

0

1/10W

603

MF-LF

ELEC 10X12.5-TH

100V

20%

C9823

56UF

C9843

10X12.5-TH

100V ELEC

20%

C9863

56UF

10X12.5-TH

100V

20%

ELEC

PLACE_NEAR=U9800.4:7MM

R9814

143K

1/10W

1%

MF-LF 603

PLACE_NEAR=U9800.12:6MM

R9815

143K

MF-LF

1/10W

603

1%

PLACE_NEAR=U9800.27:5MM

R9816

1/10W MF-LF 603

1%

143K

603

PLACE_NEAR=R9815.2:25MM

C0G-CERM

C9816

1000PF

5% 50V

PLACE_NEAR=R9815.2:2MM

C0G-CERM 603

5% 50V

C9815

1000PF

C0G-CERM

PLACE_NEAR=R9814.2:2MM

5% 50V

603

C9814

1000PF

1/16W MF-LF

1%

6.98K

402

R9898

1210-2

X7R-CERM

100V

10%

CRITICAL

C9826

2.2UF

1210-2

X7R-CERM

100V

10%

CRITICAL

C9827

2.2UF

1210-2

CRITICAL

100V X7R-CERM

10%

C9828

2.2UF

1210-2

C9840

2.2UF

CRITICAL

10% 100V X7R-CERM

1210-2

100V

2.2UF

C9841

CRITICAL

10%

X7R-CERM

1210-2

X7R-CERM

100V

10%

2.2UF

C9842

CRITICAL

1210-2

C9853

2.2UF

CRITICAL

10% 100V X7R-CERM

1210-2

C9854

2.2UF

CRITICAL

10% 100V X7R-CERM

1210-2

C9855

2.2UF

CRITICAL

10% 100V X7R-CERM

1210-2

2.2UF

C9856

CRITICAL

10% 100V X7R-CERM

1210-2

X7R-CERM

100V

10%

CRITICAL

C9857

2.2UF

1210-2

2.2UF

C9858

CRITICAL

10% 100V X7R-CERM

R9817

2.0M

MF-LF

1/10W

PLACE_NEAR=U9800.4:5MM

0603

1%

R9812

2.0M

1/10W

PLACE_NEAR=U9800.12:4MM

0603

MF-LF

1%

PLACE_NEAR=U9800.27:3MM

2.0M

1% 1/10W MF-LF 0603

R9818

PLACE_NEAR=U9800.1:4MM

X5R-X7R 603-2

1UF

10% 16V

C9809

PLACE_NEAR=U9800.33:3MM

1UF

C9810

603-2

10% 16V X5R-X7R

PLACE_NEAR=U9800.30:3MM

10%

603-2

X5R-X7R

16V

1UF

C9811

SHORT-1206

XW9801

XW9802

SHORT-1206

SYNC_DATE=04/23/2012

Backlight LED Driver

SYNC_MASTER=D8_MLB

152S1668 CRITICAL

L9820,L9840,L9860

IND,PWR,33UH,20%,10A,35.5MOHM

3

PRE_REG_OUT

BLC_VOUT1

PRE_REG_OUT

BLC_SNUB_3

LED_DRVR_CS_RC_3

LED_DRVR_DRAIN_3

LED_DRVR_DRAIN_1

BLC_GND_1

BLC_VOUT1

BLC_GND_1

BLC_VOUT1

BLC_GND_1

BLC_GND_3

LED_DRIVER_OVP3

BLC_VOUT3

LED_DRIVER_OVP3P

LED_DRIVER_OVP2_OUT

BLC_GND_2

BLC_VIN_SNS

PP5V_S0_BLC_R

LED_DRIVER_GATE3

BLC_GND_2

IS2_BLC

LED_DRVR_CS_C1

LED_DRIVER_GATE3

BLC_GND_2

BLC_GND_3

BLC_GND_1

BLC_VOUT2

BLC_SNUB_2

BLC_SKIP

LED_DRIVER_REF3

LED_DRIVER_REF1

LED_DRIVER_OVP1_OUT

LED_DRIVER_GATE2

BLC_GND_1

LED_DRIVER_FDBK3

BLC_PWM_3

BLC_GND_3

LED_DRIVER_FDBK3

LED_DRIVER_FDBK_R_3

LED_DRIVER_OVP3

BLC_GND_2

LED_DRIVER_FDBK_R_2

BLC_GND_1

LED_DRIVER_FDBK_R_1

PRE_REG_OUT

LED_DRIVER_OVP2

LED_DRIVER_GATE3_R

LED_DRIVER_OVP1

BLC_GND_1

LED_DRIVER_GATE2_R

PP12V_S0_BLC_VIN2

SPTX_VIN

LED_DRIVER_FDBK1

LED_DRIVER_REF2

BLC_GND_1

LED_DRIVER_OVP2P

LED_DRIVER_OVP2

LED_DRIVER_OVP1P

LED_DRVR_CS_RC_1

LED_DRIVER_CS2

LED_DRIVER_FDBK2

LED_DRIVER_CS1

LED_DRVR_CS_C3

LED_DRVR_DRAIN_2

IS3_BLC

BLC_GND_3

U9800_PIN20

FLAG_V

BLC_VIN_SNS

LED_DRIVER_OVP1

LED_DRIVER_FLT1

BLC_VIN2

BLC_SNUB_1

LED_DRIVER_FDBK2

LED_DRIVER_FLT3

LED_DRIVER_OVP2_OUT

LED_DRIVER_CS2

LED_DRIVER_FLT2

BLC_VIN2

LED_DRIVER_GATE2

BLC_VIN2

LED_DRIVER_FLT3

IS1_BLC

AGND_BLC

LED_DRIVER_OVP3_OUT

BLC_PWM_2_R

BLC_PWM_1_R

BLC_P_ON

BLC_PWM_3_R

PP8V_BLC

BLC_EN

AGND_BLC

BLC_GND_1

LED_DRIVER_OVP3_OUT

LED_DRIVER_CS3

LED_DRIVER_FLT2

LED_DRIVER_GATE1

BLC_PWM_1

LED_DRIVER_CS3

BLC_GND_3

BLC_PWM_2

LED_DRIVER_EN

BCOMP3

U9800_SC

BCOMP1

BLC_GND_3

BLC_GND_2

BLC_VIN2

LED_DRIVER_GATE1_R

LED_DRVR_CS_RC_2

BCOMP2

AGND_BLC

LED_DRVR_CLK

STRCLK_R1

BLC_GND_2

BLC_GND_3

AGND_BLC

BLC_GND_3

LED_DRIVER_COMP2

LED_DRIVER_COMP1

LED_DRIVER_COMP3

BLC_GND_1 BLC_GND_2

LED_DRVR_CS_C2

BLC_GND_2

90 OF 117

7.0.0

051-9504

prefsb

98 OF 143

1

2

1

2

1

12

2

1

AK

1

2

5

123

4

12

1

2

12

1

3

2

12

1

3

2

1

2

1

2

1

2

1

12

5

123

4

12

2

1

12

1

2

1

3

2

12

2

1

2

1

2

1

2

1

12

5

123

4

12

1

2

1

6712

43

5

6712

43

5

6712

43

5

12

AK

2

1

30

8

1339

40

3

5

7

2

37

35

14

31

36

38

26

29

28

24

391134

32

41

18

17

19

25

13

6

23

10

4

27

12

15

21

22

16

20

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

2

1

21

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

1

2

12

1

2

1

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

109

89 90

109

89 90

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90

114

90 91

109

90

112

89 91

109

90

109

90 91

109

90

109

90 91

109

90 91

109

90 91

109

112

114

90

109

90 91

109

90

109

91

109

90 91

109

90

109

90 91

114

90 91

109

90 91

109

89 90

109

90 91

114

109

90 91

109

89 91

109

90 91

109

90

109

90

109

90 91

109

89 91 113

90

112

90 91

114

109

90 91 109

90

109

90

109

90

114

90

109

90

109

90 91

109

90

109

90 91

109

90

109

90 91

109

90

114

89

109

89

109

89 91

112

89

109

89

109

90 91

109

90 91

109

90

114

90

109

90

109

91

109

90

109

90 91

109

91

109

91

114

109 109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

90 91

109

OUT

G

S

D

G

S

D

G

S

D

G

S

D

B

Y

A

IN

B

Y

A

S

D

G

NC

1IN+ 1IN-

2IN+ 2IN-

3IN+

4IN-

3IN-

4IN+

1OUT

2OUT

GND

VCC

3OUT

4OUT

1IN+ 1IN-

2IN+ 2IN-

3IN+

4IN-

3IN-

4IN+

1OUT

2OUT

GND

VCC

3OUT

4OUT

SYM_VER-1

D

S

G

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

UVLO VIN2 BLC_BL

2.0V @10V = "0" (SHUTDOWN)

2.5V @12V = "1"

Backlight Connector

518S0862

NOSTUFF STUFF NOSTUFF STUFF

NO BYPASS NOSTUFF

R9999:

R9976:

UVP PROTECTION

PWM <= 50% -> TURN ON BOOST PWM > 50% -> TURN OFF BOOST

NOSTUFF

BYPASS STUFF

R9995:

R9998:

STUFF NOSTUFF

R9994:

STUFF

OVP PROTECTION

Output Current Adjustment

BLC12V BYPASS STUFFING OPTION

IN-RUSH CURRENT LIMITER

90

109

90

109

90

109

SOT23-HF1

2N7002

Q9940

5%

0

603

R9940

MF-LF

1/10W

BSH111DG

SOT23-3

Q9951

BSH111DG

SOT23-3

Q9953

Q9952

BSH111DG

SOT23-3

499K

603

1%

MF-LF

1/10W

R9955

10%

0.1UF

50V

603-1

C9955

X7R

R9951

5%

0

1/10W MF-LF

603

5%

0

R9952

1/10W MF-LF

603

R9953

1/10W MF-LF

603

0

5%

25V

20%

4.7UF

CERM

C9973

1206

C9972

CERM

25V

4.7UF

20%

1206

603

MF-LF

5%

1/10W

10K

R9980

D9900

SOD323-SM

BAS316DG

1.0K

5%

R9981

603

MF-LF

1/10W

603

MF-LF

1/10W

R9979

1.0M

5%

10K

5%

R9974

1/10W

603

MF-LF

1/10W MF-LF

5%

603

10K

R9970

R9972

603

MF-LF

1/10W

100K

5%

Q9926

2N7002

SOT23-HF1

1M

R9967

603

MF-LF

1/10W

1%

1/10W MF-LF

1%

2.0M

0603

R9968

603

0

5%

MF-LF

1/10W

R9966

SOD323-SM

BAS316DG

D9901

R9964

130K

603

MF-LF

1/10W

1%

C9964

1UF

16V X5R 603

10%

MF-LF

10K

R9962

1/10W

1%

603

2.0M

1% 1/10W MF-LF 0603

R9963

5%

0

603

MF-LF

1/10W

R9961

603

X5R

16V

10%

1UF

C9962

C9963

0.1UF

603-1

50V

10%

X7R

D9902

BAS316DG

SOD323-SM

603

MF-LF

1/10W

R9914

1%

38.3K

10

R9934

5% 1/10W MF-LF

603

603-1

0.1UF

50V

10%

C9912

X7R

603-1

0.1UF

C9913

50V X7R

10%

1%

603

MF-LF

1/10W

100K

R9912

34.8K

MF-LF

1/10W

1%

R9913

603

5%

10

1/10W

603

MF-LF

R9936

X7R 603-1

50V

10%

0.1UF

C9911

R9910

100K

MF-LF 603

1% 1/10W

1% 1/10W MF-LF 0603

43K

R9911

50V

603-1

C9910

10%

X7R

0.1UF

Q9924

2N7002

SOT23-HF1

1/10W

10K

603

5%

R9918

MF-LF

SOT23-HF1

2N7002

Q9925

MF-LF

10

5%

1/10W

603

R9938

MF-LF

603

1.5M

5%

1/10W

R9969

603-1

0.1UF

C9914

X7R

10% 50V

C9970

10%

NOSTUFF

50V

0.1UF

0402

X5R-CERM

1UF

X5R

16V

603

10%

C9931

1UF

C9934

603

16V X5R

10%

603

1UF

10%

X5R

C9936

16V

C9949

X7R

CRITICAL

1000PF

603

10% 100V100V

1000PF

CRITICAL

X7R 603

10%

C9948C9947

CRITICAL

1000PF

603

X7R

100V

10%

100V

1000PF

603

C9946

10%

CRITICAL

X7RX7R

10%

CRITICAL

100V

603

C9945

1000PF

C9938

16V

10%

1UF

603

X5R

100V

10%

X7R 603

1000PF

C9944

CRITICAL

C9990

10%

603

CRITICAL

X7R

1000PF

100V

1000PF

C9969

10% 100V X7R

CRITICAL

603

10%

0.1UF

603-1

50V X7R

C9935

10% 100V X7R 603

CRITICAL

C9968

1000PF

CRITICAL

1000PF

10%

C9967

100V X7R 603603

X7R

100V

10%

1000PF

C9966

CRITICAL

C9965

CRITICAL

100V

603

10%

X7R

1000PF

0.1UF

C9937

50V X7R 603-1

10%

R9919

MF-LF

1/10W

603

5%

10K

SOT353

U9960

74LVC1G08GW

74

115

603-1

0.1UF

50V

C9939

10%

X7R

74LVC1G08GW

SOT353

U9970

1%

603

MF-LF

R9915

1/10W

10K

5%

0

402

R9996

MF-LF

1/16W

NOSTUFF

R9995

MF-LF

0

1/16W

402

5%

1/16W

5%

1K

R9994

MF-LF 402

402

MF-LF

1K

R9971

5%

1/16W

NOSTUFF

C9997

603-1

10%

0.1UF

50V X7R

FDMS6681Z

Q9970

POWER56

MF-LF

1W1% 2512

215

R9977

R9997

1%

215

MF-LF

1W 2512

10AMP-63V

1206

F9900

R9999

BLC12V_BYPASS:Y

0

402

MF-LF

1/16W

5%

0603

L9921

220-OHM-1.4A

MF-LF

R9998

1/16W

402

0

5%

BLC12V_BYPASS:Y

SOI

U9950

LM324DEX

U9920

SOI

100UF

C9974

6.3X8-SM-HF

20% 35V ELEC

250-OHM-5A

DLW5BT-SM-HF

L9920

NOSTUFF

L9922

250-OHM-5A

DLW5BT-SM-HF

0603

220-OHM-1.4A

L9923

250-OHM-5A

L9924

NOSTUFF

DLW5BT-SM-HF

BSS84

Q9971

S0T23-3-HF

5%

CERM

25V

1000PF

C9998

603

25V

5%

1000PF

C9999

CERM 603

10% 50V X7R-CERM 0603

0.068UF

C9971

NOSTUFF

L9925

0603

220-OHM-1.4A

Q9973

SOT23-3

BSH111DG

Q9972

SOT23-3

BSH111DG

SOT23-3

BSH111DG

Q9941

Q9974

SOT23-3

BSH111DG

R9927

MF-LF

1/16W

5%

402

100K

1% 1/10W MF-LF 603

R9917

71.5K

5%

56K

1/10W MF-LF 603

R9965

5%

603

1/10W MF-LF

R9928

0

R9920

5%

805

MF-LF

1/8W

0

2512

MF

1%

R9976

0.005

1W

25V X5R 603-1

1UF

C9942

NOSTUFF

10%

3.57K

603

0.1% 1/10W FF

R9932 R9933

FF

1/10W

0.1%

603

3.57K

20K

R9954

MF-LF 603

0.5% 1/16W

42.2K

MF-LF

1/10W

1%

603

R9916

805

MF-LF

0

5% 1/8W

R9921

10.0K

R9931

603

1/16W MF-LF

0.1%

0.047UF

603

5% 16V CERM

C9975

NOSTUFF

R9942

499K

MF-LF 603

1% 1/10W

100K

603

MF-LF

1%

1/10W

R9943

100K

R9941

603

1/10W MF-LF

1%

R9922

MF-LF

0

1/8W

5%

805

603

R9978

10K

1% 1/10W MF-LF

1%

603

10K

1/10W MF-LF

R9975

J9920

M-RT-SM

504050-0691

CRITICAL

1210-2

100V X7R-CERM

2.2UF

10%

C9920

CRITICAL

100V X7R-CERM

C9921

2.2UF

10%

1210-2

CRITICAL

100V X7R-CERM

C9923

2.2UF

10%

1210-2

100V X7R-CERM

C9993

2.2UF

10%

CRITICAL

1210-2

0

5% 1/8W

MF-LF

805

R9923

CRITICAL

100V X7R-CERM

C9925

2.2UF

10%

1210-2

X7R-CERM

100V

CRITICAL

10%

2.2UF

C9926

1210-2

CRITICAL

100V X7R-CERM

C9927

10%

2.2UF

1210-2

CRITICAL

100V X7R-CERM

C9928

2.2UF

10%

1210-2

100V X7R-CERM

C9929

2.2UF

10%

CRITICAL

1210-2

CRITICAL

100V X7R-CERM

10%

2.2UF

C9960

1210-2

X7R-CERM

100V

CRITICAL

10%

C9961

2.2UF

1210-2

X7R-CERM

100V

10%

2.2UF

C9992

CRITICAL

1210-2

X7R-CERM

100V

10%

2.2UF

CRITICAL

C9991

1210-2

R9924

1/8W

805

MF-LF

0

5%

CRITICAL

2.2UF

10% 100V X7R-CERM

C9941

1210-2

CRITICAL

2.2UF

10% 100V X7R-CERM

C9940

1210-2

2.2UF

10% 100V X7R-CERM

C9989

CRITICAL

1210-2

CRITICAL

100V X7R-CERM

10%

2.2UF

C9987

1210-2

100V

10%

2.2UF

CRITICAL

C9986

X7R-CERM 1210-2

CRITICAL

2.2UF

10% 100V

C9985

X7R-CERM 1210-2

CRITICAL

2.2UF

10% 100V X7R-CERM

C9984

1210-2

X7R-CERM

CRITICAL

C9983

2.2UF

10% 100V

1210-2

CRITICAL

10% 100V X7R-CERM

C9982

2.2UF

1210-2

C9981

100V

10%

CRITICAL

2.2UF

X7R-CERM 1210-2

805

5%

R9925

0

MF-LF

1/8W

CRITICAL

2.2UF

1210-2

10% 100V X7R-CERM

C9980

0.1UF

C9995

X7R-CERM

16V

10%

0402

10% 16V X7R-CERM

0.1UF

C9951

0.1UF

C9996

0402

10% 16V X7R-CERM

90

109

90

109

90

109

90 91

109

90

109

90 91

109

SYNC_DATE=04/23/2012

Backlight Controller

SYNC_MASTER=D8_MLB

IS2_BLC_F

BLC_VOUT1

IS1_BLC

BLC_LED_P_1

BLC_LED_N_2

BLC_LED_P_2

BLC_LED_N_3

PP12V_S0_BLC_VIN2

BLC_P_ON_D_R

FLAG_V_L

PP5V_S0_BLC_R

BLC_UVLO

LED_DRIVER_EN_L_R

LED_DRIVER_EN_L

AGND_BLC

BLC_P3V3S

BLC_P_ON_D

BLC_LED_P_3

PP5V_S0_BLC_R

OVP_OUT1

BLC_P3V3S

BLC_VINP_GATE

BLC_P_ON_DRAIN

PP12V_S0_BLC_VINP

UVP_REF

BLC_P3V3_REF

BLC_MCU_BV_D

BLC_MCU_BV

IS1_BLC_F

LED_DRIVER_REF1

LED_DRIVER_REF2

BLC_P3V3_REF

BLC_MCU_AOUT_R

OVP_OUT3_R

AGND_BLC

BLC_PWM_3

OVP_OUT3 AGND_BLC

BLC_P3V3_REF

=PP12V_S0_BLC

BLC_VIN2_GATE

BLC_VIN2_SRC

BLC_ON_DRAIN

AGND_BLC

LED_DRIVER_OVP1

BLC_VOUT3

=PP5V_S0_BLC

IS3_BLC_F

UVP_IN_4

PP5V_S0_BLC_R

BLC_BL_GATE

PP12V_S0_BLC_VINP

PP12V_S0_BLC_VIN2

BLC_GND_3

BLC_P_ON_R

LED_DRIVER_REF3

BLC_P3V3S

IS2_BLC

BLC_VOUT2

BLC_BST

BLC_P_ON_GATE

BLC_MCU_BV_R

LED_DRIVER_OVP2

LED_DRIVER_OVP3

BLC_PWM_2

OVP_OUT2_R

OVP_OUT2

BLC_P_ON

OVP_OUT1_R

BLC_GND_2

BLC_GND_1

BOOST_BYPASS

BLC_BYPASS_GATE

BLC_BL

BLC_ENA1

BLC_BL

BLC_ON_R

BLC_ENA1

BLC_P_ON

FLAG_V

BLC_P3V3S

BLC_ON

PP12V_S0_BLC_F

OCA_FET_DRAIN

PM_PGOOD_FET_P12V_S0_BLC

LED_DRIVER_EN

BLC_VIN2

AGND_BLC

BLC_PWM_1

BLC_P_ON_BYPASS

IS3_BLC

BLC_LED_N_1

UVP_IN_3

BLC_VOUT3

OVP_OREF

AGND_BLC

BLC_GND_2

BLC_GND_3

UVP_IN_1

UVP_IN_1_REF UVP_IN_2

BLC_MCU_BV

BLC_GND_2

BLC_VOUT2

BLC_VOUT3

BLC_VOUT2

prefsb

051-9504

7.0.0

99 OF 143

91 OF 117

3

2

1

2

3

2

1

3

2

1

3

2

1

2

1

12

2

1

2

1

12

AK

12

1

2

1

2

1

2

1

2

3

2

1

2

1

2

1

2

AK

1

2

1

2

1

2

1

2

1

2

1

KA

1

2

12

2

1

2

1

2

1

2

12

2

1

2

1

2

1

3

2

1

2

3

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

4

3

1

2

5

2

1

4

3

1

2

5

1

2

12

1

2

1

2

12

2

1

3 2 1

5

4

12

21

1

2

21

1

2

3 2

5 6

10

13

9

12

1

7

11 4

8

14

3 2

5 6

10

13

9

12

1

7

11 4

8

14

1

2

4

32

1

4

32

1 21

4

32

1

3

2

1

2

1

2

1

2

1

21

3

2

1

3

2

1

3

2

1

3

2

1

2

1

2

1

2

12

2

1

2

1

2

1

2

1

2

12

2

1

2

12

1

2

12

1

2

1

2

1

2

4

3

5

6

8

7

2

1

2

1

2

1

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

2

1

2

1

2

1

2

1

109

89 90 91

109

112

89 90 91

109

89

112

114

90 91

109

89 91

109

112

109

89 90 91

109

114

89 91

109

112

89 91

109

117

89 91

109

112

89 91

112

109

89 91

109

112

114

90 91 109

90

109

114

90 91 109

89 91

109

6

112

90 91

109

90

114

6

117

89 90 91

109

112

89 91

109

89 90 91

109

90 91

109

112

89 91

109

89

112

90

114

90 114

90

109

114 114

89 90 91

112

114

90 91

109

90

109

89

112

89 91

112

89 91

112

89 91 112

112

89 91

112

89 90 91

112

89 90

113

89 91

109

112

109

114

90 114

90

109

90 91

109

90

109

112

109

117

90 91

109

114

90 91

109

90 91

109

90 91

109

90 91

109

117

89 91

112

90 91

109

90 91

109

90 91

109

90 91

109

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

COMP

ISEN1-

VDIFF VSEN RGND

EN_PWR

DAC

REF

TM

PWM4

PWM3

FS

SS

VID1

VID6

VID2 VID3 VID4 VID5

VID7

VR_RDY

VID0

VCC

OFS

PSI*

TCOMP

FB

PWM2

ISEN1+

ISEN2+ ISEN2-

ISEN3+ ISEN3-

ISEN4+

VR_HOT

THRM

EN_VTT

ISEN4-

IMON

PWM1

H_CPURST_N

PAD

SYM_VER_2

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DEFAULT: 0.9000V STEP: 12.5MV

LAYOUT: PLACE RTB401 NEAR HOT SPOT.

LOCAL 5V

GPU CORE REG 1.1V/???A O/P= PPGPUCORE_S0_REG

AVG = ???A

PEAK = ???A

VOUT = VCORE

GPU VCORE

VR_HOT goes HIGH when VTM/VCC < 28% and LOW when VTM/VCC > 33%.

152-0110

IMAX = 10.5A

1.25 mOhm loadline

GPU CORE INPUT Filtering

NEED TO FIGURE OUT SEQUENCING FOR ENABLE

OMIT

SM

XWB401

49.9K

MF-LF 402

1% 1/16W

RB415

MF-LF

1%

1/16W

RB414

402

49.9K

1/16W

RB412

2.0K

MF-LF

402

5%

6

72 92

5

64

110

51

110

VR_GPU_IMON

402

0.0022UF

10% 50V CERM

CB403

50V CERM

10%

402

CB402

0.0022UF

NOSTUFF

0.0022UF

CERM 402

50V

CB401

10%

SIGNAL_MODEL=EMPTY

NOSTUFF

100K

1%

402

1/16W MF-LF

RB409

21K

402

MF-LF

1/16W

1%

RB407

NOSTUFF

20.0K

1/16W MF-LF

1%

RB405

402

NOSTUFF

RB400

1/16W

1%

402

1.02K

MF-LF

RB406

1/16W

0

MF-LF 402

5%

93

110

93

110

93

110

93

110

93

110

93

110

93

110

93

110

93

110

82

110

1/16W

RB445

5%

402

0

MF-LF

0

5% 1/16W MF-LF 402

RB404

1/16W MF-LF

402

5%

0

RB498

NOSTUFF

20%

402

10V CERM

CB480

0.1UF

CB430

NOSTUFF

50V

15PF

1%

402

C0G

CB440

NOSTUFF

15PF

402

C0G

1%

50V

CB450

402

1% 50V C0G

15PF

NOSTUFF

RB450

1/16W

5%

MF-LF

402

0

5%

MF-LF

402

1/16W

RB440

RB432

402

1/16W

0

MF-LF

5%

402

MF-LF

0

1/16W

RB442

5%

RB452

402

5%

MF-LF

0

1/16W

RB449

MF-LF

402

1%

1/16W

47.5

MF-LF 402

NOSTUFF

5%

RB446

1M

1/16W

SM

XWB420

OMIT

SM

XWB430

6.8K

0603

RTB401

110

1.02K

MF-LF

402

1/16W

1%

RB433

RB443

1.02K

MF-LF

1/16W

1%

402

1.02K

RB453

1%

MF-LF

402

1/16W

0.1%

MF-LF

RB411

10K

0402

RB408

75K

402

MF-LF

1/16W

1%

RB402

402

1K

1/16W MF-LF

1%

402

47PF

CERM

5%

50V

CB404

287

RB403

1% 1/16W MF-LF

402

150PF

50V CERM

5%

402

CB441

CB451

5%

150PF

CERM

50V

402

CB431

402

5%

150PF

CERM

50V

RB417

1/16W

10K

MF-LF 402

1%

5%

1/16W

402

MF-LF

0

RB438

94

110

94

110

RB420

MF-LF

5%

1/16W

0

402

MF-LF

RB421

1.02K

1%

1/16W

402

CB461

150PF

CERM

50V

5%

402

CB460

NOSTUFF

402

15PF

C0G

50V

1%

1/16W

5%

402

MF-LF

0

RB434

94

110

78

110

78

110

RB475

MF-LF

1/16W

1%

1K

402

1/16W MF-LF

RB474

1K

1%

402

NOSTUFF

1K

402

MF-LF

1/16W

1%

RB476

1/16W

NOSTUFF

1%

MF-LF

1K

RB495

402

1/16W

1%

1K

RB497

MF-LF 402

MF-LF

NOSTUFF

1%

1K

1/16W

402

RB480 RB483

MF-LF

1%

402

1K

1/16W

MF-LF

1% 1/16W

RB470

1K

402

NOSTUFF

1/16W MF-LF

RB471

1%

1K

402

1%

MF-LF

1/16W

1K

RB496

402

RB472

NOSTUFF

MF-LF

1/16W

1%

1K

402

RB473

1/16W MF-LF

1%

1K

402

RB481

NOSTUFF

1K

1/16W MF-LF

1%

402

1K

RB482

NOSTUFF

1/16W

1%

MF-LF 402

RB485

1/16W

1K

MF-LF

1%

402

RB499

0402

MF-LF

1/16W

10K

0.1%

MF-LF

RB484

1/16W

402

5%

0

NOSTUFF

1K

1% 1/16W MF-LF 402

RB478

UB400

ISL6334D

QFN

CRITICAL

5%

220PF

25V

0402

C0G-CERM

CB433

0402

25V C0G-CERM

220PF

5%

CB443

5%

220PF

C0G-CERM

25V

0402

CB453

CB463

25V C0G-CERM

5%

220PF

0402

NOSTUFF

CB409

16V X7R-CERM

0.01UF

10%

MF-LF 402

RB444

0

1/16W

5%

NOSTUFF

0

1/16W

402

5%

RB455

MF-LF

NOSTUFF

0

MF-LF 402

5%

RB448

1/16W

NOSTUFF

1/16W

0

MF-LF

402

5%

RB447

NOSTUFF

178

MF-LF

RB431

402

1/16W

1%

402

MF-LF

1/16W

178

1%

RB441

RB451

1%

178

1/16W MF-LF

402

1/16W

1%

MF-LF

178

RB439

1% 1/16W MF-LF

RB410

2.15K

402

5%

0

1/16W MF-LF

RB416

402

CB410

10% 50V

0402

0.0033UF

X7R-CERM

1/16W

RB401

402

MF-LF

8.06K

1%

10%

CERM

25V

402

CB405

0.0047UF

MF-LF 402

100K

RB477

1% 1/16W

0.001UF

CB406

0402

10% 50V

X7R-CERM

0402

CB432

0.1UF

10% 16V X7R-CERM

0402

0.1UF

10% 16V X7R-CERM

CB442

0402

0.1UF

10% 16V X7R-CERM

CB452

CB462

X7R-CERM

16V

10%

0.1UF

0402

CB412

0.022UF

10% 16V X5R-X7R-CERM

0402

1UF

10% 10V X6S-CERM

CB407

CRITICAL

LB400

SDP110808MR36MF-TH

0.36UH-30A-0.6MOHM

1/8W

5%

2.2

RB418

805

MF-LF

402

MF-LF

5%

RB479

0

1/16W

SYNC_MASTER=D8_MLB

VReg GPU Core Phases

SYNC_DATE=02/28/2012

REG_GPUCORE_VID6

REG_GPUCORE_VID1

PP12V_S0_GPUCORE_FLT

=PP12V_S0_REG_GPUCORE

VR_GPU_ISNS4_R_N

VR_GPU_ISNS3_R_N

REG_PWM_GPUCORE_4

VR_GPU_EN_VTT

REG_GPUCORE_VID2

VR_GPU_PWM3_R

VR_GPU_ISNS2_R_N

VR_GPU_IMON_R

VR_GPU_COMP_RC

VR_GPU_FB

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.3MM

MAX_NECK_LENGTH=3MM

VOLTAGE=5V

PP5V_S0_GPU_VCORE_VCC

VR_GPU_PWM4_R

VR_GPU_PWM1_R

AGND_GPU

VR_GPU_ISNS1_R_N

VR_GPU_PWM2_R

VR_GPU_COMP_R

=PP3V3_S0_GPU

REG_GPUCORE_VID3

=PP3V3_S0_GPU

PM_PGOOD_REG_GPUCORE_S0

VR_GPU_DAC

VR_GPU_IOUT_PD

VR_GPU_ISNS4_R_P

VR_GPU_ISNS2_R_P

VR_GPU_ISNS1_R_P

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_1

REG_ISEN_GCORE_1_N

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_3

REG_ISEN_GCORE_3_N

AGND_GPU

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.3MM

MAX_NECK_LENGTH=3MM

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_4

REG_ISEN_GCORE_4_N

REG_ISEN_GCORE_3_P

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_3

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_2

REG_ISEN_GCORE_2_N

VSNS_GPU_VSS

VR_GPU_COMP

AGND_GPU

VSNS_GPU_VDD

=PP5V_S0_VRD

PM_EN_REG_GPUCORE_S0

PM_EN_REG_GPUCORE_S0_R

REG_PWM_GPUCORE_3

REG_ISEN_GCORE_4_P

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_4

=PP3V3_S0_VRD

PP5V_S0_GPU_VCORE_VCC

AGND_GPU

=PP5V_S0_VRD

VR_GPU_VDIFF

VR_VDF_R1

VR_GPU_OFS

VR_GPU_FS

PP5V_S0_GPU_VCORE_VCC

VR_GPU_TCOMP

VR_GPU_VSEN

VOLTAGE=1.1V

VR_VDF_R2

VR_GPU_FB_R

VR_GPU_RGND

VOLTAGE=0V

VR_GPU_ISNS3_R_P

REG_PWM_GPUCORE_1

REG_PWM_GPUCORE_2

VR_GPU_ISNS1_RR_2

VR_GPU_ISNS2_RR_2

VR_GPU_ISNS3_RR_2

VR_GPU_ISNS4_RR_2

AGND_GPU

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_2

REG_ISEN_GCORE_2_P

REG_GPUCORE_VID5

GPU_PSI_L

VR_GPU_FAN

REG_GPUCORE_VID4

REG_GPUCORE_VID0

VR_GPU_VRDHOT

REG_GPUCORE_VID7

DIFFERENTIAL_PAIR=REG_ISEN_GCORE_1

REG_ISEN_GCORE_1_P

VR_GPU_REF

VR_GPU_SS

VR_GPU_TM

92 OF 117

114 OF 143

7.0.0

051-9504

prefsb

NET_PHYSICAL_TYPE=SNS_DIFF_PHY

12

121

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

1

2

12

2

1

12

1

2

12

2

1

2

1

2

1

2

12

2

1

2

1

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

13

27

15 17 16

32

11

12

39

25

31

34

35

6

1

5 4 3 2

40

36

7

19

9

8

18

14

20

28

22 21

29 30

23

38

41

33

24

10

26

37

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

12

1

2

12

2

1

2

1

2

1

2

1

2

1

2

1

21

12

78

110

78

110

93 94

110

6

110

78

110

92

110

92

110

6

78 92

78

110

6

78 92

110

92

110

92

110

64

110

115

6

66 69 70 72 95

92

110

92

110

6

72 92

110

92

110

92

110

78

110

78

110

OUT

NC

IN

NC

OUT

S

G

D

S

G

D

S

G

D

G

S

D

G

S

D

G

S

NCNC

NC

BOOT

UGATE

PHASE

NC NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

IN

NC

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND

THRML

PHASE

LVCC

UVCC

PAD

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU Output Decoupling

GPU Phase 3

GPU Phase 1

GPU Phase 2

92

110

MF-LF

RB537

2.2

1/8W

5%

805

NOSTUFF

92

110

92

110

6

93 94

RB516

1/10W MF-LF

603

5%

0

92

110

6

93 94

92

110

92

110

CRITICAL

RB550

1% 1W MF

0.0005

0612

805

5% 1/8W MF-LF

2.2

RB557

NOSTUFF

RB556

1/10W MF-LF

603

5%

0

MF-LF 603

10

1/10W

5%

RB567

NOSTUFF

MF

1%

0612

0.0005

1W

RB510

CRITICAL

QB510

SQ

IRF6811STRPBF

CRITICAL

IRF6811STRPBF

SQ

QB512

CRITICAL

IRF6811STRPBF

SQ

QB514

DIRECTFET-MX

QB511

IRF6893MTRPBF

CRITICAL

QB531

IRF6893MTRPBF

CRITICAL

DIRECTFET-MX

QB551

DIRECTFET-MX

CRITICAL

IRF6893MTRPBF

CRITICAL

RB530

1%

0612

1W MF

0.0005

UB530

CRITICAL

QFN1

ISL6612

0.001UF

CB517

NOSTUFF

0402

50V X7R-CERM

10%

NOSTUFF

CB537

10%

X7R-CERM

50V

0402

0.001UF

10%

X7R-CERM

50V

0402

NOSTUFF

CB557

0.001UF

92

110

NOSTUFF

1/10W MF-LF

RB527

5%

10

603

CRITICAL

ISL6622

DFN

UB550

5%

0

MF-LF

603

1/10W

RB531

603

RB528

MF-LF

1/10W

0

5%

0

MF-LF

RB529

603

1/10W

5%

X7R

25V

10%

0.22UF

CB516

0603

0.22UF

10% 25V X7R

CB536

10%

X7R

25V

0.22UF

0603

CB556

X7R

16V

10%

0603

CB525

1.0UF

CB526

1.0UF

X7R

16V

10%

0603

16V

1.0UF

0603

10%

X7R

CB527

1.0UF

0603

10% 16V X7R

CB545

1.0UF

10%

X7R

16V

0603

CB547

1.0UF

10% 16V X7R 0603

CB565

CB566

1.0UF

0603

10% 16V X7R

CB567

X7R

16V

10%

1.0UF

0603

10UF

CRITICAL

X6S

25V

10%

0805

CB512

X6S

25V

10%

0805

10UF

CB513

CRITICAL

10UF

0805

10% 25V X6S

CB533

X6S

CRITICAL

10UF

0805

10% 25V

CB532

X6S

25V

10%

0805

10UF

CRITICAL

CB553

10UF

X6S

25V

10%

0805

CRITICAL

CB552

EMC

1UF

0402

10% 25V X6S-CERM

CB515

EMC

1UF

0402

10% 25V X6S-CERM

CB514

CB535

X6S-CERM

25V

10%

0402

1UF

EMC

CB534

X6S-CERM

25V

10%

0402

1UF

EMC

CB555

EMC

1UF

0402

10% 25V X6S-CERMX6S-CERM

25V

10%

0402

1UF

EMC

CB554

CRITICAL

POLY

180UF

20% 16V

CB510

TH1

CRITICAL

POLY

180UF

20% 16V

CB511

TH1

CRITICAL

CB530

POLY

180UF

20% 16V

TH1

CRITICAL

POLY

180UF

20% 16V

CB531

TH1

CRITICAL

POLY

180UF

20% 16V

CB595

TH1

0.24UH-30A-0.35MOHM

LB510

CRITICAL

SDP110808M-TH

LB530

0.24UH-30A-0.35MOHM

CRITICAL

SDP110808M-TH

LB550

SDP110808M-TH

0.24UH-30A-0.35MOHM

CRITICAL

330UF-0.006OHM

POLY

2V

20%

CASE-D2-SM

CB580

5%

2.2

805

1/8W MF-LF

NOSTUFF

RB517

CB581

CRITICAL

CASE-D2-SM

POLY

2V

20%

330UF-0.006OHM

CB582

CRITICAL

330UF-0.006OHM

POLY

2V

20%

CASE-D2-SM

330UF-0.006OHM

POLY

2V

20%

CASE-D2-SM

CB585

CRITICAL

2V

CASE-D2-SM

POLY

20%

330UF-0.006OHM

CB584

CRITICAL

CB583

CRITICAL

330UF-0.006OHM

POLY

2V

20%

CASE-D2-SM

ISL6622

UB510

CRITICAL

DFN

92

110

92

110

6

93 94

RB547

5%

10

MF-LF 603

1/10W

603

0

MF-LF

RB536

1/10W

5%

SYNC_DATE=02/25/2012

VReg GPU Core Phases

SYNC_MASTER=D8_MLB

PP12V_S0_GPUCORE_FLT

PPGPUCORE_S0_SENSE_1

REG_PHASE_GPUCORE_1

PPGPUCORE_S0_SENSE_2

REG_PHASE_GPUCORE_2

PPGPUCORE_S0_SENSE_3

REG_PHASE_GPUCORE_3

REG_SNUBBER_GPUCORE_2

REG_LGATE_GPUCORE_2

REG_ISEN_GCORE_2_N

PPGPUCORE_S0_REG

PP12V_S0_GPUCORE_FLT

REG_LVCC_UB550

REG_UGATE_GPUCORE_3

REG_UVCC_UB550

REG_LVCC_UB530

PP12V_S0_GPUCORE_FLT

REG_LVCC_UB510

PP12V_S0_GPUCORE_FLT

REG_UVCC_UB510

PPGPUCORE_S0_REG

REG_LGATE_GPUCORE_3

REG_PWM_GPUCORE_3

REG_BOOT_GPUCORE_1

REG_UGATE_GPUCORE_1

REG_BOOT_GPUCORE_2

REG_PWM_GPUCORE_2

REG_SNUBBER_GPUCORE_3

REG_SNUBBER_GPUCORE_1

REG_ISEN_GCORE_3_P

REG_ISEN_GCORE_1_P

REG_ISEN_GCORE_1_N

PPGPUCORE_S0_REG

REG_ISEN_GCORE_3_N

REG_PWM_GPUCORE_1

REG_ISEN_GCORE_2_P

REG_UGATE_GPUCORE_2

REG_LGATE_GPUCORE_1

REG_BOOT_GPUCORE_1_RC

REG_BOOT_GPUCORE_2_RC

REG_BOOT_GPUCORE_3_RC

REG_BOOT_GPUCORE_3

REG_VCC_UB550

prefsb

051-9504

7.0.0

115 OF 143

93 OF 117

1

2

1

2

43

21

1

2

1

2

1

2

43

21

3

4

2

1

5

6

3

4

2

1

5

6

3

4

2

1

5

6

5

34

7126

5

34

7126

5

34

7126

43

21

2

1

10

3 8

5

6

7

9

11

4

2

1

2

1

2

1

2

3

6

9

4

2

1

5

11

10

7

8

12

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

21

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

6

9

4

2

1

5

11

10

7

8

1

2

1

2

92 93 94

110

92 93 94

110

92 93 94

110

92 93 94

110

6

93 94

110

OUT

NC

IN

NC

S

G

D

G

S

NCNC

NC

BOOT

UGATE

PHASE

NC NC

GND

LGATE

VCC

PVCC

THRML

PWM

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU PHASE 4

1/10W MF-LF

5%

10

603

RB667

1/10W

5%

0

603

MF-LF

RB656

NOSTUFF

5% 1/8W

RB657

2.2

MF-LF 805

92

110

92

110

6

93

92

110

CRITICAL

0612

1% 1W MF

0.0005

RB650

SQ

IRF6811STRPBF

CRITICAL

QB650

IRF6893MTRPBF

DIRECTFET-MX

CRITICAL

QB651

QFN1

CRITICAL

ISL6612

UB650

X7R-CERM

50V

NOSTUFF

0402

0.001UF

CB657

10%

X7R

25V

10%

0.22UF

0603

CB656

X7R

16V

10%

0603

CB665

1.0UF 1.0UF

0603

10% 16V X7R

CB667

X6S

25V

10%

0805

CB652

10UF

CRITICAL

X6S

25V

10%

0805

10UF

CRITICAL

CB653

1UF

0402

10% 25V X6S-CERM

CB655

EMC

CB654

EMC

1UF

0402

10% 25V X6S-CERM

CRITICAL

POLY

180UF

20% 16V

CB650

TH1

0.24UH-30A-0.35MOHM

LB650

CRITICAL

SDP110808M-TH

SYNC_DATE=02/06/2012

VREG GPU CORE PHASE 4

SYNC_MASTER=D8_MLB

PPGPUCORE_S0_SENSE_4

REG_PHASE_GPUCORE_4

PP12V_S0_GPUCORE_FLT

PPGPUCORE_S0_REG

REG_LVCC_UB650

PP12V_S0_GPUCORE_FLT

REG_SNUBBER_GPUCORE_4

REG_ISEN_GCORE_4_N

REG_ISEN_GCORE_4_P

REG_PWM_GPUCORE_4

REG_BOOT_GPUCORE_4

REG_LGATE_GPUCORE_4

REG_UGATE_GPUCORE_4

REG_BOOT_GPUCORE_4_RC

prefsb

051-9504

7.0.0

116 OF 143

94 OF 117

1

2

1

2

1

2

43

21

3

4

2

1

5

6

5

34

7126

2

1

10

3 8

5

6

7

9

11

4

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

11

2

21

110

92 93 94

110

92 93 94

110

OUT

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

VSW

PGND

TGR

TG

BG

VIN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

IN

OUT

IN

NCNC

D

S

G

S

G

D

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

GPU/PCH/TBT 1V05 SUPPLY

Vout = 0.5V * (1 + Ra / Rb)

audio frequencies

prevent noise in the

Note:

<Rb>

SENSING LOCATION TBD

GPIO_16 VID 1

GPU VDDQ SUPPLY

??? A MAX OUTPUT

0

VOUT = 1.5V / 1.35V

0 1

1.35 V

1.5 V

0

GPU VDDQ

F = ??? KHZ

VID 0

5.3A MAX OUTPUT

F = 500 KHZ

<Rb>

VOUT = 1.05V

Vout = 0.5 * (1 + Ra / Rb)

<Rb>

a minimum load to

Regulator requires

To regulator:

<Rb>

6

110

10UF

X5R 603

6.3V

20%

CB717

5

64 95

115

CRITICAL

POLY

2V

20%

CB716

330UF-0.009OHM

CASE-D2-HF

CRITICAL

2V

CASE-D2-HF

330UF-0.009OHM

20%

POLY

CB715

CRITICAL

CASE-D2-HF

20%

POLY

2V

CB714

330UF-0.009OHM

X5R-CERM

20%

0603

CB708

CRITICAL

10UF

25V

CB713

1000PF

NP0-C0G

402

25V

5%

20K

5% 1/16W MF-LF 402

RB713

X5R-CERM

CRITICAL

0603

25V

10UF

20%

CB707

QB710.2:5MM

EMC

CB710

402

25V

10%

X5R

1UF

X5R

25V

EMC

402

10%

1UF

CB709

QB710.2:5MM

NOSTUFF

MF-LF

1/10W

5%

RB709

603

2.2

UB750

UTQFN

ISL95870AH

CRITICAL

SIGNAL_MODEL=EMPTY

SM

XWB771

SIGNAL_MODEL=EMPTY

XWB770

SM

MF-LF

RB706

1/8W

805

2.2

5%

CB704

X5R

16V

10%

2.2UF

603

10

MF-LF

RB705

805

1/8W

5%

402

1UF

16V

10%

X5R

CB703

78

110

XWB773

SM

UB750.3:1MM

64

115

301K

1%

1/16W

402

MF-LF

RB774

1/16W MF-LF

0

5%

402

RB777

82

113

RB776

0

402

MF-LF

1/16W

5%

NOSTUFF

150K

1%

1/16W

RB775

MF-LF

402

1/16W

RB778

MF

1%

27K

2.32K

MF-LF

1/16W

1%

SIGNAL_MODEL=EMPTY

402

RB771RB770

MF-LF

1/16W

SIGNAL_MODEL=EMPTY

1%

402

2.32K

MF-LF

1%

RB773

1/16W

2.74K

402

NOSTUFFNOSTUFF

RB772

402

1/16W

1%

2.74K

MF-LF

CRITICAL

CB734

603

10UF

20% 10V X5R

NOSTUFF

0

5%

RB718

1/20W 201

MF

6.3V

20%

10UF

X5R 603

CB745

6.3V

20%

CB744

603

10UF

X5R

CASE-D2-HF

20%

CRITICAL

CB743

330UF-0.009OHM

2V POLY

QB720.1:6MM

EMC

CB738

402

X5R

1UF

25V

10%

CRITICAL

CB742

POLY

2V

20%

CASE-D2-HF

330UF-0.009OHM

25V 402

NP0-C0G

1000PF

CB741

5%

SM

XWB706

QB720.1:7MM

CB737

1UF

402

X5R

25V

10%

EMC

XWB705

SM

NOSTUFF

1000PF

CB739

5%

402

25V

NP0-C0G

CSD58872Q5D

QB720

SON5X6

10K

1/16W

5%

RB722

MF-LF

402

10% 16V X5R 603

2.2UF

CB733

UTQFN

ISL95870

UB700

CRITICAL

SM

XWB704

64

115

6

95

5

64 95

115

SIGNAL_MODEL=EMPTY

SM

XWB710

SM

XWB711

SIGNAL_MODEL=EMPTY

RB719

5%

1/8W

MF-LF

3.3

805

NOSTUFF

RB723

1

MF-LF

1/10W

603

5%

200

402

MF-LF

1/16W

RB712

402

RB740

1/16W

200

MF-LF

5%

78

110

CRITICAL

QB711

649135PBF

DIRECTFET_S3C

649136PBF

S1

CRITICAL

QB710

5% 50V

0402

10PF

CB731

C0G-CERM

CB730

C0G-CERM 0402

5%

10PF

50V

CB785

5% 50V

0402

10PF

C0G-CERM

CB770

C0G-CERM 0402

50V

5%

10PF

16V

0402

CB732

X7R-CERM

10%

0.047UF

0.1UF

16V

0402

CB705

X7R-CERM

10%

10% 50V

0.001UF

0402

NOSTUFF

CB711

X7R-CERM

CERM

CB740

10% 16V

402

0.22UF

402

10%

X5R

16V

CB790

0.033UF

5%

0

1/10W MF-LF 603

RB707

10% 16V

603

CB712

RB710.2:3MM

0.33UF

CERM-X7R

CRITICAL

LB710

0.68UH-20%-32A-0.00066OHM

SDP1182M-TH

RB711

LB710.2:25MM

2.8K

402

MF-LF

1% 1/16W

1% 1/16W MF-LF

RB710

402

2.8K

RB714

402

MF-LF

1/16W

11.3K

1%

MF-LF

1%

11.3K

1/16W

402

RB716

MF-LF

RB715

1/16W

10.2K

402

1%

MF-LF

1%

10.2K

1/16W

402

RB717

CRITICAL

POLY

180UF

20% 16V

CB702

TH1 TH1

CB706

16V

20%

180UF

POLY

CRITICAL

TH1

CB720

16V

20%

180UF

POLY

CRITICAL

CB736

TH1

POLY

180UF

20% 16V

CB750

CRITICAL

180UF

POLY

20% 16V

TH1

RB721

805

MF-LF

1/8W

0

5%

0

1/16W MF-LF 402

RB720

1%

3.83K

1/16W

RB724

MF-LF 402

1%

3.83K

1/16W MF-LF 402

RB725

X7R-CERM

16V

10%

0.1UF

0402

CB735

SDP1182-SM

1.0UH-27A-1.05MOHM

LB720

CRITICAL

GPU VDDQ AND 1V05 GPU/PCH/TBT VREGS

SYNC_MASTER=D8_MLB

SYNC_DATE=04/18/2012

REG_P1V05S0_VO_R

P1V05_OCSET_R

REG_P1V05S0_OCSET

REG_P1V05S0_VO

REG_BOOT_P1V05S0

REG_LGATE_P1V05S0

REG_SNUBBER_P1V05S0

=PP12V_S0_REG_FBVDDQ

FBVDD_ALTVO

REG_BOOT_FBVDDQ_RC

REG_BOOT_FBVDDQ

REG_FBVDDQ_OCSET

REG_FBVDDQ_VO

REG_SNUBBER_FBVDDQ

REG_LGATE_FBVDDQ

REG_FBVDDQ_VO

REG_UGATE_FBVDDQ

REG_VCC_UB750

REG_PVCC_UB750

SNS_FBVDDQ_XW_P

PP1V05_S0_REG

PM_PGOOD_REG_FBVDDQ_S0

=PP5V_S0_REG_P1V05

REG_VCC_UB700

=PP3V3_S0_VRD

=PP5V_S0_REG_FBVDDQ

PM_PGOOD_REG_P1V05_S0

REG_FBVDDQ_OCSET

PM_EN_REG_FBVDDQ_S0

PM_PGOOD_REG_P1V05_S0

REG_P1V05S0_OCSET

REG_FBVDDQ_SET1

REG_P1V05S0_SREF

REG_P1V05S0_FSEL

MAKE_BASE=TRUE

PM_PGOOD_REG_FBVDDQ_S0

REG_FBVDDQ_SET0

REG_FBVDDQ_SET1_R

REG_FBVDDQ_SREF

SNS_FBVDDQ_XW_N

PM_EN_REG_P1V05_S0

SNS_P1V05_IOVDD_XW_PSNS_P1V05_IOVDD_XW_N

REG_P1V05S0_FB

REG_P1V05S0_RTN

REG_PHASE_FBVDDQ

P1V05_AGND

VSNS_FBVDDQ_P

VSNS_FBVDDQ_N

REG_FBVDDQ_FB

AGND_FBVDDQ

REG_FBVDDQ_RTN

REG_FBVDDQ_FSEL

PP1V5R1V35_S0_GPU_REG

REG_UGATE_P1V05S0_R

=PP12V_S0_REG_P1V05

REG_UGATE_P1V05S0

REG_PHASE_P1V05S0

REG_BOOT_P1V05S0_RC

REG_P1V05S0_VO

REG_PHASE_P1V05S0_L

PP1V05_S0_REG

VOLTAGE=0V

prefsb

051-9504

7.0.0

117 OF 143

95 OF 117

2

11

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

10

15

20

19

7

12

11

14

13

4

16

1

17

18

2

3

8

9

6

5

212

1

2

1

2

1

12

1

2

12

1

2

1

2

1

2

121

2

121

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

6

9

4

3

5

8

7

1

2

1

12

11

15

10

2

5

9

7

8

4

13

14

1

16

3

6

12

2

1

2

1

2

1

2

1

2

1

2

128

356

7

4

3

4

2

1

5

6

2

1

2

1

2

1

2

1

2

1

2

1

2

1

12

2

1

2

12

21

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

1

2

1

2

1

21

104

95

104

95

104

6

110

95

110

95

110

95

110

5

64 95

115

6

104

6

66 69 70 72 92 95

6

66 69 70 72 92 95

6

95

110

5

64

95

115

95 104

116

104

116

110

105 105

104

110

104

110

104

6

104

95

104

6

95

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

BGA Area Constraints

D8 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS

Fixed and Dielectric

General Physical Rule Definitions

General Spacing Definitions

Default

Board Stack-up

Top

Signal

0.5 oz (Cu plated)

FINISHED BOARD THICKNESS: 1.94 MM

Plane

1 oz

Core

0.5 oz

Signal

Prepreg

Plane

Core

Plane

1 oz

Plane

Prepreg

Signal

1 oz

0.076 MM

Core 0.101 MM

Core

Plane

1 oz

Plane

0.071 MM

Prepreg

0.071 MM

Prepreg

0.5 oz (Cu plated)

Signal

Btm

Prepreg

0.115 MM

0.5 oz

0.101 MM

0.5 oz

0.115 MM

0.380 MM

0.5 oz

0.380 MM

1 oz

Prepreg

Signal

2

3

4

6

7

8

9

10

11

5

0.076 MM

Compensation Physical Rule Definition

Power and Common

GENERIC

BGA

NOTE: line width based on 12 mil recommendation

NOTE: neck width based on 4 mil recommendation

45_OHM_SE =STANDARD

0.115 MM

*Y

0.085 MM

=STANDARD=STANDARD

=STANDARD

0.085 MM

*Y

=STANDARD

50_OHM_SE

0.090 MM

=STANDARD

0.080 MM0.080 MM

=STANDARD

Y

55_OHM_SE ISL5,ISL8

=STANDARD

0.171 MM

68_OHM_DIFF

*Y

0.085 MM

0.1 MM

0.130 MM

0.150 MM

0.085 MM

=STANDARD

0.185 MM

68_OHM_DIFF

TOP,BOTTOM

Y

0.1 MM

0.126 MM

=STANDARD

Y

=STANDARD

45_OHM_SE ISL5,ISL8

0.085 MM

=STANDARD

Y

0.085 MM

TOP,BOTTOM

0.135 MM

=STANDARD

45_OHM_SE =STANDARD

TOP,BOTTOM

=STANDARD

0.085 MM

Y

50_OHM_SE

0.105 MM

=STANDARD=STANDARD

0.075 MM0.075 MM

=STANDARD

*

=STANDARD

55_OHM_SE

Y

*PM *

PM_ISO

*PM

DEFAULT

GND

D8 RULE DEFINITIONS

SYNC_MASTER=D8_KOSECOFF

SYNC_DATE=03/19/2012

*

?

0.1 MM

1:1_SPACING

BGA_P1MM

**

BGA

0.1 MM

*

80_OHM_DIFF

0.136 MM

Y

=STANDARD

0.085 MM

0.190 MM

TOP,BOTTOM

0.1 MM

0.185 MM

0.141 MM

Y

=STANDARD

0.085 MM

80_OHM_DIFF

0.190 MM

0.1 MM

0.085 MM

Y*

85_OHM_DIFF

=STANDARD

0.121 MM

0.1 MM

100_OHM_DIFF

0.230 MM

0.090 MM

=STANDARD

0.085 MM

Y

TOP,BOTTOM

0.1 MM

0.200 MM

0.086 MM

Y

=STANDARD

0.085 MM

*

100_OHM_DIFF

0.109 MM

0.1 MM

Y

0.085 MM

90_OHM_DIFF

*

=STANDARD

0.200 MM

TOP,BOTTOM

=STANDARD

0.085 MM

=STANDARD

42_OHM_SE

Y

0.155 MM

0.1 MM

=50_OHM_SE

Y*

0 MM 0 MM

DEFAULT

10 MM

=STANDARD=STANDARD

Y

=STANDARD39_OHM_SE

0.085 MM0.165 MM

ISL5,ISL8

Y

0.305 MM

=STANDARD=STANDARD

3 MM

0.105 MM

*

COMP_SE

*

0.1 MM

?

DEFAULT

0.076 MM

*

1X_DIELECTRIC

?

TOP,BOTTOM

1X_DIELECTRIC

0.071 MM

?

=STANDARD

Y

=STANDARD

0.085 MM0.220 MM

=STANDARD

34_OHM_SE

TOP,BOTTOM

=STANDARD

ISL5,ISL8

Y

=STANDARD

0.085 MM0.205 MM

=STANDARD

34_OHM_SE

0.085 MM

39_OHM_SE =STANDARD

=STANDARD=STANDARD

0.175 MM

Y

TOP,BOTTOM

*

=STANDARD=STANDARD

Y

39_OHM_SE

0.150 MM 0.085 MM

=STANDARD

=STANDARDISL5,ISL8

=STANDARD=STANDARD

50_OHM_SE

Y

0.085 MM0.100 MM

0.111 MM

Y

TOP,BOTTOM

0.085 MM

=STANDARD

0.200 MM

90_OHM_DIFF

0.1 MM

0.190 MM

0.125 MM 0.085 MM

=STANDARD

85_OHM_DIFFYTOP,BOTTOM

*Y

=STANDARD

0.085 MM0.185 MM

34_OHM_SE

=STANDARD

*

=STANDARD

0.085 MM

Y

=STANDARD

42_OHM_SE

0.130 MM

=STANDARD

42_OHM_SE ISL5,ISL8 =STANDARD

=STANDARD

0.085 MM

Y

=STANDARD

0.145 MM

0.085 MM

=STANDARD

Y

0.085 MM

=STANDARD

55_OHM_SE

TOP,BOTTOM

=STANDARD

0.101 MM

ISL3,ISL10

1X_DIELECTRIC

?

STANDARD =DEFAULT

?

*

10 MM

=DEFAULT

*Y

=DEFAULTSTANDARD

=DEFAULT

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

16.2

MM

NO_TYPE,BGA,BGA_TBT

=1:1_SPACING

PM_ISO

*

?

=1:1_SPACING

GENERIC_ISO

*

?

=2:1_SPACING

*

1100

PWR_P2MM

=2:1_SPACING

*

1000

GND_P2MM

=STANDARD

GND_ISO

*

8000

BGA_P1MM

*

?

=STANDARD

prefsb

051-9504

7.0.0

120 OF 143

96 OF 117

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DDR3-specific Spacing Definitions

Clocks: CK[3:0], CK#[3:0]

Constraints

Physical Net Type to Rule Map

DDR3 Power-specific Spacing Definitions

Data: DQS[7:0], DQS#[7:0], DQ[63:0]

Command: MA[15:0], RAS#, CAS#, WE# BS[2:0]

Control: CS#[3:0], CKE[3:0], ODT[3:0]

See Note (1)

See Note (2)

See Note (3)

See Note (1)

Note (2):

Note (1):

complexity to contraints, even though it can be less. Only

and via to pad to two different channels. DDR3 draws about 20 mA per trace with edge rates in the 100s of ps. The main

Intel suggests 25 mil (0.65 mm) spacing for via to channel,

one rule per channel is needed by trading off a little space.

To meet these rules, the spacing must be applied to the net.

coupling however). These rules are far too conservative.

for power nets, which draw far more current (inductive

coupling mechanism is capacitive. A 0.65 mm spacing is used

Note (3):

DDR_DQ2DQ must have a weight greater than DDR_BL2BL.

out over DDR_{A,B}_DQ_BYTE* to DDR_{A,B}_DQ_BYTE* so that

In order for the constraints DDR_*_DQ_BYTE* to =SAME to win

the small intra-bytelane spacing is used, the spacing rule

Spacing

DDR3-specific Physical Rules

DDR3

Minimum diff spacing is 4 mil Table 3-5, Intel Doc# 473718

Reset

Channel A

DDR3

Channel B

Electrical Contraint Set

Physical

Deliberately set DQ to DQS spacing to 3:1 to avoid adding

I178

I179

I180

I181

I182

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

DDR3 Constraints

SYNC_DATE=03/19/2012

SYNC_MASTER=D8_KOSECOFF

DDR_DQ2DQS ISL3,ISL10

=3.3X_DIELECTRIC

?

DDR_CH2CH

TOP,BOTTOM

=9.1X_DIELECTRIC

?

=10.9X_DIELECTRIC

?

*

DDR_CH2CH

TOP,BOTTOM

=7X_DIELECTRIC

CMD2DATA_ISO

?

=5X_DIELECTRIC

*

CMD2DATA_ISO

?

ISL3,ISL10

=5X_DIELECTRIC

CMD2DATA_ISO

?

ISL3,ISL10

DDR_CH2CH

?

=8.2X_DIELECTRIC

DDR_BL2BL

TOP,BOTTOM

=4.5X_DIELECTRIC

?

DDR_DQ2DQS

=4.4X_DIELECTRIC

*

?

DDR_DQ2DQS TOP,BOTTOM

=3.7X_DIELECTRIC

?

=3.8X_DIELECTRIC

900

DDR_DQ2DQ

*

TOP,BOTTOM

=3.2X_DIELECTRIC

900

DDR_DQ2DQ

ISL3,ISL10

=2.8X_DIELECTRIC

DDR_DQ2DQ

900

DDR_BL2BL

=5.3X_DIELECTRIC

?

*

DDR_BL2BL

ISL3,ISL10?=4.0X_DIELECTRIC

=5.3X_DIELECTRIC

?

DDR_DATA_ISO

*

DDR_B_DQ_BYTE*

*

DDR_DQ2DQSDDR_B_DQS*

DDR_*_DQ_BYTE*

=SAME

DDR_DQ2DQ

*

=5.3X_DIELECTRIC

DDR_CTRL_ISO

*

?

=4.0X_DIELECTRIC

?

ISL3,ISL10

DDR_CTRL_ISO

?

TOP,BOTTOM

=4.5X_DIELECTRIC

DDR_CTRL_ISO

=6.5X_DIELECTRIC

?

DDR_CLK_ISO

*

DDR_68D

*

DDR_CLK_PHY

DDR_DATA_ISO

**

DDR_B_DQ_BYTE*

**

DDR_DATA_ISO

DDR_B_DQS*

*

DDR_BL2BL

DDR_A_DQ_BYTE* DDR_A_DQ_BYTE*

**

DDR_CLK

DDR_CLK_ISO

**

DDR_CTRL

DDR_CTRL_ISO

DDR_CTRL

*

DDR_CTRL2CTRL

DDR_CTRL

DDR_CMD

*

DDR_CMD_ISO

*

DDR_CMD

DDR_CMD2CMD

*

DDR_CMD

DDR_A_DQ_BYTE*

*

DDR_CMD

CMD2DATA_ISO

*

DDR_A_DQS*

DDR_CMD

CMD2DATA_ISO

DDR_CMD

*

CMD2DATA_ISO

DDR_B_DQ_BYTE*

*

CMD2DATA_ISO

DDR_CMD

DDR_B_DQS*

**

DDR_DATA_ISO

DDR_A_DQ_BYTE*

**

DDR_DATA_ISO

DDR_A_DQS*

DDR_A_DQ_BYTE*

DDR_A_DQS*

*

DDR_DQ2DQS

*

DDR_BL2BL

DDR_B_DQ_BYTE* DDR_B_DQ_BYTE*

DDR_B_*

DDR_CH2CH

*

DDR_A_*

POWER_DDR

POWER_DDR_ISO

**

=4.3X_DIELECTRIC

*

POWER_DDR_ISO

?

*

POWER_DDR_P4MM

POWER_DDR_PHY

DDR_CTRL_PHY

DDR_39S

*

DDR_42S_D

DDR_DQS_PHY

*

DDR_CMD_PHY

*

DDR_34S

DDR_DQ_PHY

DDR_42S

*

=3.0X_DIELECTRIC

DDR_CTRL2CTRL

TOP,BOTTOM

?

DDR_CTRL2CTRL

=2.6X_DIELECTRIC

ISL3,ISL10

?

=3.5X_DIELECTRIC

DDR_CTRL2CTRL

*

?

=4.0X_DIELECTRIC

DDR_CMD_ISO

ISL3,ISL10

?

DDR_CMD_ISO

=4.5X_DIELECTRIC

TOP,BOTTOM

?

DDR_CMD_ISO

?

*

=5.3X_DIELECTRIC

DDR_CMD2CMD

=2.7X_DIELECTRIC

*

?

DDR_CMD2CMD

ISL3,ISL10

=2.0X_DIELECTRIC

?

=2.3X_DIELECTRIC

DDR_CMD2CMD?TOP,BOTTOM

=4.5X_DIELECTRIC

DDR_DATA_ISO

TOP,BOTTOM

?

ISL3,ISL10

DDR_DATA_ISO

=4.0X_DIELECTRIC

?

=5.5X_DIELECTRIC

TOP,BOTTOM

DDR_CLK_ISO

?

=4.9X_DIELECTRIC

ISL3,ISL10

DDR_CLK_ISO

?

=42_OHM_SE

BOTTOM

=55_OHM_SE=55_OHM_SE

0.1016 MM 0.1016 MM

2.0 MM

DDR_42S_D

*

=42_OHM_SE

0.1016 MM

=42_OHM_SE=42_OHM_SE

0.1016 MM

=42_OHM_SE

DDR_42S_D

=34_OHM_SE

=STANDARD

=34_OHM_SE=34_OHM_SE

*

=STANDARD

DDR_34S

=34_OHM_SE

DDR_34S

BOTTOM 2.0 MM

=STANDARD

=34_OHM_SE

=STANDARD

=34_OHM_SE=34_OHM_SE

*

DDR_39S

=STANDARD=STANDARD

=39_OHM_SE=39_OHM_SE =39_OHM_SE=39_OHM_SE

DDR_42S

=42_OHM_SE

*

=42_OHM_SE =42_OHM_SE =42_OHM_SE

=STANDARD=STANDARD

ISL5,ISL8

=42_OHM_SE =55_OHM_SE =55_OHM_SE

0.1016 MM 0.1016 MM

2.0 MM

DDR_42S_D

POWER_DDR_P4MM

=STANDARD

0.400 MM

*

=STANDARD

Y

3.0 MM

0.100 MM

BOTTOM

=55_OHM_SE=55_OHM_SE

DDR_42S

=42_OHM_SE

=STANDARD=STANDARD

2.0 MM

ISL5,ISL8

=55_OHM_SE=55_OHM_SE

2.0 MM

=STANDARD =STANDARD

=42_OHM_SE

DDR_42S

=50_OHM_SE

=STANDARD=STANDARD

=50_OHM_SE

DDR_50S

*

=50_OHM_SE=50_OHM_SE

=68_OHM_DIFF =68_OHM_DIFF

=68_OHM_DIFF

DDR_68D

=68_OHM_DIFF

*

=68_OHM_DIFF =68_OHM_DIFF

MEM_B_CLK_N<3..2>

DDR_CLK

DDR_CLK_PHY

DDR_B_CLK1

DDR_CTRL

MEM_B_CKE<3..2>

DDR_B_CTRL1

DDR_CTRL_PHY

DDR_CMD

MEM_B_BA<2..0>

DDR_B_CMD

DDR_CMD_PHY

MEM_B_DQ<23..16>

DDR_B_DQ_BYTE2

DDR_DQ_PHY

DDR_B_DQ_BYTE2

DDR_B_DQ_BYTE3

DDR_DQ_PHY

DDR_B_DQ_BYTE3

MEM_B_DQ<31..24>

DDR_B_DQ_BYTE6

MEM_B_DQ<55..48>

DDR_B_DQ_BYTE6

DDR_DQ_PHY

DDR_B_DQS2

MEM_B_DQS_P<2>

DDR_DQS_PHY

DDR_B_DQS2

DDR_B_DQS3 DDR_B_DQS3

DDR_DQS_PHY

MEM_B_DQS_P<3>

DDR_B_DQS4

MEM_B_DQS_N<4>

DDR_B_DQS4

DDR_DQS_PHY

MEM_B_DQ<39..32>

DDR_B_DQ_BYTE4

DDR_DQ_PHY

DDR_B_DQ_BYTE4

DDR_CMD

MEM_A_RAS_L

DDR_A_CMD

DDR_CMD_PHY

DDR_CLK

DDR_A_CLK0

DDR_CLK_PHY

MEM_A_CLK_P<1..0>

DDR_CLK

MEM_A_CLK_N<1..0>

DDR_A_CLK0

DDR_CLK_PHY

DDR_CMD

MEM_A_WE_L

DDR_A_CMD

DDR_CMD_PHY

DDR_CMD

MEM_A_CAS_L

DDR_A_CMD

DDR_CMD_PHY

DDR_CMD

MEM_A_BA<2..0>

DDR_A_CMD

DDR_CMD_PHY

DDR_CMD

MEM_A_A<15..0>

DDR_A_CMD

DDR_CMD_PHY

DDR_CLK

DDR_A_CLK1

DDR_CLK_PHY

MEM_A_CLK_P<3..2>

DDR_CLK

MEM_A_CLK_N<3..2>

DDR_A_CLK1

DDR_CLK_PHY

MEM_A_CKE<1..0>

DDR_CTRL

DDR_A_CTRL0

DDR_CTRL_PHY

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL0

MEM_A_CS_L<1..0> MEM_A_ODT<1..0>

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL0

DDR_B_CLK1

DDR_CLK

DDR_CLK_PHY

MEM_B_CLK_P<3..2>

DDR_A_DQS7

MEM_A_DQS_N<7>

DDR_A_DQS7

DDR_DQS_PHY

MEM_A_DQS_P<7>

DDR_A_DQS7DDR_A_DQS7

DDR_DQS_PHY

DDR_A_DQS6

MEM_A_DQS_N<6>

DDR_A_DQS6

DDR_DQS_PHY

DDR_A_DQS5

MEM_A_DQS_N<5>

DDR_A_DQS5

DDR_DQS_PHY

DDR_A_DQS5

MEM_A_DQS_P<5>

DDR_A_DQS5

DDR_DQS_PHY

MEM_B_CLK_N<1..0>

DDR_CLK

DDR_CLK_PHY

DDR_B_CLK0

MEM_A_DQ<47..40>

DDR_A_DQ_BYTE5DDR_A_DQ_BYTE5

DDR_DQ_PHY

DDR_A_DQ_BYTE6

MEM_A_DQ<55..48>

DDR_A_DQ_BYTE6

DDR_DQ_PHY

DDR_A_DQ_BYTE7DDR_A_DQ_BYTE7

MEM_A_DQ<63..56>

DDR_DQ_PHY

DDR_A_DQ_BYTE1

MEM_A_DQ<15..8>

DDR_A_DQ_BYTE1

DDR_DQ_PHY

DDR_A_DQS0

MEM_A_DQS_N<0>

DDR_A_DQS0

DDR_DQS_PHY

DDR_CTRL

DDR_B_CTRL0

MEM_B_CKE<1..0>

DDR_CTRL_PHY

DDR_CTRL

DDR_B_CTRL0

MEM_B_CS_L<1..0>

DDR_CTRL_PHY

DDR_A_DQS1

MEM_A_DQS_P<1>

DDR_A_DQS1

DDR_DQS_PHY

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL1

MEM_A_CKE<3..2>

MEM_A_ODT<3..2>

DDR_CTRL

DDR_A_CTRL1

DDR_CTRL_PHY

DDR_CTRL

DDR_CTRL_PHY

DDR_A_CTRL1

MEM_A_CS_L<3..2>

DDR_A_DQ_BYTE0

MEM_A_DQ<7..0>

DDR_A_DQ_BYTE0

DDR_DQ_PHY

DDR_A_DQ_BYTE3

MEM_A_DQ<31..24>

DDR_A_DQ_BYTE3

DDR_DQ_PHY

DDR_A_DQ_BYTE2 DDR_A_DQ_BYTE2

MEM_A_DQ<23..16>

DDR_DQ_PHY

MEM_A_DQ<39..32>

DDR_A_DQ_BYTE4DDR_A_DQ_BYTE4

DDR_DQ_PHY

DDR_A_DQS0 DDR_A_DQS0

MEM_A_DQS_P<0>

DDR_DQS_PHY

MEM_A_DQS_N<1>

DDR_A_DQS1DDR_A_DQS1

DDR_DQS_PHY

DDR_A_DQS2

MEM_A_DQS_N<2>

DDR_A_DQS2

DDR_DQS_PHY

DDR_A_DQS4

MEM_A_DQS_P<4>

DDR_A_DQS4

DDR_DQS_PHY

DDR_CLK

MEM_B_CLK_P<1..0>

DDR_CLK_PHY

DDR_B_CLK0

DDR_CTRL

DDR_B_CTRL0

MEM_B_ODT<1..0>

DDR_CTRL_PHY

DDR_CTRL

MEM_B_CS_L<3..2>

DDR_B_CTRL1

DDR_CTRL_PHY

DDR_CTRL

MEM_B_ODT<3..2>

DDR_B_CTRL1

DDR_CTRL_PHY

DDR_CMD

MEM_B_A<15..0>

DDR_B_CMD

DDR_CMD_PHY

MEM_B_WE_L

DDR_B_CMD

DDR_CMD

DDR_CMD_PHY

DDR_CMD

MEM_B_CAS_L

DDR_B_CMD

DDR_CMD_PHY

DDR_B_DQ_BYTE0

MEM_B_DQ<7..0>

DDR_B_DQ_BYTE0

DDR_DQ_PHY

MEM_B_DQS_P<0>

DDR_B_DQS0 DDR_B_DQS0

DDR_DQS_PHY

MEM_B_DQS_N<0>

DDR_B_DQS0 DDR_B_DQS0

DDR_DQS_PHY

MEM_B_DQS_P<1>

DDR_B_DQS1 DDR_B_DQS1

DDR_DQS_PHY

DDR_B_DQS7DDR_B_DQS7

MEM_B_DQS_P<7>

DDR_DQS_PHY

DDR_A_DQS2

MEM_A_DQS_P<2>

DDR_A_DQS2

DDR_DQS_PHY

DDR_B_DQS2

MEM_B_DQS_N<2>

DDR_B_DQS2

DDR_DQS_PHY

DDR_B_DQ_BYTE7 DDR_B_DQ_BYTE7

MEM_B_DQ<63..56>

DDR_DQ_PHY

DDR_B_DQS6

MEM_B_DQS_N<6>

DDR_B_DQS6

DDR_DQS_PHY

DDR_B_DQS7

DDR_DQS_PHY

MEM_B_DQS_N<7>

DDR_B_DQS7

DDR_B_DQS1

MEM_B_DQS_N<1>

DDR_DQS_PHY

DDR_B_DQS1

MEM_B_DQ<47..40>

DDR_B_DQ_BYTE5 DDR_B_DQ_BYTE5

DDR_DQ_PHY

DDR_DQS_PHY

DDR_B_DQS6

MEM_B_DQS_P<6>

DDR_B_DQS6

DDR_A_DQS3 DDR_A_DQS3

MEM_A_DQS_N<3>

DDR_DQS_PHY

DDR_A_DQS3 DDR_A_DQS3

MEM_A_DQS_P<3>

DDR_DQS_PHY

DDR_B_DQS4

MEM_B_DQS_P<4>

DDR_B_DQS4

DDR_DQS_PHY

MEM_B_DQS_N<3>

DDR_B_DQS3 DDR_B_DQS3

DDR_DQS_PHY

MEM_B_DQS_N<5>

DDR_B_DQS5 DDR_B_DQS5

DDR_DQS_PHY

MEM_B_DQS_P<5>

DDR_B_DQS5 DDR_B_DQS5

DDR_DQS_PHY

CPU

DDR_50S

MEM_RESET_L

MEM_B_DQ<15..8>

DDR_B_DQ_BYTE1DDR_B_DQ_BYTE1

DDR_DQ_PHY

DDR_CMD

MEM_B_RAS_L

DDR_B_CMD

DDR_CMD_PHY

DDR_A_DQS6 DDR_A_DQS6

MEM_A_DQS_P<6>

DDR_DQS_PHY

DDR_A_DQS4 DDR_A_DQS4

MEM_A_DQS_N<4>

DDR_DQS_PHY

prefsb

051-9504

7.0.0

121 OF 143

97 OF 117

12 32

12 31 32

12 33

12 29 30

12 29

12 29 30

12 30

12 29

12 32

12 33

12 31

12 33

12 31

12 33

12 30

12 33

12 31

12 32

12 31 32

12 33

28 29 30 31 32

12 33

12 31 32

12 33

TABLE_SPACING_ASSIGNMENT_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

PCIe and DMI Compensation Rules (mils)

Imp

Physical

Spacing

DMI. Numbers based on Intel stack-up.

x1 AirPort

PCIe. Impedance inferred from Table 4-7.

Spacing

PCIe (CPU)

Electrical Contraint Set Electrical Contraint Set

x16 Graphics

Physical Physical

PCIe (CPU)

PCIe-specific Spacing Definitions

CPU PCIe Compensation

Physical Net Type to Rule Map

PCI EXPRESS

PCIe-specific Physical Rules

4-5

Table

PCIe Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

15.75

15

Design

x16 Graphics

4-7

Spacing

CPU PCIe Clocks

Comments PCIe Gen2, PCIe Gen3, DMI

Design

15.75

Iso 16

Design 8580

Section

4.2.1

Comments

15.75

Design

Iso

5050

50

Imp

50

8

Constraints

Physical

Spacing

Electrical Contraint Set

PCIe (PCH)

PCIE (PCH - TBT)

Electrical Contraint Set

x4 Thunderbolt

x1 Caesar IV

I440

I441

I442

I443

I444

I445

I446

I447

I448

I449

I450

I451

I452

I453

I454

I455

I456

I457

I458

I459

I460

I461

I462

I463

I464

I465

I466

I467

I468

I469

I470

I471

I472

I473

I474

I475

I476

I477

I478

I479

I480

I481

I482

I483

I484

I485

I486

I487

I488

I489

I490

I491

I492

I493

I494

I495

I496

I497

I498

I499

I500

I501

I502

I503

I504

I505

I506

I507

I508

I509

I510

I511

I512

I513

I514

I515

I516

I517

I518

I519

I520

I521

I522

I523

I524

I525

I526

I527

I528

I529

I530

I531

I532

I533

I534

I535

I536

I537

I538

I539

I540

I541

I542

I543

I544

I545

I546

I547

I548

I549

I550

I551

I552

I553

I554

I555

I556

I557

I558

I559

I560

I561

I562

I563

I564

I565

I566

I567

I568

I569

I570

I571

I572

I573

I574

I575

I576

I577

I578

I579

I580

I599

I600

I601

I602

I603

I604

I607

I608

I609

I610

I611

I612

I613

I614

I615

I616

I617

I618

I619

I620

I621

I622

I623

I624

*

COMP_PCIE_ISO

=4:1_SPACING

?

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

*

=90_OHM_DIFF

PCIE_90D

*

=80_OHM_DIFF

PCIE_80D

=80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF

PCIE_ISO

*

=4X_DIELECTRIC

?

CLK_PCIE_PHY

*

PCIE_90D

*

PCIE_80DPCIE_PHY

PCIE_ISO

?

TOP,BOTTOM

=5X_DIELECTRIC

COMP_PCIE_PHY

*

COMP_SE

PCIE_50S

=50_OHM_SE

=STANDARD

*

=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE

?

*

CLK_PCIE_ISO =5:1_SPACING

CPU PCIe Constraints

SYNC_DATE=03/13/2012SYNC_MASTER=D8_AARON

**

COMP_PCIE

COMP_PCIE_ISO

CLK_PCIE

**

CLK_PCIE_ISO

**

PCIE

PCIE_ISO

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_TBT_R2D_P<2..0>

PCIE_GEN2_R2D_PINV

NO_TEST=TRUE

PEG_D2R_C_N<3>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_N<1>

PCIE

PCIE_PHY

PCIE_GEN3_D2R

NO_TEST=TRUE

PEG_D2R_P<1>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PEG_D2R_C_P<2>

PCIE

NO_TEST=TRUECLK_PCIE_PHY

PEG_CLK100M_N

CLK_PCIE

PCIE_REF_CLK

CPU_PEG_COMP

COMP_PCIE_PHY

COMP_PCIE

PCIE_CLK100M_ENET_N

CLK_PCIE

PCIE_REF_CLK CLK_PCIE_PHY

NO_TEST=TRUE

PCIE_AP_D2R_N

PCIE_GEN2_D2R_CONN_AP

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE

PCIE_PHY

PCIE_GEN2_D2R_CONN_AP

PCIE_AP_D2R_P

NO_TEST=TRUE

PCIE_AP_R2D_P

PCIE

PCIE_PHY

PCIE_GEN2_R2D_CONN_AP

PCIE

PCIE_AP_R2D_C_N

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN2_R2D

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_TBT_R2D_P<3>

PCIE_GEN2_R2D

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_TBT_R2D_N<3>

PCIE_GEN2_R2D_PINV

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_TBT_R2D_N<2..0>

NO_TEST=TRUE

PCIE_TBT_R2D_C_P<3..0>

PCIE

PCIE_PHY

PCIE_GEN2_D2R_PINV

PCIE

PCIE_PHY

PCIE_TBT_D2R_C_P<1..0>

NO_TEST=TRUE

PCIE_GEN2_D2R

PCIE_ENET_D2R_P

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_ENET_D2R_C_P

NO_TEST=TRUE

PEG_D2R_C_P<8>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_P<8>

PCIE

PCIE_GEN3_D2R_PINV

NO_TEST=TRUE

PEG_D2R_C_N<8>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_C_P<0>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_R2D

PCIE

PCIE_PHY

PEG_R2D_P<11>

PCIE_PHY

PCIE

PEG_D2R_C_N<7>

NO_TEST=TRUE

PEG_D2R_P<13>

PCIE_GEN3_D2R_PINV

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_D2R_C_P<13>

NO_TEST=TRUE

PEG_R2D_C_P<12>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_R2D

PEG_R2D_N<11>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE

PCIE_PHY

PEG_R2D_C_N<11>

NO_TEST=TRUE

PCIE_GEN3_D2R

PCIE

PCIE_PHY

PEG_D2R_P<10>

PEG_D2R_N<14>

PCIE

PCIE_PHY

PCIE_GEN3_D2R

NO_TEST=TRUE

PEG_D2R_C_P<14>

PCIE

PCIE_PHY

PEG_D2R_C_N<14>

PCIE

NO_TEST=TRUE

PCIE_GEN3_R2D

PCIE

PCIE_PHY

PEG_R2D_P<13>

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PEG_R2D_N<2>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_R2D_PINV

PEG_R2D_P<2>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PEG_D2R_C_N<2>

PCIE

NO_TEST=TRUE

PEG_D2R_C_N<1>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_D2R_N<0>

PCIE

PCIE_PHY

PCIE_GEN3_D2R_PINV

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_P<0>

PCIE

PCIE_GEN3_D2R_PINV

NO_TEST=TRUE

PEG_R2D_C_N<0>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_R2D

PEG_R2D_N<0>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_P<0>

PCIE_GEN3_R2D

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PEG_D2R_C_N<0>

PCIE

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PEG_R2D_N<1>

PCIE

PCIE_PHY

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PEG_R2D_P<1>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_P<3>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_R2D_PINV

PEG_R2D_N<3>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE

PCIE_PHY

PCIE_GEN3_R2D_PINV

PEG_R2D_P<3>

PEG_D2R_C_P<7>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_P<6>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE_GEN3_D2R_PINV

PCIE

PEG_D2R_P<5>

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PEG_R2D_P<5>

PEG_R2D_C_P<6>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_R2D_P<9>

PCIE_GEN3_R2D

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_D2R_C_P<10>

NO_TEST=TRUE

PCIE_GEN3_R2D_PINV

PCIE

PCIE_PHY

PEG_R2D_N<10>

NO_TEST=TRUE

PCIE_GEN3_D2R

PCIE_PHY

PEG_D2R_N<9>

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_R2D_N<9>

PCIE_GEN3_R2D

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_R2D_C_P<11>

NO_TEST=TRUE

PCIE

PEG_D2R_C_N<11>

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_P<15>

PCIE_PHY

PCIE_GEN3_R2D

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE_GEN3_R2D

PCIE

PEG_R2D_N<15>

NO_TEST=TRUE

PEG_R2D_C_P<15>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_D2R_C_N<13>

PCIE

NO_TEST=TRUE

PEG_R2D_N<13>

PCIE_PHY

PCIE_GEN3_R2D

NO_TEST=TRUE

PEG_R2D_C_P<13>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_N<13>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_P<14>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_P<14>

PCIE_GEN3_D2R

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_P<12>

PCIE

PCIE_PHY

PCIE_GEN3_D2R

NO_TEST=TRUE

PCIE_PHY

PCIE_GEN3_D2R_PINV

PCIE

PEG_D2R_N<13>

NO_TEST=TRUE

PCIE_GEN3_R2D

PCIE

PCIE_PHY

PEG_R2D_P<14>

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_D2R_C_P<12>

NO_TEST=TRUE

PEG_D2R_C_N<15>

PCIE

PCIE_PHY

PEG_D2R_C_N<4>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_N<6>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PEG_R2D_N<5>

NO_TEST=TRUE

PEG_CLK100M_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

PCIE_GEN3_D2R

PEG_D2R_N<4>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_R2D_C_N<12>

NO_TEST=TRUE

PEG_D2R_N<12>

PCIE_PHY

PCIE_GEN3_D2R

PCIE

NO_TEST=TRUE

PCIE

PEG_R2D_C_P<9>

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_P<9>

PCIE_GEN3_D2R

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_P<2>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_N<1>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_P<0>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_N<9>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_R2D

PCIE

PCIE_PHY

PEG_R2D_P<12>

NO_TEST=TRUE

PEG_D2R_C_N<12>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_R2D_C_P<10>

NO_TEST=TRUE

PEG_R2D_N<12>

PCIE

PCIE_PHY

PCIE_GEN3_R2D

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_D2R_C_N<10>

NO_TEST=TRUE

PCIE

PCIE_GEN3_D2R

PCIE_PHY

PEG_D2R_P<11>

NO_TEST=TRUE

PCIE_GEN3_D2R

PCIE

PCIE_PHY

PEG_D2R_N<11>

NO_TEST=TRUE

PEG_D2R_C_P<11>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE

PCIE_PHY

PEG_R2D_P<10>

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PEG_D2R_N<10>

PCIE_GEN3_D2R

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_N<10>

PCIE_PHY

PCIE

PEG_D2R_C_P<9>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_GEN3_R2D_PINV

PEG_R2D_P<8>

PCIE

NO_TEST=TRUE

PCIE_PHY

PEG_R2D_C_P<8>

NO_TEST=TRUE

PEG_R2D_N<8>

PCIE_PHY

PCIE

PCIE_GEN3_R2D_PINV

PEG_R2D_C_N<14>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE

PEG_R2D_N<14>

PCIE_GEN3_R2D

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_N<15>

PCIE_PHY

PCIE

PCIE_PHY

PCIE

PEG_R2D_C_N<7>

NO_TEST=TRUE

PEG_D2R_P<15>

PCIE_PHY

PCIE_GEN3_D2R

PCIE

NO_TEST=TRUE

PEG_D2R_C_P<15>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_D2R_N<15>

PCIE_PHY

PCIE_GEN3_D2R

PCIE

PEG_R2D_N<6>

PCIE

PCIE_PHY

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

PCIE

PCIE_PHY

PEG_R2D_C_P<7>

NO_TEST=TRUE

PCIE_GEN3_R2D_PINV

PEG_R2D_N<7>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE_GEN3_D2R_PINV

PEG_D2R_N<5>

PCIE

NO_TEST=TRUE

PCIE

PCIE_PHY

PEG_D2R_C_P<5>

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_N<6>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE

PCIE_PHY

PEG_R2D_C_N<5>

NO_TEST=TRUE

PCIE

PCIE_PHY

PEG_R2D_C_P<4>

NO_TEST=TRUE

PCIE_GEN3_R2D

PEG_R2D_N<4>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_PHY

PCIE

PEG_D2R_C_N<5>

NO_TEST=TRUE

PEG_R2D_C_P<5>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_D2R_C_N<6>

PCIE_PHY

NO_TEST=TRUE

PCIE

PEG_D2R_C_P<6>

NO_TEST=TRUE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_P<2>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_D2R_PINV

PEG_D2R_N<3>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_D2R_PINV

PEG_D2R_P<3>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_D2R_C_N<9>

PCIE

PCIE_PHY

NO_TEST=TRUE

PEG_R2D_C_N<8>

PCIE

PCIE_PHY

PCIE_GEN3_D2R_PINV

NO_TEST=TRUE

PEG_D2R_N<8>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_D2R_C_P<1>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_P<1>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_N<2>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PEG_R2D_C_N<2>

PCIE

NO_TEST=TRUE

PEG_D2R_C_P<3>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_N<3>

PCIE_PHY

PCIE

PEG_D2R_C_P<4>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_P<4>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_C_N<4>

PCIE

PCIE_PHY

PCIE_GEN3_R2D

PEG_R2D_P<4>

PCIE

NO_TEST=TRUE

PCIE_GEN3_R2D_PINV

PCIE_PHY

PCIE

PEG_R2D_P<6>

NO_TEST=TRUE

PCIE_GEN2_R2D_CONN_AP

PCIE_PHY

PCIE

PCIE_AP_R2D_N

NO_TEST=TRUE

PCIE

PCIE_AP_R2D_C_P

PCIE_PHY

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_ENET_D2R_C_N

NO_TEST=TRUE

PCIE_TBT_R2D_C_N<3..0>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_TBT_D2R_P<3..0>

PCIE

PCIE_PHY

PCIE

PCIE_TBT_D2R_N<3..0>

NO_TEST=TRUE

PCIE_GEN2_D2R_PINV

PCIE_TBT_D2R_C_P<3>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN2_D2R_PINV

PCIE_TBT_D2R_C_N<3>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_CLK100M_TBT_P

CLK_PCIE

CLK_PCIE_PHYPCIE_REF_CLK

PCIE_CLK100M_TBT_N

CLK_PCIE

CLK_PCIE_PHYPCIE_REF_CLK

PCIE_GEN3_D2R

PEG_D2R_N<7>

PCIE_PHY

PCIE

NO_TEST=TRUE

PCIE_GEN3_D2R

PEG_D2R_P<7>

PCIE_PHY

PCIE

NO_TEST=TRUE

PEG_R2D_P<7>

PCIE

PCIE_PHY

PCIE_GEN3_R2D_PINV

NO_TEST=TRUE

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK_CONN

PCIE_CLK100M_AP_P

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK_CONN

PCIE_CLK100M_AP_N

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_GEN2_R2D

PCIE_ENET_R2D_P

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_GEN2_R2D

PCIE_ENET_R2D_N

NO_TEST=TRUE

PCIE_PHY

PCIE

PCIE_ENET_R2D_C_P

PCIE_PHY

PCIE

PCIE_ENET_D2R_N

PCIE_GEN2_D2R

NO_TEST=TRUE

PCIE_PHY

NO_TEST=TRUE

PCIE_ENET_R2D_C_N

PCIE

PCIE_CLK100M_ENET_P

CLK_PCIE

PCIE_REF_CLK CLK_PCIE_PHY

PCIE_GEN2_D2R

PCIE_TBT_D2R_C_N<2>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN2_D2R

PCIE_TBT_D2R_C_P<2>

PCIE

PCIE_PHY

NO_TEST=TRUE

PCIE_GEN2_D2R_PINV

PCIE

PCIE_PHY

PCIE_TBT_D2R_C_N<1..0>

NO_TEST=TRUE

prefsb

051-9504

7.0.0

122 OF 143

98 OF 117

36

10 75

75

10 75

18 75

10

18 39

18 35

35

18 35

36

18 36

36

18 39

39

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

18 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

75

10 75

35

18 35

39

18 36

36

18 36

75

10 75

18 35

39

18 39

36

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Spacing

Physical

Electrical Contraint Set

Spacing

DMI

DMI Compensation

Desktop Debug Design Guide (Intel Doc# 430883)

15.75

CPU Misc.

Standard usage branch off from OBS

Electrical Contraint Set

Physical

DMI

Spacing

Physical

XDP

Spacing

FDI

DMI

Constraints

XDP-specific Spacing Definitions

Physical Net Type to Rule Map

XDP

XDP-specific Physical Rules

Constraints

Physical Net Type to Rule Map

CPU-specific Spacing Definitions

Section

1.5

45-65

Imp

Design50Iso

-

Comments

6-4

Table

Design

11.81

Trace 10

Iso

-

15.75

Design

Using PCIe guidelines

Comments

CPU Misc / FDI

Isolation is for JTAG clocks.

Physical Net Type to Rule Map

CPU-specific Physical Rules

All signals default are 50 Ohm SE.

FDI Compensation

DMI-specific Physical Rules

XDP MISC.

Design

CPU JTAG

Electrical Contraint Set

PCH JTAG

Physical

Spacing

OBS PCH Side

Electrical Contraint Set

OBS XDP Side

Electrical Contraint Set

Physical

Chipset Test Interface

FDI Compensation Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

CPU Misc.

I165

I166

I167

I168

I171

I174

I175

I176

I177

I178

I179

I180

I181

I182

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204

I205

I206

I207

I208

I209

I210

I211

I212

I213

I214

I215

I216

I217

I218

I219

I220

I221

I222

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I283

I284

SYNC_DATE=03/23/2012

CPU MISC/DMI/FDI/XDP Constraints

SYNC_MASTER=D8_ROSITA

=STANDARD

*

=50_OHM_SE =50_OHM_SE

CPU_50S

=50_OHM_SE=50_OHM_SE

=STANDARD

*

CPU_ISO

?

=3:1_SPACING

*

COMP_FDI

COMP_FDI_ISO

*

=50_OHM_SE =50_OHM_SE

=STANDARD

=50_OHM_SE

XDP_50S

=STANDARD

=50_OHM_SE

*

DMI_PHY DMI_85D

*

CPU_PHY CPU_50S

*

COMP_FDI_PHY

COMP_FDI_SE

?

*

COMP_FDI_ISO =4:1_SPACING

CPU_ISO

*

CPU

*

XDP_50SXDP_PHY

?

*

=4:1_SPACING

XDP_CLK_ISO

XDP_ISO

?

*

=2:1_SPACING

0.25 MM

3 MM

Y

=STANDARD

*

0.3 MM

=STANDARD

COMP_FDI_SE

XDP_CLK_ISO

**

OBS_STROBE

XDP_CLK_ISO

CLK_JTAG

**

XDP

XDP_ISO

=85_OHM_DIFF

*

=85_OHM_DIFF

DMI_85D

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

XDP

XDP_PHY

XDP_DC3_SATARDRVR_EN

XDP_DA1_USB_EXTB_OC_L

XDP

XDP_PHY

XDP_DC1_GPU_GOOD

XDP

XDP_PHY

XDP_DD1_JTAG_TBT_TCK

XDP

XDP_PHY

XDP

USB_EXTB_OC_L

XDP

XDP_PHY

USB_EXTD_OC_L

XDP

XDP_PHY

USB_EXTB_OC_EHCI_L

XDP

XDP_PHY

USB_EXTD_OC_EHCI_L

XDP_PHY

XDP_PCH_OBS_UNUSED

OBS_STROBE

XDP_PIN03

XDP_PHY

XDP

AUD_IPHS_SWITCH_EN_PCH_R

XDP_PCH_OBS

XDP_PHY

XDP

XDP_PCH_OBS

ENET_LOW_PWR_PCH_R

XDP

XDP_PHY

USB_EXTB_OC_EHCI_R_L

XDP_PCH_OBS

XDP_PHY

XDP

USB_EXTD_OC_R_L

XDP_PHY

XDP

USB_EXTC_OC_R_L

XDP_PCH_OBS

NO_TEST=TRUE

DMI_N2S_N<3..0>

PCIE

DMI_N2S DMI_PHY

NO_TEST=TRUE

DMI_S2N_N<3..0>

DMI_PHYDMI_S2N

PCIE

XDP_DA2_USB_EXTC_OC_L

XDP

XDP_PHY

XDP_DA0_USB_EXTA_OC_L

XDP_PHY

XDP

CLK_PCIE_PHY

CLK_PCIE

ITP_CLK_CONN

ITPXDP_CLK100M_P

XDP_DBRESET_L

XDP

XDP_PHY

XDP

XDP_PCH_OBS

USB_EXTA_OC_R_L

XDP_PHY

XDP

XDP_PCH_OBS

ISOLATE_CPU_MEM_R_L

XDP_PCH_OBS

GPU_GOOD_R

XDP

XDP_PHY

XDP

XDP_PHY

DP_AUXCH_ISOL_R

XDP_PCH_OBS

XDP

XDP_PHY

XDP_PCH_OBS

DP_TBT_SEL_R

XDP

JTAG_TBT_TCK_R

XDP_PCH_OBS

XDP_PHY

XDP

XDP_PHY

SATARDRVR_EN_R

XDP_PCH_OBS

XDP

XDP_PHY

SDCONN_STATE_CHANGE_R

CLK_PCIE_PHY

CLK_PCIE

ITP_CLK_CONN

ITPXDP_CLK100M_N

CLK_PCIE_PHY

XDP_CPU_CLK100M_N

CLK_PCIE

XDP

XDP_PHY

XDP_DB2_AP_PWR_EN

XDP

XDP_PHY

XDP_DD2_AUD_IPHS_SWITCH_EN_PCH

XDP_PHY

XDP

SDCONN_STATE_CHANGE

COMP_FDI

CPU_FDI_COMPIO

COMP_FDI_PHY

XDP_PHY

XDP

XDP_VR_READY

XDP

XDP_PHY

XDP_CPU_PRDY_L

XDP_PCH_TCK

XDP_PHY

CLK_JTAG

XDP_CPU_TMS

XDP

XDP_PHY

XDP

XDP_PHY

XDP_PCH_PLTRST_L

CPU_PHY

CPU

CPU_PWRGD

CPU_PHY

CPU

CPU_RESET_L

XDP_PCH_TDO

XDP

XDP_PHY

XDP_PCH_TDI

XDP

XDP_PHY

XDP_PCH_TMS

XDP

XDP_PHY

XDP

XDP_CPU_PREQ_L

XDP

XDP_CPU_TDO

XDP_PHY

XDP

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP

XDP_PHY

XDP_CPU_TCK

CLK_JTAG

XDP_PHY

CLK_PCIE_PHY

XDP_CPU_CLK100M_P

CLK_PCIE

XDP

XDP_PHY

XDP_CPU_CFG<0>

XDP_PHY

XDP_PCH_PWRBTN_L

XDP

XDP_PHY

XDP

XDP_PCH_PWRGD

XDP_CPU_PWRGD

XDP_PHY

XDP

XDP_DD0_DP_TBT_SEL

XDP

XDP_PHY

CPU

CPU_PHY

PM_MEM_PWRGD

CPU_PHY

CPU

CPU_PROCHOT_L

XDP_PHY

TBT_CIO_PLUG_EVENT_R

OBS_STROBE

XDP_PCH_OBS

XDP

XDP_PHY

USB_EXTC_OC_L

XDP_PHY

AP_PWR_EN

XDP

XDP_DC2_DP_AUXCH_ISOL

XDP

XDP_PHY

CPU

CPU_PHY

CPU_PROCHOT_R_L

XDP_DB3_SDCONN_STATE_CHANGE

XDP

XDP_PHY

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP

XDP_PHY

XDP

XDP_PHY

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP

XDP_PHY

XDP_DD3_ENET_LOW_PWR_PCH

XDP

XDP_PHY

XDP_DC0_ISOLATE_CPU_MEM_L

OBS_STROBE

XDP_PHY

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_DA3_USB_EXTD_OC_L

XDP

XDP_PHY

CLK_PCIE

CLK_PCIE_PHY

ITPCPU_CLK100M_P

CLK_PCIE_PHY

CLK_PCIE

ITPCPU_CLK100M_N

XDP_PHY

XDP

XDP_CPU_PWRBTN_L

CPU_PHY

CPU

CPU_MEM_RESET_L

XDP_PHY

XDP

XDP_CPU_PLTRST_L

CPU_PECI

CPU

CPU_PHY

CPU

PM_SYNC

NO_TEST=TRUE

DMI_S2N_P<3..0>

DMI_PHYDMI_S2N

PCIE

PM_MEM_PWRGD_R

CPU

CPU_PHY

PCH_DMI_COMP

COMP_PCIE_PHY

COMP_PCIE

XDP

USB_EXTB_OC_R_L

XDP_PHY

XDP_PCH_OBS

CPU_PHY

CPU

PLT_RESET_LS1V05_L

CPU_THRMTRIP_L

CPU_PHY

CPU

CPU_PHY

CPU_CATERR_L

CLK_PCIE_PHY

CLK_PCIE

PCIE_REF_CLK

DMI_CLK100M_CPU_N

CPU_PROC_SEL

CPU

CPU_PHY

CPU_SKTOCC_L

CPU_PHY

CPU

XDP_PCH_OBS

XDP

XDP_PHY

AP_PWR_EN_R

COMP_PCIE_PHY

PCH_DMI2RBIAS

COMP_PCIE

CLK_PCIE

PCIE_REF_CLK

DMI_CLK100M_CPU_P

CLK_PCIE_PHY

NO_TEST=TRUE

DMI_N2S

PCIE

DMI_N2S_P<3..0>

DMI_PHY

XDP_PHY

XDP

USB_EXTD_OC_EHCI_R_L

XDP_PCH_OBS

XDP

XDP_PHY

CPU_CFG<17..16>

XDP_PHY

XDP

CPU_CFG<11..0>

XDP

XDP_PHY

XDP_BPM_L<7..0>

XDP_BPM_L

XDP_FC0_PCH_GPIO15

XDP_PHY

OBS_STROBE

USB_EXTA_OC_L

XDP_PHY

XDP

XDP_PHY

OBS_STROBE

TBT_CIO_PLUG_EVENT

XDP_PHY

XDP

ISOLATE_CPU_MEM_L

XDP

XDP_PHY

GPU_GOOD

XDP_PHY

XDP

DP_AUXCH_ISOL

XDP

XDP_PHY

SATARDRVR_EN

XDP

XDP_PHY

JTAG_TBT_TCK

XDP_PHY

XDP

AUD_IPHS_SWITCH_EN_PCH

XDP_PHY

XDP

ENET_LOW_PWR_PCH

DP_AUXCH_ISOL_EN

XDP

XDP_PHY

XDP

JTAG_TBT_TCK_ISOL

XDP

XDP_PHY

DP_TBT_SEL

prefsb

051-9504

7.0.0

123 OF 143

99 OF 117

25

15 20 45

15 20 46

15 20

21 25

20 25

10 19

25

15 18 25

11 25

20 25

21 25

18 25

21 25

18 25

20 25

15 18 25

25

15 20 41

10

25

11 25

18 25

11 25

25 26

11 21 25 28

11 26

18 25

11 25

25

11 19 28

11 47 48 66

21 25

15 20 46

15 20

25

11

25

11 15

25

11 28

25 26

11 21 47 48

11 19

10 19

11

19

20 25

11

11 48

11 18

11 19

11 64

20 25

19

11 18

10 19

20 25

10 25

10 15 25

11 25

25

15 20 45

15 21

21 28 34

5

21

15 18

15 21

21 26

15 21 26

15

15 36

21 62 84

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH SATA Port 0 (HDD)

PCH SATA Compensation

Physical

Electrical Contraint Set

PCH SATA Port 1 (SSD)

Spacing

Constraints

15.75

SATA

SATA-specific Physical Rules

Design

23.62

Iso

20

Iso

Design

Imp

Design

90 95

15.2.1

Section

1550

15-3

Electrical Contraint Set

50

SATA Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

SATA Gen2, SATA Gen3

Comments

Spacing

Physical

Unused

Table

SATA Compensation Rules (mils)

Physical Net Type to Rule Map

SATA-specific Spacing Definitions

Comments SATA Gen2, SATA Gen3

I102

I103

I104

I105

I106

I88

I89

I90

I91

I92

I93

I94

I95

I97

I99

SYNC_MASTER=D8_MARK

SATA/FDI/XDP Constraints

SYNC_DATE=02/10/2012

=STANDARD

=50_OHM_SE

*

=50_OHM_SE =50_OHM_SE

=STANDARD

SATA_50S

=50_OHM_SE

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

*

SATA_90D

=90_OHM_DIFF

*

SATA_90DSATA_PHY

COMP_SATA_PHY

*

SATA_50S

SATA_ISO

?

*

=7.2X_DIELECTRIC

=5.4X_DIELECTRIC

COMP_SATA_ISO

?

*

COMP_SATA

*

COMP_SATA_ISO

*

SATA

*

SATA_ISO

*

COMP_SATA_PHY

COMP_SATA

PCH_SATA3COMP

SATA_HDD_R2D_C_N

SATA

SATA_PHY

SATA_HDD_D2R_C_P

SATA

SATA_PHY

SATA_HDD_R2D_C_P

SATA

SATA_PHY

SATA

SATA_HDD_R2D_P

SATA_PHYSATA_R2D

SATA_HDD_D2R_N

SATA_D2R

SATA

SATA_PHY

SATA_SSD_R2D_N

SATA

SATA_PHY

SATA_R2D_MUX_SSD

SATA_PHY

SATA

SATA_D2R_MUX_SSD

SATA_SSD_D2R_P

COMP_SATA

COMP_SATA_PHY

PCH_SATA3RBIAS

COMP_SATA_PHY

COMP_SATA

PCH_SATAICOMP

SATA_HDD_D2R_C_N

SATA

SATA_PHY

SATA

SATA_SSD_R2D_P

SATA_PHY

SATA_R2D_MUX_SSD

SATA_PHY

SATA

SATA_D2R_MUX_SSD

SATA_SSD_D2R_N

SATA_HDD_D2R_P

SATA_D2R

SATA

SATA_PHY

SATA_PHYSATA_R2D

SATA

SATA_HDD_R2D_N

prefsb

051-9504

7.0.0

124 OF 143

100 OF 117

18

18 44

44

18 44

44

18 44

18

44

18 44

44

Apple iMac 27 A1419 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual