UTRON UT62W256BSC-35LL, UT62W256BSC-35L, UT62W256BPC-70LL, UT62W256BPC-70L, UT62W256BPC-35LL Datasheet

UTRON	UT62W256B
Rev. 1.0	32K X 8 BIT LOW POWER (6T) CMOS SRAM

FEATURES

Access time : 35ns (VCC 4.5V)

70ns (VCC 2.7V) Low power consumption:

Operating : 30/20 mA (max.) (VCC 3.6V)

45/30 mA (max.) (VCC 5.5V) Standby : 1uA (typical) L-version

0.5uA (typical) LL-version Wide Range power supply: 2.7V~5.5V All inputs and outputs are TTL compatible Fully static operation

Three state outputs

Six transistors memory cell

Data retention voltage : 1.5V (min.) Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8x13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

A4

A3

A14

.

A13

MEMORY ARRAY

VCC

ROW

.

A12

DECODER

512ROWS × 512COLUMNS

VSS

A7

.

A6

A5

A8

. . .

I/O1

.

I/O

.

COLUMN I/O

.

CONTROL

I/O8

.

COLUMN DECODER

CE

LOGIC

WE

CONTROL

A10 A9 A11

A2

A1

A0

OE

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

CE

Write Enable Input

WE

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

GENERAL DESCRIPTION

The UT62W256B is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology with 6T cell. its standby current is stable within the range of operating temperature.

The UT62W256B is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT62W256B operates with wide range power supply and all inputs and outputs are fully TTL compatible

PIN CONFIGURATION

					A14		1		28			Vcc
									27
					A12		2						WE
					A7		3	UT62W256B	26			A13
					A6				18						A8
							11
							4		25
					A5		5		24					A9
							6		23
					A4							A11
									22
					A3		7							OE
					A2		8		21			A10
					A1		9		20
															CE
					A0		10		19			I/O8
					I/O1				17			I/O7
					I/O2		12					I/O6
					I/O3		13		16			I/O5
					Vss		14		15			I/O4
							PDIP/SOP
																				A10
	OE				1							28
A11					2							27									CE
	A9				3							26								I/O8
	A8				4							25								I/O7
A13					5							24								I/O6
WE					6							23								I/O5
	Vcc				7	UT62W256B						22								I/O4
A14					8							21								Vss
A12					9							20								I/O3
	A7				10							19								I/O2
	A6				11							18								I/O1
	A5				12							17									A0
	A4				13							16									A1
	A3				14							15									A2

STSOP

UTRON TECHNOLOGY INC.

P80030

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

UTRON			UT62W256B
Rev. 1.0	32K X 8 BIT LOW POWER (6T) CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER		SYMBOL	RATING	UNIT
Terminal Voltage with Respect to VSS		VTERM	-0.5 to +7.0	V
Operating Temperature		TA	0 to +70
Storage Temperature		TSTG	-65 to +150
Power Dissipation		PD	1	W
DC Output Current		IOUT	50	mA
Soldering Temperature (under 10 sec0		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE							I/O OPERATION	SUPPLY CURRENT
	CE		OE		WE
Standby	H		X		X		High - Z	ISB, ISB1
Output Disable	L		H		H		High - Z	ICC
Read	L		L		H		DOUT	ICC
Write	L		X		L		DIN	ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (TA = 0																to 70			)
PARAMETER	SYMBOL			TEST CONDITION											Vcc=2.7V~3.6V					Vcc=4.5V~5.5V			UNIT
															MIN.		TYP.	MAX.		MIN.	TYP.	MAX.
Input High Voltage	VIH														2.0		-	VCC+0.5		2.2	-	VCC+0.5	V
Input Low Voltage	VIL														- 0.5		-		0.6	- 0.5	-	0.6	V
Input Leakage Curre	ILI	VSS VIN VCC													- 1		-		1	- 1	-	1	µA
Output Leakage	ILO	VSS VI/O VCC													- 1		-		1	- 1	-	1	µA
Current							=VIH or					= VIH
			CE							OE
				or					= VIL
								WE
Output High Voltage	VOH	IOH= - 1mA													2.2		-		-	2.4	-	-	V
Output Low Voltage	VOL	IOL= 4mA														-	-		0.4	-	-	0.4	V
Operating Power	ICC						= VIL ,						- 35			-	-		30	-	-	45	mA
				CE
Supply Current		II/O = 0mA ,Cycle=Min.											- 70			-	-		20	-	-	30	mA
	ICC1	Tcycle=500ns														-	-		12	-	-	20	mA
				CE			= 0.2V; II/O = 0mA
		other pins at 0.2V or VCC-0.2V
	ICC2	Tcycle=1µs														-	-		6	-	-	10	mA
			CE				= 0.2V; II/O = 0mA
		other pins at 0.2V or VCC-0.2V
Standby Power	ISB		CE				=VIH										-		2		-	3	mA
Supply Current
	ISB1												-L			-	1		30	-	1	40	µA
			CE VCC-0.2V
													-LL				0.5		5		0.5	5	µA

UTRON TECHNOLOGY INC.

P80030

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

UTRON				UT62W256B
Rev. 1.0		32K X 8 BIT LOW POWER (6T) CMOS SRAM
CAPACITANCE	(TA=25 , f=1.0MHz)
PARAMETER		SYMBOL	MIN.	MAX	UNIT
Input Capacitance		CIN	-	8	pF
Input/Output Capacitance		CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS		(VCC = 5V±10% , TA = 0 to 70 )
(1) READ CYCLE
PARAMETER	SYMBOL		VCC=5.0V±0.5V		VCC=2.7V~3.6V		UNIT
			MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC		35	-	70	-	ns
Address Access Time	tAA		-	35	-	70	ns
Chip Enable Access Time	tACE		-	35	-	70	ns
Output Enable Access Time	tOE		-	25	-	35	ns
Chip Enable to Output in Low Z	tCLZ*		10	-	10	-	ns
Output Enable to Output in Low Z	tOLZ*		5	-	5	-	ns
Chip Disable to Output in High Z	tCHZ*		-	25	-	35	ns
Output Disable to Output in High Z	tOHZ*		-	25	-	35	ns
Output Hold from Address Change	tOH		5	-	5	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL		VCC=5.0V±0.5V		VCC=2.7V~3.6V		UNIT
			MIN.	MAX.	MIN.	MAX.
Write Cycle Time	tWC	35		-	70	-	ns
Address Valid to End of Write	tAW	30		-	60	-	ns
Chip Enable to End of Write	tCW	30		-	60	-	ns
Address Set-up Time	tAS	0		-	0	-	ns
Write Pulse Width	tWP	25		-	50	-	ns
Write Recovery Time	tWR	0		-	0	-	ns
Data to Write Time Overlap	tDW	20		-	30	-	ns
Data Hold from End of Write Time	tDH	0		-	0	-	ns
Output Active from End of Write	tOW*	5		-	5	-	ns
Write to Output in High Z	tWHZ*	-		15	-	25	ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80030

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON	UT62W256B
Rev. 1.0	32K X 8 BIT LOW POWER (6T) CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

	tAA
	tOH	tOH
DOUT		Data Valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
	tRC
Address
	tAA
CE
	tACE
OE
	tOE	tCHZ
	tCLZ	tOHZ
DOUT	tOLZ	tOH
	High-z	High-Z
		Data valid

Notes :

1.WE is HIGH for read cycle.

2.Device is continuously selected CE =VIL.

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4.OE is LOW.

5.	tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
	±
6.	At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.

UTRON TECHNOLOGY INC.

P80030

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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