UTRON UT62L1024SC-70LLI, UT62L1024SC-70LI, UT62L1024SC-55LLI, UT62L1024SC-55LI, UT62L1024LS-70LLI Datasheet

UTRON	UT62L1024(I)
Preliminary Rev. 0.1	128K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Access time : 55/70ns (max.) Low power consumption : Operating : 30/20 mA (typical)

Standby : 10µA (max) L-version TA 50 3µA (max) LL-version TA 50

Power supply range : 2.5V ~ 3.6V

All inputs and outputs TTL compatible Fully static operation

Data retention voltage : 2V (min.) Operation Temperature Industrial : -40 ~+85 Package : 32-pin 450mil SOP

32-pin 8x20mm TSOP-1

32-pin 8x13.4mm STSOP

36-pin 6×8mm TFBGA

GENERAL DESCRIPTION

The UT62L1024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

Easy memory expansion is provided by using two chip enable input ( CE1 ,CE2) and supports industrial operating temperature range.

The UT62L1024 operates from a wide range 2.5V~3.6V power supply and all inputs and outputs are fully TTL compatible.

FUNCTIONAL BLOCK DIAGRAM

2048 × 512

A0-A16 DECODER MEMORY ARRAY

Vcc

Vss

	I/O1-I/O8	I/O DATA	COLUMN I/O
		CIRCUIT

CE1
CE2								CONTROL
								CIRCUIT
			OE
		WE

UTRON TECHNOLOGY INC.

P80078

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

UTRON

Preliminary Rev. 0.1

PIN CONFIGURATION

NC		1		32
A16				31
		2
A14		3		30
A12			UT62L1024	29
		4
A7		5		28
A6		6		27
A5				26
		7
A4		8		25
A3				24
		9
A2				23
		10
A1				22
		11
A0				21
		12
I/O1				20
		13
I/O2				19
		14
I/O3				18
		15
Vss				17
		16

SOP

	A11			1
	A9			2
	A8			3
	A13			4
	WE			5
CE2				6
	A15			7	UT62L1024
	Vcc			8
	NC			9
	A16			10
	A14			11
	A12			12
	A7			13
	A6			14
	A5			15
	A4			16

TSOP-1/STSOP

UT62L1024(I)

128K X 8 BIT LOW POWER CMOS SRAM

Vcc

A15

CE2

WE

A13

A8

A9

A11

OE

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

32 OE

31 A10

30 CE1

29 I/O8

28 I/O7

27 I/O6

26 I/O5

25 I/O4

24 Vss

23 I/O3

22 I/O2

21 I/O1

20 A0

19 A1

18 A2

17 A3

A	A0	A1	CE2	A3	A6	A8
B	I/O5	A2	WE	A4	A7	I/O1
C	I/O6		NC	A5		I/O2
D	Vss					Vcc
E	Vcc					Vss
F	I/O7		NC	NC		I/O3
G	I/O8	OE	CE1	A16	A15	I/O4
H	A9	A10	A11	A12	A13	A14
	1	2	3	4	5	6
			TFBGA

PIN DESCRIPTION

SYMBOL							DESCRIPTION
	A0 - A16						Address Inputs
I/O1 - I/O8							Data Inputs/Outputs
							Chip enable 1,2 Inputs
	CE1 ,CE2
							Write Enable Input
		WE
							Output Enable Input
			OE
		VCC					Power Supply
		VSS					Ground
			NC				No Connection

UTRON TECHNOLOGY INC.

P80078

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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UTRON			UT62L1024(I)
Preliminary Rev. 0.1		128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER		SYMBOL	RATING	UNIT
Terminal Voltage with Respect to Vss		VTERM	-0.5 to Vcc+0.5	V
Operating Temperature	Industrial	TA	-40 to +85
Storage Temperature		TSTG	-65 to +150
Power Dissipation		PD	1	W
DC Output Current		IOUT	50	mA
Soldering Temperature (under 10 sec)		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

I/O OPERATION

SUPPLY CURRENT

CE1

OE

WE

Standby

H

X

X

X

High - Z

ISB,ISB1

Standby

X

L

X

X

High -Z

ISB,ISB1

Output Disable

L

H

H

H

High - Z

ICC, ICC1

Read

L

H

L

H

DOUT

ICC, ICC1

Write

L

H

X

L

DIN

ICC, ICC1,

Note: H = VIH, L=VIL, X = Don't care.

UTRON TECHNOLOGY INC.

P80078

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON

UT62L1024(I)

Preliminary Rev. 0.1

128K X 8 BIT LOW POWER CMOS SRAM

DC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = -40 ~+85 )

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2.0

-

VCC+0.5

V

Input Low Voltage

VIL

- 0.5

-

0.6

V

Input Leakage Current

IIL

VSS VIN VCC

- 1

-

1

µA

VSS VI/O VCC

Output Leakage Current

IOL

or

- 1

-

1

µA

CE1 =VIH or CE2 = VIL

= VIH or

= VIL

OE

WE

Output High Voltage

VOH

IOH = - 1mA

2.0

-

-

V

Output Low Voltage

VOL

IOL= 2.1mA

-

-

0.4

V

ICC

Cycle time = Min.,100% Duty,

55

-

30

40

mA

70

-

20

30

mA

Average Operating

CE1 =VIL, CE2 = VIH,II/O=0mA

Power Supply Courrent

ICC1

Cycle time = 1µs, 100% Duty,

-

-

5

mA

. CE1 0.2V,CE2 VCC-0.2V, II/O

= 0mA

ISB

-

-

1.0

mA

CE1 =VIH or CE2 = VIL

TA = -40

~+85

-

-

50

Standby Power

CE1 VCC-0.2V

- L

µA

TA=+50

-

-

10

Supply Current

ISB1

or .CE2 0.2V

-

~+85

-

-

10

TA = -40

µA

LL

TA=+50

-

-

3

CAPACITANCE (TA=25 , f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

Input Capacitance

CIN

-

6

pF

Input/Output Capacitance

CI/O

-

8

pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0.4V to 2.2V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL=30pF, IOH/IOL=-1mA/2.1mA

UTRON TECHNOLOGY INC.

P80078

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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UTRON				UT62L1024(I)
Preliminary Rev. 0.1		128K X 8 BIT LOW POWER CMOS SRAM
AC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V , TA = -40 ~+85 )
(1) READ CYCLE
PARAMETER	SYMBOL	UT62L1024-55		UT62L1024-70			UNIT
		MIN.	MAX.	MIN.		MAX.
Read Cycle Time	tRC	55	-	70		-	ns
Address Access Time	tAA	-	55	-		70	ns
Chip Enable Access Time	tACE1, tACE2	-	55	-		70	ns
Output Enable Access Time	tOE	-	30	-		35	ns
Chip Enable to Output in Low-Z	tCLZ1*, tCLZ2*	10	-	10		-	ns
Output Enable to Output in Low-Z	tOLZ*	5	-	5		-	ns
Chip Disable to Output in High-Z	tCHZ1*, tCHZ2*	-	30	-		35	ns
Output Disable to Output in High-Z	tOHZ*	-	30	-		35	ns
Output Hold from Address Change	tOH	5	-	5		-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT62L1024-55		UT62L1024-70			UNIT
		MIN.	MAX.	MIN.		MAX.
Write Cycle Time	tWC	55	-	70		-	ns
Address Valid to End of Write	tAW	50	-	60		-	ns
Chip Enable to End of Write	tCW1, tCW2	50	-	60		-	ns
Address Set-up Time	tAS	0	-	0		-	ns
Write Pulse Width	tWP	40	-	45		-	ns
Write Recovery Time	tWR	0	-	0		-	ns
Data to Write Time Overlap	tDW	25	-	30		-	ns
Data Hold from End of Write-Time	tDH	0	-	0		-	ns
Output Active from End of Write	tOW*	5	-	5		-	ns
Write to Output in High-Z	tWHZ*	-	20	-		25	ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80078

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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