UTRON UT611024JC-10, UT611024LS-15, UT611024LS-12, UT611024LS-10, UT611024LC-12 Datasheet

UTRON

Rev. 1.5

FEATURES

Fast access time : 10/12/15ns (max.)

Low operating power consumption:

100 mA (typical.)

Single5V power supply

All inputs and outputs are TTL compatible

Fully static operation

Three state outputs

Package : 32-pin 288 mil skinny PDIP

32-pin 300 mil SOJ

32-pin 8mm×20mm TSOP-1

32-pin 8mm×13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

A4

A5

A6

.

VCC

A7

MEMORY ARRAY

A8

.

ROW

A12

1024ROWS × 1024COLUMNS

DECODER

.

VSS

A13

A14

A15

A16

. . .

I/O1

.

.

I/O

COLUMN I/O

.

CONTROL

I/O8

.

COLUMN DECODER

CE1

CE2

LOGIC

A11 A10 A9 A3 A2 A1 A0

CONTROL

WE

OE

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A16

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

,CE2

Chip Enable Inputs

CE1

Write Enable Input

WE

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

NC

No Connection

UT611024

128K X 8 BIT HIGH SPEED CMOS SRAM

GENERAL DESCRIPTION

The UT611024 is a 1,048,576-bit high speed CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT611024 is designed for high-speed system application. It is particularly suited for use in high speed and high density system applications.

The UT611024 operates from a signal 5V power supply and all inputs and outputs are fully TTL compatible

PIN CONFIGURATION

			NC		1		32			Vcc
			A16				31			A15
					2
										CE2
			A14		3		30
			A12				29
					4	UT611024					WE
										A13
			A7		5		28
			A6		6		27				A8
											A9
			A5		7		26
			A4				25			A11
					8
			A3
					9		24				OE
			A2				23		A10
					10
			A1		11		22			CE1
										I/O8
			A0		12		21
			I/O1		13		20			I/O7
										I/O6
			I/O2		14		19
			I/O3				18			I/O5
					15
			Vss				17			I/O4
					16
					PDIP / SOJ
A11
			1					32										OE
A9			2					31										A10
A8			3					30									CE 1
																		I/O8
A13			4					29
																		I/O7
WE			5					28
CE2			6					27										I/O6
A15			7	UT611024				26										I/O5
Vcc			8					25										I/O4
NC			9					24										Vss
																		I/O3
A16			10					23
																		I/O2
A14			11					22
																		I/O1
A12			12					21
A7			13					20										A0
A6			14					19										A1
A5			15					18										A2
A4			16					17										A3

STSOP / TSOP-1

UTRON TECHNOLOGY INC.

P80048

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

	UTRON			UT611024
Rev. 1.5		128K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER		SYMBOL	RATING		UNIT
Terminal Voltage with Respect to VSS		VTERM	-0.5 to + 7.0		V
Operating Temperature		TA	0 to +70
Storage Temperature		TSTG	-65 to +150
Power Dissipation		PD	1		W
DC Output Current		IOUT	50		mA
Soldering Temperature (under 10 sec)		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

I/O OPERATION

SUPPLY CURRENT

CE1

OE

WE

Standby

H

X

X

X

High - Z

ISB, ISB1

Standby

X

L

X

X

High - Z

ISB, ISB1

Output Disable

L

H

H

H

High - Z

ICC

Read

L

H

L

H

DOUT

ICC

Write

L

H

X

L

DIN

ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V± 10%, TA = 0 to 70 )

PARAMETER

SYMBOL

TEST CONDITION

MIN.

MAX.

UNIT

Input High Voltage

VIH

2.2

VCC+0.5

V

Input Low Voltage

VIL

-0.5

0.8

V

Input Leakage Current

ILI

VSS

VIN VCC

- 1

1

µA

Output Leakage

ILO

V

V

V

=V

or CE2=V

- 1

1

µA

CC, CE1

Current

SS

I/O

IH

IL

or OE =VIH or WE = VIL

Output High Voltage

VOH

IOH= - 4mA

2.4

-

V

Output Low Voltage

VOL

IOL= 8mA

-

0.4

V

Operating Power

ICC

Cycle time =Min., II/O = 0mA ,

- 10

-

180

mA

Supply Current

= VIL ,CE2= VIH

- 12

-

160

mA

CE1

- 15

-

140

mA

Standby Power

ISB

=VIH or CE2=VIL

-

30

mA

CE1

Supply Current

VIN VIH or VIN VIL

ISB1

VCC-0.2V or CE2 0.2V

-

5

mA

CE1

VIN VCC-0.2V or VIN 0.2V

Notes : VIL = -3.0V for pulse width less than 10ns.

UTRON TECHNOLOGY INC.

P80048

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

UTRON										UT611024
Rev. 1.5		128K X 8 BIT HIGH SPEED CMOS SRAM
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER	SYMBOL			MIN.				MAX				UNIT
Input Capacitance	CIN			-				8				pF
Input/Output Capacitance	CI/O			-				10				pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels				0V to 3.0V
Input Rise and Fall Times				3ns
Input and Output Timing Reference Levels				1.5V
Output Load				CL = 30pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS		(VCC = 5V± 10%, TA = 0 to 70 )
(1) READ CYCLE
PARAMETER	SYMBOL	UT611024-10			UT611024-12				UT611024-15				UNIT
		MIN.		MAX.	MIN.			MAX.	MIN.			MAX.
Read Cycle Time	tRC	10		-		12		-		15		-		ns
Address Access Time	tAA	-		10		-		12		-		15		ns
Chip Enable Access Time	tACE1, tACE2	-		10		-		12		-		15		ns
Output Enable Access Time	tOE	-		5		-		6		-		7		ns
Chip Enable to Output in Low Z	tCLZ1*, tCLZ2*	2		-		3		-		4		-		ns
Output Enable to Output in Low Z	tOLZ*	0		-		0		-		0		-		ns
Chip Disable to Output in High Z	tCHZ*1,tCHZ*2	-		5		-		6		-		7		ns
Output Disable to Output in High Z	tOHZ*	-		5		-		6		-		7		ns
Output Hold from Address Change	tOH	3		-		3		-		3		-		ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT611024-10			UT611024-12				UT611024-15				UNIT
		MIN.		MAX.	MIN.			MAX.	MIN.			MAX.
Write Cycle Time	tWC	10		-		12		-		15		-		ns
Address Valid to End of Write	tAW	8		-		10		-		12		-		ns
Chip Enable to End of Write	tCW1, tCW2	8		-		10		-		12		-		ns
Address Set-up Time	tAS	0		-		0		-		0		-		ns
Write Pulse Width	tWP	8		-		9		-		10		-		ns
Write Recovery Time	tWR	0		-		0		-		0		-		ns
Data to Write Time Overlap	tDW	6		-		7		-		8		-		ns
Data Hold from End of Write Time	tDH	0		-		0		-		0		-		ns
Output Active from End of Write	tOW*	2		-		3		-		4		-		ns
Write to Output in High Z	tWHZ*	-		6		-		7		-		8		ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80048

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON	UT611024
Rev. 1.5	128K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
	tRC
Address

tAA

	tOH				tOH
DOUT				Data Valid
READ CYCLE 2 ( CE1 CE2 and			OE Controlled) (1,3,5,6)
			t RC
Address
			t AA
CE1			t ACE1
CE2			t ACE2
OE				t CHZ1
			t OE
	t CLZ1			t	CHZ2
				t OHZ
	t CLZ2
		t OLZ		t OH
Dout	HIGH-Z				HIGH-Z

Data Valid

Notes :

1.WE is HIGH for read cycle.

2. Device is continuously selected CE1 =VIL and CE2=VIH.

3.Address must be valid prior to or coincident with CE1 and CE2 transition; otherwise tAA is the limiting parameter.

4.OE is low.

5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ±500mV from steady state. 6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.

UTRON TECHNOLOGY INC.

P80048

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

4