UTRON UT62L2568LS-70LLL, UT62L2568LS-70LLE, UT62L2568LS-70LE, UT62L2568LS-70L, UT62L2568LS-55LLL Datasheet

	UTRON	UT62L2568
Preliminary Rev. 0.1		256K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Access time:55ns(max) for Vcc=3.0V~3.6V 70/100ns(max) for Vcc=2.7V~3.6V

CMOS Low operating power Operating : 45/35/25mA (Icc max) Standby : 20µA (TYP.) L-version

3µA (TYP.) LL-version Single 2.7V~3.6V power supply Operating Temperature:

Commercial : 0 ~70

Extended : -20 ~80

All inputs and outputs TTL compatible Fully static operation

Three state outputs

Data retention voltage : 1.5V (min) Package : 32 pin 8mm×20 mm TSOP-I

32 pin 8mm×13.4mm STSOP

36 pin 6mm×8mmTFBGA

FUNCTIONAL BLOCK DIAGRAM

A0

A1

A2

A3

.

MEMORY ARRAY

A4

VCC

ROW

A8

. 2048 ROWS × 128 COLUMNS × 8bits

A13

DECODER

A14

.

VSS

A15

A16

A17

.

. .

I/O1

.

I/O

.

COLUMN I/O

.

.

CONTROL

I/O8

COLUMN DECODER

CE1

LOGIC

CE2

CONTROL

A9 A10

A12 A5 A6

A7

WE

A11

OE

GENERAL DESCRIPTION

The UT62L2568 is a 2,097,152-bit high speed CMOS static random access memory organized as 262,144 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT62L2568 is designed for high speed system applications. It is particularly well suited for battery back-up nonvolatile memory applications.

The UT62L2568 operates from a single 2.7V~3.6V power supply and all inputs and outputs are fully TTL compatible.

PIN DESCRIPTION

		SYMBOL				DESCRIPTION
A0 - A17						Address Inputs
I/O1 - I/O8						Data Inputs/Outputs
					,CE2	Chip Enable 1,2 Input
	CE1
						Write Enable Input
		WE
						Output Enable Input
		OE
Vcc						Power Supply
Vss						Ground
NC						No Connection

UTRON TECHNOLOGY INC.

P80059

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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		UTRON							UT62L2568
Preliminary Rev. 0.1					256K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
A11	1		32	OE	A	A0	A1	CE2	A3	A6	A8
A9	2		31	A10	B
A8	3		30	CE1		I/O5	A2		A4	A7	I/O1
A13	4		29	I/O8
WE	5		28	I/O7	C	I/O6		NC	A5		I/O2
CE2	6		27	I/O6
A15	7	UT62L2568	26	I/O5	D	Vss					Vcc
Vcc	8		25	I/O4
A17	9		24	Vss	E	Vcc					Vss
A16	10		23	I/O3
A14	11		22	I/O2	F	I/O7		NC	A17		I/O3
A12	12		21	I/O1
A7	13		20	A0	G
A6	14		19	A1		I/O8			A16	A15	I/O4
A5	15		18	A2	H
A4	16		17	A3		A9	A10	A11	A12	A13	A14
		TSOP-1/STSOP
						1	2	3	4	5	6
								TFBGA

TRUTH TABLE

MODE

CE2

I/O OPERATION

SUPPLY CURRENT

CE1

OE

WE

Standby

H

X

X

X

High - Z

ISB,ISB1

Standby

X

L

X

X

High -Z

ISB,ISB1

Output Disable

L

H

H

H

High - Z

ICC

Read

L

H

L

H

DOUT

ICC

Write

L

H

X

L

DIN

ICC

Note: H = VIH, L=VIL, X = Don't care.

UTRON TECHNOLOGY INC.

P80059

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

UTRON			UT62L2568
Preliminary Rev. 0.1		256K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER		SYMBOL	RATING	UNIT
Terminal Voltage with Respect to VSS		VTERM	-0.5 to 4.6	V
Operating Temperature	Commercial	TA	0 to 70
	Extended	TA	-20 to 80
Storage Temperature		TSTG	-65 to 150
Power Dissipation		PD	1	W
DC Output Current		IOUT	50	mA
Soldering Temperature (under 10 secs)		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA =0 to 70 / -20 to 80 (E))

PARAMETER	SYMBOL			TEST CONDITION				MIN.	TYP.	MAX.	UNIT
Power Voltage	Vcc							2.7	3.0	3.6	V
Input High Voltage	VIH							2.0	-	Vcc+0.3	V
Input Low Voltage	VIL							- 0.2	-	0.6	V
Input Leakage Current	ILI	VSS VIN VCC						- 1	-	1	µA
Output Leakage Current	ILO	VSS VI/O VCC, Output Disabled						- 1	-	1	µA
Output High Voltage	VOH	IOH= - 1mA						2.2	-	-	V
Output Low Voltage	VOL	IOL= 2mA						-	-	0.4	V
Operating Power	ICC	Cycle time=Min.100% duty,					55	-	30	45	mA
Supply Current							70	-	25	35	mA
			CE1 =VIL, CE2 = VIH, II/O =0mA ,
							100	-	20	25	mA
	Icc1	Cycle time = 1µs,100% duty,						-	4	5	mA
				CE1 0.2V,CE2 VCC-0.2V,
		II/O=0mA,
		other pins at 0.2V or Vcc-0.2V,
	Icc2	Cycle time =500ns,100% duty,						-	8	10	mA
			CE1 0.2V,CE2 VCC-0.2V,
		II/O=0mA,
		other pins at 0.2V or Vcc-0.2V,
Standby Current(TTL)	ISB1							-	0.3	0.5	mA
				CE1 =VIH or CE2 = VIL
Standby Current(CMOS)	ISB1			CE1 VCC-0.2V or CE2 0.2V,			-L	-	20	80	µA
		other pins at 0.2V or Vcc-0.2V,					-LL	-	3	25	µA

UTRON TECHNOLOGY INC.

P80059

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

	UTRON			UT62L2568
	Preliminary Rev. 0.1	256K X 8 BIT LOW POWER CMOS SRAM
	CAPACITANCE (TA=25	, f=1.0MHz)
	PARAMETER	SYMBOL	MIN.	MAX	UNIT
	Input Capacitance	CIN	-	6	pF
	Input/Output Capacitance	CI/O	-	8	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL = 30pF, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA =0 to 70 / -20 to 80 (E))

(1) READ CYCLE

PARAMETER	SYMBOL	UT62L2568-55*		UT62L2568-70		UT62L2568-100		UNIT
		MIN.	MAX.	MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC	55	-	70	-	100	-	ns
Address Access Time	tAA	-	55	-	70	-	100	ns
Chip Enable Access Time	tACE1, tACE2	-	55	-	70	-	100	ns
Output Enable Access Time	tOE	-	30	-	35	-	50	ns
Chip Enable to Output in Low Z	tCLZ1*, tCLZ2*	10	-	10	-	10	-	ns
Output Enable to Output in Low Z	tOLZ*	5	-	5	-	5	-	ns
Chip Disable to Output in High Z	tCHZ1*, tCHZ2*	-	20	-	25	-	30	ns
Output Disable to Output in High Z	tOHZ*	-	20	-	25	-	35	ns
Output Hold from Address Change	tOH	5	-	5	-	5	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT62L2568-55*		UT62L2568-70		UT62L2568-100		UNIT
		MIN.	MAX.	MIN.	MAX.	MIN.	MAX.
Write Cycle Time	tWC	55	-	70	-	100	-	ns
Address Valid to End of Write	tAW	50	-	60	-	80	-	ns
Chip Enable to End of Write	tCW1, tCW2	50	-	60	-	80	-	ns
Address Set-up Time	tAS	0	-	0	-	0	-	ns
Write Pulse Width	tWP	45	-	55	-	70	-	ns
Write Recovery Time	tWR	0	-	0	-	0	-	ns
Data to Write Time Overlap	tDW	25	-	30	-	40	-	ns
Data Hold from End of Write Time	tDH	0	-	0	-	0	-	ns
Output Active from End of Write	tOW*	5	-	5	-	5	-	ns
Write to Output in High Z	tWHZ*	-	30	-	30	-	40	ns

*These parameters are guaranteed by device characterization, but not production tested. *55ns for Vcc=3.0V~3.6V

UTRON TECHNOLOGY INC.

P80059

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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