UTRON UT62V5128LS-70LLI, UT62V5128LS-70LI, UT62V5128LS-100LLI, UT62V5128LS-100LI, UT62V5128LC-70LLI Datasheet

UTRON	UT62V5128(I)
Rev. 1.0	512K X 8 BIT LOW POWER CMOS SRAM
FEATURES	GENERAL DESCRIPTION

Access time : 70/100ns(max)

CMOS Low operating power Operating : 30/20mA (Icc max) Standby : 20µA (TYP.) L-version

2µA (TYP.) LL-version

Single 2.3V~2.7V power supply

Operating Temperature: Industrial : -40 ~85

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 1.5V (min)

Package : 32-pin 8mm×20mm TSOP-I

32-pin 8mm×13.4mm STSOP

The UT62V5128(I) is a 4,194,304-bit high speed CMOS static random access memory organized as 524,288 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT62V5128(I) is designed for high speed system applications. It is particularly well suited for battery back-up nonvolatile memory applications.

The UT62V5128(I) operates from a single 2.3V~2.7V power supply and all inputs and outputs are fully TTL compatible.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

A0

A11

A1

1

32

OE

A9

2

31

A10

A2

A8

3

30

CE

A3

.

A13

4

29

I/O8

MEMORY ARRAY

WE

5

28

I/O7

A4

VCC

A17

6

27

I/O6

A8

ROW

.

2048 ROWS × 256 COLUMNS × 8bits

A15

7

UT62V5128

26

I/O5

A13

DECODER

VSS

Vcc

8

25

I/O4

A14

.

A18

9

24

Vss

A16

10

23

I/O3

A15

A14

11

22

I/O2

A16

A12

12

21

I/O1

A7

13

20

A0

A17

. . .

A6

14

19

A1

A5

15

18

A2

I/O1

A4

16

17

A3

.

I/O

.

COLUMN I/O

.

.

CONTROL

I/O8

COLUMN DECODER

TSOP-1 / STSOP

CE

LOGIC

WE

CONTROL

A18A12 A11

A10

A9

A7 A6 A5

OE

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A18

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

CE

Write Enable Input

WE

Output Enable Input

OE

Vcc

Power Supply

Vss

Ground

NC

No Connection

UTRON TECHNOLOGY INC.

P80068

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone]

FAX: [phone]

1

	UTRON							UT62V5128(I)
	Rev. 1.0					512K X 8 BIT LOW POWER CMOS SRAM
	TRUTH TABLE
	MODE							I/O OPERATION	SUPPLY CURRENT
		WE		CE		OE
	Standby	X		H		X		High – Z	ISB, ISB1
	Output Disable	H		L		H		High – Z	ICC,ICC1,ICC2
	Read	H		L		L		DOUT	ICC,ICC1,ICC2
	Write	L		L		X		DIN	ICC,ICC1,ICC2

Note: H = VIH, L=VIL, X = Don't care.

ABSOLUTE MAXIMUM RATINGS*

PARAMETER		SYMBOL	RATING	UNIT
Terminal Voltage with Respect to VSS		VTERM	-0.5 to 3.6	V
Operating Temperature	Industrial	TA	-20 to 85
Storage Temperature		TSTG	-65 to 150
Power Dissipation		PD	1	W
DC Output Current		IOUT	50	mA
Soldering Temperature (under 10 secs)		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

DC ELECTRICAL CHARACTERISTICS (VCC = 2.3V~2.7V, TA =-40 to 85 (I))

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Power Voltage

Vcc

2.3

2.5

2.7

V

Input High Voltage

VIH

2.0

-

Vcc+0.3

V

Input Low Voltage

VIL

- 0.2

-

0.6

V

Input Leakage Current

ILI

VSS

VIN VCC

- 1

-

1

µA

Output Leakage Current

ILO

V

V

V

Output Disabled

- 1

-

1

µA

SS

I/O

CC,

Output High Voltage

VOH

IOH= -0.5mA

2.0

-

-

V

Output Low Voltage

VOL

IOL= 0.5mA

-

-

0.4

V

Operating Power

ICC

Cycle time=Min.100% duty,

70

-

20

30

mA

Supply Current

= VIL, II/O =0mA ,

100

-

15

20

mA

CE

Icc1

Cycle time = 1µs,100% duty,

-

3

4

mA

0.2,II/O=0mA,

CE

other pins at 0.2V or Vcc-0.2V,

Icc2

Cycle time =500ns,100% duty,

-

6

8

mA

0.2,II/O=0mA

CE

other pins at 0.2V or Vcc-0.2V,

Standby Current(TTL)

ISB1

=VIH

-

0.3

0.5

mA

CE

Standby Current(CMOS)

ISB1

CE

VCC-0.2V

-L

-

20

80

µA

other pins at 0.2V or Vcc-0.2V,

-LL

-

2

15

µA

UTRON TECHNOLOGY INC.

P80068

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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	UTRON				UT62V5128(I)
	Rev. 1.0		512K X 8 BIT LOW POWER CMOS SRAM
	CAPACITANCE	(TA=25	, f=1.0MHz)
	PARAMETER		SYMBOL	MIN.	MAX	UNIT
	Input Capacitance		CIN	-	6	pF
	Input/Output Capacitance		CI/O	-	8	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 2.2V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.2V
Output Load	CL = 30pF, IOH/IOL = -0.5mA/0.5mA

AC ELECTRICAL CHARACTERISTICS			(VCC = 2.3V~2.7V , TA = -40 to 85 (I))
(1) READ CYCLE
PARAMETER	SYMBOL		UT62V5128(I)-70		UT62V5128(I)-100		UNIT
			MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC		70	-	100	-	ns
Address Access Time	tAA		-	70	-	100	ns
Chip Enable Access Time	tACE		-	70	-	100	ns
Output Enable Access Time	tOE		-	35	-	50	ns
Chip Enable to Output in Low Z	tCLZ*		10	-	10	-	ns
Output Enable to Output in Low Z	tOLZ*		5	-	5	-	ns
Chip Disable to Output in High Z	tCHZ*		-	25	-	30	ns
Output Disable to Output in High Z	tOHZ*		-	25	-	35	ns
Output Hold from Address Change	tOH		5	-	5	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL		UT62V5128(I)-70		UT62V5128(I)-100		UNIT
			MIN.	MAX.	MIN.	MAX.
Write Cycle Time	tWC		70	-	100	-	ns
Address Valid to End of Write	tAW		60	-	80	-	ns
Chip Enable to End of Write	tCW		60	-	80	-	ns
Address Set-up Time	tAS		0	-	0	-	ns
Write Pulse Width	tWP		55	-	70	-	ns
Write Recovery Time	tWR		0	-	0	-	ns
Data to Write Time Overlap	tDW		30	-	40	-	ns
Data Hold from End of Write Time	tDH		0	-	0	-	ns
Output Active from End of Write	tOW*		5	-	5	-	ns
Write to Output in High Z	tWHZ*		-	30	-	40	ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80068

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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