UTRON UT61256SC-15, UT61256LS-8, UT61256LS-15, UT61256LS-10, UT61256LS-12 Datasheet

	UTRON	UT61256
Rev. 1.1		32K X 8 BIT HIGH SPEED CMOS SRAM

FEATURES

Fast access time : 8/10/12/15ns (max.) Low operating power consumption:

80 mA (typical.) Single5V power supply

All inputs and outputs are TTL compatible Fully static operation

Three state outputs

Package : 28-pin 300 mil skinny PDIP 28-pin 300 mil SOJ

28-pin 330 mil SOP

28-pin 8mm×13.4 mm STSOP

GENERAL DESCRIPTION

The UT61256 is a 262,144-bit high speed CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT61256 is designed for high-speed system application. It is particularly suited for use in high speed and high density system applications.

The UT61256 operates from a signal 5V power supply and all inputs and outputs are fully TTL compatible

FUNCTIONAL BLOCK DIAGRAM

A4

A3

A14

.

A13

MEMORY ARRAY

VCC

ROW

.

A12

DECODER

512ROWS × 512COLUMNS

VSS

A7

.

A6

A5

A8

. . .

I/O1

.

I/O

.

COLUMN I/O

.

CONTROL

I/O8

.

COLUMN DECODER

CE

LOGIC

WE

CONTROL

A11 A9 A10

A2

A1

A0

OE

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

CE

Write Enable Input

WE

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

PIN CONFIGURATION

						A14		1		28		Vcc
										27
						A12		2					WE
						A7		3		26		A13
						A6		4	UT61256	25					A8
						A5		5		24				A9
								6		23
						A4						A11
										22
						A3		7						OE
						A2		8		21		A10
						A1		9		20
															CE
						A0		10		19		I/O8
						I/O1		11		18		I/O7
						I/O2		12		17		I/O6
						I/O3		13		16		I/O5
						Vss		14		15		I/O4
								PDIP/SOP/SOJ
		OE				1						28
A11						2						27
		A9				3						26
		A8				4						25
A13						5						24
	WE					6						23
		Vcc				7		UT61256				22
A14						8						21
A12						9						20
		A7				10						19
		A6				11						18
		A5				12						17
		A4				13						16
		A3				14						15

STSOP

A10

CE

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

A0

A1

A2

UTRON TECHNOLOGY INC.

P80020

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

	UTRON			UT61256
Rev. 1.1		32K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER		SYMBOL	RATING		UNIT
Terminal Voltage with Respect to VSS		VTERM	-0.5 to +7.0		V
Operating Temperature		TA	0 to +70
Storage Temperature		TSTG	-65 to +150
Power Dissipation		PD	1		W
DC Output Current		IOUT	50		mA
Soldering Temperature (under 10 sec)		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE							I/O OPERATION	SUPPLY CURRENT
	CE		OE		WE
Standby	H		X		X		High - Z	ISB, ISB1
Output Disable	L		H		H		High - Z	ICC
Read	L		L		H		DOUT	ICC
Write	L		X		L		DIN	ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = 0

to 70 )

PARAMETER

SYMBOL

TEST CONDITION

MIN.

MAX.

UNIT

Input High Voltage

VIH

2.2

VCC+0.5

V

Input Low Voltage

VIL

-0.5

0.8

V

Input Leakage Current

ILI

VSS VIN VCC

- 1

1

µA

Output Leakage

ILO

VSS VI/O VCC

- 1

1

µA

Current

=VIH or

=VIH or

= VIL

CE

OE

WE

Output High Voltage

VOH

IOH= - 4mA

2.4

-

V

Output Low Voltage

VOL

IOL= 8mA

-

0.4

V

Operating Power

ICC

= VIL ,

- 8

-

190

mA

CE

Supply Current

II/O = 0mA ,Cycle=Min.

- 10

-

180

mA

- 12

-

160

mA

- 15

-

140

mA

Standby Power

ISB

=VIH

-

30

mA

CE

Supply Current

ISB1

-

5

mA

CE VCC-0.2V

UTRON TECHNOLOGY INC.

P80020

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

	UTRON					UT61256
	Rev. 1.1		32K X 8 BIT HIGH SPEED CMOS SRAM
	CAPACITANCE	(TA=25 , f=1.0MHz)
	PARAMETER		SYMBOL	MIN.	MAX	UNIT
	Input Capacitance		CIN	-	8	pF
	Input/Output Capacitance		CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	3ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL = 30pF, IOH/IOL = -4mA/8mA

AC ELECTRICAL CHARACTERISTICS				(VCC = 5V±10%, TA = 0 to 70 )
(1) READ CYCLE
PARAMETER	SYMBOL		UT61256-8			UT61256-10		UT61256-12		UT61256-15		UNIT
			MIN.		MAX.	MIN.	MAX.	MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC	8			-	10	-	12	-	15	-	ns
Address Access Time	tAA	-			8	-	10	-	12	-	15	ns
Chip Enable Access Time	tACE	-			8	-	10	-	12	-	15	ns
Output Enable Access Time	tOE	-			4	-	5	-	6	-	7	ns
Chip Enable to Output in Low Z	tCLZ*	2			-	2	-	3	-	4	-	ns
Output Enable to Output in Low Z	tOLZ*	0			-	0	-	0	-	0	-	ns
Chip Disable to Output in High Z	tCHZ*	-			4	-	5	-	6	-	7	ns
Output Disable to Output in High Z	tOHZ*	-			4	-	5	-	6	-	7	ns
Output Hold from Address Change	tOH	3			-	3	-	3	-	3	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL		UT61256-8			UT61256-10 UT61256-12 UT61256-15 UNIT
			MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time	tWC		8	-		10	-	12	-	15	-	ns
Address Valid to End of Write	tAW		6.5	-		8	-	12	-	15	-	ns
Chip Enable to End of Write	tCW		6.5	-		8	-	12	-	15	-	ns
Address Set-up Time	tAS		0	-		0	-	0	-	0	-	ns
Write Pulse Width	tWP		6.5	-		8	-	9	-	10	-	ns
Write Recovery Time	tWR		0	-		0	-	0	-	0	-	ns
Data to Write Time Overlap	tDW		5	-		6	-	7	-	8	-	ns
Data Hold from End of Write Time	tDH		0	-		0	-	0	-	0	-	ns
Output Active from End of Write	tOW*		1.5	-		2	-	3	-	4	-	ns
Write to Output in High Z	tWHZ*		-	5		-	6	-	7	-	8	ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80020

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON

UT61256

Rev. 1.1

32K X 8 BIT HIGH SPEED CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

	tAA
	tOH	tOH
DOUT		Data Valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
	tRC
Address
	tAA
CE
	tACE
OE
	tOE	tCHZ
	tCLZ	tOHZ
DOUT	tOLZ	tOH
	High-z	High-Z
		Data valid

Notes :

1.WE is HIGH for read cycle.

2.Device is continuously selected CE =VIL.

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4.OE is LOW.

5.	tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
	±
6.	At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.

UTRON TECHNOLOGY INC.

P80020

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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