UTRON UT62L25716BS-55LLI, UT62L25716BS-55LI, UT62L25716BS-70LLI, UT62L25716BS-70LI Datasheet

UTRON	UT62L25716(I)
Rev. 1.0	256K X 16 BIT LOW POWER CMOS SRAM
FEATURES	GENERAL DESCRIPTION

High speed access time :

55ns(max) for Vcc=3.0V~3.6V 70/100 ns(max) for Vcc=2.7V~3.6V

CMOS Low power consumption

Operation current : 45/35/25 (Icc,max.)

Standby: 20uA (TYP.) L-version

3uA (TYP.) LL-version

Single 2.7V~3.6V power supply

Operation temperature: Industrial : -40 ~85

All inputs and outputs are TTL compatible

Fully static operation

Three state outputs

Data retention voltage:1.5V (min.)

The UT62L25716(I) is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits.

The UT62L25716(I) operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible.

The UT62L25716(I) is designed for low power system applications. It is particularly well suited for use in high-density low power system applications.

PIN DESCRIPTION

Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16)

Package : 48-pin 6mm × 8mm TFBGA

FUNCTIONAL BLOCK DIAGRAM

A0

A1

A2

.

A3

MEMORY ARRAY

A4

ROW

.

A8

DECODER

2048 Rows x 128 Columns x 16 bits

A13

.

A14

A15

A16

.

.

.

A17

.

I/O1

I/O

. .

CONTROL

.

COLUMN I/O

.

I/O16

CE1

COLUMN DECODER

CE2

LOGIC

WE

CONTROL

OE

LB

A12 A11

A10 A9

A7

A6

A5

UB

	SYMBOL			DESCRIPTION
	A0 - A17			Address Inputs
	I/O1 - I/O16			Data Inputs/Outputs
	CE1 , CE2			Chip Enable Input
	WE			Write Enable Input
	OE			Output Enable Input
	LB			Lower-Byte Control
	UB			High-Byte Control
VCC	Vcc			Power Supply
	Vss			Ground
VSS	NC			No Connection
PIN CONFIGURATION
A	LB	OE	A0	A1	A2	CE2
B	I/O9	UB	A3	A4	CE 1	I/O1
C	I/O10	I/O11	A5	A6	I/O2	I/O3
D	Vss	I/O12	A17	A7	I/O4	Vcc
E	Vcc	I/O13	NC	A16	I/O5	Vss
F	I/O15	I/O14	A14	A15	I/O6	I/O7
G	I/O16	NC	A12	A13	WE	I/O8
H	NC	A8	A9	A10	A11	NC

1

2

3

4

5

6

TFBGA

UTRON TECHNOLOGY INC.

P80046

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

UTRON				UT62L25716(I)
Rev. 1.0			256K X 16 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER			SYMBOL	RATING	UNIT
Terminal Voltage with Respect to VSS			VTERM	-0.3 to 4.6	V
Operating Temperature		Industrial	TA	-40 to 85
Storage Temperature			TSTG	-65 to 150
Power Dissipation			PD	1.0~1.5	W
DC Output Current			IOUT	20	mA
Soldering Temperature (under 10 secs)			Tsolder	260.10	.sec

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

I/O1-I/O8

I/O9-I/O16

SUPPLY CURRENT

CE1

OE

WE

LB

UB

Standby

H

X

X

X

X

X

High – Z

High – Z

ISB, ISB1

X

L

X

X

X

X

High – Z

High – Z

ISB, ISB1

X

X

X

X

H

H

High – Z

High – Z

ISB, ISB1

Output

L

H

H

H

L

X

High – Z

High – Z

ICC1,ICC2

Disable

L

H

H

H

X

L

High – Z

High – Z

Read

L

H

L

H

L

H

DOUT

High – Z

ICC1,ICC2

L

H

L

H

H

L

High – Z

DOUT

L

H

L

H

L

L

DOUT

DOUT

Write

L

H

X

L

L

H

DIN

High – Z

ICC1,ICC2

L

H

X

L

H

L

High – Z

DIN

L

H

X

L

L

L

DIN

DIN

Note: H = VIH, L=VIL, X = Don't care.(Must be low or high state)

DC ELECTRICAL CHARACTERISTICS (Vcc = 2.7V~3.6V, TA = -40 to 85 (I))

PARAMETER	SYMBOL						TEST CONDITION				MIN.	TYP.	MAX.	UNIT
Power Voltage	Vcc										2.7	3.0	3.6	V
Input High Voltage	VIH										2.0	-	Vcc+0.3	V
Input Low Voltage	VIL										- 0.2	-	0.6	V
Input Leakage Current	ILI		VSS VIN Vcc								- 1	-	1	µA
Output Leakage Current	ILO		VSS VI/O Vcc, Output Disabled								- 1	-	1	µA
Output High Voltage	VOH		IOH= - 1.0mA								2.2	-	-	V
Output Low Voltage	VOL		IOL= 2.1mA								-	-	0.4	V
Operating Power	ICC		Cycle time =min,100% duty, II/O=0mA,							55	-	30	45	mA
Supply Current			CE2=VIH,						=VIL, VIN=VIH or VIL,	70	-	25	35	mA
								CE1
										100	-	20	25	mA
	Icc1		Cycle time = 1us,100% duty, II/O=0mA,								-	4	5	mA
							0.2V, CE2 Vcc-0.2V
					CE1
			other pins at 0.2V or Vcc-0.2V,
	Icc2		Cycle time =500ns,100% duty, II/O=0mA,								-	8	10	mA
				CE1			0.2V, CE2 Vcc-0.2V
			other pins at 0.2V or Vcc-0.2V,
Standby Current	ISB						=VIH,or CE2=VIH,other pins =VIH or VIL,				-	0.3	0.5	mA
				CE1
Standby Current	ISB1		CE1			VCC-0.2V,or CE2 0.2V,				-L	-	20	80	µA
		other pins at 0.2V or Vcc-0.2V,								-LL	-	3	25	µA

UTRON TECHNOLOGY INC.

P80046

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

	UTRON				UT62L25716(I)
	Rev. 1.0			256K X 16 BIT LOW POWER CMOS SRAM
	CAPACITANCE	(TA=25	, f=1.0MHz)
	PARAMETER		SYMBOL	MIN.	MAX	UNIT
	Input Capacitance		CIN	-	6	pF
	Input/Output Capacitance		CI/O	-	8	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

				Input Pulse Levels								0V to 3.0V
				Input Rise and Fall Times								5ns
				Input and Output Timing Reference Levels								1.5V
				Output Load								CL = 30pF, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V , TA = -40 to 85 (I))
(1) READ CYCLE
						PARAMETER	SYMBOL		UT62L25716(I)-55*			UT62L25716(I)-70		UT62L25716(I)-100			UNIT
									MIN.	MAX.		MIN.	MAX.	MIN.		MAX.
		Read Cycle Time					tRC	55		-		70	-	100	-		ns
		Address Access Time					tAA	-		55		-	70	-	100		ns
		Chip Enable Access Time					tACE	-		55		-	70	-	100		ns
		Output Enable Access Time					tOE	-		30		-	35	-	50		ns
		Chip Enable to Output in Low Z					tCLZ*	10		-		10	-	10	-		ns
		Output Enable to Output in Low Z					tOLZ*	5		-		5	-	5	-		ns
		Chip Disable to Output in High Z					tCHZ*	-		20		-	25	-	30		ns
		Output Disable to Output in High Z					t	-		20		-	25	-	30		ns
							OHZ*
		Output Hold from Address Change					t	5		-		5	-	5	-		ns
							OH
			,			Access Time	tBA	-		55		-	70	-	100		ns
		LB			UB
				,		to High-Z Output	tHZB	-		25		-	30	0	40		ns
	LB				UB
			,			to Low-Z Output	tLZB	0		-		0	-	0	-		ns
		LB			UB
(2) WRITE CYCLE
		PARAMETER					SYMBOL		UT62L25716(I)-55*			UT62L25716(I)-70		UT62L25716(I)-100			UNIT
									MIN.	MAX.		MIN.	MAX.	MIN.		MAX.
		Write Cycle Time					tWC		55	-		70	-	100		-	ns
		Address Valid to End of Write					tAW		50	-		60	-	80		-	ns
		Chip Enable to End of Write					tCW		50	-		60	-	80		-	ns
		Address Set-up Time					tAS		0	-		0	-	0		-	ns
		Write Pulse Width					tWP		45	-		55	-	70		-	ns
		Write Recovery Time					tWR		0	-		0	-	0		-	ns
		Data to Write Time Overlap					tDW		25	-		30	-	40		-	ns
		Data Hold from End of Write Time					tDH		0	-		0	-	0		-	ns
		Output Active from End of Write					tOW*		5	-		5	-	5		-	ns
		Write to Output in High Z					tWHZ*		-	30		-	30	-		40	ns
			,			Valid to End of Write	tPWB		45	-		60	-	80		-	ns
		LB			UB

*These parameters are guaranteed by device characterization, but not production tested.

*55ns for 3.0V~3.6V.

UTRON TECHNOLOGY INC.

P80046

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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