UTRON UT62256CPC-70LLE, UT62256CPC-70LE, UT62256CPC-70E, UT62256CLS-70LLE, UT62256CLS-70LE Datasheet

UTRON

Rev. 1.0

FEATURES

Access time : 35/70ns (max.) Low power consumption: Operating : 40/30 mA (typical.) Standby : 2uA (typ.) L-version

1uA (typ.) LL-version Single 5V power supply

Extended temperature : -20 ~80

All inputs and outputs are TTL compatible Fully static operation

Three state outputs

Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8mmx13.4mm STSOP

UT62256C(E)

32K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION

The UT62256C(E) is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT62256C(E) is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT62256C(E) operates from a single

5V

power supply and all inputs and outputs are fully TTL compatible

FUNCTIONAL BLOCK DIAGRAM

A3

A4

.

A5

MEMORY ARRAY

VCC

A6

ROW

.

A7

DECODER

512ROWS × 512COLUMNS

VSS

A8

.

A12

A13

A14

. . .

I/O1

.

.

I/O

COLUMN I/O

.

CONTROL

I/O8

.

COLUMN DECODER

CE

LOGIC

WE

CONTROL

A11 A10 A9 A2

A1

A0

OE

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

CE

Write Enable Input

WE

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

PIN CONFIGURATION

A14		1	28		Vcc
			27
A12		2				WE
A7		3	26		A13
A6		4	25			A8

					A5		5	UT62256C	24			A9
					A4		6		23		A11
									22
					A3		7					OE
					A2		8		21		A10
					A1		9		20
													CE
					A0		10		19		I/O8
					I/O1		11		18		I/O7
					I/O2		12		17		I/O6
					I/O3		13		16		I/O5
					Vss		14		15		I/O4
							PDIP/SOP
																	A10
	OE				1					28
A11					2					27								CE
	A9				3					26							I/O8
	A8				4					25							I/O7
A13					5					24							I/O6
WE					6					23							I/O5
	Vcc				7	UT62256C				22							I/O4
A14					8					21							Vss
A12					9					20							I/O3
	A7				10					19							I/O2
	A6				11					18							I/O1
	A5				12					17								A0
	A4				13					16								A1
	A3				14					15								A2

STSOP

UTRON TECHNOLOGY INC.

P80071

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

UTRON		UT62256C(E)
Rev. 1.0	32K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER	SYMBOL	RATING	UNIT
Terminal Voltage with Respect to VSS	VTERM	-0.5 to +7.0	V
Operating Temperature	TA	0 to +70
Storage Temperature	TSTG	-65 to +150
Power Dissipation	PD	1	W
DC Output Current	IOUT	50	mA
Soldering Temperature (under 10 secs)	Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE							I/O OPERATION	SUPPLY CURRENT
	CE		OE		WE
Standby	H		X		X		High - Z	ISB, ISB1
Output Disable	L		H		H		High - Z	ICC, ICC1, ICC2
Read	L		L		H		DOUT	ICC, ICC1, ICC2
Write	L		X		L		DIN	ICC, ICC1, ICC2

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = -20

~80

)

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2.2

-

VCC+0.5

V

Input Low Voltage

VIL

- 0.5

-

0.8

V

Input Leakage Current

ILI

VSS VIN VCC

- 1

-

1

µA

Output Leakage

ILO

VSS VI/O VCC

- 1

-

1

µA

Current

=VIH or

= VIH or

= VIL

CE

OE

WE

Output High Voltage

VOH

IOH= - 1mA

2.4

-

-

V

Output Low Voltage

VOL

IOL= 4mA

-

-

0.4

V

Operating Power

ICC

Cycle time=Min

- 35

-

40

50

mA

Supply Current

= VIL ,II/O = 0mA ,.

- 70

-

30

40

mA

CE

ICC1

Cycle time=1µs,

=0.2V; II/O=0mA,

-

-

10

mA

CE

other pins at 0.2V or VCC-0.2V

ICC2

Cycle time=500ns,

=0.2V;II/O=0mA,

-

-

20

mA

CE

other pins at 0.2V or VCC-0.2V

Standby Current(TTL)

ISB

=VIH

-

-

3

mA

CE

Standby Current(CMOS)

ISB1

CE

VCC-0.2V

-L

-

2

100

µA

-LL

-

1

50

µA

UTRON TECHNOLOGY INC.

P80071

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

UTRON				UT62256C(E)
Rev. 1.0		32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE	(TA=25 , f=1.0MHz)
PARAMETER		SYMBOL	MIN.	MAX	UNIT
Input Capacitance		CIN	-	8	pF
Input/Output Capacitance		CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS		(VCC = 5V±10% , TA = -20 ~80 )
(1) READ CYCLE
PARAMETER	SYMBOL		UT62256C(E)-35		UT62256C(E)-70		UNIT
			MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC		35	-	70	-	ns
Address Access Time	tAA		-	35	-	70	ns
Chip Enable Access Time	tACE		-	35	-	70	ns
Output Enable Access Time	tOE		-	25	-	35	ns
Chip Enable to Output in Low Z	tCLZ*		10	-	10	-	ns
Output Enable to Output in Low Z	tOLZ*		5	-	5	-	ns
Chip Disable to Output in High Z	tCHZ*		-	25	-	35	ns
Output Disable to Output in High Z	tOHZ*		-	25	-	35	ns
Output Hold from Address Change	tOH		5	-	5	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL		UT62256C(E)-35		UT62256C(E)-70		UNIT
			MIN.	MAX.	MIN.	MAX.
Write Cycle Time	tWC	35		-	70	-	ns
Address Valid to End of Write	tAW	30		-	60	-	ns
Chip Enable to End of Write	tCW	30		-	60	-	ns
Address Set-up Time	tAS	0		-	0	-	ns
Write Pulse Width	tWP	25		-	50	-	ns
Write Recovery Time	tWR	0		-	0	-	ns
Data to Write Time Overlap	tDW	20		-	30	-	ns
Data Hold from End of Write Time	tDH	0		-	0	-	ns
Output Active from End of Write	tOW*	5		-	5	-	ns
Write to Output in High Z	tWHZ*	-		15	-	25	ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80071

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON

UT62256C(E)

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

	tAA
	tOH	tOH
DOUT		Data Valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
	tRC
Address
	tAA
CE
	tACE
OE
	tOE	tCHZ
	tCLZ	tOHZ
DOUT	tOLZ	tOH
	High-z	High-Z
		Data valid

Notes :

1.WE is HIGH for read cycle.

2.Device is continuously selected CE =VIL.

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4.OE is LOW.

5.	tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured	500mV from steady state.
		±
6.	At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.

UTRON TECHNOLOGY INC.

P80071

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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