UTRON UT62256CSC-35, UT62256CPC-70LL, UT62256CPC-70L, UT62256CPC-70, UT62256CLS-70LL Datasheet

	UTRON	UT62256C
Rev. 1.0		32K X 8 BIT LOW POWER CMOS SRAM
FEATURES		GENERAL DESCRIPTION

Access time : 35/70ns (max.) Low power consumption: Operating : 40/30 mA (typical.) Standby : 3mA (typical) normal

2uA (typical) L-version 1uA (typical) LL-version

Single 5V power supply

All inputs and outputs are TTL compatible Fully static operation

Three state outputs

Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8mmx13.4mm STSOP

The UT62256C is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT62256C is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT62256C operates from a single 5V power supply and all inputs and outputs are fully TTL compatible

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

A4

A14

A3

A12

A14

.

A7

A6

A13

VCC

ROW

.

MEMORY ARRAY

A5

A12

DECODER

512ROWS × 512COLUMNS

A4

VSS

A7

.

A3

A6

A2

A5

A1

A0

A8

I/O1

. . .

I/O2

I/O1

I/O3

.

I/O

.

COLUMN I/O

Vss

.

CONTROL

I/O8

.

COLUMN DECODER

CE

LOGIC

OE

1

WE

CONTROL

A10 A9 A11

A2

A1

A0

A11

2

A9

3

OE

A8

4

PIN DESCRIPTION

A13

5

WE

6

Vcc

7

SYMBOL

DESCRIPTION

A14

8

A0 - A14

Address Inputs

A12

9

I/O1 - I/O8

Data Inputs/Outputs

A7

10

Chip Enable Input

A6

11

CE

A5

12

WE

Write Enable Input

A4

13

A3

14

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

	1		28
	2		27
			26
	3
		UT62256C	25
	4
	5		24
	6		23
			22
	7
	8		21
	9		20
	10		19
	11		18
	12		17
			16
	13
	14		15

PDIP/SOP

UT62256C

STSOP

Vcc
	WE
A13
	A8
	A9
A11
	OE
A10
	CE
I/O8
I/O7
I/O6
I/O5
I/O4
28						A10
27
							CE
26						I/O8
25						I/O7
24						I/O6
23						I/O5
22						I/O4
21						Vss
20						I/O3
19						I/O2
18						I/O1
17							A0
16							A1
15							A2

____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

	UTRON			UT62256C
Rev. 1.0		32K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
	PARAMETER		SYMBOL	RATING	UNIT
	Terminal Voltage with Respect to VSS		VTERM	-0.5 to +7.0	V
	Operating Temperature		TA	0 to +70
	Storage Temperature		TSTG	-65 to +150
	Power Dissipation		PD	1	W
	DC Output Current		IOUT	50	mA
	Soldering Temperature (under 10 sec0		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE							I/O OPERATION	SUPPLY CURRENT
	CE		OE		WE
Standby	H		X		X		High - Z	ISB, ISB1
Output Disable	L		H		H		High - Z	ICC
Read	L		L		H		DOUT	ICC
Write	L		X		L		DIN	ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = 0

to 70

)

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2.2

-

VCC+0.5

V

Input Low Voltage

VIL

- 0.5

-

0.8

V

Input Leakage Curren

ILI

VSS VIN VCC

- 1

-

1

µA

Output Leakage

ILO

VSS VI/O VCC

- 1

-

1

µA

Current

=VIH or

= VIH

CE

OE

or

= VIL

WE

Output High Voltage

VOH

IOH= - 1mA

2.4

-

-

V

Output Low Voltage

VOL

IOL= 4mA

-

-

0.4

V

Operating Power

ICC

= VIL ,

- 35

-

40

50

mA

CE

Supply Current

II/O = 0mA ,Cycle=Min.

- 70

-

30

40

mA

ICC1

= 0.2V; I

= 0mA

Tcycle

-

-

20

mA

CE

I/O

=500ns

other pins at 0.2V or

ICC2

VCC-0.2V

Tcycle

-

-

10

mA

=1ms

Standby Power

ISB

=VIH

normal

-

1

10

mA

CE

Supply Current

ISB1

0.3

5

mA

CE VCC-0.2V

ISB

=VIH

-L/-LL

-

-

3

mA

CE

ISB1

VCC-0.2V

-L

-

2

100

µA

CE

-LL

-

1

50

µA

____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

	UTRON				UT62256C
	Rev. 1.0		32K X 8 BIT LOW POWER CMOS SRAM
	CAPACITANCE	(TA=25 , f=1.0MHz)
	PARAMETER		SYMBOL	MIN.	MAX	UNIT
	Input Capacitance		CIN	-	8	pF
	Input/Output Capacitance		CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS		(VCC = 5V±10% , TA = 0 to 70 )
(1) READ CYCLE
PARAMETER	SYMBOL	UT62256C-35		UT62256C-70		UNIT
		MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC	35	-	70	-	ns
Address Access Time	tAA	-	35	-	70	ns
Chip Enable Access Time	tACE	-	35	-	70	ns
Output Enable Access Time	tOE	-	25	-	35	ns
Chip Enable to Output in Low Z	tCLZ*	10	-	10	-	ns
Output Enable to Output in Low Z	tOLZ*	5	-	5	-	ns
Chip Disable to Output in High Z	tCHZ*	-	25	-	35	ns
Output Disable to Output in High Z	tOHZ*	-	25	-	35	ns
Output Hold from Address Change	tOH	5	-	5	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT62256C-35		UT62256C-70		UNIT
		MIN.	MAX.	MIN.	MAX.
Write Cycle Time	tWC	35	-	70	-	ns
Address Valid to End of Write	tAW	30	-	60	-	ns
Chip Enable to End of Write	tCW	30	-	60	-	ns
Address Set-up Time	tAS	0	-	0	-	ns
Write Pulse Width	tWP	25	-	50	-	ns
Write Recovery Time	tWR	0	-	0	-	ns
Data to Write Time Overlap	tDW	20	-	30	-	ns
Data Hold from End of Write Time	tDH	0	-	0	-	ns
Output Active from End of Write	tOW*	5	-	5	-	ns
Write to Output in High Z	tWHZ*	-	15	-	25	ns

*These parameters are guaranteed by device characterization, but not production tested.

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON	UT62256C
Rev. 1.0	32K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

	tAA
tOH	tOH
DOUT	Data Valid

READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)

tRC

Address

	tAA
CE
	tACE
OE
	tOE
	tCLZ
DOUT	tOLZ
	High-z

Notes :

1.WE is HIGH for read cycle.

2.Device is continuously selected CE =VIL.

tCHZ

tOHZ

tOH

High-Z

Data valid

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4.OE is LOW.

5.	tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
	±
6.	At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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