UTRON UT61256CLS-8, UT61256CLS-15, UT61256CLS-12, UT61256CLS-10, UT61256CJC-15 Datasheet

UTRON

Rev. 1.2

FEATURES

Fast access time : 8/10/12/15 ns (max.) Low operating power consumption :

80 mA (typical)

Single 5V power supply

All inputs and outputs TTL compatible Fully static operation

Three state outputs

Package : 28-pin 300 mil SOJ

28-pin 8mm×13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

32K × 8

A0-A14 DECODER MEMORY ARRAY

Vcc

Vss

	I/O1-I/O8	I/O DATA	COLUMN I/O
		CIRCUIT

	CE			CONTROL
OE
				CIRCUIT
	WE

PIN DESCRIPTION

SYMBOL						DESCRIPTION
A0 - A14						Address Inputs
I/O1 - I/O8						Data Inputs/Outputs
						Chip Enable Input
	CE
						Write Enable Input
		WE
						Output Enable Input
		OE
VCC						Power Supply
VSS						Ground

UT61256C

32K X 8 BIT HIGH SPEED CMOS SRAM

The UT61256C is a 262,144-bit high-speed CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT61256C is designed for high-speed system applications. It is particularly suited for use in high-density high-speed system applications.

The UT61256C operates from a single 5V power supply and all inputs and outputs are fully TTL compatible.

PIN CONFIGURATION

			A14			1		28			Vcc
			A12			2		27			WE
				A7		3		26			A13
							UT61256C
											A8
				A6		4		25
											I/O8
				A0		10
				A5		5		24			A9
						6		23			A11
				A4
				A3		7		22			OE
				A2		8		21			A10
				A1		9		20			CE
								19
								18			I/O7
			I/O1			11
			I/O2			12		17			I/O6
			I/O3			13		16			I/O5
			Vss			14	SOJ	15			I/O4
	OE			1						28				A10
A11				2						27					CE
	A9			3						26				I/O8
	A8			4						25				I/O7
A13				5						24				I/O6
				6						23
WE														I/O5
Vcc				7		UT61256C				22				I/O4
A14				8						21				Vss
A12				9						20				I/O3
	A7			10						19				I/O2
	A6			11						18				I/O1
	A5			12						17					A0
	A4			13						16					A1
	A3			14						15					A2

STSOP

GENERAL DESCRIPTION

UTRON TECHNOLOGY INC.

P80031

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

UTRON			UT61256C
Rev. 1.2	32K X 8 BIT HIGH SPEED CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER	SYMBOL	RATING		UNIT
Terminal Voltage with Respect to Vss	VTERM	-0.5 to +6.5		V
Operating Temperature	TA	0 to +70
Storage Temperature	TSTG	-65 to +150
Power Dissipation	PD	1		W
DC Output Current	IOUT	50		mA
Soldering Temperature (under 10 sec)	Tsolder	260

*Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE										I/O OPERATION	SUPPLY CURRENT
		CE			OE			WE
Standby		H			X			X		High - Z	ISB,ISB1
Output Disable		L			H			H		High - Z	ICC
Read		L			L			H		DOUT	ICC
Write		L			X			L		DIN	ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V± 10%, TA = 0 to 70 )

PARAMETER

SYMBOL

TEST CONDITION

MIN.

MAX.

UNIT

Input High Voltage

VIH

2.2

VCC+0.5

V

Input Low Voltage

VIL

- 0.5

0.8

V

Input Leakage Current

ILI

VSS VIN VCC

- 1

1

µA

Output Leakage Current

ILO

VSS VI/O VCC

- 1

1

µA

CE =VIH or OE =VIH or WE =VIL

Output High Voltage

VOH

IOH = - 4mA

2.4

-

V

Output Low Voltage

VOL

IOL = 8mA

-

0.4

V

Cycle time=Min.

- 8

-

190

mA

Operating Power

ICC

- 10

-

180

mA

Supply Current

CE = VIL , II/O = 0mA

- 12

-

160

mA

- 15

-

140

mA

Standby Current (TTL)

ISB

= VIH

-

30

mA

CE

Standby Current (CMOS)

ISB1

VCC-0.2V

-

5

mA

CE

UTRON TECHNOLOGY INC.

P80031

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

UTRON			UT61256C
Rev. 1.2	32K X 8 BIT HIGH SPEED CMOS SRAM
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER	SYMBOL	MIN.	MAX.	UNIT
Input Capacitance	CIN	-	8	pF
Input/Output Capacitance	CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	3ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL=30pF, IOH/IOL=-4mA/8mA

AC ELECTRICAL CHARACTERISTICS (VCC = 5V± 10% , TA = 0 to 70 )

(1) READ CYCLE

PARAMETER	SYMBOL	UT61256C					UT61256C			UT61256C				UT61256C				UNIT
			-8					-10			-12				-15
		MIN.			MAX.		MIN.		MAX.	MIN.			MAX.	MIN.			MAX.
Read Cycle Time	tRC	8			-		10		-	12			-	15			-	ns
Address Access Time	tAA	-			8		-		10	-			12	-			15	ns
Chip Enable Access Time	tACE	-			8		-		10	-			12	-			15	ns
Output Enable Access Time	tOE	-			4		-		5	-			6	-			7	ns
Chip Enable to Output in Low Z	tCLZ*	2			-		2		-	3			-	4			-	ns
Output Enable to Output in Low Z	tOLZ*	0			-		0		-	0			-	0			-	ns
Chip Disable to Output in High Z	tCHZ*	-			4		-		5	-			6	-			7	ns
Output Disable to Output in High Z	tOHZ*	-			4		-		5	-			6	-			7	ns
Output Hold from Address Change	tOH	3			-		3		-	3			-	3			-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT61256C					UT61256C			UT61256C				UT61256C				UNIT
			-8					-10			-12				-15
		MIN.		MAX.		MIN.			MAX.	MIN.			MAX.	MIN.			MAX.
Write Cycle Time	tWC	8		-			10		-	12			-	15			-	ns
Address Valid to End of Write	tAW	6.5		-			8		-	10			-	12			-	ns
Chip Enable to End of Write	tCW	6.5		-			8		-	10			-	12			-	ns
Address Set-up Time	tAS	0		-			0		-	0			-	0			-	ns
Write Pulse Width	tWP	6.5		-			8		-	9			-	10			-	ns
Write Recovery Time	tWR	0		-			0		-	0			-	0			-	ns
Data to Write Time Overlap	tDW	5		-			6		-	7			-	8			-	ns
Data Hold from End of Write Time	tDH	0		-			0		-	0			-	0			-	ns
Output Active from End of Write	tOW*	1.5		-			2		-	3			-	4			-	ns
Write to Output in High Z	tWHZ*	5					-		6	-			7	-			8	ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON TECHNOLOGY INC.

P80031

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3