UTRON UT62256BSC-35LI, UT62256BPC-70LLI, UT62256BPC-70LI, UT62256BLS-70LLI, UT62256BLS-70LI Datasheet

		UTRON	UT62256B(I)
Rev. 1.1		32K X 8 BIT LOW POWER (6T) CMOS SRAM

FEATURES

Access time : 35/70ns (max.) Low power consumption: Operating : 45/30 mA (max.) Standby :

1uA (typical) L-version 0.5uA (typical) LL-version

Single 5V power supply

All inputs and outputs are TTL compatible Fully static operation

Three state outputs

Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

28-pin 8x13.4mm STSOP Temperature: Industrial: -40 ~85

GENERAL DESCRIPTION

The UT62256B(I) is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology with 6T cell. its standby current is stable within the range of operating temperature.

The UT62256B(I) is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT62256B(I) operates from a single 5V power supply and all inputs and outputs are fully TTL compatible

FUNCTIONAL BLOCK DIAGRAM

A4

A3

A14

.

A13

MEMORY ARRAY

VCC

ROW

.

A12

DECODER

512ROWS × 512COLUMNS

VSS

A7

.

A6

A5

A8

. . .

I/O1

.

I/O

.

COLUMN I/O

.

CONTROL

I/O8

.

COLUMN DECODER

CE

LOGIC

WE

CONTROL

A10 A9 A11

A2

A1

A0

OE

PIN

DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

CE

Write Enable Input

WE

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

PIN CONFIGURATION

						A14		1		28		Vcc
										27
						A12		2					WE
						A7		3	UT62256B(I)	26		A13
						A6				18					A8
								11
								4		25
						A5		5		24				A9
								6		23
						A4						A11
										22
						A3		7						OE
						A2		8		21		A10
						A1		9		20
															CE
						A0		10		19		I/O8
						I/O1				17		I/O7
						I/O2		12				I/O6
						I/O3		13		16		I/O5
						Vss		14		15		I/O4
								PDIP/SOP
		OE				1						28
A11						2						27
		A9				3						26
		A8				4						25
A13						5						24
	WE					6						23
		Vcc				7	UT62256B(I)					22
A14						8						21
A12						9						20
		A7				10						19
		A6				11						18
		A5				12						17
		A4				13						16
		A3				14						15

STSOP

A10

CE

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

A0

A1

A2

____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80026

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

1

Rev. 1.1

UTRON

UT62256B(I)

32K X 8 BIT LOW POWER (6T) CMOS SRAM

ABSOLUTE MAXIMUM RATINGS*

PARAMETER	SYMBOL	RATING	UNIT
Terminal Voltage with Respect to VSS	VTERM	-0.5 to +7.0	V
Operating Temperature	TA	-40 to +85
Storage Temperature	TSTG	-65 to +150
Power Dissipation	PD	1	W
DC Output Current	IOUT	50	mA
Soldering Temperature (under 10 sec0	Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE							I/O OPERATION	SUPPLY CURRENT
	CE		OE		WE
Standby	H		X		X		High - Z	ISB, ISB1
Output Disable	L		H		H		High - Z	ICC
Read	L		L		H		DOUT	ICC
Write	L		X		L		DIN	ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = -40 to 85 )

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2.2

-

VCC+0.5

V

Input Low Voltage

VIL

- 0.5

-

0.8

V

Input Leakage Curren

ILI

VSS VIN VCC

- 1

-

1

µA

Output Leakage

ILO

VSS VI/O VCC

- 1

-

1

µA

Current

=VIH or

= VIH

CE

OE

or

= VIL

WE

Output High Voltage

VOH

IOH= - 1mA

2.4

-

-

V

Output Low Voltage

VOL

IOL= 4mA

-

-

0.4

V

Operating Power

ICC

= VIL ,

- 35

-

-

45

mA

CE

Supply Current

II/O = 0mA ,Cycle=Min.

- 70

-

-

30

mA

ICC1

= 0.2V; I

= 0mA

Tcycle

-

-

20

mA

CE

I/O

=500ns

other pins at 0.2V or

ICC2

VCC-0.2V

Tcycle

-

-

10

mA

=1ms

Standby Power

ISB

=VIH

-

3

mA

CE

Supply Current

ISB1

-L

-

1

40

µA

CE VCC-0.2V

-LL

0.5

5

µA

____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80026

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

2

	UTRON				UT62256B(I)
	Rev. 1.1		32K X 8 BIT LOW POWER (6T) CMOS SRAM
	CAPACITANCE (TA=25		, f=1.0MHz)
	PARAMETER		SYMBOL	MIN.	MAX	UNIT
	Input Capacitance		CIN	-	8	pF
	Input/Output Capacitance		CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS		(VCC = 5V±10% , TA = -40 to 85 )
(1) READ CYCLE
PARAMETER	SYMBOL	UT62256BI-35		UT62256BI-70		UNIT
		MIN.	MAX.	MIN.	MAX.
Read Cycle Time	tRC	35	-	70	-	ns
Address Access Time	tAA	-	35	-	70	ns
Chip Enable Access Time	tACE	-	35	-	70	ns
Output Enable Access Time	tOE	-	25	-	35	ns
Chip Enable to Output in Low Z	tCLZ*	10	-	10	-	ns
Output Enable to Output in Low Z	tOLZ*	5	-	5	-	ns
Chip Disable to Output in High Z	tCHZ*	-	25	-	35	ns
Output Disable to Output in High Z	tOHZ*	-	25	-	35	ns
Output Hold from Address Change	tOH	5	-	5	-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT62256BI-35		UT62256BI-70		UNIT
		MIN.	MAX.	MIN.	MAX.
Write Cycle Time	tWC	35	-	70	-	ns
Address Valid to End of Write	tAW	30	-	60	-	ns
Chip Enable to End of Write	tCW	30	-	60	-	ns
Address Set-up Time	tAS	0	-	0	-	ns
Write Pulse Width	tWP	25	-	50	-	ns
Write Recovery Time	tWR	0	-	0	-	ns
Data to Write Time Overlap	tDW	20	-	30	-	ns
Data Hold from End of Write Time	tDH	0	-	0	-	ns
Output Active from End of Write	tOW*	5	-	5	-	ns
Write to Output in High Z	tWHZ*	-	15	-	25	ns

*These parameters are guaranteed by device characterization, but not production tested.

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80026

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

3

UTRON

UT62256B(I)

Rev. 1.1

32K X 8 BIT LOW POWER (6T) CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

Address

tRC

tAA

tOH

tOH

DOUT

Data Valid

READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)

tRC

Address

	tAA
CE
	tACE
OE
	tOE
	tCLZ
DOUT	tOLZ
	High-z

Notes :

1.WE is HIGH for read cycle.

2.Device is continuously selected CE =VIL.

tCHZ

tOHZ

tOH

High-Z

Data valid

3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.

4.OE is LOW.

5.	tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
	±
6.	At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80026

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: [phone] FAX: [phone]

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