UTRON UT621024SC-70LL, UT621024SC-70L, UT621024SC-55LL, UT621024SC-55L, UT621024SC-35LL Datasheet

UTRON	UT621024
Rev. 1.5	128K X 8 BIT LOW POWER CMOS SRAM
	GENERAL DESCRIPTION

FEATURES

Access time : 35/55/70ns (max.)

Low power consumption : Operating : 60/50/40 mA (typical)

Standby : 2µA (typical) L-version

1µA (typical) LL-version

Single 5V power supply

All inputs and outputs TTL compatible

Fully static operation

Three state outputs

Data retention voltage : 2V (min.)

Package : 32-pin 600 mil PDIP

32-pin 450 mil SOP

32-pin 8mmx20mm TSOP-1

32-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

A16

A15

A13

.

VCC

A14

MEMORYARRAY

A12

.

ROW

A7

1024ROWS×1024 COLUMNS

DECODER

VSS

A6

.

A5

A4

A8

. . .

I/O1

.

.

I/O

COLUMN I/O

.

CONTROL

.

I/O8

COLUMN DECODER

CE1

LOGIC

CE2

A10

A11 A9 A3 A2 A1 A0

CONTROL

WE

OE

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A16

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

,CE2

Chip enable 1,2 Inputs

CE1

Write Enable Input

WE

Output Enable Input

OE

VCC

Power Supply

VSS

Ground

NC

No Connection

The UT621024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT621024 is designed for low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT621024 operates from a single 5V power supply and all inputs and outputs are fully TTL compatible.

PIN CONFIGURATION

			NC		1		32			Vcc
			A16				31			A15
					2
										CE2
			A14		3		30
			A12		4	UT621024	29				WE
			A7		5		28		A13
			A1		11		22		CE1
			A6		6		27				A8
											A9
			A5		7		26
										A11
			A4		8		25
			A3		9		24				OE
									A10
			A2		10		23
										I/O8
			A0		12		21
										I/O7
			I/O1		13		20
										I/O6
			I/O2		14		19
			I/O3		15		18			I/O5
			Vss		16		17			I/O4
					PDIP / SOP
A11
			1						32							OE
A9			2						31							A10
A8			3						30
																CE1
A13			4						29							I/O8
																I/O7
WE			5						28
CE2			6						27								I/O6
A15			7	UT621024					26								I/O5
Vcc			8						25								I/O4
NC			9						24								Vss
A16			10						23								I/O3
A14			11						22								I/O2
A12			12						21								I/O1
A7			13						20								A0
A6			14						19								A1
A5			15						18								A2
A4			16						17								A3

TSOP-I/STSOP

________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone] FAX: [phone]

1

UTRON			UT621024
Rev. 1.5	128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER		SYMBOL	RATING	UNIT
Terminal Voltage with Respect to Vss		VTERM	-0.5 to +7.0	V
Operating Temperature		TA	0 to +70
Storage Temperature		TSTG	-65 to +150
Power Dissipation		PD	1	W
DC Output Current		IOUT	50	mA
Soldering Temperature (under 10 sec)		Tsolder	260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

I/O OPERATION

SUPPLY CURRENT

CE1

OE

WE

Standby

H

X

X

X

High - Z

ISB,ISB1

Standby

X

L

X

X

High -Z

ISB,ISB1

Output Disable

L

H

H

H

High - Z

ICC

Read

L

H

L

H

DOUT

ICC

Write

L

H

X

L

DIN

ICC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, TA = 0

to 70 )

±

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2.2

-

VCC+0.5

V

Input Low Voltage

VIL

- 0.5

-

0.8

V

Input Leakage Current

IIL

VSS VIN VCC

- 1

-

1

µA

Output Leakage Current

IOL

VSS VI/O VCC

- 1

-

1

µA

CE1 =VIH or CE2 = VIL or

= VIH or

= VIL

OE

WE

Output High Voltage

VOH

IOH = - 1mA

2.4

-

-

V

Output Low Voltage

VOL

IOL= 4mA

-

-

0.4

V

Average Operating

ICC

Cycle time=min, 100% duty,

-35

-

60

100

mA

Power Supply Courrent

-55

-

50

85

mA

CE1 =VIL, CE2 = VIH,

II/O = 0mA

-70

-

40

70

mA

ICC1

Cycle time=1µs,100% duty,II/O=0mA

-

-

10

mA

CE1 0.2V,CE2 VCC-0.2V,

other pins at 0.2V or VCC-0.2V,

Standby Power

ISB

CE1 =VIH or CE2 = VIL

-

-

3

mA

Supply Current

other pins at 0.2V or VCC-0.2V,

ISB1

CE1 VCC-0.2V or

- L

-

2

100

µA

40*

CE2 0.2V

-

50

other pins at 0.2V or VCC-0.2V,

A

-

1

LL

15*

µ

*Those parameters are for reference only under 50

________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone] FAX: [phone]

2

UTRON	UT621024
Rev. 1.5	128K X 8 BIT LOW POWER CMOS SRAM

CAPACITANCE (TA=25 , f=1.0MHz)

PARAMETER	SYMBOL	MIN.	MAX.	UNIT
Input Capacitance	CIN	-	8	pF
Input/Output Capacitance	CI/O	-	10	pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels	0V to 3.0V
Input Rise and Fall Times	5ns
Input and Output Timing Reference Levels	1.5V
Output Load	CL=100pF, IOH/IOL=-1mA/4mA

			±	10% , TA = 0
AC ELECTRICAL CHARACTERISTICS (VCC = 5V								to 70 )
(1) READ CYCLE
PARAMETER	SYMBOL	UT621024-35		UT621024-55		UT621024-70					UNIT
		MIN.	MAX.	MIN.	MAX.	MIN.				MAX.
Read Cycle Time	tRC	35	-	55	-		70			-	ns
Address Access Time	tAA	-	35	-	55		-			70	ns
Chip Enable Access Time	tACE1, tACE2	-	35	-	55		-			70	ns
Output Enable Access Time	tOE	-	25	-	30		-			35	ns
Chip Enable to Output in Low-Z	tCLZ1*, tCLZ2*	10	-	10	-		10			-	ns
Output Enable to Output in Low-Z	tOLZ*	5	-	5	-		5			-	ns
Chip Disable to Output in High-Z	tCHZ1*, tCHZ2*	-	25	-	30		-			35	ns
Output Disable to Output in High-Z	tOHZ*	-	25	-	30		-			35	ns
Output Hold from Address Change	tOH	5	-	5	-		5			-	ns
(2) WRITE CYCLE
PARAMETER	SYMBOL	UT621024-		UT621024-55		UT621024-70					UNIT
		35
		MIN.	MAX.	MIN.	MAX.	MIN.				MAX.
Write Cycle Time	tWC	35	-	55	-		70			-	ns
Address Valid to End of Write	tAW	30	-	50	-		60			-	ns
Chip Enable to End of Write	tCW1, tCW2	30	-	50	-		60			-	ns
Address Set-up Time	tAS	0	-	0	-		0			-	ns
Write Pulse Width	tWP	25	-	40	-		45			-	ns
Write Recovery Time	tWR	0	-	0	-		0			-	ns
Data to Write Time Overlap	tDW	20	-	25	-		30			-	ns
Data Hold from End of Write-Time	tDH	0	-	0	-		0			-	ns
Output Active from End of Write	tOW*	5	-	5	-		5			-	ns
Write to Output in High-Z	tWHZ*	-	15	-	20		-			25	ns

*These parameters are guaranteed by device characterization, but not production tested.

_________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone] FAX: [phone]

3

UTRON	UT621024
Rev. 1.5	128K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2,4)

tRC

Address

	tAA
tOH	tOH
DOUT	Data Valid

READ CYCLE 2 ( CE1 , CE2 and OE Controlled) (1,3,5,6)

tRC

Address

tAA

CE1

tACE1

CE2

tACE2

OE

			tOE	tCHZ1
		tCLZ1		tCHZ2 tOHZ
		tCLZ2	tOLZ	tOH
	DOUT	High-Z			High-Z
				Data Valid

Notes :

1.WE is HIGH for read cycle.

2.Device is continuously selected CE1 =VIL and CE2=VIH.

3.Address must be valid prior to or coincident with CE1 and CE2 transition; otherwise tAA is the limiting parameter.

4.OE is low.

5.tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state.

6.At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.

_________________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80036 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: [phone] FAX: [phone]

4