Texas Instruments CD74HCT221M96, CD74HCT221M, CD74HCT221E, CD74HC221M96, CD74HC221M Datasheet

CD74HC221,

/
j

[ /Title
(CD74
HC221
,
CD74
HCT22

1)
Sub­ect

(High
Speed
CMOS
Logic
Dual
Monos
table
Multi-

Data sheet acquired from Harris Semiconductor
SCHS166A

November 1997 - Revised April 1999

Features

• Overriding RESET Terminates Output Pulse

• Triggering from the Leading or Trailing Edge

• Q and

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on B Inputs

• Fanout (Over Temperature Range)

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

• HC Types

• HCT Types

Q Buffered Outputs

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

Logic ICs

- 2V to 6V Operation

- High Noise Immunity: N
at VCC = 5V

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

Dual Monostable Multivibrator with Reset

C to 125oC

CC

OH

CD74HCT221

High Speed CMOS Logic

Description

The CD74HC221, and CH74HCT221 are dual monostable
multivibrators with reset. An external resistor (R
external capacitor (C
for the circuit. Adjustment of R
range of output pulse widths from the Q and
Pulse triggering on the B input occurs at a particular voltage
level and is not related to the rise and fall time of the trigger
pulse.

Once triggered, the outputs are independent of further trigger
inputs on
LOW level on the Reset (
and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
the IC is reset. If either Mono is not used each input (on the
unused device) must be terminated either high or low.

The minimum value of external resistance, R
The minimum value of external capacitance, C
calculation for the pulse width is t

A and B. The output pulse can be terminated by a

) control the timing and the accuracy

X

R) pin. Trailing Edge triggering (A)

and CXprovides a wide

X

, is typically 500Ω.

X

= 0.7 RXCX at VCC = 4.5V.

W

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC221E -55 to 125 16 Ld PDIP E16.3
CD74HCT221E -55 to 125 16 Ld PDIP E16.3
CD74HC221M -55 to 125 16 Ld SOIC M16.15
CD74HCT221M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer or die are available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

) and an

X

Q terminals.

, is 0pF. The

X

PKG.

NO.

Pinout

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

CD74HC221, CD74HCT221

(PDIP, SOIC)

TOP VIEW

1

1A
1B

2
3

1R

4

1Q

5

2Q

2C

6

X

7

2C

XRX

8

GND

1

16

V

CC

15

1C

XRX

14

1C

X

13

1Q

12

2Q

11

2R
2B

10

9

2A

File Number 1670.1

Functional Diagram

CD74HC221, CD74HCT221

1A

1B

1R

2R

2A

2B

14 15

1C

X

1

2

3

11

9

10

2C

X

67

1CX1R

MONO 1

MONO 2

2CX2R

1CXR

2CXR

X

V

CC

X

13

1Q

4

1Q

5

2Q

12

2Q

X

V

CC

X

TRUTH TABLE

INPUTS OUTPUTS

ABRQQ

HXHLH
XLHLH

L↑H

↓

HH

XXLLH

LH↑

(Note 3) (Note 3)

NOTE:
H = High Voltage Level,L = Low VoltageLevel,X = Irrelevant, ↑ = Transitionfrom Low
to High Level,↓ = Transition from High to Low Level, = One High Level Pulse,

= One Low Level Pulse

3. For this combination the reset input must be low and the following sequence must
be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9)
must be low and pin 2 (or 10) set high. Now the reset input goes from low-to-high
and the device will be triggered.

2

CD74HC221, CD74HCT221

Logic Diagram

1 (9)A2 (10)

S

QM QM

MASK

FF

B

R

S

QQ

4 (12) (13) 5

QQ

R

3 (11)

C

N

R

MAIN

FF

P

RESET

FF

V

CC

PP

R1

N

V

CC

V

CC

R

D
C

QC

MIRROR VOLTAGE

PULLDOWN

FF

QD

C

Q

C

R

OP

AMP

R4

V

CC

16

R

X

P

P

R2

N

15 (7)

RXC

14 (6)

C

8

X

C

X

GND

X

-

+

R3

+

­OP AMP

3

CD74HC221, CD74HCT221

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, tf on Inputs A and R

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Input Rise and Fall Time, tr, tf on Input B

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

4. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 180 N/A

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

4