Siemens SLA24C64-D, SLA24C64-D-3, SLA24C64-D-3-P, SLA24C64-D-P, SLA24C64-S Datasheet

Standard EEPROM ICs

SLx 24C64

64 Kbit (8192 × 8bit)

Serial CMOS-EEPROM with

I

2

C Synchronous 2-Wire Bus

Data Sheet Preliminary 1998-07-27

I

2

CBus

Purchase of Siemens I

2

C components conveys the license under the Philips I

2

C patent to use the components in

the I

2

C system p rovided the system conforms to the I

2

C specifications defined by Philips.

Edition Preliminary 1998-07-27

Published by Siemens AG,

Bereich Halbleiter, Marketing-

Kommunikation, Balanstraße 73,

81541 München

©

Siemens AG 1998.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes

and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help y ou – get in touch with your nearest sales office. B y agreement we

will take packing material back, if it is sorted. You must bear the costs of transport.

For pa cking material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-

curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

written appr oval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

SLx 24C64

Revision History: Current Version: Preliminary 1998-07-27

Previous Version: 05.98

Page

(in previous

Version)

Page

(in current

Version)

Subjects (major changes since last revision)

3 3 Text was changed to “Typical programming time 5 ms for up to

32 bytes”.

11, 12 11, 13 The erase/write cycle is finished latest after 10

8ms.

21 21 The write or erase cycle is finished latest after 10

4ms.

24 24 The line “erase/write cycle” was removed.

24 24 Chapter 8.4 “Erase and Write Characteristics” has been added.

P-DIP-8-4

P-DSO-8-3

64 Kbit (8192 × 8bit)SerialCMOS

EEPROMs, I

2

C Synchronous 2-Wire Bus

SLx 24C64

Semiconductor Group 3 Preliminary 1998-07-27

Preliminary

Features

• Data EEPROM internally organized as

8192 bytes and 256 pages × 32 bytes

• Page Protection Mode for protecting the EEPROM

against unintended data changes

(SLx 24C64.../P types only)

• Low power CMOS

•

V

CC

= 2.7 to 5.5 V operation

• Two wire serial interface bus, I

2

C-Bus compatible

• Three chip select pins to address 8 devices

• Filtered inputs for noise suppression with

Schmitt trigger

• Clock frequency up to 400 kHz

• High programming flexibility

– Internal programming voltage

– Self timed programming cycle including erase

– Byte-write and page-write programming, between

1 and 32 bytes

– Typical programming time 5 ms for up to 32 bytes

• High reliability

– Endurance 10

6

cycles

1)

– Data retention 40 years

1)

– ESD protection 4000 V on all pins

• 8 pin DIP/DSO packages

• Available for extended temperature ranges

– Industrial: − 40 °C to + 85 °C

– Automotive: − 40 °C to + 125 °C

1)

Values are temperature dependent, for further information please refer to your Siemens sales office.

SLx 24C64

Semiconductor Group 4 Preliminary 1998-07-27

Ordering Information

Other types are available on request:

– Temperature range (– 55 °C … + 150 °C)

– Package (die, wafer delivery)

– 3V types with automotive temperature range (– 40 °C … + 125 °C)

1 Pin Configuration

Figure 1

Pin Configuration (top view)

Type Ordering Code Package Temperature Voltage

SLA 24C64-D

SLA 24C64-D/P

Q67100-H3768

Q67100-H3762

P-DIP-8-4 – 40 °C … + 85 °C 4.5 V...5.5 V

SLA 24C64-S

SLA 24C64-S/P

Q67100-H3767

Q67100-H3761

P-DSO-8-3 – 40 °C … + 85 °C 4.5 V...5.5 V

SLA 24C64-D-3

SLA 24C64-D-3/P

Q67100-H3766

Q67100-H3760

P-DIP-8-4 – 40 °C … + 85 °C 2.7 V...5.5 V

SLA 24C64-S-3

SLA 24C64-S-3/P

Q67100-H3765

Q67100-H3759

P-DSO-8-3 – 40 °C … + 85 °C 2.7 V...5.5 V

SLE 24C64-D

SLE 24C64-D/P

Q67100-H3238

Q67100-H3758

P-DIP-8-4 – 40°C … + 125 °C 4.5 V...5.5 V

SLE 24C64-S

SLE 24C64-S/P

Q67100-H3239

Q67100-H3757

P-DSO-8-3 – 40°C … + 125 °C 4.5 V...5.5 V

P-DSO-8-3P-DIP-8-4

IEP02125

CC

V

CS1

18

WP

V

72

SCL63

SDA54

SS

CS2

CS0

IEP02124

CS0

5

6

7

8

4

3

2

1

V

SS

CS1

WP

CS2

SCL

SDA

CC

V

SLx 24C64

Semiconductor Group 5 Preliminary 1998-07-27

Pin Definitions and Functions

Pin Description

Serial Clock (SCL)

The SCL input is used to clock data into the device on the rising edge and to clock data

out of the device on the falling edge.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses, data or control information into the

device or to transfer data out of the device. The output is open drain, performing a wired

AND function with any number of other open drain or open collector devices. The SDA

bus requires a pull-up resistor to

V

CC

.

Chip Select (CS0, CS1, CS2)

The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven

to

V

CC

or V

SS

. These inputs allow the selection of one of eight possible devices sharing

acommonbus.

Write Protection (WP)

WP switched to

V

SS

allows normal read/write operations.

WP switched to

V

CC

protects the EEPROM against changes (hardware write protection).

Table 1

Pin No. Symbol Function

1, 2, 3 CS0, CS1, CS2 Chip select inputs

4

V

SS

Ground

5 SDA Serial bidirectional data bus

6 SCL Serial clock input

7 WP Write protection input

8

V

CC

Supply voltage

SLx 24C64

Semiconductor Group 6 Preliminary 1998-07-27

2 Description

The SLx 24C64 device is a serial electrically erasable and programmable read only

memory (EEPROM), organized as 8192 × 8 bit. The data memory is divided into

256 pages. The 32 bytes of a page can be programmed simultaneously.

The device conforms to the specification of the 2-wire serial I

2

C-Bus. Three chip select

pins allow the addressing of 8 devices on the I

2

C-Bus. Low voltage design permits

operation down to 2.7 V with low active and standby currents. All devices have a

minimum endurance of 10

6

erase/write cycles.

The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at

2.7 ... 5.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V

type (

V

CC

= 4.5 … 5.5 V) with two temperature ranges for industrial and automotive

applications and as 3 V type (

V

CC

= 2.7 … 5.5 V) for industrial applications. The

EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as

chips.

Figure 2

Block Diagram

DEC

X

EEPROM

Y DEC

Dout/ACK

SDA

SCL

IEB02525

Logic

Stop

Start/

Control

Chip Address

Logic

H.V. Pump

Programming

Control

Control

Serial

Logic

Logic

Address

Page Logic

CS0 CS1 CS2

SS

V

CC

V

WP

SLx 24C64

Semiconductor Group 7 Preliminary 1998-07-27

3 I

2

C-Bus Characteristics

AccesstotheSLx24C64deviceisgivenviatheI

2

C bus. This bidirectional bus consists

of two wires SCL and SDA for clock and data. The protocol is master/slave oriented,

where the serial EEPROM always takes the role of a slave.

Figure 3

Bus Configuration

Master Device that initiates the transfer of data and provides the clock for transmit

and receive operations.

Slave Device addressed by the master, capable of receiving and transmitting

data.

Transmitter The device using the SDA as output is defined as the transmitter. Due to

the open drain characteristic of the SDA output the device applying a low

level wins.

Receiver The device using the SDA as input is defined as the receiver.

Slave 1 Slave 2 Slave 3 Slave 4

Slave 8Slave 5 Slave 6 Slave 7

Master

V

CC

CC

V

IES02183

SCL

SDA

SLx 24C64

Semiconductor Group 8 Preliminary 1998-07-27

The conventions for the serial clock line and the bidirectional data line are shown in

figure 4.

Figure 4

I

2

C-Bus Timing Conventions for START Condition, STOP Condition, Data

Validation and Transfer of Acknowledge ACK

Standby Mode in which the bus is not busy (no serial transmission, no

programming): both clock (SCL) and data line (SDA) are in high

state. The device enters the standby mode after a STOP condition

or after a programming cycle.

START Condition High to low transition of SDA when SCL is high, preceding all

commands.

STOP Condition Low to high transition of SDA when SCL is high, terminating all

communications. A STOP condition after writing data initiates an

EEPROM programming cycle. A STOP condition after reading

data from the EEPROM initiates the standby mode.

Acknowledge A successful reception of eight data bits is indicated by the

receiver by pulling down the SDA line during the following clock

cycle of SCL (ACK). The transmitter on the other hand has to

release the SDA line after the transmission of eight data bits.

The EEPROM as the receiving device responds with an

acknowledge, when addressed. The master, on the other side,

acknowledges each data byte transmitted by the EEPROM and

can at any time end a read operation by releasing the SDAline (no

ACK) followed by a STOP condition.

Data Transfer Data must change only during low SCL state, data remains valid

on the SDA bus during high SCL state. Nine clock pulses are

required to transfer one data byte, the most significant bit (MSB)

is transmitted first.

12

8

9

1

9

ACK ACK

START Condition Data allowed STOP Condition

to Change

Acknowledge

SCL

SDA

IED02128