Loading...Siemens SLA24C01-D, SLA24C01-D-3, SLA24C01-S, SLA24C01-S-3, SLA24C02-D Datasheet
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Standard EEPROM ICs
SLx 24C01/02
1/2 Kbit (128/256 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus
Data Sheet 1998-07-27
SLx 24C01/02 |
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Revision History: |
Current Version: 1998-07-27 |
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Previous Version: |
06.97 |
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Page |
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Subjects (major changes since last revision) |
(in previous |
(in current |
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Version) |
Version) |
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3 |
3 |
Text was changed to “Typical programming time 5 ms for up to 8 bytes”. |
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5 |
5 |
WP = VCC protects the upper half entire memory. |
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15 |
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Figure 11: second command byte is a CSR and not CSW. |
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4, 5 |
4, 5 |
CS0, CS1 and CS2 were replaced by n.c. |
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5 |
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The paragraph “Chip Select (CS0, CS1, CS2)” was removed |
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completely. |
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11, 12 |
11, 12 |
The erase/write cycle is finished latest after 10 8 ms. |
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19 |
19 |
“Capacitive load …” were added. |
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20 |
20 |
Some timings were changed. |
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20 |
20 |
The line “erase/write cycle” was removed. |
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20 |
20 |
Chapter 7.4 “Erase and Write Characteristics” has been added. |
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I2C Bus
Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
Edition 1998-07-27
Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München
© Siemens AG 1998.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
1/2 Kbit (128/256 × 8 bit) Serial CMOS |
SLx 24C01/02 |
EEPROMs, I2C Synchronous 2-Wire Bus |
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Features
•Data EEPROM internally organized as 128/256 bytes and 16/32 pages × 8 bytes
•Low power CMOS
•VCC = 2.7 to 5.5 V operation
•Two wire serial interface bus, I2C-Bus compatible
•Filtered inputs for noise suppression with Schmitt trigger
•Clock frequency up to 400 kHz
•High programming flexibility
–Internal programming voltage
–Self timed programming cycle including erase
–Byte-write and page-write programming, between 1 and 8 bytes
–Typical programming time 5 ms for up to 8 bytes
•High reliability
–Endurance 106 cycles1)
–Data retention 40 years1)
–ESD protection 4000 V on all pins
•8 pin DIP/DSO packages
•Available for extended temperature ranges
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Industrial: |
− 40 |
°C to + 85 °C |
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Automotive: |
− 40 |
°C to + 125 °C |
P-DIP-8-4
P-DSO-8-3
1) Values are temperature dependent, for further information please refer to your Siemens Sales office.
Semiconductor Group |
3 |
1998-07-27 |
SLx 24C01/02
Ordering Information
Type |
Ordering Code |
Package |
Temperature |
Voltage |
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SLA 24C01-D |
Q67100-H3543 |
P-DIP-8-4 |
– 40 °C … + 85 °C |
4.5 |
V...5.5 V |
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SLA 24C01-S |
Q67100-H3218 |
P-DSO-8-3 |
– 40 °C … + 85 °C |
4.5 |
V...5.5 V |
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SLA 24C01-D-3 |
Q67100-H3217 |
P-DIP-8-4 |
– 40 °C … + 85 °C |
2.7 |
V...5.5 V |
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SLA 24C01-S-3 |
Q67100-H3496 |
P-DSO-8-3 |
– 40 °C … + 85 °C |
2.7 |
V...5.5 V |
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SLE 24C01-D |
Q67100-H3544 |
P-DIP-8-4 |
– 40°C … + 125 °C |
4.5 V...5.5 V |
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SLE 24C01-S |
Q67100-H3492 |
P-DSO-8-3 |
– 40°C … + 125 °C |
4.5 V...5.5 V |
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SLA 24C02-D |
Q67100-H3539 |
P-DIP-8-4 |
– 40 °C … + 85 °C |
4.5 |
V...5.5 V |
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SLA 24C02-S |
Q67100-H3534 |
P-DSO-8-3 |
– 40 °C … + 85 °C |
4.5 |
V...5.5 V |
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SLA 24C02-D-3 |
Q67100-H3538 |
P-DIP-8-4 |
– 40 °C … + 85 °C |
2.7 |
V...5.5 V |
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SLA 24C02-S-3 |
Q67100-H3533 |
P-DSO-8-3 |
– 40 °C … + 85 °C |
2.7 |
V...5.5 |
V |
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SLE 24C02-D |
Q67100-H3220 |
P-DIP-8-4 |
– 40°C … + 125 °C |
4.5 V...5.5 |
V |
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SLE 24C02-S |
Q67100-H3221 |
P-DSO-8-3 |
– 40°C … + 125 °C |
4.5 V...5.5 |
V |
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Other types are available on request
–Temperature range (– 55 °C … + 150 °C)
–Package (die, wafer delivery)
1 Pin Configuration
P-DIP-8-4
N.C. |
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1 |
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8 |
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VCC |
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N.C. |
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2 |
7 |
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WP |
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N.C. |
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3 |
6 |
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SCL |
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VSS |
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4 |
5 |
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SDA |
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P-DSO-8-3
N.C. |
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1 |
8 |
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VCC |
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N.C. |
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7 |
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WP |
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N.C. |
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6 |
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SCL |
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VSS |
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5 |
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SDA |
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IEP02514 |
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IEP02515
Figure 1
Pin Configuration (top view)
Semiconductor Group |
4 |
1998-07-27 |
SLx 24C01/02
Pin Definitions and Functions
Table 1
Pin No. |
Symbol |
Function |
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1, 2, 3 |
N.C. |
Not connected |
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4 |
VSS |
Ground |
5 |
SDA |
Serial bidirectional data bus |
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6 |
SCL |
Serial clock input |
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7 |
WP |
Write protection input |
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8 |
VCC |
Supply voltage |
Pin Description
Serial Clock (SCL)
The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to VCC.
Write Protection (WP)
WP switched to VSS allows normal read/write operations.
WP switched to VCC protects the entire EEPROM against changes (hardware write protection).
Semiconductor Group |
5 |
1998-07-27 |
SLx 24C01/02
2 Description
The SLx 24C01/02 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 128/256 × 8 bit. The data memory is divided into 16/ 32 pages. The 8 bytes of a page can be programmed simultaneously.
The device conforms to the specification of the 2-wire serial I2C-Bus. Low voltage design permits operation down to 2.7 V with low active and standby currents.
The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at 2.7 ... 4.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V type (VCC = 4.5 … 5.5 V) with two temperature ranges for industrial and automotive applications and as 3 V type (VCC = 2.7 … 5.5 V) for industrial applications. The EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.
V SS |
V CC |
WP |
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Chip Address |
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Programming |
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Control |
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Control |
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Logic |
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H.V. Pump |
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Start/ |
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Stop |
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Logic |
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Serial |
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SCL |
Control |
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Logic |
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SDA |
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Address |
X |
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EEPROM |
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Logic |
DEC |
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Page Logic |
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Y DEC |
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Dout/ACK |
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IEB02530 |
Figure 2
Block Diagram
Semiconductor Group |
6 |
1998-07-27 |
SLx 24C01/02
3 I2C-Bus Characteristics
The SLx 24C01/02 devices support a master/slave bidirectional bus oriented protocol in which the EEPROM always takes the role of a slave.
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VCC |
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Slave 1 |
Slave 2 |
Slave 3 |
Slave 4 |
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SCL |
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Master |
SDA |
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Slave 5 |
Slave 6 |
Slave 7 |
Slave 8 |
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VCC |
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IES02183 |
Figure 3
Bus Configuration
Master Device that initiates the transfer of data and provides the clock for both transmit and receive operations.
Slave Device addressed by the master, capable of receiving and transmitting data.
Transmitter The device with the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a low level wins.
Receiver The device with the SDA as input is defined as the receiver.
Semiconductor Group |
7 |
1998-07-27 |
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