Siemens SLA24C32-D, SLA24C32-D-3, SLA24C32-D-3-P, SLA24C32-D-P, SLA24C32-S Datasheet

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Standard EEPROM ICs

SLx 24C32

32 Kbit (4096 × 8 bit)

Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus

Data Sheet Preliminary 1998-07-27

SLx 24C32
Revision History:		Current Version: Preliminary 1998-07-27

Previous Version:		02.98, 04.98

Page	Page	Subjects (major changes since last revision)
(in previous	(in current
Version)	Version)

3	3	Text was changed to “Typical programming time 5 ms for up to
		32 bytes”.

11, 12	11, 13	The erase/write cycle is finished latest after 10 8 ms.

21	21	The write or erase cycle is finished latest after 10 4 ms.

24	24	The line “erase/write cycle” was removed.

24	24	Chapter 8.4 “Erase and Write Characteristics” has been added.

I2C Bus

Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.

Edition Preliminary 1998-07-27

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Attention please!

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For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).

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Packing

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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

32 Kbit (4096 × 8 bit) Serial CMOS	SLx 24C32
EEPROMs, I2C Synchronous 2-Wire Bus

Preliminary

Features

•Data EEPROM internally organized as 4096 bytes and 128 pages × 32 bytes

•Page Protection Mode for protecting the EEPROM against unintended data changes (SLx 24C32.../P types only)

•Low power CMOS

•VCC = 2.7 to 5.5 V operation

•Two wire serial interface bus, I2C-Bus compatible

•Three chip select pins to address 8 devices

•Filtered inputs for noise suppression with Schmitt trigger

•Clock frequency up to 400 kHz

•High programming flexibility

–Internal programming voltage

–Self timed programming cycle including erase

–Byte-write and page-write programming, between 1 and 32 bytes

–Typical programming time 5 ms for up to 32 bytes

•High reliability

–Endurance 106 cycles1)

–Data retention 40 years1)

–ESD protection 4000 V on all pins

•8 pin DIP/DSO packages

•Available for extended temperature ranges

–	Industrial:	− 40	°C to + 85 °C
–	Automotive:	− 40	°C to + 125 °C

P-DIP-8-4

P-DSO-8-3

1) Values are temperature dependent, for further information please refer to your Siemens sales office.

Semiconductor Group

Preliminary 1998-07-27

SLx 24C32

Ordering Information

Type	Ordering Code	Package	Temperature	Voltage

SLA 24C32-D	Q67100-H3746	P-DIP-8-4	– 40 °C … + 85 °C	4.5	V...5.5 V
SLA 24C32-D/P	Q67100-H3752

SLA 24C32-S	Q67100-H3748	P-DSO-8-3	– 40 °C … + 85 °C	4.5	V...5.5 V
SLA 24C32-S/P	Q67100-H3753

SLA 24C32-D-3	Q67100-H3747	P-DIP-8-4	– 40 °C … + 85 °C	2.7	V...5.5 V
SLA 24C32-D-3/P	Q67100-H3754

SLA 24C32-S-3	Q67100-H3749	P-DSO-8-3	– 40 °C … + 85 °C	2.7	V...5.5	V
SLA 24C32-S-3/P	Q67100-H3769

SLE 24C32-D	Q67100-H3235	P-DIP-8-4	– 40°C … + 125 °C	4.5 V...5.5		V
SLE 24C32-D/P	Q67100-H3755

SLE 24C32-S	Q67100-H3236	P-DSO-8-3	– 40°C … + 125 °C	4.5 V...5.5		V
SLE 24C32-S/P	Q67100-H3756

Other types are available on request:

–Temperature range (– 55 °C … + 150 °C)

–Package (die, wafer delivery)

–3V types with automotive temperature range (– 40 °C … + 125 °C)

1 Pin Configuration

P-DIP-8-4

CS0	1		8	VCC


CS1	2	7		WP


CS2	3	6		SCL


VSS	4	5		SDA

P-DSO-8-3

CS0	1	8	VCC


CS1	2	7	WP


CS2	3	6	SCL


VSS	4	5	SDA


		IEP02124

IEP02125

Figure 1

Pin Configuration (top view)

Semiconductor Group

Preliminary 1998-07-27

SLx 24C32

Pin Definitions and Functions

Table 1

Pin No.	Symbol	Function

1, 2, 3	CS0, CS1, CS2	Chip select inputs

4	VSS	Ground
5	SDA	Serial bidirectional data bus

6	SCL	Serial clock input

7	WP	Write protection input

8	VCC	Supply voltage

Pin Description

Serial Clock (SCL)

The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to VCC.

Chip Select (CS0, CS1, CS2)

The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven to VCC or VSS. These inputs allow the selection of one of eight possible devices sharing a common bus.

Write Protection (WP)

WP switched to VSS allows normal read/write operations.

WP switched to VCC protects the EEPROM against changes (hardware write protection).

Semiconductor Group

Preliminary 1998-07-27

Siemens SLA24C32-D, SLA24C32-D-3, SLA24C32-D-3-P, SLA24C32-D-P, SLA24C32-S Datasheet

SLx 24C32

2 Description

The SLx 24C32 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 4096 × 8 bit. The data memory is divided into 128 pages. The 32 bytes of a page can be programmed simultaneously.

The device conforms to the specification of the 2-wire serial I2C-Bus. Three chip select pins allow the addressing of 8 devices on the I2C-Bus. Low voltage design permits operation down to 2.7 V with low active and standby currents. All devices have a minimum endurance of 106 erase/write cycles.

The device operates at 5.0 V ± 10% with a maximum clock frequency of 400 kHz and at 2.7 ... 5.5 V with a maximum clock frequency of 100 kHz. The device is available as 5 V type (VCC = 4.5 … 5.5 V) with two temperature ranges for industrial and automotive applications and as 3 V type (VCC = 2.7 … 5.5 V) for industrial applications. The EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.

V SS

V CC

CS0 CS1 CS2 WP

	Chip Address		Programming
	Chip Address			Control
	Control			Control
	Control
	Logic			H.V. Pump
				H.V. Pump
	Start/
	Stop
	Logic
	Serial
SCL	Control
	Logic
SDA
	Address	X		EEPROM
	Logic	DEC		EEPROM
	Logic	DEC
				Page Logic
				Y DEC
				Dout/ACK
				IEB02525

Figure 2

Block Diagram

Semiconductor Group

Preliminary 1998-07-27

SLx 24C32

3 I2C-Bus Characteristics

Access to the SLx 24C32 device is given via the I2C bus. This bidirectional bus consists of two wires SCL and SDA for clock and data. The protocol is master/slave oriented, where the serial EEPROM always takes the role of a slave.

				VCC
	Slave 1	Slave 2	Slave 3	Slave 4
	SCL
Master	SDA
	Slave 5	Slave 6	Slave 7	Slave 8
				VCC
				IES02183

Figure 3

Bus Configuration

Master	Device that initiates the transfer of data and provides the clock for transmit
	and receive operations.

Slave Device addressed by the master, capable of receiving and transmitting data.

Transmitter The device using the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a low level wins.

Receiver The device using the SDA as input is defined as the receiver.

Semiconductor Group

Preliminary 1998-07-27

SLx 24C32

The conventions for the serial clock line and the bidirectional data line are shown in

figure 4.
SCL	1	2	8	9	1	9
SDA				ACK		ACK
START Condition		Data allowed		Acknowledge		STOP Condition
		to Change				IED02128

Figure 4

I2C-Bus Timing Conventions for START Condition, STOP Condition, Data

Validation and Transfer of Acknowledge ACK

Standby	Mode in which the bus is not busy (no serial transmission, no
	programming): both clock (SCL) and data line (SDA) are in high
	state. The device enters the standby mode after a STOP condition
	or after a programming cycle.
START Condition	High to low transition of SDA when SCL is high, preceding all
	commands.
STOP Condition	Low to high transition of SDA when SCL is high, terminating all
	communications. A STOP condition after writing data initiates an
	EEPROM programming cycle. A STOP condition after reading
	data from the EEPROM initiates the standby mode.

Acknowledge A successful reception of eight data bits is indicated by the receiver by pulling down the SDA line during the following clock cycle of SCL (ACK). The transmitter on the other hand has to release the SDA line after the transmission of eight data bits.

The EEPROM as the receiving device responds with an acknowledge, when addressed. The master, on the other side, acknowledges each data byte transmitted by the EEPROM and can at any time end a read operation by releasing the SDA line (no ACK) followed by a STOP condition.

Data Transfer Data must change only during low SCL state, data remains valid on the SDA bus during high SCL state. Nine clock pulses are required to transfer one data byte, the most significant bit (MSB) is transmitted first.

Semiconductor Group

Preliminary 1998-07-27

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