SGS Thomson Microelectronics TSA1005-40IF, TSA1005-20IFT, TSA1005-20IF, TSA1005, TSA1005-40IFT Datasheet

TSA1005

DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER

■10-bit, dual-channel A/D converter in deep submicron CMOS technology, 20/40Msps

■Single supply voltage: 2.5V

Independent supply for CMOS output stage with 2.5V/3.3V capability

■ENOB=9.5 @ 20Msps, ENOB=9.2 @ 40Msps, Fin=10MHz

■SFDR typically up to 62.5dB @ 40Msps, Fin=10MHz.

■1GHz analog bandwidth Track-and-Hold

■Common clocking between channels

■Multiplexed outputs

DESCRIPTION

The TSA1005 belongs to a new generation of high speed, dual-channel Analog to Digital converters, processed in a mainstream 0.25 µm CMOS technology and yielding high performances.

The TSA1005 is specifically designed for applications requiring a very low noise floor, high SFDR and good isolation between channels. It is based on a pipeline structure and digital error correction, providing high static linearity at 20/40 Msp, and Fin = 10 MHz.

For each channel, a voltage reference is integrated to simplify the design and minimize external components. It is nevertheless possible to use the circuit with external references.

Each ADC output is multiplexed on a common bus with small number of pins. A tri-state capability is available for the output signals, allowing for chip selection. The input signals of the ADC must be differentially driven.

The TSA1005 is supports an extended (0 to +85°C) temperature range, and is available in the small 48-pin TQFP package.

APPLICATIONS

■Medical imaging and ultrasound

■I/Q signal processing applications

■High speed data acquisition system

■Portable instrumentation

■High resolution fax and scanners

ORDER CODE

	Part Number	Temperature	Status	Conditioning
		Range
	TSA1005-20IF	-40°C to +85°C	Sample	Tray
	TSA1005-20IFT	-40°C to +85°C	Sample	Tape & Reel
	TSA1005I-40IF	0°C to +85°C	Production	Tray
	TSA1005-40IFT	0°C to +85°C	Production	Tape & Reel
	EVAL1005-20/BA		Evaluation board
	EVAL1005-40/BA

PIN CONNECTIONS (top view)

index

REFPI

REFMI

INCMI

AVCC

AVCC

OEB

VCCBI

VCCBI

GNDBE

VCCBE

NC

NC

corner

48

47

46

45

44

43

42

41

40

39

38

37

D0(LSB)

36

AGND

1

D1

35

INI

2

D2

AGND

3

34

INIB

4

33

D3

AGND

5

32

D4

IPOL

6

TSA1005

31

D5

AVCCB

7

30

D6

D7

AGND

8

29

INQ

D8

9

28

D9(MSB)

AGND

10

27

INBQ

11

26

VCCBE

GNDBE

AGND

12

25

13

14

15

16

17

18

19

20

21

22

23

24

REFPQ

REFMQ

INCMQ

AGND

AVCC

DVCC

DGND

CLK

SELECT

DGND

DVCC

GNDBI

BLOCK DIAGRAM

+2.5V/3.3V

CLK

SELECT

OEB

VCCBE

VINI

Timing

AD 10

10

VINBI

I channel

VINCMI

VREFPI

common mode

VREFMI

REF I

10

10

D0

M

Buffers

TO

IPOL

Polar.

U

X

D9

VREFPQ

VREFMQ

REF Q

VINCMQ

common mode

VINQ

10

AD 10

VINBQ

Q channel

GND

GNDBE

PACKAGE

7 × 7 mm TQFP48

June 2003	1/22

TSA1005

ABSOLUTE MAXIMUM RATINGS

	Symbol	Parameter	Values	Unit
	AVCC	Analog Supply voltage (1)	0 to 3.3	V
	DVCC	Digital Supply voltage 1)	0 to 3.3	V
	VCCBE	Digital buffer Supply voltage 1)	0 to 3.6	V
	VCCBI	Digital buffer Supply voltage 1)	0 to 3.3	V
	IDout	Digital output current	-100 to 100	mA
	Tstg	Storage temperature	+150	°C
	ESD	HBM: Human Body Model(2)	2	kV
		CDM: Charged Device Model(3)	1.5
	Latch-up	Class(4)	A

1All voltage values, except for differential voltage, are with respect to the network ground terminal. The magnitude of input and output voltages must not exceed -0.3 V or VCC

2ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ

3Discharge to Ground of a device that has been previously charged.

4Corporate ST Microelectronics procedure number 0018695

OPERATING CONDITIONS

Symbol	Parameter	TSA1005-20(1)				TSA1005-40
		Min.	Typ.	Max.	Min.		Typ.		Max.	Unit
AVCC	Analog Supply voltage	2.25	2.5	2.7	2.25		2.5		2.7	V
DVCC	Digital Supply voltage	2.25	2.5	2.7	2.25		2.5		2.7	V
VCCBE	External Digital buffer Supply voltage	2.25	2.5	3.5	2.25		2.5		3.5	V
VCCBI	Internal Digital buffer Supply voltage	2.25	2.5	2.7	2.25		2.5		2.7	V
VREFPI	Forced top voltage reference	0.94		1.4	0.94				1.4	V
VREFPQ
VREFMI	Forced bottom reference voltage	0		0.4	0				0.4	V
VREFMQ
INCMI	Forced input common mode voltage	0.2		1	0.2				1	V
INCMQ

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TSA1005

PIN CONNECTIONS (top view)

index corner

AGND 1

INI 2

AGND 3

INIB 4

AGND 5

IPOL 6

AVCCB 7

AGND 8

INQ 9

AGND 10

INBQ 11

AGND 12

	REFPI			REFMI		INCMI		AVCC		AVCC			OEB		VCCBI			VCCBI		GNDBE			VCCBE		NC		NC
	48			47		46		45		44			43		42			41		40			39		38		37
																																D0(LSB)
																														36
																																D1
																														35
																																D2
																														34
																																D3
																														33
																														32		D4
																														31		D5
								TSA1005
																																D6
																														30
																																D7
																														29
																														28	D8
																															D9(MSB)
																														27
																														26	VCCBE
																															GNDBE
																														25
13			14			15	16			17		18		19			20			21		22		23			24
	REFPQ			REFMQ		INCMQ		AGND		AVCC			DVCC			DGND		CLK		SELECT			DGND		DVCC		GNDBI

PIN DESCRIPTION

Pin No	Name	Description	Observation		Pin No	Name	Description	Observation
1	AGND	Analog ground	0V		25	GNDBE	Digital buffer ground	0V
2	INI	I channel analog input			26	VCCBE	Digital Buffer power supply	2.5V/3.3V
3	AGND	Analog ground	0V		27	D9(MSB)	Most Significant Bit output	CMOS output (2.5V/3.3V)
4	INBI	I channel inverted analog input			28	D8	Digital output	CMOS output (2.5V/3.3V)
5	AGND	Analog ground	0V		29	D7	Digital output	CMOS output (2.5V/3.3V)
6	IPOL	Analog bias current input			30	D6	Digital output	CMOS output (2.5V/3.3V)
7	AVCC	Analog power supply	2.5V		31	D5	Digital output	CMOS output (2.5V/3.3V)
8	AGND	Analog ground	0V		32	D4	Digital output	CMOS output (2.5V/3.3V)
9	INQ	Q channel analog input			33	D3	Digital output	CMOS output (2.5V/3.3V)
10	AGND	Analog ground	0V		34	D2	Digital output	CMOS output (2.5V/3.3V)
11	INBQ	Q channel inverted analog input			35	D1	Digital output	CMOS output (2.5V/3.3V)
12	AGND	Analog ground	0V		36	D0(LSB)	Least Significant Bit output	CMOS output (2.5V/3.3V)
13	REFPQ	Q channel top reference voltage			37	NC	Non connected
14	REFMQ	Q channel bottom reference	0V		38	NC	Non connected
		voltage
15	INCMQ	Q channel input common mode			39	VCCBE	Digital Buffer power supply	2.5V/3.3V - See Application
								Note
16	AGND	Analog ground	0V		40	GNDBE	Digital buffer ground	0V
17	AVCC	Analog power supply	2.5V		41	VCCBI	Digital Buffer power supply	2.5V
18	DVCC	Digital power supply	2.5V		42	VCCBI	Digital Power Supply	2.5V
19	DGND	Digital ground	0V		43	OEB	Output Enable input	2.5V/3.3V CMOS input
20	CLK	Clock input	2.5V CMOS input		44	AVCC	Analog power supply	2.5V
21	SELECT	Channel selection	2.5V CMOS input		45	AVCC	Analog power supply	2.5V
22	DGND	Digital ground	0V		46	INCMI	I channel input common mode
23	DVCC	Digital power supply	2.5V		47	REFMI	I channel bottom reference voltage	0V
24	GNDBI	Digital buffer ground	0V		48	REFPI	I channel top reference voltage

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TSA1005

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5 V, Fs = 20/40 Msps, Fin = 10.13 MHz, Vin@ -1 dBFS, VREFP = 0.8 V, VREFM = 0 V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

Symbol	Parameter.		TSA1005-20(1)				TSA1005-40
			Min.	Typ.	Max.	Min.		Typ.		Max.	Unit
FS	Sampling Frequency		0.5		20	0.5				40	MHz
DC	Clock Duty Cycle			50		45		50		55	%
TC1	Clock pulse width (high)			25				12.5			ns
TC2	Clock pulse width (low)			25				12.5			ns
Tod	Data Output Delay (Clock edge to Data			5				5			ns
	Valid) - 10pF load capacitance
Tpd I	Data Pipeline delay for I channel			7				7			cycles
Tpd Q	Data Pipeline delay for Q channel			7.5				7.5			cycles
Ton	Falling edge of OEB to digital output			1				1			ns
	valid data
Toff	Rising edge of OEB to digital output			1				1			ns
	tri-state
1 Preliminary data.

TIMING DIAGRAM

Simultaneous sampling
on I/Q channels		N+4	N+5	N+13
		N+3	N+6	N+12
I		N+2	N+7	N+11
N-1	N+1		N+8	N+10
N
				N+9

Q

CLK

Tpd I + Tod

Tod

SELECT

CLOCK AND SELECT CONNECTED TOGETHER

OEB

sample N-8	sample N-6	sample	N	sample N+1	sample N+2
I channel	Q channel	Q channel		Q channel	Q channel

DATA

OUTPUT

sample N-9	sample N-7	sample N+1	sample N+2	sample N+3
I channel	Q channel	I channel	I channel	I channel

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TSA1005

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V Tamb = 25°C (unless otherwise specified)

ANALOG INPUTS

Symbol	Parameter		TSA1005-20(1)				TSA1005-40
			Min.	Typ.	Max.	Min.		Typ.		Max.	Unit
VIN-VINB	Full scale reference voltage		1.1	2.0	2.8	1.1		2.0		2.8	Vpp
Cin	Input capacitance			7.0				7			pF
Req	Equivalent input resistor			3.3				1.6			KΩ
BW	Analog Input Bandwidth			1000				1000			MHz
	Vin Full scale, Fs max
ERB	Effective Resolution Bandwidth			70				70			MHz
1 Preliminary data
DIGITAL INPUTS AND OUTPUTS

Symbol		Parameter	Test conditions	Min	Typ	Max	Unit
Clock and Select inputs
VIL		Logic "0" voltage			0	0.8	V
VIH		Logic "1" voltage		2.0	2.5		V
OEB input
VIL		Logic "0" voltage			0	0.25 x	V
						VCCBE
VIH		Logic "1" voltage		0.75 x	VCCBE		V
				VCCBE
Digital Outputs
VOL		Logic "0" voltage	Iol=10µA		0	0.1 x	V
						VCCBE
VOH		Logic "1" voltage	Ioh=10µA	0.9 x	VCCBE		V
				VCCBE
IOZ		High Impedance leakage current	OEB set to VIH	-1.67	0	1.67	µA
CL		Output Load Capacitance				15	pF

REFERENCE VOLTAGE

Symbol	Parameter		TSA1005-20(1)				TSA1005-40
			Min.	Typ.	Max.	Min.		Typ.		Max.	Unit
VREFPI	Top internal reference voltage		0.81	0.88	0.94	0.81		0.88		0.94	V
VREFPQ
VINCMI	Input common mode voltage		0.41	0.46	0.50	0.41		0.46		0.50	V
VINCMQ

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TSA1005

CONDITIONS

AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V Tamb = 25°C (unless otherwise specified)

POWER CONSUMPTION

Symbol

Parameter

TSA1005-20(1)

TSA1005-40

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

ICCA

Analog Supply current

30

69.5

72.8

mA

ICCD

Digital Supply Current

4

3.5

3.6

mA

ICCBE

Digital Buffer Supply Current (10pF

6

6.5

6.9

mA

load)

ICCBI

Digital Buffer Supply Current

274

131

149

uA

Pd

Power consumption in normal opera-

100

199.5

207.7

mW

tion mode

Rthja

Thermal resistance (TQFP48)

80

80

°C/W

ACCURACY

Symbol

Parameter

TSA1005-20(1)

TSA1005-40

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

OE

Offset Error

2.97

2.97

LSB

GE

Gain Error

0.1

0.1

%

DNL

Differential Non Linearity

±0.5

±0.6

LSB

INL

Integral Non Linearity

±0.7

±1

LSB

-

Monotonicity and no missing codes

Guaranteed

Guaranteed

DYNAMIC CHARACTERISTICS

Symbol

Symbol

TSA1005-20(1)

TSA1005-40

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

SFDR

Spurious Free Dynamic Range

-73

-62.6

-58.1

dBc

SNR

Signal to Noise Ratio

60

57.1

59.8

dB

THD

Total Harmonics Distortion

-73

-62

-57.5

dBc

SINAD

Signal to Noise and Distortion Ratio

59

54.9

57.3

dB

ENOB

Effective number of bits

9.5

8.8

9.2

bits

MATCHING BETWEEN CHANNELS

Symbol

Parameter

TSA1005-20(1)

TSA1005-40

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

GM

Gain match

0.04

0.04

1

%

OM

Offset match

0.5

0.5

LSB

PHM

Phase match

1

1

dg

XTLK

Crosstalk rejection

85

85

dB

1 Preliminary data

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TSA1005

Static parameter: Integral Non Linearity

Fs=20MSPS; Icca=30mA; Fin=10MHz
	1
	0.8
	0.6
(LSBs)	0.4
	0.2
	0
INL	-0.2
	-0.4
	-0.6
	-0.8
	-1
	0	200	400	600	800	1000

Output Code

Static parameter: Integral Non Linearity

Fs=40MSPS; Icca=45mA; Fin=10MHz
	2
	1.5
(LSBs)	1
	0.5
	0
INL	-0.5
	-1
	-1.5
	-2
	0	200	400	600	800	1000

Output Code

Static parameter: Differential Non Linearity

Fs=20MSPS; Icca=30mA; Fin=10MHz
	1
	0.8
	0.6
(LSBs)	0.4
	0.2
	0
DNL	-0.2
	-0.4
	-0.6
	-0.8
	-1
	0	200	400	600	800	1000
				Output Code

7/22