SGS Thomson Microelectronics VIPER20SP, VIPER20DIP, VIPER20ASP, VIPER20ADIP, VIPER20A Datasheet

T YPE	VDSS	In	RDS(on)
VIPer20/SP/DIP	620V	0.5 A	16 Ω
VIPer20A/ASP/ADIP	700V	0.5 A	18 Ω

VIPer20/SP/DIP

VIPer20A/ASP/ADIP

SMPS PRIMARY I.C.

FEATURE

■ADJUSTABLE SWITCHING FREQUENCY UP TO 200KHZ

■CURRENT MODE CONTROL

■SOFT START AND SHUT DOWN CONTROL

■AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET ºBLUE ANGELº NORM (<1W TOTAL POWER CONSUMPTION)

■INTERNALLY TRIMMED ZENER REFERENCE

■UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS

■INTEGRATED START-UP SUPPLY

■AVALANCHE RUGGED

■OVERTEMPERATURE PROTECTION

■LOW STAND-BY CURRENT

■ADJUSTABLE CURRENT LIMITATION

DESCRIPTION

VIPer20/20A, made using VIPower M0

BLOCK DIAGRAM

	ON/OFF
		SECURITY
		LATCH
VDD	UVLO	R/S FF Q
	LOGIC
		S
		OVERTEMP.
		DETECTOR
	0.5 V +	1.7
	_	μs
		delay
	ERROR
	AMPLIFIER
	_
	13 V +
	4.5V

PENTAWATT HV	PENTAWATT HV (022Y)
10
1
PowerSO-10	DIP-8

Technology, combines on the same silicon chip a state-of-the-art PWM circuit together with an optimized high voltage avalanche rugged Vertical Power MOSFET (620V or 700V / 0.5A).

Typical applications cover off line power supplies with a secondary power capability of 10W in wide range condition and 20W in single range or with doubler configuration. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components.

OSC					DRAIN
OSCILLATOR
PWM
LATCH
	S
R1 FF Q
R2	R3
			0.5V
		+	+	_	6 V/A
	250 ns
	Blanking	_
					CURRENT
					AMPLIFIER
COMP					SOURCE	FC00491

November 1999

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VIPer20/SP/DIP - VIPer20A/ASP/ADIP

ABSOLUTE MAXIMUM RATING

Symb ol	Parameter	Value	Uni t
VDS	Continuous Drain-Source Voltage (Tj = 25 to 125oC)
	for VIPer20/SP/ DIP	-0.3 to 620	V
	for VIPer20A/ ASP/ADIP	-0.3 to 700	V
ID	Maximum Current	Internally Limited	A
VDD	Supply Voltage	0 to 15	V
VOSC	Voltage Range Input	0 to VDD	V
VCOMP	Voltage Range Input	0 to 5	V
ICOMP	Maximum Continuous Current	±2	mA
Vesd	Electrostatic discharge (R = 1.5 KΩ C = 100pF)	4000	V
ID(AR)	Avalanche Drain-Source Current, Repetitive or Not-Repetitive
	(TC = 100 oC, Pulse Width Limited by TJ max, δ <1%)	0.5	A
	for VIPer20/SP
	for VIPer20A/ ASP/ADIP	0.4	A
Ptot	Power Dissipation at Tc = 25oC	57	W
Tj	Junction Operating Temperature	Internally Limited	oC
Ts tg	Storage Temperature	-65 to 150	oC

THERMAL DATA

				PENT AW ATT PowerSO-10		DIP-8
Rthj-p in						20	oC/W
Rt hj-ca se	Thermal	Resistance Junction-case	Max	2.0	2.0		oC/W
Rth j-a mb.	Thermal	Resistance Ambient-case	Max	70	60	35 #	oC/W
(*) When mounted using the minimum recommended pad size on FR-4 board.
# On multylayer PCB

CONNECTION DIAGRAMS (Top View)
PENTAWATT HV PENTAWATT HV (022Y)		PowerSO-10	DIP-8
		OS C	1	8	DRAIN
		Vdd			DRAIN
		SOURC E			DRAIN
		COMP	4	5	DRAIN
				SC 10540
CURRENT AND VOLTAGE CONVENTIONS
IDD		ID
VDD	DRAIN
IOSC	-
OSC	+
13V
VDD	COMP SOURCE

VDS

ICOMP

VOSC

VCOMP

FC00020

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ORDERING NUMBERS

PENTAW AT T HV	PENT AW ATT HV (022Y)	PowerSO-10	DIP -8
VIPer20	VIPer20 (022Y)	VIPer20SP	VIPer20DIP
VIPer20A	VIPer20A (022Y)	VIPer20ASP	VIPer20ADIP

PINS FUNCTIONAL DESCRIPTION

DRAIN PIN:

Integrated power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power.

SOURCE PIN:

Power MOSFET source pin. Primary side circuit common ground connection.

VDD PIN :

This pin provides two functions :

-It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the start-up current source is activated and the output power MOSFET is switched off until the VDD voltage reaches 11V. During this phase, the internal current consumption is reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again.

-This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to stuck the output of the transconductance amplifier to the high state. The COMP pin behaves as a

constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control.

COMP PIN :

This pin provides two functions :

-It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin.

-When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever is the configuration) to provide a burst mode operation in case of negligible output power or open load condition.

OSC PIN :

An RT-CT network must be connected on that pin to define the switching frequency. Note that despite the connection of RT to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It provides also a synchronisation capability, when connected to an external frequency source.

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VIPer20/SP/DIP - VIPer20A/ASP/ADIP

AVALANCHE CHARACTERISTICS

Symb ol	Parameter	Max	Valu e	Uni t
ID(a r)	Avalanche Current, Repetitive or Not-Repetitive
	(pulse width limited by Tj max, δ < 1%)		0.5	A
	for VIPer20/SP/ DIP
	for VIPer20A/ ASPA/ DIP	(see fig.12)	0.4	A
E(ar)	Single Pulse Avalanche Energy		10	mJ
	(starting Tj = 25 oC, ID = ID(ar))	(see fig.12)

ELECTRICAL CHARACTERISTICS (TJ = 25 oC,			VDD = 13 V, unless otherwise specified)
POWER SECTION
Symb ol	Parameter	T est Con ditio ns		Mi n.	Typ .	Max.	Un it
BVDSS	Drain-Source Voltage	ID = 1 mA	VCOMP = 0 V
		for VIPer20/SP/DIP		620			V
		for VIPer20A/ASP/DI P (see fig.5)		700			V
IDSS	Off-State Drain Current	VCOMP = 0 V	TJ= 125 oC
		VDS = 620 V				1.0	mA
		for VIPer20/SP/DIP
		VDS = 700 V				1.0	mA
		for VIPer20A/ASP/ADIP
RDS( on)	Static Drain Source on	ID = 0.4 A					Ω
	Resistance	for VIPer20/SP/DIP			13.5	16
		for VIPer20A/ASP/ADIP			15.5	18	Ω
		ID = 0.4 A	TJ = 100 oC				Ω
		for VIPer20/SP/DIP				29
		for VIPer20A/ASP/ADIP				32	Ω
tf	Fall Time	ID = 0.2 A	Vin = 300 V (1)		100		ns
		(see fig.3)
tr	Rise Time	ID = 0.4 A	Vin = 300 V (1)		50		ns
		(see fig. 3)
COSS	Output Capacitance	VDS = 25 V			90		pF
(1) On Inductive Load, Clamped.
SUPPLY SECTION
Symb ol	Parameter	T est Con ditio ns		Mi n.	Typ .	Max.	Un it
IDDch	Start-up Charging	VDD = 5 V	VDS = 70 V		-2		mA
	Current	(see fig. 2 and fig. 15)
IDD0	Operating Supply Current	VDD = 12 V,	FSW = 0 KHz		12	16	mA
		(see fig. 2)
IDD1	Operating Supply Current	VDD = 12 V,	FSW = 100 KHz		13		mA
IDD2	Operating Supply Current	VDD = 12 V,	FSW = 200 KHz		14		mA
VDDo ff	Undervoltage Shutdown	(see fig. 2)		7.5	8		V
VDDo n	Undervoltage Reset	(see fig. 2)			11	12	V
VDDhyst	Hysteresis Start-up	(see fig. 2)		2.4	3		V

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ELECTRICAL CHARACTERISTICS (continued)

OSCILLATOR SECTION

Symb ol	Parameter	T est Con ditio ns
FSW	Oscillator Frequency	RT = 8.2 KΩ	CT =2.4 nF
	Total Variation	VDD = 9 to15 V
		with RT ± 1%	CT ± 5%

(see fig. 6 and fig. 9)

Mi n. Typ . Max. Un it

90 100 110 KHz

VOSCih	Oscillator Peak Voltage	7.1	V
VOSCi l	Oscillator Valley Voltage	3.7	V

ERROR AMPLIFIER SECTION

Symb ol	Parameter	Test Cond ition s			Mi n. Typ . Max. Un it
VDDreg	VDD Regulation Point	ICOMP = 0 mA	(see fig.1)		12.6	13	13.4	V
VDDreg	Total Variation	TJ = 0 to 100 oC				2		%
GBW	Unity Gain Bandwidth	From Input = VDD to Output = VCOMP				150		KHz
		COMP pin is open		(see fig. 10)
AVOL	Open Loop Voltage	COMP pin is open		(see fig. 10)	45	52		dB
	Gain
Gm	DC Transconductance	VCOMP = 2.5 V	(see fig. 1)		1.1	1.5	1.9	mA/V
VCOMPL O	Output Low Level	ICOMP = -400 μA		VDD = 14 V		0.2		V
VCOMPHI	Output High Level	ICOMP = 400 μA		VDD = 12 V		4.5		V
ICOMPLO	Output Low Current	VCOMP = 2.5 V		VDD = 14 V		-600		μA
	Capability
ICOMPHI	Output High Current	VCOMP = 2.5 V		VDD = 12 V		600		μA
	Capability

PWM COMPARATOR SECTION

Symb ol	Parameter
HID	VCOMP / IDpea k
VCOMPof f VCOMP offset
IDpeak	Peak Current Limitation
td	Current Sense Delay
	to turn-off
tb	Blanking Time
ton( mi n)	Minimum on Time

Test Cond ition s	Mi n. Typ . Max.			Un it
VCOMP = 1 to 3 V	4.2	6	7.8	V/A
IDp eak = 10 mA		0.5		V
VDD = 12 V COMP pin open	0.5	0.67	0.9	A
ID = 1 A		250		ns
		250	360	ns
		350		ns

SHUTDOWN AND OVERTEMPERATURE SECTION

Symb ol	Parameter	Test Cond ition s	Mi n.	Typ .	Max.	Un it
VCOMPth	Restart threshold	(see fig. 4)		0.5		V
tDI Ssu	Disable Set Up Time	(see fig. 4)		1.7	5	μs
Tt sd	Thermal Shutdown	(see fig. 8)	140	170	190	oC
	Temperature
Thyst	Thermal Shutdown	(see fig. 8)		40		oC
	Hysteresis

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VIPer20/SP/DIP - VIPer20A/ASP/ADIP

Figure 1: VDD Regulation Point

COMP
I	Slope =
ICOMPHI	Gm in mA/V

VDD

0

ICOMPLO

VDDreg

FC00150

Figure 3: Transition Time

ID

10% Ipeak

t

VDS

90% VD

10% VD

t

tf

tr

FC00160

Figure 5: Breakdown Voltage vs Temperature

FC0 0 180

1.15

BVDS S

(Nor malize d)

1. 1

1.05

1

0.95

0

20

40

60

80

100

120

Temp era ture ( C)

Figure 2: Undervoltage Lockout

IDD

IDD0

	VDDhyst	VDS = 70 V
		Fsw = 0
	VDDoff	VDD
		VDDon
	IDDch
		FC00170

Figure 4: Shut Down Action

VOS C
	t
VCOMP	tDIS s u
VCOMPth	t
ID
	t
ENABLE	ENABLE
	DISABLE
	FC 00 0 6 0

Figure 6: Typical Frequency Variation

FC0 019 0

1

(%)

0

-1

-2

-3

-4

-5

0

20

40

60

80

100

120

140

Temperature ( C)

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Figure 7: Start-up Waveforms

Figure 8: Overtemperature Protection

Tj

Tt sd

Tt s d-Thys t

t

Vdd

Vddo n

Vddoff

t

Id

t

Vco mp

t

SC1 019 1

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